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https://github.com/nyanmisaka/ffmpeg-rockchip.git
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04d092e7d5
RV64G supports MIN & MAX instructions natively only on floating point registers, not general purpose ones. The later would require the Zbb extension. Due to that, it is actually faster to perform the clipping "properly" in FPU. Benchmarks on SiFive U74-MC (courtesy of Shanghai StarFive Tech): audiodsp.vector_clipf_c: 29551.5 audiodsp.vector_clipf_rvf: 17871.0 Also tried unrolling with 2 or 8 elements but it gets worse either way.
50 lines
1.5 KiB
ArmAsm
50 lines
1.5 KiB
ArmAsm
/*
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* Copyright © 2022 Rémi Denis-Courmont.
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*
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* This file is part of FFmpeg.
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*
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* FFmpeg is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2.1 of the License, or (at your option) any later version.
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*
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* FFmpeg is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with FFmpeg; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include "libavutil/riscv/asm.S"
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func ff_vector_clipf_rvf, f
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NOHWF fmv.w.x fa0, a3
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NOHWF fmv.w.x fa1, a4
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1:
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flw ft0, (a1)
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flw ft1, 4(a1)
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fmax.s ft0, ft0, fa0
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flw ft2, 8(a1)
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fmax.s ft1, ft1, fa0
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flw ft3, 12(a1)
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fmax.s ft2, ft2, fa0
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addi a2, a2, -4
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fmax.s ft3, ft3, fa0
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addi a1, a1, 16
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fmin.s ft0, ft0, fa1
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fmin.s ft1, ft1, fa1
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fsw ft0, (a0)
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fmin.s ft2, ft2, fa1
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fsw ft1, 4(a0)
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fmin.s ft3, ft3, fa1
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fsw ft2, 8(a0)
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fsw ft3, 12(a0)
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addi a0, a0, 16
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bnez a2, 1b
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ret
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endfunc
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