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044ab993d2
* ppocr cls preprocessor use manager * hwc2chw cvcuda * ppocr rec preproc use manager * ocr rec preproc cvcuda * fix rec preproc bug * ppocr cls&rec preproc set normalize * fix pybind * address comment
117 lines
3.8 KiB
Plaintext
117 lines
3.8 KiB
Plaintext
// Copyright (c) 2022 PaddlePaddle Authors. All Rights Reserved.
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#ifdef WITH_GPU
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#include "fastdeploy/vision/common/processors/normalize.h"
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namespace fastdeploy {
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namespace vision {
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__global__ void NormalizeKernel(const uint8_t* src, float* dst,
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const float* alpha, const float* beta,
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int num_channel, bool swap_rb, int batch_size,
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int edge) {
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int idx = blockDim.x * blockIdx.x + threadIdx.x;
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if (idx >= edge) return;
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int img_size = edge / batch_size;
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int n = idx / img_size; // batch index
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int p = idx - (n * img_size); // pixel index within the image
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for (int i = 0; i < num_channel; ++i) {
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int j = i;
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if (swap_rb) {
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j = 2 - i;
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}
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dst[num_channel * idx + j] =
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src[num_channel * idx + j] * alpha[i] + beta[i];
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}
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}
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bool Normalize::ImplByCuda(FDMat* mat) {
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if (mat->layout != Layout::HWC) {
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FDERROR << "The input data must be NHWC format!" << std::endl;
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return false;
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}
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// Prepare input tensor
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FDTensor* src = CreateCachedGpuInputTensor(mat);
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src->ExpandDim(0);
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FDMatBatch mat_batch;
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mat_batch.SetTensor(src);
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mat_batch.mat_type = ProcLib::CUDA;
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mat_batch.input_cache = mat->input_cache;
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mat_batch.output_cache = mat->output_cache;
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bool ret = ImplByCuda(&mat_batch);
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FDTensor* dst = mat_batch.Tensor();
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dst->Squeeze(0);
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mat->SetTensor(dst);
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mat->mat_type = ProcLib::CUDA;
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return true;
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}
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bool Normalize::ImplByCuda(FDMatBatch* mat_batch) {
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if (mat_batch->layout != FDMatBatchLayout::NHWC) {
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FDERROR << "The input data must be NHWC format!" << std::endl;
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return false;
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}
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// Prepare input tensor
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FDTensor* src = CreateCachedGpuInputTensor(mat_batch);
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// Prepare output tensor
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mat_batch->output_cache->Resize(src->Shape(), FDDataType::FP32,
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"batch_output_cache", Device::GPU);
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// Copy alpha and beta to GPU
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gpu_alpha_.Resize({1, 1, static_cast<int>(alpha_.size())}, FDDataType::FP32,
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"alpha", Device::GPU);
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cudaMemcpy(gpu_alpha_.Data(), alpha_.data(), gpu_alpha_.Nbytes(),
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cudaMemcpyHostToDevice);
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gpu_beta_.Resize({1, 1, static_cast<int>(beta_.size())}, FDDataType::FP32,
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"beta", Device::GPU);
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cudaMemcpy(gpu_beta_.Data(), beta_.data(), gpu_beta_.Nbytes(),
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cudaMemcpyHostToDevice);
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int jobs =
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mat_batch->output_cache->Numel() / mat_batch->output_cache->shape[3];
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int threads = 256;
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int blocks = ceil(jobs / (float)threads);
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NormalizeKernel<<<blocks, threads, 0, mat_batch->Stream()>>>(
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reinterpret_cast<uint8_t*>(src->Data()),
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reinterpret_cast<float*>(mat_batch->output_cache->Data()),
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reinterpret_cast<float*>(gpu_alpha_.Data()),
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reinterpret_cast<float*>(gpu_beta_.Data()),
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mat_batch->output_cache->shape[3], swap_rb_,
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mat_batch->output_cache->shape[0], jobs);
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mat_batch->SetTensor(mat_batch->output_cache);
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mat_batch->mat_type = ProcLib::CUDA;
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return true;
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}
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#ifdef ENABLE_CVCUDA
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bool Normalize::ImplByCvCuda(FDMat* mat) { return ImplByCuda(mat); }
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bool Normalize::ImplByCvCuda(FDMatBatch* mat_batch) {
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return ImplByCuda(mat_batch);
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}
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#endif
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} // namespace vision
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} // namespace fastdeploy
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#endif
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