mirror of
https://github.com/PaddlePaddle/FastDeploy.git
synced 2025-10-07 17:41:52 +08:00
d3d914856d
* norm and permute batch processing * move cache to mat, batch processors * get batched tensor logic, resize on cpu logic * fix cpu compile error * remove vector mat api * nits * add comments * nits * fix batch size * move initial resize on cpu option to use_cuda api * fix pybind * processor manager pybind * rename mat and matbatch * move initial resize on cpu to ppcls preprocessor --------- Co-authored-by: Jason <jiangjiajun@baidu.com>
106 lines
3.6 KiB
C++
106 lines
3.6 KiB
C++
// Copyright (c) 2022 PaddlePaddle Authors. All Rights Reserved.
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#include "fastdeploy/vision/common/processors/cvcuda_utils.h"
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namespace fastdeploy {
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namespace vision {
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#ifdef ENABLE_CVCUDA
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nvcv::ImageFormat CreateCvCudaImageFormat(FDDataType type, int channel) {
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FDASSERT(channel == 1 || channel == 3 || channel == 4,
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"Only support channel be 1/3/4 in CV-CUDA.");
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if (type == FDDataType::UINT8) {
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if (channel == 1) {
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return nvcv::FMT_U8;
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} else if (channel == 3) {
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return nvcv::FMT_BGR8;
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} else {
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return nvcv::FMT_BGRA8;
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}
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} else if (type == FDDataType::FP32) {
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if (channel == 1) {
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return nvcv::FMT_F32;
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} else if (channel == 3) {
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return nvcv::FMT_BGRf32;
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} else {
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return nvcv::FMT_BGRAf32;
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}
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}
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FDASSERT(false, "Data type of %s is not supported.", Str(type).c_str());
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return nvcv::FMT_BGRf32;
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}
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nvcv::TensorWrapData CreateCvCudaTensorWrapData(const FDTensor& tensor) {
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FDASSERT(tensor.shape.size() == 3,
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"When create CVCUDA tensor from FD tensor,"
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"tensor shape should be 3-Dim, HWC layout");
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int batchsize = 1;
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int h = tensor.Shape()[0];
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int w = tensor.Shape()[1];
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int c = tensor.Shape()[2];
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nvcv::TensorDataStridedCuda::Buffer buf;
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buf.strides[3] = FDDataTypeSize(tensor.Dtype());
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buf.strides[2] = c * buf.strides[3];
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buf.strides[1] = w * buf.strides[2];
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buf.strides[0] = h * buf.strides[1];
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buf.basePtr = reinterpret_cast<NVCVByte*>(const_cast<void*>(tensor.Data()));
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nvcv::Tensor::Requirements req = nvcv::Tensor::CalcRequirements(
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batchsize, {w, h}, CreateCvCudaImageFormat(tensor.Dtype(), c));
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nvcv::TensorDataStridedCuda tensor_data(
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nvcv::TensorShape{req.shape, req.rank, req.layout},
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nvcv::DataType{req.dtype}, buf);
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return nvcv::TensorWrapData(tensor_data);
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}
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void* GetCvCudaTensorDataPtr(const nvcv::TensorWrapData& tensor) {
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auto data =
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dynamic_cast<const nvcv::ITensorDataStridedCuda*>(tensor.exportData());
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return reinterpret_cast<void*>(data->basePtr());
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}
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nvcv::ImageWrapData CreateImageWrapData(const FDTensor& tensor) {
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FDASSERT(tensor.shape.size() == 3,
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"When create CVCUDA image from FD tensor,"
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"tensor shape should be 3-Dim, HWC layout");
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int h = tensor.Shape()[0];
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int w = tensor.Shape()[1];
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int c = tensor.Shape()[2];
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nvcv::ImageDataStridedCuda::Buffer buf;
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buf.numPlanes = 1;
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buf.planes[0].width = w;
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buf.planes[0].height = h;
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buf.planes[0].rowStride = w * c * FDDataTypeSize(tensor.Dtype());
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buf.planes[0].basePtr =
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reinterpret_cast<NVCVByte*>(const_cast<void*>(tensor.Data()));
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nvcv::ImageWrapData nvimg{nvcv::ImageDataStridedCuda{
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nvcv::ImageFormat{CreateCvCudaImageFormat(tensor.Dtype(), c)}, buf}};
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return nvimg;
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}
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void CreateCvCudaImageBatchVarShape(std::vector<FDTensor*>& tensors,
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nvcv::ImageBatchVarShape& img_batch) {
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for (size_t i = 0; i < tensors.size(); ++i) {
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FDASSERT(tensors[i]->device == Device::GPU, "Tensor must on GPU.");
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img_batch.pushBack(CreateImageWrapData(*(tensors[i])));
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}
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}
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#endif
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} // namespace vision
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} // namespace fastdeploy
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