From dd39853956285bcd0300955ac9dcb6320e2bf367 Mon Sep 17 00:00:00 2001 From: "github-action[bot]" Date: Thu, 4 Jul 2024 20:30:59 +0200 Subject: [PATCH] Update On Thu Jul 4 20:30:58 CEST 2024 --- .github/update.log | 1 + clash-nyanpasu/frontend/nyanpasu/package.json | 2 +- clash-nyanpasu/package.json | 4 +- clash-nyanpasu/pnpm-lock.yaml | 64 +- clash-verge-rev/scripts/check.mjs | 12 - clash-verge-rev/src-tauri/src/config/verge.rs | 8 +- .../src/enhance/builtin/meta_guard.js | 2 +- .../src/enhance/builtin/meta_hy_alpn.js | 2 +- clash-verge-rev/src-tauri/src/enhance/mod.rs | 22 +- .../src-tauri/src/enhance/script.rs | 10 +- clash-verge-rev/src-tauri/src/enhance/seq.rs | 16 +- clash-verge-rev/src-tauri/src/utils/tmpl.rs | 2 +- .../src/components/profile/group-item.tsx | 163 ++ .../profile/groups-editor-viewer.tsx | 829 ++++++ .../src/components/profile/profile-item.tsx | 26 +- .../profile/proxies-editor-viewer.tsx | 521 ++++ .../src/components/profile/proxy-item.tsx | 116 + .../src/components/profile/rule-item.tsx | 105 +- .../profile/rules-editor-viewer.tsx | 67 +- .../setting/mods/clash-port-viewer.tsx | 16 +- clash-verge-rev/src/locales/en.json | 24 +- clash-verge-rev/src/locales/fa.json | 24 +- clash-verge-rev/src/locales/ru.json | 24 +- clash-verge-rev/src/locales/zh.json | 24 +- clash-verge-rev/src/services/types.d.ts | 59 +- echo/go.mod | 9 +- echo/go.sum | 14 +- geoip/README.md | 4 + geoip/config-example.json | 49 + geoip/lib/func.go | 19 +- geoip/plugin/maxmind/mmdb_in.go | 2 +- geoip/plugin/plaintext/text_in.go | 2 +- geoip/plugin/singbox/srs_in.go | 2 +- geoip/plugin/special/stdin.go | 113 + geoip/plugin/special/stdout.go | 128 + geoip/plugin/v2ray/dat_in.go | 2 +- lede/package/kernel/mt76/Makefile | 6 +- ...mt76-mt7925-add-EHT-radiotap-support.patch | 195 ++ .../firmware/mt7981_eeprom_mt7976_dbdc.bin | Bin 0 -> 4096 bytes .../lean/autocore/files/arm/sbin/cpuinfo | 19 +- .../files/zzz-default-settings | 8 +- .../wwan/driver/quectel_QMI_WWAN/Makefile | 2 +- .../driver/quectel_QMI_WWAN/src/qmi_wwan_q.c | 25 +- .../driver/quectel_QMI_WWAN/src/rmnet_nss.c | 1 + .../mt7981-rfb-mxl-2p5g-phy-eth1.dtso | 32 + .../mt7981-rfb-mxl-2p5g-phy-swp5.dtso | 33 + .../dts/mediatek/mt7981-rfb-spim-nand.dtso | 66 + .../arm64/boot/dts/mediatek/mt7981-rfb.dts | 188 ++ .../arch/arm64/boot/dts/mediatek/mt7981.dtsi | 1424 ++++----- .../dts/mediatek/mt7986a-rfb-spim-nand.dts | 4 +- .../dts/mediatek/mt7986a-rfb-spim-nor.dts | 4 +- .../arm64/boot/dts/mediatek/mt7986a-rfb.dtsi | 2 +- .../dts/mediatek/mt7988a-bananapi-bpi-r4.dts | 27 +- .../dts/mediatek/mt7988a-rfb-snfi-nand.dtso | 4 +- .../dts/mediatek/mt7988a-rfb-spim-nand.dtso | 4 +- .../arm64/boot/dts/mediatek/mt7988a-rfb.dts | 2 +- .../arch/arm64/boot/dts/mediatek/mt7988a.dtsi | 1100 ++++--- .../drivers/clk/mediatek/clk-mt7988-apmixed.c | 113 - .../drivers/clk/mediatek/clk-mt7988-eth.c | 141 - .../clk/mediatek/clk-mt7988-infracfg.c | 376 --- .../clk/mediatek/clk-mt7988-topckgen.c | 446 --- .../drivers/net/phy/mediatek-2p5ge.c | 214 +- .../drivers/pinctrl/mediatek/pinctrl-mt7988.c | 59 +- .../dt-bindings/clock/mediatek,mt7988-clk.h | 276 -- .../mediatek/files/block/partitions/fit.c | 15 +- .../files/drivers/leds/leds-smartrg-system.c | 13 + .../files/drivers/net/phy/rtk/rtl8367c/acl.c | 30 +- .../files/drivers/net/phy/rtk/rtl8367c/cpu.c | 4 +- .../files/drivers/net/phy/rtk/rtl8367c/igmp.c | 10 +- .../net/phy/rtk/rtl8367c/include/acl.h | 32 +- .../net/phy/rtk/rtl8367c/include/cpu.h | 6 +- .../net/phy/rtk/rtl8367c/include/dot1x.h | 2 +- .../net/phy/rtk/rtl8367c/include/eee.h | 2 +- .../net/phy/rtk/rtl8367c/include/i2c.h | 2 +- .../net/phy/rtk/rtl8367c/include/igmp.h | 12 +- .../net/phy/rtk/rtl8367c/include/interrupt.h | 2 +- .../drivers/net/phy/rtk/rtl8367c/include/l2.h | 50 +- .../net/phy/rtk/rtl8367c/include/leaky.h | 2 +- .../net/phy/rtk/rtl8367c/include/led.h | 20 +- .../net/phy/rtk/rtl8367c/include/mirror.h | 8 +- .../net/phy/rtk/rtl8367c/include/port.h | 34 +- .../net/phy/rtk/rtl8367c/include/ptp.h | 4 +- .../net/phy/rtk/rtl8367c/include/qos.h | 8 +- .../net/phy/rtk/rtl8367c/include/rate.h | 2 +- .../net/phy/rtk/rtl8367c/include/rtk_error.h | 8 +- .../net/phy/rtk/rtl8367c/include/rtk_switch.h | 8 +- .../net/phy/rtk/rtl8367c/include/rtk_types.h | 4 +- .../include/rtl8367c_asicdrv_cputag.h | 2 +- .../rtl8367c/include/rtl8367c_asicdrv_green.h | 2 +- .../rtl8367c/include/rtl8367c_asicdrv_qos.h | 2 +- .../rtl8367c_asicdrv_unknownMulticast.h | 2 +- .../phy/rtk/rtl8367c/include/rtl8367c_base.h | 2 +- .../phy/rtk/rtl8367c/include/rtl8367c_reg.h | 4 +- .../files/drivers/net/phy/rtk/rtl8367c/l2.c | 48 +- .../files/drivers/net/phy/rtk/rtl8367c/led.c | 16 +- .../drivers/net/phy/rtk/rtl8367c/mirror.c | 4 +- .../files/drivers/net/phy/rtk/rtl8367c/port.c | 38 +- .../files/drivers/net/phy/rtk/rtl8367c/ptp.c | 2 +- .../files/drivers/net/phy/rtk/rtl8367c/qos.c | 8 +- .../files/drivers/net/phy/rtk/rtl8367c/rldp.c | 4 +- .../drivers/net/phy/rtk/rtl8367c/rtk_switch.c | 10 +- .../phy/rtk/rtl8367c/rtl8367c_asicdrv_acl.c | 34 +- .../rtk/rtl8367c/rtl8367c_asicdrv_cputag.c | 26 +- .../phy/rtk/rtl8367c/rtl8367c_asicdrv_eav.c | 18 +- .../phy/rtk/rtl8367c/rtl8367c_asicdrv_fc.c | 4 +- .../phy/rtk/rtl8367c/rtl8367c_asicdrv_green.c | 16 +- .../phy/rtk/rtl8367c/rtl8367c_asicdrv_hsb.c | 2 +- .../phy/rtk/rtl8367c/rtl8367c_asicdrv_igmp.c | 20 +- .../rtk/rtl8367c/rtl8367c_asicdrv_inbwctrl.c | 4 +- .../rtk/rtl8367c/rtl8367c_asicdrv_interrupt.c | 4 +- .../phy/rtk/rtl8367c/rtl8367c_asicdrv_led.c | 2 +- .../phy/rtk/rtl8367c/rtl8367c_asicdrv_lut.c | 60 +- .../phy/rtk/rtl8367c/rtl8367c_asicdrv_mib.c | 18 +- .../phy/rtk/rtl8367c/rtl8367c_asicdrv_port.c | 8 +- .../phy/rtk/rtl8367c/rtl8367c_asicdrv_qos.c | 2 +- .../rtl8367c/rtl8367c_asicdrv_scheduling.c | 8 +- .../phy/rtk/rtl8367c/rtl8367c_asicdrv_svlan.c | 16 +- .../rtl8367c_asicdrv_unknownMulticast.c | 2 +- .../files/drivers/net/phy/rtk/rtl8367c/smi.c | 4 +- .../files/drivers/net/phy/rtk/rtl8367c/stat.c | 8 +- .../drivers/net/phy/rtk/rtl8367c/storm.c | 24 +- .../drivers/net/phy/rtk/rtl8367c/svlan.c | 40 +- .../files/drivers/net/phy/rtk/rtl8367c/vlan.c | 12 +- .../files/drivers/net/phy/rtk/rtl8367s_mdio.c | 4 +- lede/target/linux/mediatek/filogic/config-6.1 | 12 +- lede/target/linux/mediatek/filogic/target.mk | 2 +- ...-mt7986-add-spi-related-device-nodes.patch | 8 +- ...6.3-arm64-dts-mt7986-add-Bananapi-R3.patch | 6 +- ...define-3W-max-power-to-both-SFP-on-.patch} | 0 ...m64-dts-mt7986-change-cooling-trips.patch} | 0 ...7986-change-thermal-trips-on-BPI-R3.patch} | 0 .../041-block-fit-partition-parser.patch | 2 +- .../patches-6.1/104-mt7622-add-snor-irq.patch | 2 +- .../106-dts-mt7622-disable_btif.patch | 26 + .../112-dts-fix-bpi64-lan-names.patch | 2 +- .../113-dts-fix-bpi64-leds-and-buttons.patch | 8 +- .../114-dts-bpi64-disable-rtc.patch | 2 +- .../115-dts-bpi64-add-snand-support.patch | 50 - ...-declare-SPI-NAND-present-on-BPI-R64.patch | 70 + .../131-dts-mt7622-add-snand-support.patch | 2 +- ...dts-fix-wmac-support-for-mt7622-rfb1.patch | 4 +- ...ts-mt7623-bpi-r2-rootdisk-for-fitblk.patch | 55 + ...80-dts-mt7622-bpi-r64-add-mt7531-irq.patch | 13 - ...-handle-interrupts-from-MT7531-switc.patch | 32 + .../181-mt7622_fix_dts_mt7531_reg.patch | 28 + ...-dts-mediatek-mt7622-fix-GICv2-range.patch | 2 +- ...7986a-bpi-r3-use-all-ubi-nand-layout.patch | 131 + ...assign-functions-to-configure-pin-b.patch} | 0 ...981-topckgen-flag-SGM_REG_SEL-as-cri.patch | 30 + ...k-mediatek-Add-pcw-chg-shift-control.patch | 24 - ...ngs-clock-Add-compatibles-for-MT7981.patch | 75 + ...lk-mediatek-add-mt7988-clock-support.patch | 31 - ...mediatek-sgmiisys-Convert-to-DT-sche.patch | 107 + ...pcs-mediatek-sgmiisys-add-MT7981-SoC.patch | 37 + ...mediatek-move-ethsys-controller-conv.patch | 113 + ...t-mediatek-add-MT7988-ethwarp-reset-.patch | 35 + ...-clock-mediatek-add-MT7988-clock-IDs.patch | 302 ++ ...k-mediatek-add-clock-controllers-of-.patch | 260 ++ ...-pcw_chg_bit-control-for-PLLs-of-MT7.patch | 50 + ...-mediatek-add-drivers-for-MT7988-SoC.patch | 1026 +++++++ ...-infracfg-reset-controller-for-mt798.patch | 57 + ...-reset-mediatek-add-MT7988-reset-IDs.patch | 25 + ...hdog-mediatek-mt7988-add-wdt-support.patch | 125 + ...988-infracfg-fix-clocks-for-2nd-PCIe.patch | 31 + ...tek-mt7981-add-additional-uart-group.patch | 63 + ...tek-mt7981-add-additional-emmc-group.patch | 82 + .../331-mt7622-rfb1-enable-bmt.patch | 2 +- ...Add-support-for-the-Fidelix-FM35X1GA.patch | 4 +- ...freq-mediatek-Add-support-for-MT7988.patch | 32 +- ...nctrl-add-mt7988-pd-pulltype-support.patch | 99 + ...-Add-support-for-dynamic-calibration.patch | 10 +- ...s-mediatek-add-mt7622-pcie-slot-node.patch | 4 +- ...1-pcie-mediatek-gen3-PERST-for-100ms.patch | 17 + ...xsphy-support-type-switch-by-pericfg.patch | 167 ++ ...ediatek-add-support-for-coherent-DMA.patch | 13 +- ...-don-t-use-SGMII-AN-if-using-phylink.patch | 8 +- ...-ge-soc-sync-driver-with-MediaTek-SD.patch | 270 ++ .../735-net-phy-add-Airoha-EN8801SC-PHY.patch | 38 + ... => 804-v6.2-pwm-add-mt7986-support.patch} | 0 ...-pwm-mediatek-Add-support-for-MT7981.patch | 147 + ...-pwm-mediatek-add-support-for-MT7988.patch | 44 + ...mtk_thermal-Fix-kernel-doc-function-.patch | 37 + ...mtk_thermal-Use-devm_platform_get_an.patch | 37 + ...tk-Use-function-pointer-for-raw_to_.patch} | 12 +- ...tk-Add-support-for-MT7986-and-MT798.patch} | 32 +- ...mediatek-Relocate-driver-to-mediatek.patch | 2602 +++++++++++++++++ ...mediatek-Add-the-Low-Voltage-Thermal.patch | 1298 ++++++++ ...mal-mediatek-Add-LVTS-thermal-contro.patch | 186 ++ ...mal-mediatek-Add-AP-domain-to-LVTS-t.patch | 35 + ...-Add-a-thermal-zone-devdata-accessor.patch | 65 + ...-thermal_zone_device-structure-type-.patch | 55 + ...-the-thermal-zone-devdata-accessor-i.patch | 74 + ...e-the-right-device-for-devm_thermal_.patch | 201 ++ ...e-device-internal-thermal-zone-struc.patch | 79 + ...se-thermal_zone_device_type-accessor.patch | 62 + ...mediatek-Control-buffer-enablement-t.patch | 81 + ...-mediatek-Add-support-for-MT8365-SoC.patch | 123 + ...mediatek-Add-delay-after-thermal-ban.patch | 50 + ...mediatek-lvts_thermal-Fix-sensor-1-i.patch | 46 + ...mediatek-lvts_thermal-Add-AP-domain-.patch | 149 + ...rivers-mediatek-Add-delay-after-ther.patch | 53 + ...mediatek-Add-temperature-constraints.patch | 78 + ...mediatek-Use-devm_of_iomap-to-avoid-.patch | 53 + ...mediatek-Change-clk_prepare_enable-t.patch | 100 + ...-mediatek-Use-of_address_to_resource.patch | 36 + ...rivers-mediatek-Use-devm_of_iomap-to.patch | 57 + ...mediatek-lvts_thermal-Register-therm.patch | 37 + ...mediatek-lvts_thermal-Remove-redunda.patch | 28 + ...mediatek-lvts_thermal-Handle-IRQ-on-.patch | 40 + ...mediatek-lvts_thermal-Honor-sensors-.patch | 120 + ...mediatek-lvts_thermal-Use-offset-thr.patch | 77 + ...mediatek-lvts_thermal-Disable-undesi.patch | 51 + ...mediatek-lvts_thermal-Don-t-leave-th.patch | 70 + ...mediatek-lvts_thermal-Manage-thresho.patch | 156 + ...mediatek-lvts-Fix-parameter-check-in.patch | 29 + ...mediatek-Clean-up-redundant-dev_err_.patch | 33 + ...mediatek-lvts_thermal-Make-readings-.patch | 95 + ...mediatek-auxadc_thermal-Removed-call.patch | 30 + ...vert-to-platform-remove-callback-ret.patch | 58 + ...mediatek-lvts_thermal-Make-coeff-con.patch | 198 ++ ...mal-mediatek-Add-LVTS-thermal-sensor.patch | 35 + ...mediatek-lvts_thermal-Add-mt7988-sup.patch | 91 + ...mediatek-lvts_thermal-Fix-error-chec.patch | 30 + ...rs-mediatek-Fix-probe-for-THERMAL_V2.patch | 33 + ...mediatek-lvts_thermal-Add-suspend-an.patch | 83 + ...mal-mediatek-Add-LVTS-thermal-contro.patch | 49 + ...mediatek-lvts_thermal-Add-mt8192-sup.patch | 151 + ...mediatek-lvts_thermal-Update-calibra.patch | 70 + ...-control-buffer-enablement-on-MT7896.patch | 59 + ...i2c-mt65xx-allow-optional-pmic-clock.patch | 45 + ...oC-mediatek-mt7986-add-common-header.patch | 269 ++ ...7986-support-etdm-in-platform-driver.patch | 430 +++ ...-mediatek-mt7986-add-platform-driver.patch | 685 +++++ ...t7986-add-machine-driver-with-wm8960.patch | 243 ++ ...-mediatek-mt7986-wm8960-add-mt7986-w.patch | 87 + ...-mediatek-mt7986-afe-add-audio-afe-d.patch | 180 ++ ...7986-drop-the-remove-callback-of-mt7.patch | 42 + ...7986-remove-the-mt7986_wm8960_priv-s.patch | 105 + ...iatek-mt7986-add-sample-rate-checker.patch | 49 + ...7986-silence-error-in-case-of-EPROBE.patch | 26 + .../862-arm64-dts-mt7986-add-afe.patch | 40 + ...63-arm64-dts-mt7986-add-sound-wm8960.patch | 61 + ...-mt7986-add-sound-overlay-for-bpi-r3.patch | 75 + ...mt7622-bpi-r64-aliases-for-dtoverlay.patch | 2 +- .../901-arm-add-cmdline-override.patch | 2 +- .../910-dts-mt7622-bpi-r64-wifi-eeprom.patch | 2 +- .../911-dts-mt7622-bpi-r64-add-rootdisk.patch | 103 + ...986-move-cpuboot-in-a-dedicated-node.patch | 6 +- ...-mt7986-move-ilm-in-a-dedicated-node.patch | 6 +- ...-mt7986-move-dlm-in-a-dedicated-node.patch | 6 +- .../950-smartrg-i2c-led-driver.patch | 34 + ...iatek-split-tx-and-rx-fields-in-mtk_.patch | 599 ++++ ...iatek-use-QDMA-instead-of-ADMAv2-on-.patch | 123 + ...ernet-mtk_eth_soc-fix-WED-wifi-reset.patch | 49 + openwrt-packages/adguardhome/Makefile | 6 +- openwrt-packages/luci-app-store/Makefile | 2 +- .../luasrc/controller/store.lua | 200 +- openwrt-packages/luci-app-store/swagger.yaml | 71 +- sing-box/docs/changelog.md | 2 + sing-box/go.mod | 1 - small/v2ray-geodata/Makefile | 4 +- suyu/README.md | 2 +- xray-core/go.mod | 2 +- xray-core/go.sum | 4 +- yass/.github/workflows/releases-rpm.yml | 29 +- yass/src/net/resolver.cpp | 146 +- yass/src/net/resolver.hpp | 79 +- yass/src/qt6/yass_window.cpp | 1 + yt-dlp/yt_dlp/extractor/douyutv.py | 6 +- 269 files changed, 19212 insertions(+), 3637 deletions(-) create mode 100644 clash-verge-rev/src/components/profile/group-item.tsx create mode 100644 clash-verge-rev/src/components/profile/groups-editor-viewer.tsx create mode 100644 clash-verge-rev/src/components/profile/proxies-editor-viewer.tsx create mode 100644 clash-verge-rev/src/components/profile/proxy-item.tsx create mode 100644 geoip/plugin/special/stdin.go create mode 100644 geoip/plugin/special/stdout.go create mode 100644 lede/package/kernel/mt76/patches-6.x/002-Revert-wifi-mt76-mt7925-add-EHT-radiotap-support.patch create mode 100644 lede/package/kernel/mt76/src/firmware/mt7981_eeprom_mt7976_dbdc.bin create mode 100644 lede/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7981-rfb-mxl-2p5g-phy-eth1.dtso create mode 100644 lede/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7981-rfb-mxl-2p5g-phy-swp5.dtso create mode 100644 lede/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7981-rfb-spim-nand.dtso create mode 100644 lede/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7981-rfb.dts delete mode 100644 lede/target/linux/mediatek/files-6.1/drivers/clk/mediatek/clk-mt7988-apmixed.c delete mode 100644 lede/target/linux/mediatek/files-6.1/drivers/clk/mediatek/clk-mt7988-eth.c delete mode 100644 lede/target/linux/mediatek/files-6.1/drivers/clk/mediatek/clk-mt7988-infracfg.c delete mode 100644 lede/target/linux/mediatek/files-6.1/drivers/clk/mediatek/clk-mt7988-topckgen.c delete mode 100644 lede/target/linux/mediatek/files-6.1/include/dt-bindings/clock/mediatek,mt7988-clk.h rename lede/target/linux/mediatek/patches-6.1/{020-arm64-dts-mt7986-define-3W-max-power-to-both-SFP-on-.patch => 020-v6.7-arm64-dts-mt7986-define-3W-max-power-to-both-SFP-on-.patch} (100%) rename lede/target/linux/mediatek/patches-6.1/{021-arm64-dts-mt7986-change-cooling-trips.patch => 021-v6.7-arm64-dts-mt7986-change-cooling-trips.patch} (100%) rename lede/target/linux/mediatek/patches-6.1/{022-arm64-dts-mt7986-change-thermal-trips-on-BPI-R3.patch => 022-v6.7-arm64-dts-mt7986-change-thermal-trips-on-BPI-R3.patch} (100%) create mode 100644 lede/target/linux/mediatek/patches-6.1/106-dts-mt7622-disable_btif.patch delete mode 100644 lede/target/linux/mediatek/patches-6.1/115-dts-bpi64-add-snand-support.patch create mode 100644 lede/target/linux/mediatek/patches-6.1/115-v6.5-arm64-dts-mt7622-declare-SPI-NAND-present-on-BPI-R64.patch create mode 100644 lede/target/linux/mediatek/patches-6.1/164-dts-mt7623-bpi-r2-rootdisk-for-fitblk.patch delete mode 100644 lede/target/linux/mediatek/patches-6.1/180-dts-mt7622-bpi-r64-add-mt7531-irq.patch create mode 100644 lede/target/linux/mediatek/patches-6.1/180-v6.5-arm64-dts-mt7622-handle-interrupts-from-MT7531-switc.patch create mode 100644 lede/target/linux/mediatek/patches-6.1/181-mt7622_fix_dts_mt7531_reg.patch create mode 100644 lede/target/linux/mediatek/patches-6.1/196-dts-mt7986a-bpi-r3-use-all-ubi-nand-layout.patch rename lede/target/linux/mediatek/patches-6.1/{219-pinctrl-mediatek-assign-functions-to-configure-pin-b.patch => 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lede/target/linux/mediatek/patches-6.1/245-v6.8-dt-bindings-reset-mediatek-add-MT7988-ethwarp-reset-.patch create mode 100644 lede/target/linux/mediatek/patches-6.1/246-v6.8-dt-bindings-clock-mediatek-add-MT7988-clock-IDs.patch create mode 100644 lede/target/linux/mediatek/patches-6.1/247-v6.8-dt-bindings-clock-mediatek-add-clock-controllers-of-.patch create mode 100644 lede/target/linux/mediatek/patches-6.1/248-v6.8-clk-mediatek-add-pcw_chg_bit-control-for-PLLs-of-MT7.patch create mode 100644 lede/target/linux/mediatek/patches-6.1/249-v6.8-clk-mediatek-add-drivers-for-MT7988-SoC.patch create mode 100644 lede/target/linux/mediatek/patches-6.1/250-clk-mediatek-add-infracfg-reset-controller-for-mt798.patch create mode 100644 lede/target/linux/mediatek/patches-6.1/250-dt-bindings-reset-mediatek-add-MT7988-reset-IDs.patch create mode 100644 lede/target/linux/mediatek/patches-6.1/251-v6.8-watchdog-mediatek-mt7988-add-wdt-support.patch create mode 100644 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lede/target/linux/mediatek/patches-6.1/911-dts-mt7622-bpi-r64-add-rootdisk.patch create mode 100644 lede/target/linux/mediatek/patches-6.1/950-smartrg-i2c-led-driver.patch create mode 100644 lede/target/linux/mediatek/patches-6.1/961-net-ethernet-mediatek-split-tx-and-rx-fields-in-mtk_.patch create mode 100644 lede/target/linux/mediatek/patches-6.1/962-net-ethernet-mediatek-use-QDMA-instead-of-ADMAv2-on-.patch create mode 100644 lede/target/linux/mediatek/patches-6.1/963-net-ethernet-mtk_eth_soc-fix-WED-wifi-reset.patch diff --git a/.github/update.log b/.github/update.log index 2e85a9d22f..7f0806c59c 100644 --- a/.github/update.log +++ b/.github/update.log @@ -692,3 +692,4 @@ Update On Sun Jun 30 20:30:33 CEST 2024 Update On Mon Jul 1 20:30:34 CEST 2024 Update On Tue Jul 2 20:34:08 CEST 2024 Update On Wed Jul 3 20:29:03 CEST 2024 +Update On Thu Jul 4 20:30:48 CEST 2024 diff --git a/clash-nyanpasu/frontend/nyanpasu/package.json b/clash-nyanpasu/frontend/nyanpasu/package.json index c8f8b15750..20046ed3e4 100644 --- a/clash-nyanpasu/frontend/nyanpasu/package.json +++ b/clash-nyanpasu/frontend/nyanpasu/package.json @@ -40,7 +40,7 @@ "react-hook-form-mui": "7.0.1", "react-i18next": "14.1.2", "react-markdown": "9.0.1", - "react-router-dom": "6.24.0", + "react-router-dom": "6.24.1", "react-transition-group": "4.4.5", "react-virtuoso": "4.7.10", "swr": "2.2.5", diff --git a/clash-nyanpasu/package.json b/clash-nyanpasu/package.json index 6499c38647..333690bc04 100644 --- a/clash-nyanpasu/package.json +++ b/clash-nyanpasu/package.json @@ -90,14 +90,14 @@ "eslint-plugin-promise": "6.4.0", "eslint-plugin-react": "7.34.3", "lint-staged": "15.2.7", - "npm-run-all2": "6.2.0", + "npm-run-all2": "6.2.2", "postcss": "8.4.39", "postcss-html": "1.7.0", "postcss-import": "16.1.0", "postcss-scss": "4.0.9", "prettier": "3.3.2", "prettier-plugin-toml": "2.0.1", - "react-devtools": "5.3.0", + "react-devtools": "5.3.1", "stylelint": "16.6.1", "stylelint-config-html": "1.1.0", "stylelint-config-recess-order": "5.0.1", diff --git a/clash-nyanpasu/pnpm-lock.yaml b/clash-nyanpasu/pnpm-lock.yaml index 2289c4937d..ee0997e92f 100644 --- a/clash-nyanpasu/pnpm-lock.yaml +++ b/clash-nyanpasu/pnpm-lock.yaml @@ -86,8 +86,8 @@ importers: specifier: 15.2.7 version: 15.2.7 npm-run-all2: - specifier: 6.2.0 - version: 6.2.0 + specifier: 6.2.2 + version: 6.2.2 postcss: specifier: 8.4.39 version: 8.4.39 @@ -107,8 +107,8 @@ importers: specifier: 2.0.1 version: 2.0.1(prettier@3.3.2) react-devtools: - specifier: 5.3.0 - version: 5.3.0(bufferutil@4.0.8)(utf-8-validate@5.0.10) + specifier: 5.3.1 + version: 5.3.1(bufferutil@4.0.8)(utf-8-validate@5.0.10) stylelint: specifier: 16.6.1 version: 16.6.1(typescript@5.5.3) @@ -178,7 +178,7 @@ importers: version: 11.11.5(@emotion/react@11.11.4(react@19.0.0-rc-fb9a90fa48-20240614)(types-react@19.0.0-rc.1))(react@19.0.0-rc-fb9a90fa48-20240614)(types-react@19.0.0-rc.1) '@generouted/react-router': specifier: 1.19.5 - version: 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sha512-PTXFXGK2pyXpHzVo3rR9H7ip4lSPZZc0bHG5CARmj65fTT6qG7sTngmb6lcYu1gf3y/8KxORoy9yn59pGpCnpg==} engines: {node: '>=14.0.0'} peerDependencies: react: npm:react@rc @@ -6338,12 +6338,12 @@ snapshots: postcss: 7.0.32 purgecss: 2.3.0 - '@generouted/react-router@1.19.5(react-router-dom@6.24.0(react-dom@19.0.0-rc-fb9a90fa48-20240614(react@19.0.0-rc-fb9a90fa48-20240614))(react@19.0.0-rc-fb9a90fa48-20240614))(react@19.0.0-rc-fb9a90fa48-20240614)(vite@5.3.3(@types/node@20.14.9)(less@4.2.0)(sass@1.77.6)(stylus@0.62.0))': + '@generouted/react-router@1.19.5(react-router-dom@6.24.1(react-dom@19.0.0-rc-fb9a90fa48-20240614(react@19.0.0-rc-fb9a90fa48-20240614))(react@19.0.0-rc-fb9a90fa48-20240614))(react@19.0.0-rc-fb9a90fa48-20240614)(vite@5.3.3(@types/node@20.14.9)(less@4.2.0)(sass@1.77.6)(stylus@0.62.0))': dependencies: fast-glob: 3.3.2 generouted: 1.19.5(vite@5.3.3(@types/node@20.14.9)(less@4.2.0)(sass@1.77.6)(stylus@0.62.0)) react: 19.0.0-rc-fb9a90fa48-20240614 - react-router-dom: 6.24.0(react-dom@19.0.0-rc-fb9a90fa48-20240614(react@19.0.0-rc-fb9a90fa48-20240614))(react@19.0.0-rc-fb9a90fa48-20240614) + react-router-dom: 6.24.1(react-dom@19.0.0-rc-fb9a90fa48-20240614(react@19.0.0-rc-fb9a90fa48-20240614))(react@19.0.0-rc-fb9a90fa48-20240614) vite: 5.3.3(@types/node@20.14.9)(less@4.2.0)(sass@1.77.6)(stylus@0.62.0) '@humanwhocodes/config-array@0.11.14': @@ -6769,7 +6769,7 @@ snapshots: '@popperjs/core@2.11.8': {} - '@remix-run/router@1.17.0': {} + '@remix-run/router@1.17.1': {} '@rollup/pluginutils@5.1.0(rollup@4.17.2)': dependencies: @@ -9911,7 +9911,7 @@ snapshots: npm-normalize-package-bin@3.0.1: {} - npm-run-all2@6.2.0: + npm-run-all2@6.2.2: dependencies: ansi-styles: 6.2.1 cross-spawn: 7.0.3 @@ -10330,7 +10330,7 @@ snapshots: minimist: 1.2.8 strip-json-comments: 2.0.1 - react-devtools-core@5.3.0(bufferutil@4.0.8)(utf-8-validate@5.0.10): + react-devtools-core@5.3.1(bufferutil@4.0.8)(utf-8-validate@5.0.10): dependencies: shell-quote: 1.8.1 ws: 7.5.9(bufferutil@4.0.8)(utf-8-validate@5.0.10) @@ -10338,13 +10338,13 @@ snapshots: - bufferutil - utf-8-validate - react-devtools@5.3.0(bufferutil@4.0.8)(utf-8-validate@5.0.10): + react-devtools@5.3.1(bufferutil@4.0.8)(utf-8-validate@5.0.10): dependencies: cross-spawn: 5.1.0 electron: 23.3.13 internal-ip: 6.2.0 minimist: 1.2.8 - react-devtools-core: 5.3.0(bufferutil@4.0.8)(utf-8-validate@5.0.10) + react-devtools-core: 5.3.1(bufferutil@4.0.8)(utf-8-validate@5.0.10) update-notifier: 2.5.0 transitivePeerDependencies: - bufferutil @@ -10417,16 +10417,16 @@ snapshots: react: 19.0.0-rc-fb9a90fa48-20240614 react-dom: 19.0.0-rc-fb9a90fa48-20240614(react@19.0.0-rc-fb9a90fa48-20240614) - react-router-dom@6.24.0(react-dom@19.0.0-rc-fb9a90fa48-20240614(react@19.0.0-rc-fb9a90fa48-20240614))(react@19.0.0-rc-fb9a90fa48-20240614): + react-router-dom@6.24.1(react-dom@19.0.0-rc-fb9a90fa48-20240614(react@19.0.0-rc-fb9a90fa48-20240614))(react@19.0.0-rc-fb9a90fa48-20240614): dependencies: - '@remix-run/router': 1.17.0 + '@remix-run/router': 1.17.1 react: 19.0.0-rc-fb9a90fa48-20240614 react-dom: 19.0.0-rc-fb9a90fa48-20240614(react@19.0.0-rc-fb9a90fa48-20240614) - react-router: 6.24.0(react@19.0.0-rc-fb9a90fa48-20240614) + react-router: 6.24.1(react@19.0.0-rc-fb9a90fa48-20240614) - react-router@6.24.0(react@19.0.0-rc-fb9a90fa48-20240614): + react-router@6.24.1(react@19.0.0-rc-fb9a90fa48-20240614): dependencies: - '@remix-run/router': 1.17.0 + '@remix-run/router': 1.17.1 react: 19.0.0-rc-fb9a90fa48-20240614 react-transition-group@4.4.5(react-dom@19.0.0-rc-fb9a90fa48-20240614(react@19.0.0-rc-fb9a90fa48-20240614))(react@19.0.0-rc-fb9a90fa48-20240614): diff --git a/clash-verge-rev/scripts/check.mjs b/clash-verge-rev/scripts/check.mjs index 335bd6c46c..19e2ac6444 100644 --- a/clash-verge-rev/scripts/check.mjs +++ b/clash-verge-rev/scripts/check.mjs @@ -400,16 +400,6 @@ const resolveUninstall = () => { }); }; -const resolveSetDnsScript = () => - resolveResource({ - file: "set_dns.sh", - downloadURL: `https://github.com/clash-verge-rev/set-dns-script/releases/download/script/set_dns.sh`, - }); -const resolveUnSetDnsScript = () => - resolveResource({ - file: "unset_dns.sh", - downloadURL: `https://github.com/clash-verge-rev/set-dns-script/releases/download/script/unset_dns.sh`, - }); const resolveMmdb = () => resolveResource({ file: "Country.mmdb", @@ -449,8 +439,6 @@ const tasks = [ { name: "service", func: resolveService, retry: 5 }, { name: "install", func: resolveInstall, retry: 5 }, { name: "uninstall", func: resolveUninstall, retry: 5 }, - { name: "set_dns_script", func: resolveSetDnsScript, retry: 5 }, - { name: "unset_dns_script", func: resolveUnSetDnsScript, retry: 5 }, { name: "mmdb", func: resolveMmdb, retry: 5 }, { name: "geosite", func: resolveGeosite, retry: 5 }, { name: "geoip", func: resolveGeoIP, retry: 5 }, diff --git a/clash-verge-rev/src-tauri/src/config/verge.rs b/clash-verge-rev/src-tauri/src/config/verge.rs index a7f8827c8e..6086b8cea7 100644 --- a/clash-verge-rev/src-tauri/src/config/verge.rs +++ b/clash-verge-rev/src-tauri/src/config/verge.rs @@ -227,16 +227,16 @@ impl IVerge { #[cfg(not(target_os = "windows"))] verge_redir_port: Some(7895), #[cfg(not(target_os = "windows"))] - verge_redir_enabled: Some(true), + verge_redir_enabled: Some(false), #[cfg(target_os = "linux")] verge_tproxy_port: Some(7896), #[cfg(target_os = "linux")] - verge_tproxy_enabled: Some(true), + verge_tproxy_enabled: Some(false), verge_mixed_port: Some(7897), verge_socks_port: Some(7898), - verge_socks_enabled: Some(true), + verge_socks_enabled: Some(false), verge_port: Some(7899), - verge_http_enabled: Some(true), + verge_http_enabled: Some(false), enable_proxy_guard: Some(false), use_default_bypass: Some(true), proxy_guard_duration: Some(30), diff --git a/clash-verge-rev/src-tauri/src/enhance/builtin/meta_guard.js b/clash-verge-rev/src-tauri/src/enhance/builtin/meta_guard.js index e8ac897087..33b048f238 100644 --- a/clash-verge-rev/src-tauri/src/enhance/builtin/meta_guard.js +++ b/clash-verge-rev/src-tauri/src/enhance/builtin/meta_guard.js @@ -1,4 +1,4 @@ -function main(config) { +function main(config, _name) { if (config.mode === "script") { config.mode = "rule"; } diff --git a/clash-verge-rev/src-tauri/src/enhance/builtin/meta_hy_alpn.js b/clash-verge-rev/src-tauri/src/enhance/builtin/meta_hy_alpn.js index 92c196ed0e..dda6366caa 100644 --- a/clash-verge-rev/src-tauri/src/enhance/builtin/meta_hy_alpn.js +++ b/clash-verge-rev/src-tauri/src/enhance/builtin/meta_hy_alpn.js @@ -1,4 +1,4 @@ -function main(config) { +function main(config, _name) { if (Array.isArray(config.proxies)) { config.proxies.forEach((p, i) => { if (p.type === "hysteria" && typeof p.alpn === "string") { diff --git a/clash-verge-rev/src-tauri/src/enhance/mod.rs b/clash-verge-rev/src-tauri/src/enhance/mod.rs index 9d0f89c378..11355e8740 100644 --- a/clash-verge-rev/src-tauri/src/enhance/mod.rs +++ b/clash-verge-rev/src-tauri/src/enhance/mod.rs @@ -32,21 +32,21 @@ pub async fn enhance() -> (Mapping, Vec, HashMap) { verge.clash_core.clone(), verge.enable_tun_mode.unwrap_or(false), verge.enable_builtin_enhanced.unwrap_or(true), - verge.verge_socks_enabled.unwrap_or(true), - verge.verge_http_enabled.unwrap_or(true), + verge.verge_socks_enabled.unwrap_or(false), + verge.verge_http_enabled.unwrap_or(false), ) }; #[cfg(not(target_os = "windows"))] let redir_enabled = { let verge = Config::verge(); let verge = verge.latest(); - verge.verge_redir_enabled.unwrap_or(true) + verge.verge_redir_enabled.unwrap_or(false) }; #[cfg(target_os = "linux")] let tproxy_enabled = { let verge = Config::verge(); let verge = verge.latest(); - verge.verge_tproxy_enabled.unwrap_or(true) + verge.verge_tproxy_enabled.unwrap_or(false) }; // 从profiles里拿东西 @@ -59,6 +59,7 @@ pub async fn enhance() -> (Mapping, Vec, HashMap) { groups_item, global_merge, global_script, + profile_name, ) = { let profiles = Config::profiles(); let profiles = profiles.latest(); @@ -123,6 +124,12 @@ pub async fn enhance() -> (Mapping, Vec, HashMap) { data: ChainType::Script(tmpl::ITEM_SCRIPT.into()), }); + let name = profiles + .get_item(&profiles.get_current().unwrap_or_default()) + .ok() + .and_then(|item| item.name.clone()) + .unwrap_or_default(); + ( current, merge, @@ -132,6 +139,7 @@ pub async fn enhance() -> (Mapping, Vec, HashMap) { groups, global_merge, global_script, + name, ) }; @@ -147,7 +155,7 @@ pub async fn enhance() -> (Mapping, Vec, HashMap) { if let ChainType::Script(script) = global_script.data { let mut logs = vec![]; - match use_script(script, config.to_owned()) { + match use_script(script, config.to_owned(), profile_name.to_owned()) { Ok((res_config, res_logs)) => { exists_keys.extend(use_keys(&res_config)); config = res_config; @@ -180,7 +188,7 @@ pub async fn enhance() -> (Mapping, Vec, HashMap) { if let ChainType::Script(script) = script_item.data { let mut logs = vec![]; - match use_script(script, config.to_owned()) { + match use_script(script, config.to_owned(), profile_name.to_owned()) { Ok((res_config, res_logs)) => { exists_keys.extend(use_keys(&res_config)); config = res_config; @@ -239,7 +247,7 @@ pub async fn enhance() -> (Mapping, Vec, HashMap) { .for_each(|item| { log::debug!(target: "app", "run builtin script {}", item.uid); if let ChainType::Script(script) = item.data { - match use_script(script, config.to_owned()) { + match use_script(script, config.to_owned(), "".to_string()) { Ok((res_config, _)) => { config = res_config; } diff --git a/clash-verge-rev/src-tauri/src/enhance/script.rs b/clash-verge-rev/src-tauri/src/enhance/script.rs index 8c6781543e..e2465097e7 100644 --- a/clash-verge-rev/src-tauri/src/enhance/script.rs +++ b/clash-verge-rev/src-tauri/src/enhance/script.rs @@ -2,7 +2,11 @@ use super::use_lowercase; use anyhow::{Error, Result}; use serde_yaml::Mapping; -pub fn use_script(script: String, config: Mapping) -> Result<(Mapping, Vec<(String, String)>)> { +pub fn use_script( + script: String, + config: Mapping, + name: String, +) -> Result<(Mapping, Vec<(String, String)>)> { use boa_engine::{native_function::NativeFunction, Context, JsValue, Source}; use std::sync::{Arc, Mutex}; let mut context = Context::default(); @@ -42,7 +46,7 @@ pub fn use_script(script: String, config: Mapping) -> Result<(Mapping, Vec<(Stri let code = format!( r#"try{{ {script}; - JSON.stringify(main({config_str})||'') + JSON.stringify(main({config_str},'{name}')||'') }} catch(err) {{ `__error_flag__ ${{err.toString()}}` }}"# @@ -97,7 +101,7 @@ fn test_script() { "#; let config = serde_yaml::from_str(config).unwrap(); - let (config, results) = use_script(script.into(), config).unwrap(); + let (config, results) = use_script(script.into(), config, "".to_string()).unwrap(); let config_str = serde_yaml::to_string(&config).unwrap(); diff --git a/clash-verge-rev/src-tauri/src/enhance/seq.rs b/clash-verge-rev/src-tauri/src/enhance/seq.rs index 1aa1785c73..c253b1e6ff 100644 --- a/clash-verge-rev/src-tauri/src/enhance/seq.rs +++ b/clash-verge-rev/src-tauri/src/enhance/seq.rs @@ -16,14 +16,7 @@ pub fn use_seq(seq_map: SeqMap, config: Mapping, name: &str) -> Mapping { val.as_sequence().unwrap_or(&Sequence::default()).clone() }); let mut seq = origin_seq.clone(); - prepend.reverse(); - for item in prepend { - seq.insert(0, item); - } - for item in append { - seq.push(item); - } let mut delete_names = Vec::new(); for item in delete { let item = item.clone(); @@ -47,6 +40,15 @@ pub fn use_seq(seq_map: SeqMap, config: Mapping, name: &str) -> Mapping { } }); + prepend.reverse(); + for item in prepend { + seq.insert(0, item); + } + + for item in append { + seq.push(item); + } + let mut config = config.clone(); config.insert(Value::from(name), Value::from(seq)); return config; diff --git a/clash-verge-rev/src-tauri/src/utils/tmpl.rs b/clash-verge-rev/src-tauri/src/utils/tmpl.rs index 15aa926d7b..545672de9e 100644 --- a/clash-verge-rev/src-tauri/src/utils/tmpl.rs +++ b/clash-verge-rev/src-tauri/src/utils/tmpl.rs @@ -27,7 +27,7 @@ pub const ITEM_MERGE_EMPTY: &str = "# Profile Enhancement Merge Template for Cla /// enhanced profile pub const ITEM_SCRIPT: &str = "// Define main function (script entry) -function main(config) { +function main(config, profileName) { return config; } "; diff --git a/clash-verge-rev/src/components/profile/group-item.tsx b/clash-verge-rev/src/components/profile/group-item.tsx new file mode 100644 index 0000000000..7bf18cf567 --- /dev/null +++ b/clash-verge-rev/src/components/profile/group-item.tsx @@ -0,0 +1,163 @@ +import { + Box, + IconButton, + ListItem, + ListItemText, + alpha, + styled, +} from "@mui/material"; +import { DeleteForeverRounded, UndoRounded } from "@mui/icons-material"; +import { useSortable } from "@dnd-kit/sortable"; +import { CSS } from "@dnd-kit/utilities"; +import { downloadIconCache } from "@/services/cmds"; +import { convertFileSrc } from "@tauri-apps/api/tauri"; +import { useEffect, useState } from "react"; +interface Props { + type: "prepend" | "original" | "delete" | "append"; + group: IProxyGroupConfig; + onDelete: () => void; +} + +export const GroupItem = (props: Props) => { + let { type, group, onDelete } = props; + const sortable = type === "prepend" || type === "append"; + + const { attributes, listeners, setNodeRef, transform, transition } = sortable + ? useSortable({ id: group.name }) + : { + attributes: {}, + listeners: {}, + setNodeRef: null, + transform: null, + transition: null, + }; + + const [iconCachePath, setIconCachePath] = useState(""); + + useEffect(() => { + initIconCachePath(); + }, [group]); + + async function initIconCachePath() { + if (group.icon && group.icon.trim().startsWith("http")) { + const fileName = + group.name.replaceAll(" ", "") + "-" + getFileName(group.icon); + const iconPath = await downloadIconCache(group.icon, fileName); + setIconCachePath(convertFileSrc(iconPath)); + } + } + + function getFileName(url: string) { + return url.substring(url.lastIndexOf("/") + 1); + } + + return ( + ({ + background: + type === "original" + ? palette.mode === "dark" + ? alpha(palette.background.paper, 0.3) + : alpha(palette.grey[400], 0.3) + : type === "delete" + ? alpha(palette.error.main, 0.3) + : alpha(palette.success.main, 0.3), + height: "100%", + margin: "8px 0", + borderRadius: "8px", + transform: CSS.Transform.toString(transform), + transition, + })} + > + {group.icon && group.icon?.trim().startsWith("http") && ( + + )} + {group.icon && group.icon?.trim().startsWith("data") && ( + + )} + {group.icon && group.icon?.trim().startsWith(" + )} + + {group.name} + + } + secondary={ + + + {group.type} + + + } + secondaryTypographyProps={{ + sx: { + display: "flex", + alignItems: "center", + color: "#ccc", + }, + }} + /> + + {type === "delete" ? : } + + + ); +}; + +const StyledPrimary = styled("span")` + font-size: 15px; + font-weight: 700; + line-height: 1.5; + overflow: hidden; + text-overflow: ellipsis; + white-space: nowrap; +`; + +const ListItemTextChild = styled("span")` + display: block; +`; + +const StyledTypeBox = styled(ListItemTextChild)(({ theme }) => ({ + display: "inline-block", + border: "1px solid #ccc", + borderColor: alpha(theme.palette.primary.main, 0.5), + color: alpha(theme.palette.primary.main, 0.8), + borderRadius: 4, + fontSize: 10, + padding: "0 4px", + lineHeight: 1.5, + marginRight: "8px", +})); diff --git a/clash-verge-rev/src/components/profile/groups-editor-viewer.tsx b/clash-verge-rev/src/components/profile/groups-editor-viewer.tsx new file mode 100644 index 0000000000..cdc7833982 --- /dev/null +++ b/clash-verge-rev/src/components/profile/groups-editor-viewer.tsx @@ -0,0 +1,829 @@ +import { ReactNode, useEffect, useMemo, useState } from "react"; +import { useLockFn } from "ahooks"; +import yaml from "js-yaml"; +import { useTranslation } from "react-i18next"; +import { + DndContext, + closestCenter, + KeyboardSensor, + PointerSensor, + useSensor, + useSensors, + DragEndEvent, +} from "@dnd-kit/core"; +import { + SortableContext, + sortableKeyboardCoordinates, +} from "@dnd-kit/sortable"; +import { + Autocomplete, + Box, + Button, + Dialog, + DialogActions, + DialogContent, + DialogTitle, + List, + ListItem, + ListItemText, + TextField, + styled, +} from "@mui/material"; +import { GroupItem } from "@/components/profile/group-item"; +import { readProfileFile, saveProfileFile } from "@/services/cmds"; +import { Notice, Switch } from "@/components/base"; +import getSystem from "@/utils/get-system"; +import { BaseSearchBox } from "../base/base-search-box"; +import { Virtuoso } from "react-virtuoso"; +import MonacoEditor from "react-monaco-editor"; +import { useThemeMode } from "@/services/states"; +import { Controller, useForm } from "react-hook-form"; + +interface Props { + proxiesUid: string; + mergeUid: string; + profileUid: string; + property: string; + open: boolean; + onClose: () => void; + onSave?: (prev?: string, curr?: string) => void; +} + +const builtinProxyPolicies = ["DIRECT", "REJECT", "REJECT-DROP", "PASS"]; + +export const GroupsEditorViewer = (props: Props) => { + const { mergeUid, proxiesUid, profileUid, property, open, onClose, onSave } = + props; + const { t } = useTranslation(); + const themeMode = useThemeMode(); + const [prevData, setPrevData] = useState(""); + const [currData, setCurrData] = useState(""); + const [visualization, setVisualization] = useState(true); + const [match, setMatch] = useState(() => (_: string) => true); + + const { control, watch, register, ...formIns } = useForm({ + defaultValues: { + type: "select", + name: "", + lazy: true, + }, + }); + const [groupList, setGroupList] = useState([]); + const [proxyPolicyList, setProxyPolicyList] = useState([]); + const [proxyProviderList, setProxyProviderList] = useState([]); + const [prependSeq, setPrependSeq] = useState([]); + const [appendSeq, setAppendSeq] = useState([]); + const [deleteSeq, setDeleteSeq] = useState([]); + + const filteredGroupList = useMemo( + () => groupList.filter((group) => match(group.name)), + [groupList, match] + ); + + const sensors = useSensors( + useSensor(PointerSensor), + useSensor(KeyboardSensor, { + coordinateGetter: sortableKeyboardCoordinates, + }) + ); + const reorder = ( + list: IProxyGroupConfig[], + startIndex: number, + endIndex: number + ) => { + const result = Array.from(list); + const [removed] = result.splice(startIndex, 1); + result.splice(endIndex, 0, removed); + return result; + }; + const onPrependDragEnd = async (event: DragEndEvent) => { + const { active, over } = event; + if (over) { + if (active.id !== over.id) { + let activeIndex = 0; + let overIndex = 0; + prependSeq.forEach((item, index) => { + if (item.name === active.id) { + activeIndex = index; + } + if (item.name === over.id) { + overIndex = index; + } + }); + + setPrependSeq(reorder(prependSeq, activeIndex, overIndex)); + } + } + }; + const onAppendDragEnd = async (event: DragEndEvent) => { + const { active, over } = event; + if (over) { + if (active.id !== over.id) { + let activeIndex = 0; + let overIndex = 0; + appendSeq.forEach((item, index) => { + if (item.name === active.id) { + activeIndex = index; + } + if (item.name === over.id) { + overIndex = index; + } + }); + setAppendSeq(reorder(appendSeq, activeIndex, overIndex)); + } + } + }; + const fetchContent = async () => { + let data = await readProfileFile(property); + let obj = yaml.load(data) as ISeqProfileConfig | null; + + setPrependSeq(obj?.prepend || []); + setAppendSeq(obj?.append || []); + setDeleteSeq(obj?.delete || []); + + setPrevData(data); + setCurrData(data); + }; + + useEffect(() => { + if (currData === "") return; + if (visualization !== true) return; + + let obj = yaml.load(currData) as { + prepend: []; + append: []; + delete: []; + } | null; + setPrependSeq(obj?.prepend || []); + setAppendSeq(obj?.append || []); + setDeleteSeq(obj?.delete || []); + }, [visualization]); + + useEffect(() => { + if (prependSeq && appendSeq && deleteSeq) + setCurrData( + yaml.dump( + { prepend: prependSeq, append: appendSeq, delete: deleteSeq }, + { + forceQuotes: true, + } + ) + ); + }, [prependSeq, appendSeq, deleteSeq]); + + const fetchProxyPolicy = async () => { + let data = await readProfileFile(profileUid); + let proxiesData = await readProfileFile(proxiesUid); + let originGroupsObj = yaml.load(data) as { + "proxy-groups": IProxyGroupConfig[]; + } | null; + + let originProxiesObj = yaml.load(data) as { proxies: [] } | null; + let originProxies = originProxiesObj?.proxies || []; + let moreProxiesObj = yaml.load(proxiesData) as ISeqProfileConfig | null; + let morePrependProxies = moreProxiesObj?.prepend || []; + let moreAppendProxies = moreProxiesObj?.append || []; + let moreDeleteProxies = + moreProxiesObj?.delete || ([] as string[] | { name: string }[]); + + let proxies = morePrependProxies.concat( + originProxies.filter((proxy: any) => { + if (proxy.name) { + return !moreDeleteProxies.includes(proxy.name); + } else { + return !moreDeleteProxies.includes(proxy); + } + }), + moreAppendProxies + ); + + setProxyPolicyList( + builtinProxyPolicies.concat( + prependSeq.map((group: IProxyGroupConfig) => group.name), + originGroupsObj?.["proxy-groups"] + .map((group: IProxyGroupConfig) => group.name) + .filter((name) => !deleteSeq.includes(name)) || [], + appendSeq.map((group: IProxyGroupConfig) => group.name), + proxies.map((proxy: any) => proxy.name) + ) + ); + }; + const fetchProfile = async () => { + let data = await readProfileFile(profileUid); + let mergeData = await readProfileFile(mergeUid); + let globalMergeData = await readProfileFile("Merge"); + + let originGroupsObj = yaml.load(data) as { + "proxy-groups": IProxyGroupConfig[]; + } | null; + + let originProviderObj = yaml.load(data) as { "proxy-providers": {} } | null; + let originProvider = originProviderObj?.["proxy-providers"] || {}; + + let moreProviderObj = yaml.load(mergeData) as { + "proxy-providers": {}; + } | null; + let moreProvider = moreProviderObj?.["proxy-providers"] || {}; + + let globalProviderObj = yaml.load(globalMergeData) as { + "proxy-providers": {}; + } | null; + let globalProvider = globalProviderObj?.["proxy-providers"] || {}; + + let provider = Object.assign( + {}, + originProvider, + moreProvider, + globalProvider + ); + + setProxyProviderList(Object.keys(provider)); + setGroupList(originGroupsObj?.["proxy-groups"] || []); + }; + useEffect(() => { + fetchProxyPolicy(); + }, [prependSeq, appendSeq, deleteSeq]); + useEffect(() => { + if (!open) return; + fetchContent(); + fetchProxyPolicy(); + fetchProfile(); + }, [open]); + + const validateGroup = () => { + let group = formIns.getValues(); + if (group.name === "") { + throw new Error(t("Group Name Cannot Be Empty")); + } + }; + + const handleSave = useLockFn(async () => { + try { + await saveProfileFile(property, currData); + onSave?.(prevData, currData); + onClose(); + } catch (err: any) { + Notice.error(err.message || err.toString()); + } + }); + + return ( + + + { + + {t("Edit Groups")} + + + + + } + + + + {visualization ? ( + <> + + + ( + + + value && field.onChange(value)} + renderInput={(params) => } + /> + + )} + /> + ( + + + + + )} + /> + ( + + + + + )} + /> + ( + + + value && field.onChange(value)} + renderInput={(params) => } + /> + + )} + /> + ( + + + value && field.onChange(value)} + renderInput={(params) => } + /> + + )} + /> + + ( + + + + + )} + /> + ( + + + { + field.onChange(parseInt(e.target.value)); + }} + /> + + )} + /> + ( + + + { + field.onChange(parseInt(e.target.value)); + }} + /> + + )} + /> + ( + + + { + field.onChange(parseInt(e.target.value)); + }} + /> + + )} + /> + ( + + + + + )} + /> + ( + + + { + field.onChange(parseInt(e.target.value)); + }} + /> + + )} + /> + ( + + + + + )} + /> + ( + + + + + )} + /> + ( + + + + + )} + /> + ( + + + { + field.onChange(parseInt(e.target.value)); + }} + /> + + )} + /> + ( + + + + + )} + /> + ( + + + + + )} + /> + ( + + + + + )} + /> + ( + + + + + )} + /> + ( + + + + + )} + /> + ( + + + + + )} + /> + + + + + + + + + + + setMatch(() => match)} + /> + 0 ? 1 : 0) + + (appendSeq.length > 0 ? 1 : 0) + } + increaseViewportBy={256} + itemContent={(index) => { + let shift = prependSeq.length > 0 ? 1 : 0; + if (prependSeq.length > 0 && index === 0) { + return ( + + { + return x.name; + })} + > + {prependSeq.map((item, index) => { + return ( + { + setPrependSeq( + prependSeq.filter( + (v) => v.name !== item.name + ) + ); + }} + /> + ); + })} + + + ); + } else if (index < filteredGroupList.length + shift) { + let newIndex = index - shift; + return ( + { + if ( + deleteSeq.includes(filteredGroupList[newIndex].name) + ) { + setDeleteSeq( + deleteSeq.filter( + (v) => v !== filteredGroupList[newIndex].name + ) + ); + } else { + setDeleteSeq((prev) => [ + ...prev, + filteredGroupList[newIndex].name, + ]); + } + }} + /> + ); + } else { + return ( + + { + return x.name; + })} + > + {appendSeq.map((item, index) => { + return ( + { + setAppendSeq( + appendSeq.filter( + (v) => v.name !== item.name + ) + ); + }} + /> + ); + })} + + + ); + } + }} + /> + + + ) : ( + = 1500, // 超过一定宽度显示minimap滚动条 + }, + mouseWheelZoom: true, // 按住Ctrl滚轮调节缩放比例 + quickSuggestions: { + strings: true, // 字符串类型的建议 + comments: true, // 注释类型的建议 + other: true, // 其他类型的建议 + }, + padding: { + top: 33, // 顶部padding防止遮挡snippets + }, + fontFamily: `Fira Code, JetBrains Mono, Roboto Mono, "Source Code Pro", Consolas, Menlo, Monaco, monospace, "Courier New", "Apple Color Emoji"${ + getSystem() === "windows" ? ", twemoji mozilla" : "" + }`, + fontLigatures: true, // 连字符 + smoothScrolling: true, // 平滑滚动 + }} + onChange={(value) => setCurrData(value)} + /> + )} + + + + + + + + + ); +}; + +const Item = styled(ListItem)(() => ({ + padding: "5px 2px", +})); diff --git a/clash-verge-rev/src/components/profile/profile-item.tsx b/clash-verge-rev/src/components/profile/profile-item.tsx index 88243adf8c..081f9d9b28 100644 --- a/clash-verge-rev/src/components/profile/profile-item.tsx +++ b/clash-verge-rev/src/components/profile/profile-item.tsx @@ -24,12 +24,14 @@ import { saveProfileFile, } from "@/services/cmds"; import { Notice } from "@/components/base"; +import { GroupsEditorViewer } from "@/components/profile/groups-editor-viewer"; import { RulesEditorViewer } from "@/components/profile/rules-editor-viewer"; import { EditorViewer } from "@/components/profile/editor-viewer"; import { ProfileBox } from "./profile-box"; import parseTraffic from "@/utils/parse-traffic"; import { ConfirmViewer } from "@/components/profile/confirm-viewer"; import { open } from "@tauri-apps/api/shell"; +import { ProxiesEditorViewer } from "./proxies-editor-viewer"; const round = keyframes` from { transform: rotate(0deg); } to { transform: rotate(360deg); } @@ -491,24 +493,20 @@ export const ProfileItem = (props: Props) => { onSave={onSave} onClose={() => setRulesOpen(false)} /> - { - await saveProfileFile(option?.proxies ?? "", curr ?? ""); - onSave && onSave(prev, curr); - }} + onSave={onSave} onClose={() => setProxiesOpen(false)} /> - { - await saveProfileFile(option?.groups ?? "", curr ?? ""); - onSave && onSave(prev, curr); - }} + onSave={onSave} onClose={() => setGroupsOpen(false)} /> void; + onSave?: (prev?: string, curr?: string) => void; +} + +const builtinProxyPolicies = ["DIRECT", "REJECT", "REJECT-DROP", "PASS"]; + +export const ProxiesEditorViewer = (props: Props) => { + const { profileUid, property, open, onClose, onSave } = props; + const { t } = useTranslation(); + const themeMode = useThemeMode(); + const [prevData, setPrevData] = useState(""); + const [currData, setCurrData] = useState(""); + const [visualization, setVisualization] = useState(true); + const [match, setMatch] = useState(() => (_: string) => true); + + const { control, watch, register, ...formIns } = useForm({ + defaultValues: { + type: "ss", + name: "", + }, + }); + + const [proxyList, setProxyList] = useState([]); + const [prependSeq, setPrependSeq] = useState([]); + const [appendSeq, setAppendSeq] = useState([]); + const [deleteSeq, setDeleteSeq] = useState([]); + + const filteredProxyList = useMemo( + () => proxyList.filter((proxy) => match(proxy.name)), + [proxyList, match] + ); + + const sensors = useSensors( + useSensor(PointerSensor), + useSensor(KeyboardSensor, { + coordinateGetter: sortableKeyboardCoordinates, + }) + ); + const reorder = ( + list: IProxyConfig[], + startIndex: number, + endIndex: number + ) => { + const result = Array.from(list); + const [removed] = result.splice(startIndex, 1); + result.splice(endIndex, 0, removed); + return result; + }; + const onPrependDragEnd = async (event: DragEndEvent) => { + const { active, over } = event; + if (over) { + if (active.id !== over.id) { + let activeIndex = 0; + let overIndex = 0; + prependSeq.forEach((item, index) => { + if (item.name === active.id) { + activeIndex = index; + } + if (item.name === over.id) { + overIndex = index; + } + }); + + setPrependSeq(reorder(prependSeq, activeIndex, overIndex)); + } + } + }; + const onAppendDragEnd = async (event: DragEndEvent) => { + const { active, over } = event; + if (over) { + if (active.id !== over.id) { + let activeIndex = 0; + let overIndex = 0; + appendSeq.forEach((item, index) => { + if (item.name === active.id) { + activeIndex = index; + } + if (item.name === over.id) { + overIndex = index; + } + }); + setAppendSeq(reorder(appendSeq, activeIndex, overIndex)); + } + } + }; + + const fetchProfile = async () => { + let data = await readProfileFile(profileUid); + + let originProxiesObj = yaml.load(data) as { + proxies: IProxyConfig[]; + } | null; + + setProxyList(originProxiesObj?.proxies || []); + }; + + const fetchContent = async () => { + let data = await readProfileFile(property); + let obj = yaml.load(data) as ISeqProfileConfig | null; + + setPrependSeq(obj?.prepend || []); + setAppendSeq(obj?.append || []); + setDeleteSeq(obj?.delete || []); + + setPrevData(data); + setCurrData(data); + }; + + useEffect(() => { + if (currData === "") return; + if (visualization !== true) return; + + let obj = yaml.load(currData) as { + prepend: []; + append: []; + delete: []; + } | null; + setPrependSeq(obj?.prepend || []); + setAppendSeq(obj?.append || []); + setDeleteSeq(obj?.delete || []); + }, [visualization]); + + useEffect(() => { + if (prependSeq && appendSeq && deleteSeq) + setCurrData( + yaml.dump( + { prepend: prependSeq, append: appendSeq, delete: deleteSeq }, + { + forceQuotes: true, + } + ) + ); + }, [prependSeq, appendSeq, deleteSeq]); + + useEffect(() => { + if (!open) return; + fetchContent(); + fetchProfile(); + }, [open]); + + const handleSave = useLockFn(async () => { + try { + await saveProfileFile(property, currData); + onSave?.(prevData, currData); + onClose(); + } catch (err: any) { + Notice.error(err.message || err.toString()); + } + }); + + return ( + + + { + + {t("Edit Proxies")} + + + + + } + + + + {visualization ? ( + <> + + + ( + + + value && field.onChange(value)} + renderInput={(params) => } + /> + + )} + /> + ( + + + + + )} + /> + ( + + + + + )} + /> + ( + + + { + field.onChange(parseInt(e.target.value)); + }} + /> + + )} + /> + + + + + + + + + + + setMatch(() => match)} + /> + 0 ? 1 : 0) + + (appendSeq.length > 0 ? 1 : 0) + } + increaseViewportBy={256} + itemContent={(index) => { + let shift = prependSeq.length > 0 ? 1 : 0; + if (prependSeq.length > 0 && index === 0) { + return ( + + { + return x.name; + })} + > + {prependSeq.map((item, index) => { + return ( + { + setPrependSeq( + prependSeq.filter( + (v) => v.name !== item.name + ) + ); + }} + /> + ); + })} + + + ); + } else if (index < filteredProxyList.length + shift) { + let newIndex = index - shift; + return ( + { + if ( + deleteSeq.includes(filteredProxyList[newIndex].name) + ) { + setDeleteSeq( + deleteSeq.filter( + (v) => v !== filteredProxyList[newIndex].name + ) + ); + } else { + setDeleteSeq((prev) => [ + ...prev, + filteredProxyList[newIndex].name, + ]); + } + }} + /> + ); + } else { + return ( + + { + return x.name; + })} + > + {appendSeq.map((item, index) => { + return ( + { + setAppendSeq( + appendSeq.filter( + (v) => v.name !== item.name + ) + ); + }} + /> + ); + })} + + + ); + } + }} + /> + + + ) : ( + = 1500, // 超过一定宽度显示minimap滚动条 + }, + mouseWheelZoom: true, // 按住Ctrl滚轮调节缩放比例 + quickSuggestions: { + strings: true, // 字符串类型的建议 + comments: true, // 注释类型的建议 + other: true, // 其他类型的建议 + }, + padding: { + top: 33, // 顶部padding防止遮挡snippets + }, + fontFamily: `Fira Code, JetBrains Mono, Roboto Mono, "Source Code Pro", Consolas, Menlo, Monaco, monospace, "Courier New", "Apple Color Emoji"${ + getSystem() === "windows" ? ", twemoji mozilla" : "" + }`, + fontLigatures: true, // 连字符 + smoothScrolling: true, // 平滑滚动 + }} + onChange={(value) => setCurrData(value)} + /> + )} + + + + + + + + + ); +}; + +const Item = styled(ListItem)(() => ({ + padding: "5px 2px", +})); diff --git a/clash-verge-rev/src/components/profile/proxy-item.tsx b/clash-verge-rev/src/components/profile/proxy-item.tsx new file mode 100644 index 0000000000..5de1028414 --- /dev/null +++ b/clash-verge-rev/src/components/profile/proxy-item.tsx @@ -0,0 +1,116 @@ +import { + Box, + IconButton, + ListItem, + ListItemText, + alpha, + styled, +} from "@mui/material"; +import { DeleteForeverRounded, UndoRounded } from "@mui/icons-material"; +import { useSortable } from "@dnd-kit/sortable"; +import { CSS } from "@dnd-kit/utilities"; + +interface Props { + type: "prepend" | "original" | "delete" | "append"; + proxy: IProxyConfig; + onDelete: () => void; +} + +export const ProxyItem = (props: Props) => { + let { type, proxy, onDelete } = props; + const sortable = type === "prepend" || type === "append"; + + const { attributes, listeners, setNodeRef, transform, transition } = sortable + ? useSortable({ id: proxy.name }) + : { + attributes: {}, + listeners: {}, + setNodeRef: null, + transform: null, + transition: null, + }; + + return ( + ({ + background: + type === "original" + ? palette.mode === "dark" + ? alpha(palette.background.paper, 0.3) + : alpha(palette.grey[400], 0.3) + : type === "delete" + ? alpha(palette.error.main, 0.3) + : alpha(palette.success.main, 0.3), + height: "100%", + margin: "8px 0", + borderRadius: "8px", + transform: CSS.Transform.toString(transform), + transition, + })} + > + + {proxy.name} + + } + secondary={ + + + {proxy.type} + + + } + secondaryTypographyProps={{ + sx: { + display: "flex", + alignItems: "center", + color: "#ccc", + }, + }} + /> + + {type === "delete" ? : } + + + ); +}; + +const StyledPrimary = styled("span")` + font-size: 15px; + font-weight: 700; + line-height: 1.5; + overflow: hidden; + text-overflow: ellipsis; + white-space: nowrap; +`; + +const ListItemTextChild = styled("span")` + display: block; +`; + +const StyledTypeBox = styled(ListItemTextChild)(({ theme }) => ({ + display: "inline-block", + border: "1px solid #ccc", + borderColor: alpha(theme.palette.primary.main, 0.5), + color: alpha(theme.palette.primary.main, 0.8), + borderRadius: 4, + fontSize: 10, + padding: "0 4px", + lineHeight: 1.5, + marginRight: "8px", +})); diff --git a/clash-verge-rev/src/components/profile/rule-item.tsx b/clash-verge-rev/src/components/profile/rule-item.tsx index 07a2fa2ab9..44e1478951 100644 --- a/clash-verge-rev/src/components/profile/rule-item.tsx +++ b/clash-verge-rev/src/components/profile/rule-item.tsx @@ -1,11 +1,10 @@ import { Box, - Divider, IconButton, ListItem, ListItemText, - Typography, alpha, + styled, } from "@mui/material"; import { DeleteForeverRounded, UndoRounded } from "@mui/icons-material"; import { useSortable } from "@dnd-kit/sortable"; @@ -31,17 +30,19 @@ export const RuleItem = (props: Props) => { }; return ( ({ - p: 0, - borderRadius: "10px", - border: "solid 2px", - borderColor: + background: type === "original" - ? "var(--divider-color)" + ? palette.mode === "dark" + ? alpha(palette.background.paper, 0.3) + : alpha(palette.grey[400], 0.3) : type === "delete" - ? alpha(palette.error.main, 0.5) - : alpha(palette.success.main, 0.5), - mb: 1, + ? alpha(palette.error.main, 0.3) + : alpha(palette.success.main, 0.3), + height: "100%", + margin: "8px 0", + borderRadius: "8px", transform: CSS.Transform.toString(transform), transition, })} @@ -50,34 +51,76 @@ export const RuleItem = (props: Props) => { {...attributes} {...listeners} ref={setNodeRef} - sx={{ px: 1 }} + sx={{ cursor: sortable ? "move" : "" }} primary={ - <> - - {rule.length === 3 ? rule[1] : "-"} - - + + {rule.length === 3 ? rule[1] : "-"} + } secondary={ - - {rule[0]} - {rule.length === 3 ? rule[2] : rule[1]} - + + + {rule[0]} + + + {rule.length === 3 ? rule[2] : rule[1]} + + } + secondaryTypographyProps={{ + sx: { + display: "flex", + alignItems: "center", + color: "#ccc", + }, + }} /> - - + {type === "delete" ? : } ); }; + +const StyledPrimary = styled("span")` + font-size: 15px; + font-weight: 700; + line-height: 1.5; + overflow: hidden; + text-overflow: ellipsis; + white-space: nowrap; +`; + +const StyledSubtitle = styled("span")` + font-size: 13px; + overflow: hidden; + color: text.secondary; + text-overflow: ellipsis; + white-space: nowrap; +`; + +const ListItemTextChild = styled("span")` + display: block; +`; + +const StyledTypeBox = styled(ListItemTextChild)(({ theme }) => ({ + display: "inline-block", + border: "1px solid #ccc", + borderColor: alpha(theme.palette.primary.main, 0.5), + color: alpha(theme.palette.primary.main, 0.8), + borderRadius: 4, + fontSize: 10, + padding: "0 4px", + lineHeight: 1.5, + marginRight: "8px", +})); diff --git a/clash-verge-rev/src/components/profile/rules-editor-viewer.tsx b/clash-verge-rev/src/components/profile/rules-editor-viewer.tsx index e0832ae72c..99e20db5dc 100644 --- a/clash-verge-rev/src/components/profile/rules-editor-viewer.tsx +++ b/clash-verge-rev/src/components/profile/rules-editor-viewer.tsx @@ -43,7 +43,6 @@ interface Props { groupsUid: string; mergeUid: string; profileUid: string; - title?: string | ReactNode; property: string; open: boolean; onClose: () => void; @@ -232,22 +231,14 @@ const rules: { const builtinProxyPolicies = ["DIRECT", "REJECT", "REJECT-DROP", "PASS"]; export const RulesEditorViewer = (props: Props) => { - const { - title, - groupsUid, - mergeUid, - profileUid, - property, - open, - onClose, - onSave, - } = props; + const { groupsUid, mergeUid, profileUid, property, open, onClose, onSave } = + props; const { t } = useTranslation(); const themeMode = useThemeMode(); const [prevData, setPrevData] = useState(""); const [currData, setCurrData] = useState(""); - const [visible, setVisible] = useState(true); + const [visualization, setVisualization] = useState(true); const [match, setMatch] = useState(() => (_: string) => true); const [ruleType, setRuleType] = useState<(typeof rules)[number]>(rules[0]); @@ -302,7 +293,7 @@ export const RulesEditorViewer = (props: Props) => { }; const fetchContent = async () => { let data = await readProfileFile(property); - let obj = yaml.load(data) as { prepend: []; append: []; delete: [] } | null; + let obj = yaml.load(data) as ISeqProfileConfig | null; setPrependSeq(obj?.prepend || []); setAppendSeq(obj?.append || []); @@ -314,38 +305,51 @@ export const RulesEditorViewer = (props: Props) => { useEffect(() => { if (currData === "") return; - if (visible !== true) return; + if (visualization !== true) return; - let obj = yaml.load(currData) as { - prepend: []; - append: []; - delete: []; - } | null; + let obj = yaml.load(currData) as ISeqProfileConfig | null; setPrependSeq(obj?.prepend || []); setAppendSeq(obj?.append || []); setDeleteSeq(obj?.delete || []); - }, [visible]); + }, [visualization]); useEffect(() => { if (prependSeq && appendSeq && deleteSeq) setCurrData( - yaml.dump({ prepend: prependSeq, append: appendSeq, delete: deleteSeq }) + yaml.dump( + { prepend: prependSeq, append: appendSeq, delete: deleteSeq }, + { + forceQuotes: true, + } + ) ); }, [prependSeq, appendSeq, deleteSeq]); const fetchProfile = async () => { - let data = await readProfileFile(profileUid); - let groupsData = await readProfileFile(groupsUid); - let mergeData = await readProfileFile(mergeUid); - let globalMergeData = await readProfileFile("Merge"); + let data = await readProfileFile(profileUid); // 原配置文件 + let groupsData = await readProfileFile(groupsUid); // groups配置文件 + let mergeData = await readProfileFile(mergeUid); // merge配置文件 + let globalMergeData = await readProfileFile("Merge"); // global merge配置文件 let rulesObj = yaml.load(data) as { rules: [] } | null; let originGroupsObj = yaml.load(data) as { "proxy-groups": [] } | null; let originGroups = originGroupsObj?.["proxy-groups"] || []; - let moreGroupsObj = yaml.load(groupsData) as { "proxy-groups": [] } | null; - let moreGroups = moreGroupsObj?.["proxy-groups"] || []; - let groups = originGroups.concat(moreGroups); + let moreGroupsObj = yaml.load(groupsData) as ISeqProfileConfig | null; + let morePrependGroups = moreGroupsObj?.["prepend"] || []; + let moreAppendGroups = moreGroupsObj?.["append"] || []; + let moreDeleteGroups = + moreGroupsObj?.["delete"] || ([] as string[] | { name: string }[]); + let groups = morePrependGroups.concat( + originGroups.filter((group: any) => { + if (group.name) { + return !moreDeleteGroups.includes(group.name); + } else { + return !moreDeleteGroups.includes(group); + } + }), + moreAppendGroups + ); let originRuleSetObj = yaml.load(data) as { "rule-providers": {} } | null; let originRuleSet = originRuleSetObj?.["rule-providers"] || {}; @@ -377,6 +381,7 @@ export const RulesEditorViewer = (props: Props) => { }; useEffect(() => { + if (!open) return; fetchContent(); fetchProfile(); }, [open]); @@ -416,10 +421,10 @@ export const RulesEditorViewer = (props: Props) => { variant="contained" size="small" onClick={() => { - setVisible((prev) => !prev); + setVisualization((prev) => !prev); }} > - {visible ? t("Advanced") : t("Visible")} + {visualization ? t("Advanced") : t("Visualization")} @@ -429,7 +434,7 @@ export const RulesEditorViewer = (props: Props) => { - {visible ? ( + {visualization ? ( <> ((props, ref) => { verge?.verge_redir_port ?? clashInfo?.redir_port ?? 7895 ); const [redirEnabled, setRedirEnabled] = useState( - verge?.verge_redir_enabled ?? true + verge?.verge_redir_enabled ?? false ); const [tproxyPort, setTproxyPort] = useState( verge?.verge_tproxy_port ?? clashInfo?.tproxy_port ?? 7896 ); const [tproxyEnabled, setTproxyEnabled] = useState( - verge?.verge_tproxy_enabled ?? true + verge?.verge_tproxy_enabled ?? false ); const [mixedPort, setMixedPort] = useState( verge?.verge_mixed_port ?? clashInfo?.mixed_port ?? 7897 @@ -34,26 +34,26 @@ export const ClashPortViewer = forwardRef((props, ref) => { verge?.verge_socks_port ?? clashInfo?.socks_port ?? 7898 ); const [socksEnabled, setSocksEnabled] = useState( - verge?.verge_socks_enabled ?? true + verge?.verge_socks_enabled ?? false ); const [port, setPort] = useState( verge?.verge_port ?? clashInfo?.port ?? 7899 ); const [httpEnabled, setHttpEnabled] = useState( - verge?.verge_http_enabled ?? true + verge?.verge_http_enabled ?? false ); useImperativeHandle(ref, () => ({ open: () => { if (verge?.verge_redir_port) setRedirPort(verge?.verge_redir_port); - setRedirEnabled(verge?.verge_redir_enabled ?? true); + setRedirEnabled(verge?.verge_redir_enabled ?? false); if (verge?.verge_tproxy_port) setTproxyPort(verge?.verge_tproxy_port); - setTproxyEnabled(verge?.verge_tproxy_enabled ?? true); + setTproxyEnabled(verge?.verge_tproxy_enabled ?? false); if (verge?.verge_mixed_port) setMixedPort(verge?.verge_mixed_port); if (verge?.verge_socks_port) setSocksPort(verge?.verge_socks_port); - setSocksEnabled(verge?.verge_socks_enabled ?? true); + setSocksEnabled(verge?.verge_socks_enabled ?? false); if (verge?.verge_port) setPort(verge?.verge_port); - setHttpEnabled(verge?.verge_http_enabled ?? true); + setHttpEnabled(verge?.verge_http_enabled ?? false); setOpen(true); }, close: () => setOpen(false), diff --git a/clash-verge-rev/src/locales/en.json b/clash-verge-rev/src/locales/en.json index 19aa913681..f03c4bf644 100644 --- a/clash-verge-rev/src/locales/en.json +++ b/clash-verge-rev/src/locales/en.json @@ -61,11 +61,12 @@ "No Resolve": "No Resolve", "Prepend Rule": "Prepend Rule", "Append Rule": "Append Rule", - "Delete Rule": "Delete Rule", + "Prepend Group": "Prepend Group", + "Append Group": "Append Group", "Rule Condition Required": "Rule Condition Required", "Invalid Rule": "Invalid Rule", "Advanced": "Advanced", - "Visible": "Visible", + "Visualization": "Visualization", "DOMAIN": "Matches the full domain name", "DOMAIN-SUFFIX": "Matches the domain suffix", "DOMAIN-KEYWORD": "Matches the domain keyword", @@ -104,6 +105,25 @@ "REJECT-DROP": "Discards requests", "PASS": "Skips this rule when matched", "Edit Groups": "Edit Proxy Groups", + "Group Type": "Group Type", + "Group Name": "Group Name", + "Use Proxies": "Use Proxies", + "Use Provider": "Use Provider", + "Health Check Url": "Health Check Url", + "Interval": "Interval", + "Lazy": "Lazy", + "Timeout": "Timeout", + "Max Failed Times": "Max Failed Times", + "Interface Name": "Interface Name", + "Routing Mark": "Routing Mark", + "Include All": "Include All Proxies and Providers", + "Include All Providers": "Include All Providers", + "Include All Proxies": "Include All Proxies", + "Exclude Filter": "Exclude Filter", + "Exclude Type": "Exclude Type", + "Expected Status": "Expected Status", + "Disable UDP": "Disable UDP", + "Hidden": "Hidden", "Extend Config": "Extend Config", "Extend Script": "Extend Script", "Global Merge": "Global Extend Config", diff --git a/clash-verge-rev/src/locales/fa.json b/clash-verge-rev/src/locales/fa.json index b5a80a0316..fa5328f0ac 100644 --- a/clash-verge-rev/src/locales/fa.json +++ b/clash-verge-rev/src/locales/fa.json @@ -61,9 +61,12 @@ "No Resolve": "بدون حل", "Prepend Rule": "اضافه کردن قانون به ابتدا", "Append Rule": "اضافه کردن قانون به انتها", - "Delete Rule": "حذف قانون", + "Prepend Group": "اضافه کردن گروه به ابتدا", + "Append Group": "اضافه کردن گروه به انتها", "Rule Condition Required": "شرط قانون الزامی است", "Invalid Rule": "قانون نامعتبر", + "Advanced": "پیشرفته", + "Visualization": "تجسم", "DOMAIN": "مطابقت با نام کامل دامنه", "DOMAIN-SUFFIX": "مطابقت با پسوند دامنه", "DOMAIN-KEYWORD": "مطابقت با کلمه کلیدی دامنه", @@ -102,6 +105,25 @@ "REJECT-DROP": "درخواست‌ها را نادیده می‌گیرد", "PASS": "این قانون را در صورت تطابق نادیده می‌گیرد", "Edit Groups": "ویرایش گروه‌های پروکسی", + "Group Type": "نوع گروه", + "Group Name": "نام گروه", + "Use Proxies": "استفاده از پروکسی‌ها", + "Use Provider": "استفاده از ارائه‌دهنده", + "Health Check Url": "آدرس بررسی سلامت", + "Interval": "فاصله زمانی", + "Lazy": "تنبل", + "Timeout": "زمان قطع", + "Max Failed Times": "حداکثر تعداد شکست‌ها", + "Interface Name": "نام رابط", + "Routing Mark": "علامت مسیریابی", + "Include All": "شامل همه پروکسی‌ها و ارائه‌دهنده‌ها", + "Include All Providers": "شامل همه ارائه‌دهنده‌ها", + "Include All Proxies": "شامل همه پروکسی‌ها", + "Exclude Filter": "فیلتر استثناء", + "Exclude Type": "نوع استثناء", + "Expected Status": "وضعیت مورد انتظار", + "Disable UDP": "غیرفعال کردن UDP", + "Hidden": "مخفی", "Extend Config": "توسعه پیکربندی", "Extend Script": "ادغام اسکریپت", "Global Merge": "تنظیمات گسترده‌ی سراسری", diff --git a/clash-verge-rev/src/locales/ru.json b/clash-verge-rev/src/locales/ru.json index 72ab09adb0..89b235f1bb 100644 --- a/clash-verge-rev/src/locales/ru.json +++ b/clash-verge-rev/src/locales/ru.json @@ -61,9 +61,12 @@ "No Resolve": "Без разрешения", "Prepend Rule": "Добавить правило в начало", "Append Rule": "Добавить правило в конец", - "Delete Rule": "Удалить правило", + "Prepend Group": "Добавить группу в начало", + "Append Group": "Добавить группу в конец", "Rule Condition Required": "Требуется условие правила", "Invalid Rule": "Недействительное правило", + "Advanced": "Дополнительно", + "Visualization": "Визуализация", "DOMAIN": "Соответствует полному доменному имени", "DOMAIN-SUFFIX": "Соответствует суффиксу домена", "DOMAIN-KEYWORD": "Соответствует ключевому слову домена", @@ -102,6 +105,25 @@ "REJECT-DROP": "Отклоняет запросы", "PASS": "Пропускает это правило при совпадении", "Edit Groups": "Редактировать группы прокси", + "Group Type": "Тип группы", + "Group Name": "Имя группы", + "Use Proxies": "Использовать прокси", + "Use Provider": "Использовать провайдера", + "Health Check Url": "URL проверки здоровья", + "Interval": "Интервал", + "Lazy": "Ленивый", + "Timeout": "Таймаут", + "Max Failed Times": "Максимальное количество неудач", + "Interface Name": "Имя интерфейса", + "Routing Mark": "Марка маршрутизации", + "Include All": "Включить все прокси и провайдеры", + "Include All Providers": "Включить всех провайдеров", + "Include All Proxies": "Включить все прокси", + "Exclude Filter": "Исключить фильтр", + "Exclude Type": "Тип исключения", + "Expected Status": "Ожидаемый статус", + "Disable UDP": "Отключить UDP", + "Hidden": "Скрытый", "Extend Config": "Изменить Merge.", "Extend Script": "Изменить Script", "Global Merge": "Глобальный расширенный Настройки", diff --git a/clash-verge-rev/src/locales/zh.json b/clash-verge-rev/src/locales/zh.json index 138a9e6700..fbff87a123 100644 --- a/clash-verge-rev/src/locales/zh.json +++ b/clash-verge-rev/src/locales/zh.json @@ -61,11 +61,12 @@ "No Resolve": "跳过DNS解析", "Prepend Rule": "添加前置规则", "Append Rule": "添加后置规则", - "Delete Rule": "删除规则", + "Prepend Group": "添加前置代理组", + "Append Group": "添加后置代理组", "Rule Condition Required": "规则条件缺失", "Invalid Rule": "无效规则", "Advanced": "高级", - "Visible": "可视化", + "Visualization": "可视化", "DOMAIN": "匹配完整域名", "DOMAIN-SUFFIX": "匹配域名后缀", "DOMAIN-KEYWORD": "匹配域名关键字", @@ -104,6 +105,25 @@ "REJECT-DROP": "抛弃请求", "PASS": "跳过此规则", "Edit Groups": "编辑代理组", + "Group Type": "代理组类型", + "Group Name": "代理组组名", + "Use Proxies": "引入代理", + "Use Provider": "引入代理集合", + "Health Check Url": "健康检查测试地址", + "Interval": "检查间隔", + "Lazy": "懒惰状态", + "Timeout": "超时时间", + "Max Failed Times": "最大失败次数", + "Interface Name": "出站接口", + "Routing Mark": "路由标记", + "Include All": "引入所有出站代理以及代理集合", + "Include All Providers": "引入所有代理集合", + "Include All Proxies": "引入所有出站代理", + "Exclude Filter": "排除节点", + "Exclude Type": "排除节点类型", + "Expected Status": "期望状态码", + "Disable UDP": "禁用UDP", + "Hidden": "隐藏该组", "Extend Config": "扩展配置", "Extend Script": "扩展脚本", "Global Merge": "全局扩展配置", diff --git a/clash-verge-rev/src/services/types.d.ts b/clash-verge-rev/src/services/types.d.ts index 35a3f3c5cf..b2b3815834 100644 --- a/clash-verge-rev/src/services/types.d.ts +++ b/clash-verge-rev/src/services/types.d.ts @@ -199,9 +199,62 @@ interface IVergeTestItem { } interface ISeqProfileConfig { - prepend: string[]; - append: string[]; - delete: string[]; + prepend: []; + append: []; + delete: []; +} + +interface IProxyGroupConfig { + name: string; + type: "select" | "url-test" | "fallback" | "load-balance" | "relay"; + proxies?: string[]; + use?: string[]; + url?: string; + interval?: number; + lazy?: boolean; + timeout?: number; + "max-failed-times"?: number; + "disable-udp"?: boolean; + "interface-name": string; + "routing-mark"?: number; + "include-all"?: boolean; + "include-all-proxies"?: boolean; + "include-all-providers"?: boolean; + filter?: string; + "exclude-filter"?: string; + "exclude-type"?: string; + "expected-status"?: number; + hidden?: boolean; + icon?: string; +} + +interface IProxyConfig { + name: string; + type: + | "ss" + | "ssr" + | "direct" + | "dns" + | "snell" + | "http" + | "trojan" + | "hysteria" + | "hysteria2" + | "tuic" + | "wireguard" + | "ssh" + | "socks5" + | "vmess" + | "vless"; + server: string; + port: number; + "ip-version"?: string; + udp?: boolean; + "interface-name"?: string; + "routing-mark"?: number; + tfo?: boolean; + mptcp?: boolean; + "dialer-proxy"?: string; } interface IVergeConfig { diff --git a/echo/go.mod b/echo/go.mod index 2eb651406f..0f772ecace 100644 --- a/echo/go.mod +++ b/echo/go.mod @@ -10,10 +10,11 @@ require ( github.com/go-ping/ping v1.1.0 github.com/gobwas/ws v1.4.0 github.com/hashicorp/go-retryablehttp v0.7.7 + github.com/juju/ratelimit v1.0.2 github.com/labstack/echo/v4 v4.12.0 github.com/prometheus/client_golang v1.19.1 github.com/prometheus/client_model v0.6.1 - github.com/prometheus/common v0.54.0 + github.com/prometheus/common v0.55.0 github.com/prometheus/node_exporter v1.8.1 github.com/sagernet/sing v0.4.1 github.com/sagernet/sing-box v1.9.3 @@ -24,7 +25,7 @@ require ( go.uber.org/atomic v1.11.0 go.uber.org/zap v1.27.0 golang.org/x/time v0.5.0 - google.golang.org/grpc v1.64.0 + google.golang.org/grpc v1.65.0 gopkg.in/yaml.v3 v3.0.1 ) @@ -65,7 +66,6 @@ require ( github.com/illumos/go-kstat v0.0.0-20210513183136-173c9b0a9973 // indirect github.com/josharian/native v1.1.0 // indirect github.com/jsimonetti/rtnetlink v1.4.2 // indirect - github.com/juju/ratelimit v1.0.2 // indirect github.com/klauspost/compress v1.17.8 // indirect github.com/klauspost/cpuid/v2 v2.2.7 // indirect github.com/labstack/gommon v0.4.2 // indirect @@ -80,6 +80,7 @@ require ( github.com/mdlayher/socket v0.5.1 // indirect github.com/mdlayher/wifi v0.2.0 // indirect github.com/miekg/dns v1.1.61 // indirect + github.com/munnerz/goautoneg v0.0.0-20191010083416-a7dc8b61c822 // indirect github.com/onsi/ginkgo/v2 v2.19.0 // indirect github.com/opencontainers/selinux v1.11.0 // indirect github.com/oschwald/maxminddb-golang v1.12.0 // indirect @@ -87,7 +88,7 @@ require ( github.com/pires/go-proxyproto v0.7.0 // indirect github.com/pmezard/go-difflib v1.0.0 // indirect github.com/prometheus-community/go-runit v0.1.0 // indirect - github.com/prometheus/procfs v0.15.0 // indirect + github.com/prometheus/procfs v0.15.1 // indirect github.com/quic-go/quic-go v0.45.0 // indirect github.com/refraction-networking/utls v1.6.6 // indirect github.com/riobard/go-bloom v0.0.0-20200614022211-cdc8013cb5b3 // indirect diff --git a/echo/go.sum b/echo/go.sum index 179110cdbf..ff02e1d5e7 100644 --- a/echo/go.sum +++ b/echo/go.sum @@ -188,6 +188,8 @@ github.com/miekg/dns v1.1.61 h1:nLxbwF3XxhwVSm8g9Dghm9MHPaUZuqhPiGL+675ZmEs= github.com/miekg/dns v1.1.61/go.mod h1:mnAarhS3nWaW+NVP2wTkYVIZyHNJ098SJZUki3eykwQ= github.com/modern-go/concurrent v0.0.0-20180306012644-bacd9c7ef1dd/go.mod h1:6dJC0mAP4ikYIbvyc7fijjWJddQyLn8Ig3JB5CqoB9Q= github.com/modern-go/reflect2 v1.0.1/go.mod h1:bx2lNnkwVCuqBIxFjflWJWanXIb3RllmbCylyMrvgv0= +github.com/munnerz/goautoneg v0.0.0-20191010083416-a7dc8b61c822 h1:C3w9PqII01/Oq1c1nUAm88MOHcQC9l5mIlSMApZMrHA= +github.com/munnerz/goautoneg v0.0.0-20191010083416-a7dc8b61c822/go.mod h1:+n7T8mK8HuQTcFwEeznm/DIxMOiR9yIdICNftLE1DvQ= github.com/neelance/astrewrite v0.0.0-20160511093645-99348263ae86/go.mod h1:kHJEU3ofeGjhHklVoIGuVj85JJwZ6kWPaJwCIxgnFmo= github.com/neelance/sourcemap v0.0.0-20151028013722-8c68805598ab/go.mod h1:Qr6/a/Q4r9LP1IltGz7tA7iOK1WonHEYhu1HRBA7ZiM= github.com/onsi/ginkgo/v2 v2.19.0 h1:9Cnnf7UHo57Hy3k6/m5k3dRfGTMXGvxhHFvkDTCTpvA= @@ -219,13 +221,13 @@ github.com/prometheus/client_model v0.0.0-20180712105110-5c3871d89910/go.mod h1: github.com/prometheus/client_model v0.6.1 h1:ZKSh/rekM+n3CeS952MLRAdFwIKqeY8b62p8ais2e9E= github.com/prometheus/client_model v0.6.1/go.mod h1:OrxVMOVHjw3lKMa8+x6HeMGkHMQyHDk9E3jmP2AmGiY= github.com/prometheus/common v0.0.0-20180801064454-c7de2306084e/go.mod h1:daVV7qP5qjZbuso7PdcryaAu0sAZbrN9i7WWcTMWvro= -github.com/prometheus/common v0.54.0 h1:ZlZy0BgJhTwVZUn7dLOkwCZHUkrAqd3WYtcFCWnM1D8= -github.com/prometheus/common v0.54.0/go.mod h1:/TQgMJP5CuVYveyT7n/0Ix8yLNNXy9yRSkhnLTHPDIQ= +github.com/prometheus/common v0.55.0 h1:KEi6DK7lXW/m7Ig5i47x0vRzuBsHuvJdi5ee6Y3G1dc= +github.com/prometheus/common v0.55.0/go.mod h1:2SECS4xJG1kd8XF9IcM1gMX6510RAEL65zxzNImwdc8= github.com/prometheus/node_exporter v1.8.1 h1:qYIN+ghn7kEggHe4pcIRp9oXkljU8ARWyEHBr286RPY= github.com/prometheus/node_exporter v1.8.1/go.mod h1:rJMoAQMglUjAZ7nggHnRuwfJ0hKUVW6+Gv+IaMxh6js= github.com/prometheus/procfs v0.0.0-20180725123919-05ee40e3a273/go.mod h1:c3At6R/oaqEKCNdg8wHV1ftS6bRYblBhIjjI8uT2IGk= -github.com/prometheus/procfs v0.15.0 h1:A82kmvXJq2jTu5YUhSGNlYoxh85zLnKgPz4bMZgI5Ek= -github.com/prometheus/procfs v0.15.0/go.mod h1:Y0RJ/Y5g5wJpkTisOtqwDSo4HwhGmLB4VQSw2sQJLHk= +github.com/prometheus/procfs v0.15.1 h1:YagwOFzUgYfKKHX6Dr+sHT7km/hxC76UB0learggepc= +github.com/prometheus/procfs v0.15.1/go.mod h1:fB45yRUv8NstnjriLhBQLuOUt+WW4BsoGhij/e3PBqk= github.com/quic-go/qpack v0.4.0 h1:Cr9BXA1sQS2SmDUWjSofMPNKmvF6IiIfDRmgU0w1ZCo= github.com/quic-go/qpack v0.4.0/go.mod h1:UZVnYIfi5GRk+zI9UMaCPsmZ2xKJP7XBUvVyT1Knj9A= github.com/quic-go/qtls-go1-20 v0.4.1 h1:D33340mCNDAIKBqXuAvexTNMUByrYmFYVfKfDN5nfFs= @@ -429,8 +431,8 @@ google.golang.org/grpc v1.14.0/go.mod h1:yo6s7OP7yaDglbqo1J04qKzAhqBH6lvTonzMVmE google.golang.org/grpc v1.16.0/go.mod h1:0JHn/cJsOMiMfNA9+DeHDlAU7KAAB5GDlYFpa9MZMio= google.golang.org/grpc v1.17.0/go.mod h1:6QZJwpn2B+Zp71q/5VxRsJ6NXXVCE5NRUHRo+f3cWCs= google.golang.org/grpc v1.19.0/go.mod h1:mqu4LbDTu4XGKhr4mRzUsmM4RtVoemTSY81AxZiDr8c= -google.golang.org/grpc v1.64.0 h1:KH3VH9y/MgNQg1dE7b3XfVK0GsPSIzJwdF617gUSbvY= -google.golang.org/grpc v1.64.0/go.mod h1:oxjF8E3FBnjp+/gVFYdWacaLDx9na1aqy9oovLpxQYg= +google.golang.org/grpc v1.65.0 h1:bs/cUb4lp1G5iImFFd3u5ixQzweKizoZJAwBNLR42lc= +google.golang.org/grpc v1.65.0/go.mod h1:WgYC2ypjlB0EiQi6wdKixMqukr6lBc0Vo+oOgjrM5ZQ= google.golang.org/protobuf v1.34.2 h1:6xV6lTsCfpGD21XK49h7MhtcApnLqkfYgPcdHftf6hg= google.golang.org/protobuf v1.34.2/go.mod h1:qYOHts0dSfpeUzUFpOMr/WGzszTmLH+DiWniOlNbLDw= gopkg.in/check.v1 v0.0.0-20161208181325-20d25e280405/go.mod h1:Co6ibVJAznAaIkqp8huTwlJQCZ016jof/cbN4VW5Yz0= diff --git a/geoip/README.md b/geoip/README.md index 23505cf55e..5c993e5e74 100644 --- a/geoip/README.md +++ b/geoip/README.md @@ -194,6 +194,7 @@ These two concepts are notable: `input` and `output`. The `input` is the data so 支持的 `input` 输入格式： - **text**：纯文本 IP 和 CIDR（例如：`1.1.1.1` 或 `1.0.0.0/24`） +- **stdin**：从 standard input 获取纯文本 IP 和 CIDR（例如：`1.1.1.1` 或 `1.0.0.0/24`） - **private**：局域网和私有网络 CIDR（例如：`192.168.0.0/16` 和 `127.0.0.0/8`） - **cutter**：用于裁剪前置步骤中的数据 - **v2rayGeoIPDat**：V2Ray GeoIP dat 格式（`geoip.dat`） @@ -207,6 +208,7 @@ These two concepts are notable: `input` and `output`. The `input` is the data so 支持的 `output` 输出格式： - **text**：纯文本 CIDR（例如：`1.0.0.0/24`） +- **stdout**：将纯文本 CIDR 输出到 standard output（例如：`1.0.0.0/24`） - **v2rayGeoIPDat**：V2Ray GeoIP dat 格式（`geoip.dat`，适用于 [V2Ray](https://github.com/v2fly/v2ray-core)、[Xray-core](https://github.com/XTLS/Xray-core) 和 [Trojan-Go](https://github.com/p4gefau1t/trojan-go)） - **maxmindMMDB**：MaxMind mmdb 数据格式（`GeoLite2-Country.mmdb`，适用于 [Clash](https://github.com/Dreamacro/clash) 和 [Leaf](https://github.com/eycorsican/leaf)） - **singboxSRS**：sing-box SRS 格式（`geoip-cn.srs`，适用于 [sing-box](https://github.com/SagerNet/sing-box)） @@ -261,6 +263,7 @@ All available input formats: - maxmindGeoLite2CountryCSV (Convert MaxMind GeoLite2 country CSV data to other formats) - singboxSRS (Convert sing-box SRS data to other formats) - private (Convert LAN and private network CIDR to other formats) + - stdin (Accept plaintext IP & CIDR from standard input, separated by newline) - text (Convert plaintext IP & CIDR to other formats) - clashRuleSetClassical (Convert classical type of Clash RuleSet to other formats (just processing IP & CIDR lines)) - clashRuleSet (Convert ipcidr type of Clash RuleSet to other formats) @@ -275,6 +278,7 @@ All available output formats: - clashRuleSet (Convert data to ipcidr type of Clash RuleSet) - surgeRuleSet (Convert data to Surge RuleSet) - text (Convert data to plaintext CIDR format) + - stdout (Convert data to plaintext CIDR format and output to standard output) ``` ## License diff --git a/geoip/config-example.json b/geoip/config-example.json index 4986e4596e..253d174607 100644 --- a/geoip/config-example.json +++ b/geoip/config-example.json @@ -122,6 +122,29 @@ "onlyIPType": "ipv4" } }, + { + "type": "stdin", + "action": "add", + "args": { + "name": "cn" + } + }, + { + "type": "stdin", + "action": "add", + "args": { + "name": "cn", + "onlyIPType": "ipv4" + } + }, + { + "type": "stdin", + "action": "remove", + "args": { + "name": "cn", + "onlyIPType": "ipv6" + } + }, { "type": "private", "action": "add" @@ -220,6 +243,32 @@ "onlyIPType": "ipv6" } }, + { + "type": "stdout", + "action": "output" + }, + { + "type": "stdout", + "action": "output", + "args": { + "wantedList": ["cn", "us", "private"] + } + }, + { + "type": "stdout", + "action": "output", + "args": { + "onlyIPType": "ipv6" + } + }, + { + "type": "stdout", + "action": "output", + "args": { + "wantedList": ["cn", "us", "private"], + "onlyIPType": "ipv6" + } + }, { "type": "clashRuleSetClassical", "action": "output", diff --git a/geoip/lib/func.go b/geoip/lib/func.go index 68a3e25542..c1ce55919f 100644 --- a/geoip/lib/func.go +++ b/geoip/lib/func.go @@ -4,6 +4,7 @@ import ( "fmt" "io" "net/http" + "sort" "strings" ) @@ -14,8 +15,13 @@ var ( func ListInputConverter() { fmt.Println("All available input formats:") - for name, ic := range inputConverterMap { - fmt.Printf(" - %s (%s)\n", name, ic.GetDescription()) + keys := make([]string, 0, len(inputConverterMap)) + for name := range inputConverterMap { + keys = append(keys, name) + } + sort.Strings(keys) + for _, name := range keys { + fmt.Printf(" - %s (%s)\n", name, inputConverterMap[name].GetDescription()) } } @@ -30,8 +36,13 @@ func RegisterInputConverter(name string, c InputConverter) error { func ListOutputConverter() { fmt.Println("All available output formats:") - for name, oc := range outputConverterMap { - fmt.Printf(" - %s (%s)\n", name, oc.GetDescription()) + keys := make([]string, 0, len(outputConverterMap)) + for name := range outputConverterMap { + keys = append(keys, name) + } + sort.Strings(keys) + for _, name := range keys { + fmt.Printf(" - %s (%s)\n", name, outputConverterMap[name].GetDescription()) } } diff --git a/geoip/plugin/maxmind/mmdb_in.go b/geoip/plugin/maxmind/mmdb_in.go index e451e6dc24..eef4c7d68a 100644 --- a/geoip/plugin/maxmind/mmdb_in.go +++ b/geoip/plugin/maxmind/mmdb_in.go @@ -85,7 +85,7 @@ func (g *maxmindMMDBIn) Input(container lib.Container) (lib.Container, error) { var fd io.ReadCloser var err error switch { - case strings.HasPrefix(g.URI, "http://"), strings.HasPrefix(g.URI, "https://"): + case strings.HasPrefix(strings.ToLower(g.URI), "http://"), strings.HasPrefix(strings.ToLower(g.URI), "https://"): fd, err = g.downloadFile(g.URI) default: fd, err = os.Open(g.URI) diff --git a/geoip/plugin/plaintext/text_in.go b/geoip/plugin/plaintext/text_in.go index add60a9674..246a4ac10f 100644 --- a/geoip/plugin/plaintext/text_in.go +++ b/geoip/plugin/plaintext/text_in.go @@ -84,7 +84,7 @@ func (t *textIn) Input(container lib.Container) (lib.Container, error) { err = t.walkDir(t.InputDir, entries) case t.Name != "" && t.URI != "": switch { - case strings.HasPrefix(t.URI, "http://"), strings.HasPrefix(t.URI, "https://"): + case strings.HasPrefix(strings.ToLower(t.URI), "http://"), strings.HasPrefix(strings.ToLower(t.URI), "https://"): err = t.walkRemoteFile(t.URI, t.Name, entries) default: err = t.walkLocalFile(t.URI, t.Name, entries) diff --git a/geoip/plugin/singbox/srs_in.go b/geoip/plugin/singbox/srs_in.go index f54c2d44a3..343fd4ca66 100644 --- a/geoip/plugin/singbox/srs_in.go +++ b/geoip/plugin/singbox/srs_in.go @@ -92,7 +92,7 @@ func (s *srsIn) Input(container lib.Container) (lib.Container, error) { err = s.walkDir(s.InputDir, entries) case s.Name != "" && s.URI != "": switch { - case strings.HasPrefix(s.URI, "http://"), strings.HasPrefix(s.URI, "https://"): + case strings.HasPrefix(strings.ToLower(s.URI), "http://"), strings.HasPrefix(strings.ToLower(s.URI), "https://"): err = s.walkRemoteFile(s.URI, s.Name, entries) default: err = s.walkLocalFile(s.URI, s.Name, entries) diff --git a/geoip/plugin/special/stdin.go b/geoip/plugin/special/stdin.go new file mode 100644 index 0000000000..1f59c1fea6 --- /dev/null +++ b/geoip/plugin/special/stdin.go @@ -0,0 +1,113 @@ +package special + +import ( + "bufio" + "encoding/json" + "os" + "strings" + + "github.com/Loyalsoldier/geoip/lib" +) + +const ( + typeStdin = "stdin" + descStdin = "Accept plaintext IP & CIDR from standard input, separated by newline" +) + +func init() { + lib.RegisterInputConfigCreator(typeStdin, func(action lib.Action, data json.RawMessage) (lib.InputConverter, error) { + return newStdin(action, data) + }) + lib.RegisterInputConverter(typeStdin, &stdin{ + Description: descStdin, + }) +} + +func newStdin(action lib.Action, data json.RawMessage) (lib.InputConverter, error) { + var tmp struct { + Name string `json:"name"` + OnlyIPType lib.IPType `json:"onlyIPType"` + } + + if len(data) > 0 { + if err := json.Unmarshal(data, &tmp); err != nil { + return nil, err + } + } + + return &stdin{ + Type: typeStdin, + Action: action, + Description: descStdin, + Name: tmp.Name, + OnlyIPType: tmp.OnlyIPType, + }, nil +} + +type stdin struct { + Type string + Action lib.Action + Description string + Name string + OnlyIPType lib.IPType +} + +func (s *stdin) GetType() string { + return s.Type +} + +func (s *stdin) GetAction() lib.Action { + return s.Action +} + +func (s *stdin) GetDescription() string { + return s.Description +} + +func (s *stdin) Input(container lib.Container) (lib.Container, error) { + entry := lib.NewEntry(s.Name) + + scanner := bufio.NewScanner(os.Stdin) + for scanner.Scan() { + line := strings.TrimSpace(scanner.Text()) + if line == "" { + continue + } + line, _, _ = strings.Cut(line, "#") + line, _, _ = strings.Cut(line, "//") + line, _, _ = strings.Cut(line, "/*") + line = strings.TrimSpace(line) + if line == "" { + continue + } + + switch s.Action { + case lib.ActionAdd: + if err := entry.AddPrefix(line); err != nil { + continue + } + case lib.ActionRemove: + if err := entry.RemovePrefix(line); err != nil { + continue + } + } + } + + if err := scanner.Err(); err != nil { + return nil, err + } + + var ignoreIPType lib.IgnoreIPOption + switch s.OnlyIPType { + case lib.IPv4: + ignoreIPType = lib.IgnoreIPv6 + case lib.IPv6: + ignoreIPType = lib.IgnoreIPv4 + } + + if err := container.Add(entry, ignoreIPType); err != nil { + return nil, err + } + + return container, nil +} diff --git a/geoip/plugin/special/stdout.go b/geoip/plugin/special/stdout.go new file mode 100644 index 0000000000..736d642f48 --- /dev/null +++ b/geoip/plugin/special/stdout.go @@ -0,0 +1,128 @@ +package special + +import ( + "encoding/json" + "errors" + "io" + "os" + "strings" + + "github.com/Loyalsoldier/geoip/lib" +) + +const ( + typeStdout = "stdout" + descStdout = "Convert data to plaintext CIDR format and output to standard output" +) + +func init() { + lib.RegisterOutputConfigCreator(typeStdout, func(action lib.Action, data json.RawMessage) (lib.OutputConverter, error) { + return newStdout(action, data) + }) + lib.RegisterOutputConverter(typeStdout, &stdout{ + Description: descStdout, + }) +} + +func newStdout(action lib.Action, data json.RawMessage) (lib.OutputConverter, error) { + var tmp struct { + Want []string `json:"wantedList"` + OnlyIPType lib.IPType `json:"onlyIPType"` + } + + if len(data) > 0 { + if err := json.Unmarshal(data, &tmp); err != nil { + return nil, err + } + } + + return &stdout{ + Type: typeStdout, + Action: action, + Description: descStdout, + Want: tmp.Want, + OnlyIPType: tmp.OnlyIPType, + }, nil +} + +type stdout struct { + Type string + Action lib.Action + Description string + Want []string + OnlyIPType lib.IPType +} + +func (s *stdout) GetType() string { + return s.Type +} + +func (s *stdout) GetAction() lib.Action { + return s.Action +} + +func (s *stdout) GetDescription() string { + return s.Description +} + +func (s *stdout) Output(container lib.Container) error { + // Filter want list + wantList := make(map[string]bool) + for _, want := range s.Want { + if want = strings.ToUpper(strings.TrimSpace(want)); want != "" { + wantList[want] = true + } + } + + switch len(wantList) { + case 0: + for entry := range container.Loop() { + cidrList, err := s.generateCIDRList(entry) + if err != nil { + continue + } + for _, cidr := range cidrList { + io.WriteString(os.Stdout, cidr+"\n") + } + } + default: + for name := range wantList { + entry, found := container.GetEntry(name) + if !found { + continue + } + + cidrList, err := s.generateCIDRList(entry) + if err != nil { + continue + } + for _, cidr := range cidrList { + io.WriteString(os.Stdout, cidr+"\n") + } + } + } + + return nil +} + +func (s *stdout) generateCIDRList(entry *lib.Entry) ([]string, error) { + var entryList []string + var err error + switch s.OnlyIPType { + case lib.IPv4: + entryList, err = entry.MarshalText(lib.IgnoreIPv6) + case lib.IPv6: + entryList, err = entry.MarshalText(lib.IgnoreIPv4) + default: + entryList, err = entry.MarshalText() + } + if err != nil { + return nil, err + } + + if len(entryList) == 0 { + return nil, errors.New("empty CIDR list") + } + + return entryList, nil +} diff --git a/geoip/plugin/v2ray/dat_in.go b/geoip/plugin/v2ray/dat_in.go index 8f65c6e4ec..65b9a67456 100644 --- a/geoip/plugin/v2ray/dat_in.go +++ b/geoip/plugin/v2ray/dat_in.go @@ -81,7 +81,7 @@ func (g *geoIPDatIn) Input(container lib.Container) (lib.Container, error) { var err error switch { - case strings.HasPrefix(g.URI, "http://"), strings.HasPrefix(g.URI, "https://"): + case strings.HasPrefix(strings.ToLower(g.URI), "http://"), strings.HasPrefix(strings.ToLower(g.URI), "https://"): err = g.walkRemoteFile(g.URI, entries) default: err = g.walkLocalFile(g.URI, entries) diff --git a/lede/package/kernel/mt76/Makefile b/lede/package/kernel/mt76/Makefile index 1268710349..a4fa0bdea6 100644 --- a/lede/package/kernel/mt76/Makefile +++ b/lede/package/kernel/mt76/Makefile @@ -15,9 +15,9 @@ PKG_SOURCE_VERSION:=5b509e80384ab019ac11aa90c81ec0dbb5b0d7f2 PKG_MIRROR_HASH:=6fc25df4d28becd010ff4971b23731c08b53e69381a9e4c868091899712f78a9 PATCH_DIR:=./patches-5.4 else ifndef ($(filter on,$(CONFIG_LINUX_6_1) $(CONFIG_LINUX_6_6)),) -PKG_SOURCE_DATE:=2024-04-19 -PKG_SOURCE_VERSION:=1d0bd57e58899d9c526c7c25cbaa04dc4a0559bf -PKG_MIRROR_HASH:=09e2256ca6efcc8375f96722f0aabe539b83e35fc93d4fec44b71a0efe3f7914 +PKG_SOURCE_DATE:=2024-05-17 +PKG_SOURCE_VERSION:=513c131c6309712a51502870b041f45b4bd6a6d4 +PKG_MIRROR_HASH:=9f5d7a846912e7deafa216c2aabb038ec58666ecbf8a394e947b144001994d78 PATCH_DIR:=./patches-6.x else PKG_SOURCE_DATE:=2023-08-14 diff --git a/lede/package/kernel/mt76/patches-6.x/002-Revert-wifi-mt76-mt7925-add-EHT-radiotap-support.patch b/lede/package/kernel/mt76/patches-6.x/002-Revert-wifi-mt76-mt7925-add-EHT-radiotap-support.patch new file mode 100644 index 0000000000..0e0552027d --- /dev/null +++ b/lede/package/kernel/mt76/patches-6.x/002-Revert-wifi-mt76-mt7925-add-EHT-radiotap-support.patch @@ -0,0 +1,195 @@ +From aa868357891cf4be8e7a1ca43edd1e335aa10710 Mon Sep 17 00:00:00 2001 +From: coolsnowwolf +Date: Thu, 4 Jul 2024 13:24:22 +0800 +Subject: [PATCH] Revert "wifi: mt76: mt7925: add EHT radiotap support in + monitor mode" + +This reverts commit 1d6e4f7de8a6c93540bd8d616cb6b917d2ac400e. +--- + mt76_connac.h | 2 -- + mt76_connac3_mac.c | 85 ---------------------------------------------- + mt76_connac3_mac.h | 22 ------------ + mt7925/mac.c | 15 ++------ + 4 files changed, 2 insertions(+), 122 deletions(-) + +diff --git a/mt76_connac.h b/mt76_connac.h +index 445d0f0a..91987bdf 100644 +--- a/mt76_connac.h ++++ b/mt76_connac.h +@@ -451,6 +451,4 @@ void mt76_connac2_tx_token_put(struct mt76_dev *dev); + /* connac3 */ + void mt76_connac3_mac_decode_he_radiotap(struct sk_buff *skb, __le32 *rxv, + u8 mode); +-void mt76_connac3_mac_decode_eht_radiotap(struct sk_buff *skb, __le32 *rxv, +- u8 mode); + #endif /* __MT76_CONNAC_H */ +diff --git a/mt76_connac3_mac.c b/mt76_connac3_mac.c +index 92ad1ecf..73e9f283 100644 +--- a/mt76_connac3_mac.c ++++ b/mt76_connac3_mac.c +@@ -6,11 +6,8 @@ + #include "dma.h" + + #define HE_BITS(f) cpu_to_le16(IEEE80211_RADIOTAP_HE_##f) +-#define EHT_BITS(f) cpu_to_le32(IEEE80211_RADIOTAP_EHT_##f) + #define HE_PREP(f, m, v) le16_encode_bits(le32_get_bits(v, MT_CRXV_HE_##m),\ + IEEE80211_RADIOTAP_HE_##f) +-#define EHT_PREP(f, m, v) le32_encode_bits(le32_get_bits(v, MT_CRXV_EHT_##m),\ +- IEEE80211_RADIOTAP_EHT_##f) + + static void + mt76_connac3_mac_decode_he_radiotap_ru(struct mt76_rx_status *status, +@@ -183,85 +180,3 @@ void mt76_connac3_mac_decode_he_radiotap(struct sk_buff *skb, __le32 *rxv, + } + } + EXPORT_SYMBOL_GPL(mt76_connac3_mac_decode_he_radiotap); +- +-static void * +-mt76_connac3_mac_radiotap_push_tlv(struct sk_buff *skb, u16 type, u16 len) +-{ +- struct ieee80211_radiotap_tlv *tlv; +- +- tlv = skb_push(skb, sizeof(*tlv) + len); +- tlv->type = cpu_to_le16(type); +- tlv->len = cpu_to_le16(len); +- memset(tlv->data, 0, len); +- +- return tlv->data; +-} +- +-void mt76_connac3_mac_decode_eht_radiotap(struct sk_buff *skb, __le32 *rxv, +- u8 mode) +-{ +- struct mt76_rx_status *status = (struct mt76_rx_status *)skb->cb; +- struct ieee80211_radiotap_eht_usig *usig; +- struct ieee80211_radiotap_eht *eht; +- u32 ltf_size = le32_get_bits(rxv[4], MT_CRXV_HE_LTF_SIZE) + 1; +- u8 bw = FIELD_GET(MT_PRXV_FRAME_MODE, le32_to_cpu(rxv[2])); +- +- if (WARN_ONCE(skb_mac_header(skb) != skb->data, +- "Should push tlv at the top of mac hdr")) +- return; +- +- eht = mt76_connac3_mac_radiotap_push_tlv(skb, IEEE80211_RADIOTAP_EHT, +- sizeof(*eht) + sizeof(u32)); +- usig = mt76_connac3_mac_radiotap_push_tlv(skb, IEEE80211_RADIOTAP_EHT_USIG, +- sizeof(*usig)); +- +- status->flag |= RX_FLAG_RADIOTAP_TLV_AT_END; +- +- eht->known |= EHT_BITS(KNOWN_SPATIAL_REUSE) | +- EHT_BITS(KNOWN_GI) | +- EHT_BITS(KNOWN_EHT_LTF) | +- EHT_BITS(KNOWN_LDPC_EXTRA_SYM_OM) | +- EHT_BITS(KNOWN_PE_DISAMBIGUITY_OM) | +- EHT_BITS(KNOWN_NSS_S); +- +- eht->data[0] |= +- EHT_PREP(DATA0_SPATIAL_REUSE, SR_MASK, rxv[13]) | +- cpu_to_le32(FIELD_PREP(IEEE80211_RADIOTAP_EHT_DATA0_GI, status->eht.gi) | +- FIELD_PREP(IEEE80211_RADIOTAP_EHT_DATA0_LTF, ltf_size)) | +- EHT_PREP(DATA0_PE_DISAMBIGUITY_OM, PE_DISAMBIG, rxv[5]) | +- EHT_PREP(DATA0_LDPC_EXTRA_SYM_OM, LDPC_EXT_SYM, rxv[4]); +- +- eht->data[7] |= le32_encode_bits(status->nss, IEEE80211_RADIOTAP_EHT_DATA7_NSS_S); +- +- eht->user_info[0] |= +- EHT_BITS(USER_INFO_MCS_KNOWN) | +- EHT_BITS(USER_INFO_CODING_KNOWN) | +- EHT_BITS(USER_INFO_NSS_KNOWN_O) | +- EHT_BITS(USER_INFO_BEAMFORMING_KNOWN_O) | +- EHT_BITS(USER_INFO_DATA_FOR_USER) | +- le32_encode_bits(status->rate_idx, IEEE80211_RADIOTAP_EHT_USER_INFO_MCS) | +- le32_encode_bits(status->nss, IEEE80211_RADIOTAP_EHT_USER_INFO_NSS_O); +- +- if (le32_to_cpu(rxv[0]) & MT_PRXV_TXBF) +- eht->user_info[0] |= EHT_BITS(USER_INFO_BEAMFORMING_O); +- +- if (le32_to_cpu(rxv[0]) & MT_PRXV_HT_AD_CODE) +- eht->user_info[0] |= EHT_BITS(USER_INFO_CODING); +- +- if (mode == MT_PHY_TYPE_EHT_MU) +- eht->user_info[0] |= EHT_BITS(USER_INFO_STA_ID_KNOWN) | +- EHT_PREP(USER_INFO_STA_ID, MU_AID, rxv[8]); +- +- usig->common |= +- EHT_BITS(USIG_COMMON_PHY_VER_KNOWN) | +- EHT_BITS(USIG_COMMON_BW_KNOWN) | +- EHT_BITS(USIG_COMMON_UL_DL_KNOWN) | +- EHT_BITS(USIG_COMMON_BSS_COLOR_KNOWN) | +- EHT_BITS(USIG_COMMON_TXOP_KNOWN) | +- le32_encode_bits(0, IEEE80211_RADIOTAP_EHT_USIG_COMMON_PHY_VER) | +- le32_encode_bits(bw, IEEE80211_RADIOTAP_EHT_USIG_COMMON_BW) | +- EHT_PREP(USIG_COMMON_UL_DL, UPLINK, rxv[5]) | +- EHT_PREP(USIG_COMMON_BSS_COLOR, BSS_COLOR, rxv[9]) | +- EHT_PREP(USIG_COMMON_TXOP, TXOP_DUR, rxv[9]); +-} +-EXPORT_SYMBOL_GPL(mt76_connac3_mac_decode_eht_radiotap); +diff --git a/mt76_connac3_mac.h b/mt76_connac3_mac.h +index 353e6606..83dcd964 100644 +--- a/mt76_connac3_mac.h ++++ b/mt76_connac3_mac.h +@@ -142,28 +142,6 @@ enum { + #define MT_CRXV_HE_RU3_L GENMASK(31, 27) + #define MT_CRXV_HE_RU3_H GENMASK(3, 0) + +-#define MT_CRXV_EHT_NUM_USER GENMASK(26, 20) +-#define MT_CRXV_EHT_LTF_SIZE GENMASK(28, 27) +-#define MT_CRXV_EHT_LDPC_EXT_SYM BIT(30) +-#define MT_CRXV_EHT_PE_DISAMBIG BIT(1) +-#define MT_CRXV_EHT_UPLINK BIT(2) +-#define MT_CRXV_EHT_MU_AID GENMASK(27, 17) +-#define MT_CRXV_EHT_BEAM_CHNG BIT(29) +-#define MT_CRXV_EHT_DOPPLER BIT(0) +-#define MT_CRXV_EHT_BSS_COLOR GENMASK(15, 10) +-#define MT_CRXV_EHT_TXOP_DUR GENMASK(23, 17) +-#define MT_CRXV_EHT_SR_MASK GENMASK(11, 8) +-#define MT_CRXV_EHT_SR1_MASK GENMASK(15, 12) +-#define MT_CRXV_EHT_SR2_MASK GENMASK(19, 16) +-#define MT_CRXV_EHT_SR3_MASK GENMASK(23, 20) +-#define MT_CRXV_EHT_RU0 GENMASK(8, 0) +-#define MT_CRXV_EHT_RU1 GENMASK(17, 9) +-#define MT_CRXV_EHT_RU2 GENMASK(26, 18) +-#define MT_CRXV_EHT_RU3_L GENMASK(31, 27) +-#define MT_CRXV_EHT_RU3_H GENMASK(3, 0) +-#define MT_CRXV_EHT_SIG_MCS GENMASK(19, 18) +-#define MT_CRXV_EHT_LTF_SYM GENMASK(22, 20) +- + enum tx_header_format { + MT_HDR_FORMAT_802_3, + MT_HDR_FORMAT_CMD, +diff --git a/mt7925/mac.c b/mt7925/mac.c +index c2460ef4..1b9fbd9a 100644 +--- a/mt7925/mac.c ++++ b/mt7925/mac.c +@@ -590,25 +590,14 @@ mt7925_mac_fill_rx(struct mt792x_dev *dev, struct sk_buff *skb) + seq_ctrl = le16_to_cpu(hdr->seq_ctrl); + qos_ctl = *ieee80211_get_qos_ctl(hdr); + } +- skb_set_mac_header(skb, (unsigned char *)hdr - skb->data); + } else { + status->flag |= RX_FLAG_8023; + } + + mt792x_mac_assoc_rssi(dev, skb); + +- if (rxv && !(status->flag & RX_FLAG_8023)) { +- switch (status->encoding) { +- case RX_ENC_EHT: +- mt76_connac3_mac_decode_eht_radiotap(skb, rxv, mode); +- break; +- case RX_ENC_HE: +- mt76_connac3_mac_decode_he_radiotap(skb, rxv, mode); +- break; +- default: +- break; +- } +- } ++ if (rxv && mode >= MT_PHY_TYPE_HE_SU && !(status->flag & RX_FLAG_8023)) ++ mt76_connac3_mac_decode_he_radiotap(skb, rxv, mode); + + if (!status->wcid || !ieee80211_is_data_qos(fc)) + return 0; +-- +2.43.2 + diff --git a/lede/package/kernel/mt76/src/firmware/mt7981_eeprom_mt7976_dbdc.bin b/lede/package/kernel/mt76/src/firmware/mt7981_eeprom_mt7976_dbdc.bin new file mode 100644 index 0000000000000000000000000000000000000000..109fe883690f7a759a6e242649c1703306bd763a GIT binary patch literal 4096 zcmeHI&r1SP5FUjMDf@w;=^?sBOShnl1Q}i;x_B$<(BJTGomSuOYX6FVM3lNNcIY7D z;b|T^h)9>%N-ZmzSBVDd7MWS>43C-l=6l~8=CB(%1OR7n@c_f1%{FMkAJcREnDSSJ zU3;6`umCqWSfLYgvY3wG3WRK75^`TAL9o{Kn+&w8wxSfL2JuQrR zI?r+s>wJ$>M6_P9liMe^o%U(|R!fp3-~7^w-{uc)g?9F_l%%-@kpmlBq1^*XGM@}N z;qb{xHp^JKT(1WL;jpe}v!znCdUwaGMB@CMvCGS=D_$KRpPl9NrBbC52$+kTFs>Vo zh6%-L4{rl@_@3jWnT)P$0BJ3)B>||cX{lraBcu`FiK@0BRc&M4G89UI4m!UVp;)~} z6iV@$LJNsT+gYm_i=~i7Wkrd_+TCv1@V5I0UK*j_#vj<0HR38b*^mzxxwMjC-Sr821OGZq&?Q=)z!(bwMr2+Q6qb@B))|1l0fl literal 0 HcmV?d00001 diff --git a/lede/package/lean/autocore/files/arm/sbin/cpuinfo b/lede/package/lean/autocore/files/arm/sbin/cpuinfo index 914d03310a..60127616cc 100755 --- a/lede/package/lean/autocore/files/arm/sbin/cpuinfo +++ b/lede/package/lean/autocore/files/arm/sbin/cpuinfo @@ -10,12 +10,13 @@ elif grep -q "bcm53xx" "/etc/openwrt_release"; then cpu_freq="$(nvram get clkfreq | awk -F ',' '{print $1}')MHz" elif grep -q "mvebu" "/etc/openwrt_release"; then cpu_freq="$(cat "/proc/cpuinfo" | grep "BogoMIPS" | sed -n "1p" | awk -F ': ' '{print $2}')MHz" -elif ! grep -q "filogic" "/etc/openwrt_release"; then - cpu_freq="$(expr $(cat /sys/devices/system/cpu/cpufreq/policy0/cpuinfo_cur_freq) / 1000)MHz" - if grep -q "rockchip" "/etc/openwrt_release"; then +elif grep -q "filogic" "/etc/openwrt_release"; then + [ -f "/sys/devices/system/cpu/cpufreq/policy0/cpuinfo_cur_freq" ] && big_cpu_freq="$(expr $(cat /sys/devices/system/cpu/cpufreq/policy0/cpuinfo_cur_freq) / 1000)MHz" +elif grep -q "rockchip" "/etc/openwrt_release"; then big_cpu_freq="$(expr $(cat /sys/devices/system/cpu/cpufreq/policy4/cpuinfo_cur_freq 2>"/dev/null") / 1000 2>"/dev/null")" [ -n "${big_cpu_freq}" ] && big_cpu_freq="${big_cpu_freq}MHz " - fi +else + cpu_freq="$(expr $(cat /sys/devices/system/cpu/cpufreq/policy0/cpuinfo_cur_freq) / 1000)MHz" fi if grep -q "ipq" "/etc/openwrt_release"; then @@ -32,8 +33,12 @@ else cpu_temp="$(awk "BEGIN{printf (\"%.1f\n\",$(cat /sys/class/thermal/thermal_zone0/temp)/1000) }")°C" fi if grep -q "filogic" "/etc/openwrt_release"; then - echo -n "${cpu_arch} x ${cpu_cores} (${cpu_temp})" - else - echo -n "${cpu_arch} x ${cpu_cores} (${big_cpu_freq}${cpu_freq}, ${cpu_temp})" + if [ -n "${big_cpu_freq}" ] ; then + echo -n "${cpu_arch} x ${cpu_cores} (${big_cpu_freq}, ${cpu_temp})" + else + echo -n "${cpu_arch} x ${cpu_cores} (${cpu_temp})" + fi + else + echo -n "${cpu_arch} x ${cpu_cores} (${big_cpu_freq}${cpu_freq}, ${cpu_temp})" fi fi diff --git a/lede/package/lean/default-settings/files/zzz-default-settings b/lede/package/lean/default-settings/files/zzz-default-settings index 61b4c5e2c9..13177d8c5d 100755 --- a/lede/package/lean/default-settings/files/zzz-default-settings +++ b/lede/package/lean/default-settings/files/zzz-default-settings @@ -51,13 +51,19 @@ sed -i '/option disabled/d' /etc/config/wireless sed -i '/set wireless.radio${devidx}.disabled/d' /lib/wifi/mac80211.sh sed -i '/DISTRIB_REVISION/d' /etc/openwrt_release -echo "DISTRIB_REVISION='R24.6.6'" >> /etc/openwrt_release +echo "DISTRIB_REVISION='R24.7.7'" >> /etc/openwrt_release sed -i '/DISTRIB_DESCRIPTION/d' /etc/openwrt_release echo "DISTRIB_DESCRIPTION='OpenWrt '" >> /etc/openwrt_release sed -i '/log-facility/d' /etc/dnsmasq.conf echo "log-facility=/dev/null" >> /etc/dnsmasq.conf +if [ -f /www/luci-static/resources/luci.js ]; then + sed -i 's/ifname/device/g' /etc/config/network +else + sed -i 's/device/ifname/g' /etc/config/network +fi + rm -rf /tmp/luci-modulecache/ rm -f /tmp/luci-indexcache diff --git a/lede/package/wwan/driver/quectel_QMI_WWAN/Makefile b/lede/package/wwan/driver/quectel_QMI_WWAN/Makefile index 45452109ed..b27dfad768 100755 --- a/lede/package/wwan/driver/quectel_QMI_WWAN/Makefile +++ b/lede/package/wwan/driver/quectel_QMI_WWAN/Makefile @@ -9,7 +9,7 @@ include $(TOPDIR)/rules.mk PKG_NAME:=qmi_wwan_q PKG_VERSION:=3.0 -PKG_RELEASE:=3 +PKG_RELEASE:=2 include $(INCLUDE_DIR)/kernel.mk include $(INCLUDE_DIR)/package.mk diff --git a/lede/package/wwan/driver/quectel_QMI_WWAN/src/qmi_wwan_q.c b/lede/package/wwan/driver/quectel_QMI_WWAN/src/qmi_wwan_q.c index 4f1a468edc..acde9d15ba 100644 --- a/lede/package/wwan/driver/quectel_QMI_WWAN/src/qmi_wwan_q.c +++ b/lede/package/wwan/driver/quectel_QMI_WWAN/src/qmi_wwan_q.c @@ -1,3 +1,4 @@ + /* * Copyright (c) 2012 Bjørn Mork * @@ -828,26 +829,26 @@ static struct rtnl_link_stats64 *_rmnet_vnd_get_stats64(struct net_device *net, stats64 = per_cpu_ptr(dev->stats64, cpu); do { -#if (LINUX_VERSION_CODE < KERNEL_VERSION( 6,6,0 )) start = u64_stats_fetch_begin_irq(&stats64->syncp); -#else - start = u64_stats_fetch_begin(&stats64->syncp); -#endif +#if LINUX_VERSION_CODE < KERNEL_VERSION(5,18,0) rx_packets = stats64->rx_packets; rx_bytes = stats64->rx_bytes; tx_packets = stats64->tx_packets; tx_bytes = stats64->tx_bytes; -#if (LINUX_VERSION_CODE < KERNEL_VERSION( 6,6,0 )) - } while (u64_stats_fetch_retry_irq(&stats64->syncp, start)); #else - } while (u64_stats_fetch_retry(&stats64->syncp, start)); + rx_packets = u64_stats_read(&stats64->rx_packets); + rx_bytes = u64_stats_read(&stats64->rx_bytes); + tx_packets = u64_stats_read(&stats64->tx_packets); + tx_bytes = u64_stats_read(&stats64->tx_bytes); #endif + } while (u64_stats_fetch_retry_irq(&stats64->syncp, start)); + + + stats->rx_packets += rx_packets; + stats->rx_bytes += rx_bytes; + stats->tx_packets += tx_packets; + stats->tx_bytes += tx_bytes; - stats->rx_packets += u64_stats_read(&rx_packets); - stats->rx_bytes += u64_stats_read(&rx_bytes); - stats->tx_packets += u64_stats_read(&tx_packets); - stats->tx_bytes += u64_stats_read(&tx_bytes); -#endif } return stats; diff --git a/lede/package/wwan/driver/quectel_QMI_WWAN/src/rmnet_nss.c b/lede/package/wwan/driver/quectel_QMI_WWAN/src/rmnet_nss.c index e6e841468b..e63fa9f328 100644 --- a/lede/package/wwan/driver/quectel_QMI_WWAN/src/rmnet_nss.c +++ b/lede/package/wwan/driver/quectel_QMI_WWAN/src/rmnet_nss.c @@ -1,3 +1,4 @@ + /* Copyright (c) 2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify diff --git a/lede/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7981-rfb-mxl-2p5g-phy-eth1.dtso b/lede/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7981-rfb-mxl-2p5g-phy-eth1.dtso new file mode 100644 index 0000000000..4d0e5c0406 --- /dev/null +++ b/lede/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7981-rfb-mxl-2p5g-phy-eth1.dtso @@ -0,0 +1,32 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */ +/dts-v1/; +/plugin/; + +#include + +/ { + compatible = "mediatek,mt7981-rfb", "mediatek,mt7981"; + + fragment@0 { + target = <&gmac1>; + __overlay__ { + phy-mode = "2500base-x"; + phy-handle = <&phy5>; + }; + }; + + fragment@1 { + target = <&mdio_bus>; + __overlay__ { + reset-gpios = <&pio 14 GPIO_ACTIVE_LOW>; + reset-delay-us = <600>; + reset-post-delay-us = <20000>; + + phy5: ethernet-phy@5 { + reg = <5>; + compatible = "ethernet-phy-ieee802.3-c45"; + phy-mode = "2500base-x"; + }; + }; + }; +}; diff --git a/lede/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7981-rfb-mxl-2p5g-phy-swp5.dtso b/lede/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7981-rfb-mxl-2p5g-phy-swp5.dtso new file mode 100644 index 0000000000..710e6c0bcf --- /dev/null +++ b/lede/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7981-rfb-mxl-2p5g-phy-swp5.dtso @@ -0,0 +1,33 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */ +/dts-v1/; +/plugin/; + +#include + +/ { + compatible = "mediatek,mt7981-rfb", "mediatek,mt7981"; + + fragment@0 { + target = <&sw_p5>; + __overlay__ { + phy-mode = "2500base-x"; + phy-handle = <&phy5>; + status = "okay"; + }; + }; + + fragment@1 { + target = <&mdio_bus>; + __overlay__ { + reset-gpios = <&pio 14 GPIO_ACTIVE_LOW>; + reset-delay-us = <600>; + reset-post-delay-us = <20000>; + + phy5: ethernet-phy@5 { + reg = <5>; + compatible = "ethernet-phy-ieee802.3-c45"; + phy-mode = "2500base-x"; + }; + }; + }; +}; diff --git a/lede/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7981-rfb-spim-nand.dtso b/lede/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7981-rfb-spim-nand.dtso new file mode 100644 index 0000000000..5b51dfd671 --- /dev/null +++ b/lede/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7981-rfb-spim-nand.dtso @@ -0,0 +1,66 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */ +/dts-v1/; +/plugin/; + +/ { + compatible = "mediatek,mt7981-rfb", "mediatek,mt7981"; + + fragment@0 { + target = <&spi0>; + __overlay__ { + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + + spi_nand: spi_nand@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "spi-nand"; + reg = <1>; + spi-max-frequency = <10000000>; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "BL2"; + reg = <0x00000 0x0100000>; + read-only; + }; + + partition@100000 { + label = "u-boot-env"; + reg = <0x0100000 0x0080000>; + }; + + factory: partition@180000 { + label = "Factory"; + reg = <0x180000 0x0200000>; + }; + + partition@380000 { + label = "FIP"; + reg = <0x380000 0x0200000>; + }; + + partition@580000 { + label = "ubi"; + reg = <0x580000 0x4000000>; + }; + }; + }; + }; + }; + + fragment@1 { + target = <&wifi>; + __overlay__ { + mediatek,mtd-eeprom = <&factory 0x0>; + status = "okay"; + }; + }; +}; diff --git a/lede/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7981-rfb.dts b/lede/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7981-rfb.dts new file mode 100644 index 0000000000..b2bb692956 --- /dev/null +++ b/lede/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7981-rfb.dts @@ -0,0 +1,188 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2022 MediaTek Inc. + * Author: Sam.Shih + */ + +/dts-v1/; +#include "mt7981.dtsi" + +/ { + model = "MediaTek MT7981 RFB"; + compatible = "mediatek,mt7981-rfb", "mediatek,mt7981"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory { + reg = <0 0x40000000 0 0x20000000>; + }; + + reg_3p3v: regulator-3p3v { + compatible = "regulator-fixed"; + regulator-name = "fixed-3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + reg_5v: regulator-5v { + compatible = "regulator-fixed"; + regulator-name = "fixed-5V"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-boot-on; + regulator-always-on; + }; + + gpio-keys { + compatible = "gpio-keys"; + reset { + label = "reset"; + linux,code = ; + gpios = <&pio 1 GPIO_ACTIVE_LOW>; + }; + wps { + label = "wps"; + linux,code = ; + gpios = <&pio 0 GPIO_ACTIVE_HIGH>; + }; + }; +}; + +ð { + status = "okay"; + + gmac0: mac@0 { + compatible = "mediatek,eth-mac"; + reg = <0>; + phy-mode = "2500base-x"; + + fixed-link { + speed = <2500>; + full-duplex; + pause; + }; + }; + + gmac1: mac@1 { + compatible = "mediatek,eth-mac"; + reg = <1>; + phy-mode = "gmii"; + phy-handle = <&int_gbe_phy>; + }; +}; + +&mdio_bus { + switch: switch@1f { + compatible = "mediatek,mt7531"; + reg = <31>; + interrupt-controller; + #interrupt-cells = <1>; + interrupt-parent = <&pio>; + interrupts = <38 IRQ_TYPE_LEVEL_HIGH>; + reset-gpios = <&pio 5 GPIO_ACTIVE_HIGH>; + }; +}; + +&crypto { + status = "okay"; +}; + +&pio { + spi0_flash_pins: spi0-pins { + mux { + function = "spi"; + groups = "spi0", "spi0_wp_hold"; + }; + conf-pu { + pins = "SPI0_CS", "SPI0_HOLD", "SPI0_WP"; + drive-strength = ; + bias-pull-up = ; + }; + conf-pd { + pins = "SPI0_CLK", "SPI0_MOSI", "SPI0_MISO"; + drive-strength = ; + bias-pull-down = ; + }; + }; + +}; + +&spi0 { + pinctrl-names = "default"; + pinctrl-0 = <&spi0_flash_pins>; + cs-gpios = <0>, <0>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; +}; + +&switch { + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + label = "lan1"; + }; + + port@1 { + reg = <1>; + label = "lan2"; + }; + + port@2 { + reg = <2>; + label = "lan3"; + }; + + port@3 { + reg = <3>; + label = "lan4"; + }; + + sw_p5: port@5 { + reg = <5>; + label = "lan5"; + status = "disabled"; + }; + + port@6 { + reg = <6>; + ethernet = <&gmac0>; + phy-mode = "2500base-x"; + + fixed-link { + speed = <2500>; + full-duplex; + pause; + }; + }; + }; +}; + +&xhci { + vusb33-supply = <®_3p3v>; + vbus-supply = <®_5v>; + status = "okay"; +}; + +&uart0 { + status = "okay"; +}; + +&usb_phy { + status = "okay"; +}; + +&watchdog { + status = "okay"; +}; diff --git a/lede/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7981.dtsi b/lede/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7981.dtsi index 05d4b7d91d..54cfd0b4b9 100644 --- a/lede/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7981.dtsi +++ b/lede/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7981.dtsi @@ -27,143 +27,59 @@ #size-cells = <0>; cpu@0 { - device_type = "cpu"; compatible = "arm,cortex-a53"; - enable-method = "psci"; reg = <0x0>; + device_type = "cpu"; + enable-method = "psci"; }; cpu@1 { - device_type = "cpu"; compatible = "arm,cortex-a53"; - enable-method = "psci"; reg = <0x1>; + device_type = "cpu"; + enable-method = "psci"; }; }; - pwm: pwm@10048000 { - compatible = "mediatek,mt7981-pwm"; - reg = <0 0x10048000 0 0x1000>; - #pwm-cells = <2>; - clocks = <&infracfg CLK_INFRA_PWM_STA>, - <&infracfg CLK_INFRA_PWM_HCK>, - <&infracfg CLK_INFRA_PWM1_CK>, - <&infracfg CLK_INFRA_PWM2_CK>, - <&infracfg CLK_INFRA_PWM3_CK>; - clock-names = "top", "main", "pwm1", "pwm2", "pwm3"; + ice: ice_debug { + compatible = "mediatek,mt7981-ice_debug", "mediatek,mt2701-ice_debug"; + clocks = <&infracfg CLK_INFRA_DBG_CK>; + clock-names = "ice_dbg"; + }; + + clk40m: oscillator-40m { + compatible = "fixed-clock"; + clock-frequency = <40000000>; + clock-output-names = "clkxtal"; + #clock-cells = <0>; + }; + + psci { + compatible = "arm,psci-0.2"; + method = "smc"; }; fan: pwm-fan { compatible = "pwm-fan"; - /* cooling level (0, 1, 2, 3) : (0% duty, 50% duty, 75% duty, 100% duty) */ - cooling-levels = <0 128 192 255>; + /* cooling level (0, 1, 2, 3, 4, 5, 6, 7) : (0%/25%/37.5%/50%/62.5%/75%/87.5%/100% duty) */ + cooling-levels = <0 63 95 127 159 191 223 255>; #cooling-cells = <2>; status = "disabled"; }; - thermal-zones { - cpu_thermal: cpu-thermal { - polling-delay-passive = <1000>; - polling-delay = <1000>; - thermal-sensors = <&thermal 0>; - trips { - cpu_trip_crit: crit { - temperature = <125000>; - hysteresis = <2000>; - type = "critical"; - }; - - cpu_trip_hot: hot { - temperature = <120000>; - hysteresis = <2000>; - type = "hot"; - }; - - cpu_trip_active_high: active-high { - temperature = <115000>; - hysteresis = <2000>; - type = "active"; - }; - - cpu_trip_active_med: active-med { - temperature = <85000>; - hysteresis = <2000>; - type = "active"; - }; - - cpu_trip_active_low: active-low { - temperature = <60000>; - hysteresis = <2000>; - type = "active"; - }; - }; - - cooling-maps { - cpu-active-high { - /* active: set fan to cooling level 3 */ - cooling-device = <&fan 3 3>; - trip = <&cpu_trip_active_high>; - }; - - cpu-active-med { - /* active: set fan to cooling level 2 */ - cooling-device = <&fan 2 2>; - trip = <&cpu_trip_active_med>; - }; - - cpu-active-low { - /* passive: set fan to cooling level 1 */ - cooling-device = <&fan 1 1>; - trip = <&cpu_trip_active_low>; - }; - }; - }; - }; - - thermal: thermal@1100c800 { - #thermal-sensor-cells = <1>; - compatible = "mediatek,mt7981-thermal", "mediatek,mt7986-thermal"; - reg = <0 0x1100c800 0 0x800>; - interrupts = ; - clocks = <&infracfg CLK_INFRA_THERM_CK>, - <&infracfg CLK_INFRA_ADC_26M_CK>; - clock-names = "therm", "auxadc"; - mediatek,auxadc = <&auxadc>; - mediatek,apmixedsys = <&apmixedsys>; - nvmem-cells = <&thermal_calibration>; - nvmem-cell-names = "calibration-data"; - }; - - auxadc: adc@1100d000 { - compatible = "mediatek,mt7981-auxadc", - "mediatek,mt7986-auxadc", - "mediatek,mt7622-auxadc"; - reg = <0 0x1100d000 0 0x1000>; - clocks = <&infracfg CLK_INFRA_ADC_26M_CK>, - <&infracfg CLK_INFRA_ADC_FRC_CK>; - clock-names = "main", "32k"; - #io-channel-cells = <1>; - }; - - wdma: wdma@15104800 { - compatible = "mediatek,wed-wdma"; - reg = <0 0x15104800 0 0x400>, - <0 0x15104c00 0 0x400>; - }; - - ap2woccif: ap2woccif@151a5000 { - compatible = "mediatek,ap2woccif"; - reg = <0 0x151a5000 0 0x1000>, - <0 0x151ad000 0 0x1000>; - interrupt-parent = <&gic>; - interrupts = , - ; + reg_3p3v: regulator-3p3v { + compatible = "regulator-fixed"; + regulator-name = "fixed-3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; }; reserved-memory { + ranges; #address-cells = <2>; #size-cells = <2>; - ranges; /* 64 KiB reserved for ramoops/pstore */ ramoops@42ff0000 { @@ -194,38 +110,699 @@ }; }; - psci { - compatible = "arm,psci-0.2"; - method = "smc"; + soc { + compatible = "simple-bus"; + ranges; + #address-cells = <2>; + #size-cells = <2>; + + gic: interrupt-controller@c000000 { + compatible = "arm,gic-v3"; + reg = <0 0x0c000000 0 0x40000>, /* GICD */ + <0 0x0c080000 0 0x200000>; /* GICR */ + interrupt-parent = <&gic>; + interrupts = ; + interrupt-controller; + #interrupt-cells = <3>; + }; + + consys: consys@10000000 { + compatible = "mediatek,mt7981-consys"; + reg = <0 0x10000000 0 0x8600000>; + memory-region = <&wmcpu_emi>; + }; + + infracfg: clock-controller@10001000 { + compatible = "mediatek,mt7981-infracfg", "syscon"; + reg = <0 0x10001000 0 0x1000>; + #clock-cells = <1>; + }; + + wed_pcie: wed_pcie@10003000 { + compatible = "mediatek,wed_pcie"; + reg = <0 0x10003000 0 0x10>; + }; + + topckgen: clock-controller@1001b000 { + compatible = "mediatek,mt7981-topckgen", "syscon"; + reg = <0 0x1001b000 0 0x1000>; + #clock-cells = <1>; + }; + + watchdog: watchdog@1001c000 { + compatible = "mediatek,mt7986-wdt", + "mediatek,mt6589-wdt"; + reg = <0 0x1001c000 0 0x1000>; + interrupts = ; + #reset-cells = <1>; + status = "disabled"; + }; + + apmixedsys: clock-controller@1001e000 { + compatible = "mediatek,mt7981-apmixedsys", "syscon"; + reg = <0 0x1001e000 0 0x1000>; + #clock-cells = <1>; + }; + + pwm: pwm@10048000 { + compatible = "mediatek,mt7981-pwm"; + reg = <0 0x10048000 0 0x1000>; + clocks = <&infracfg CLK_INFRA_PWM_STA>, + <&infracfg CLK_INFRA_PWM_HCK>, + <&infracfg CLK_INFRA_PWM1_CK>, + <&infracfg CLK_INFRA_PWM2_CK>, + <&infracfg CLK_INFRA_PWM3_CK>; + clock-names = "top", "main", "pwm1", "pwm2", "pwm3"; + #pwm-cells = <2>; + }; + + sgmiisys0: syscon@10060000 { + compatible = "mediatek,mt7981-sgmiisys_0", "syscon"; + reg = <0 0x10060000 0 0x1000>; + mediatek,pnswap; + #clock-cells = <1>; + }; + + sgmiisys1: syscon@10070000 { + compatible = "mediatek,mt7981-sgmiisys_1", "syscon"; + reg = <0 0x10070000 0 0x1000>; + #clock-cells = <1>; + }; + + crypto: crypto@10320000 { + compatible = "inside-secure,safexcel-eip97"; + reg = <0 0x10320000 0 0x40000>; + interrupts = , + , + , + ; + interrupt-names = "ring0", "ring1", "ring2", "ring3"; + clocks = <&topckgen CLK_TOP_EIP97B>; + clock-names = "top_eip97_ck"; + assigned-clocks = <&topckgen CLK_TOP_EIP97B_SEL>; + assigned-clock-parents = <&topckgen CLK_TOP_CB_NET1_D5>; + }; + + uart0: serial@11002000 { + compatible = "mediatek,mt6577-uart"; + reg = <0 0x11002000 0 0x400>; + interrupts = ; + clocks = <&infracfg CLK_INFRA_UART0_SEL>, + <&infracfg CLK_INFRA_UART0_CK>; + clock-names = "baud", "bus"; + assigned-clocks = <&topckgen CLK_TOP_UART_SEL>, + <&infracfg CLK_INFRA_UART0_SEL>; + assigned-clock-parents = <&topckgen CLK_TOP_CB_CKSQ_40M>, + <&topckgen CLK_TOP_UART_SEL>; + pinctrl-0 = <&uart0_pins>; + pinctrl-names = "default"; + status = "disabled"; + }; + + uart1: serial@11003000 { + compatible = "mediatek,mt6577-uart"; + reg = <0 0x11003000 0 0x400>; + interrupts = ; + clocks = <&infracfg CLK_INFRA_UART1_SEL>, + <&infracfg CLK_INFRA_UART1_CK>; + clock-names = "baud", "bus"; + assigned-clocks = <&topckgen CLK_TOP_UART_SEL>, + <&infracfg CLK_INFRA_UART1_SEL>; + assigned-clock-parents = <&topckgen CLK_TOP_CB_CKSQ_40M>, + <&topckgen CLK_TOP_UART_SEL>; + status = "disabled"; + }; + + uart2: serial@11004000 { + compatible = "mediatek,mt6577-uart"; + reg = <0 0x11004000 0 0x400>; + interrupts = ; + clocks = <&infracfg CLK_INFRA_UART2_SEL>, + <&infracfg CLK_INFRA_UART2_CK>; + clock-names = "baud", "bus"; + assigned-clocks = <&topckgen CLK_TOP_UART_SEL>, + <&infracfg CLK_INFRA_UART2_SEL>; + assigned-clock-parents = <&topckgen CLK_TOP_CB_CKSQ_40M>, + <&topckgen CLK_TOP_UART_SEL>; + status = "disabled"; + }; + + snand: snfi@11005000 { + compatible = "mediatek,mt7986-snand"; + reg = <0 0x11005000 0 0x1000>, <0 0x11006000 0 0x1000>; + reg-names = "nfi", "ecc"; + interrupts = ; + clocks = <&infracfg CLK_INFRA_SPINFI1_CK>, + <&infracfg CLK_INFRA_NFI1_CK>, + <&infracfg CLK_INFRA_NFI_HCK_CK>; + clock-names = "pad_clk", "nfi_clk", "nfi_hclk"; + assigned-clocks = <&topckgen CLK_TOP_SPINFI_SEL>, + <&topckgen CLK_TOP_NFI1X_SEL>; + assigned-clock-parents = <&topckgen CLK_TOP_CB_M_D8>, + <&topckgen CLK_TOP_CB_M_D8>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c0: i2c@11007000 { + compatible = "mediatek,mt7981-i2c"; + reg = <0 0x11007000 0 0x1000>, + <0 0x10217080 0 0x80>; + interrupts = ; + clock-div = <1>; + clocks = <&infracfg CLK_INFRA_I2C0_CK>, + <&infracfg CLK_INFRA_AP_DMA_CK>, + <&infracfg CLK_INFRA_I2C_MCK_CK>, + <&infracfg CLK_INFRA_I2C_PCK_CK>; + clock-names = "main", "dma", "arb", "pmic"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi2: spi@11009000 { + compatible = "mediatek,mt7986-spi-ipm", "mediatek,spi-ipm"; + reg = <0 0x11009000 0 0x100>; + interrupts = ; + clocks = <&topckgen CLK_TOP_CB_M_D2>, + <&topckgen CLK_TOP_SPI_SEL>, + <&infracfg CLK_INFRA_SPI2_CK>, + <&infracfg CLK_INFRA_SPI2_HCK_CK>; + clock-names = "parent-clk", "sel-clk", "spi-clk", "hclk"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi0: spi@1100a000 { + compatible = "mediatek,mt7986-spi-ipm", "mediatek,spi-ipm"; + reg = <0 0x1100a000 0 0x100>; + interrupts = ; + clocks = <&topckgen CLK_TOP_CB_M_D2>, + <&topckgen CLK_TOP_SPI_SEL>, + <&infracfg CLK_INFRA_SPI0_CK>, + <&infracfg CLK_INFRA_SPI0_HCK_CK>; + clock-names = "parent-clk", "sel-clk", "spi-clk", "hclk"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi1: spi@1100b000 { + compatible = "mediatek,mt7986-spi-ipm", "mediatek,spi-ipm"; + reg = <0 0x1100b000 0 0x100>; + interrupts = ; + clocks = <&topckgen CLK_TOP_CB_M_D2>, + <&topckgen CLK_TOP_SPIM_MST_SEL>, + <&infracfg CLK_INFRA_SPI1_CK>, + <&infracfg CLK_INFRA_SPI1_HCK_CK>; + clock-names = "parent-clk", "sel-clk", "spi-clk", "hclk"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + thermal: thermal@1100c800 { + compatible = "mediatek,mt7981-thermal", "mediatek,mt7986-thermal"; + reg = <0 0x1100c800 0 0x800>; + interrupts = ; + clocks = <&infracfg CLK_INFRA_THERM_CK>, + <&infracfg CLK_INFRA_ADC_26M_CK>; + clock-names = "therm", "auxadc"; + nvmem-cells = <&thermal_calibration>; + nvmem-cell-names = "calibration-data"; + #thermal-sensor-cells = <1>; + mediatek,auxadc = <&auxadc>; + mediatek,apmixedsys = <&apmixedsys>; + }; + + auxadc: adc@1100d000 { + compatible = "mediatek,mt7981-auxadc", + "mediatek,mt7986-auxadc", + "mediatek,mt7622-auxadc"; + reg = <0 0x1100d000 0 0x1000>; + clocks = <&infracfg CLK_INFRA_ADC_26M_CK>, + <&infracfg CLK_INFRA_ADC_FRC_CK>; + clock-names = "main", "32k"; + #io-channel-cells = <1>; + }; + + xhci: usb@11200000 { + compatible = "mediatek,mt7986-xhci", + "mediatek,mtk-xhci"; + reg = <0 0x11200000 0 0x2e00>, + <0 0x11203e00 0 0x0100>; + reg-names = "mac", "ippc"; + interrupts = ; + clocks = <&infracfg CLK_INFRA_IUSB_SYS_CK>, + <&infracfg CLK_INFRA_IUSB_CK>, + <&infracfg CLK_INFRA_IUSB_133_CK>, + <&infracfg CLK_INFRA_IUSB_66M_CK>, + <&topckgen CLK_TOP_U2U3_XHCI_SEL>; + clock-names = "sys_ck", + "ref_ck", + "mcu_ck", + "dma_ck", + "xhci_ck"; + phys = <&u2port0 PHY_TYPE_USB2>, + <&u3port0 PHY_TYPE_USB3>; + vusb33-supply = <®_3p3v>; + status = "disabled"; + }; + + afe: audio-controller@11210000 { + compatible = "mediatek,mt79xx-audio"; + reg = <0 0x11210000 0 0x9000>; + interrupts = ; + clocks = <&infracfg CLK_INFRA_AUD_BUS_CK>, + <&infracfg CLK_INFRA_AUD_26M_CK>, + <&infracfg CLK_INFRA_AUD_L_CK>, + <&infracfg CLK_INFRA_AUD_AUD_CK>, + <&infracfg CLK_INFRA_AUD_EG2_CK>, + <&topckgen CLK_TOP_AUD_SEL>; + clock-names = "aud_bus_ck", + "aud_26m_ck", + "aud_l_ck", + "aud_aud_ck", + "aud_eg2_ck", + "aud_sel"; + assigned-clocks = <&topckgen CLK_TOP_AUD_SEL>, + <&topckgen CLK_TOP_A1SYS_SEL>, + <&topckgen CLK_TOP_AUD_L_SEL>, + <&topckgen CLK_TOP_A_TUNER_SEL>; + assigned-clock-parents = <&topckgen CLK_TOP_CB_APLL2_196M>, + <&topckgen CLK_TOP_APLL2_D4>, + <&topckgen CLK_TOP_CB_APLL2_196M>, + <&topckgen CLK_TOP_APLL2_D4>; + status = "disabled"; + }; + + mmc0: mmc@11230000 { + compatible = "mediatek,mt7986-mmc", "mediatek,mt7981-mmc"; + reg = <0 0x11230000 0 0x1000>, <0 0x11c20000 0 0x1000>; + interrupts = ; + clocks = <&infracfg CLK_INFRA_MSDC_CK>, + <&infracfg CLK_INFRA_MSDC_HCK_CK>, + <&infracfg CLK_INFRA_MSDC_66M_CK>, + <&infracfg CLK_INFRA_MSDC_133M_CK>; + assigned-clocks = <&topckgen CLK_TOP_EMMC_208M_SEL>, + <&topckgen CLK_TOP_EMMC_400M_SEL>; + assigned-clock-parents = <&topckgen CLK_TOP_CB_M_D2>, + <&topckgen CLK_TOP_CB_NET2_D2>; + clock-names = "source", "hclk", "axi_cg", "ahb_cg"; + status = "disabled"; + }; + + pcie: pcie@11280000 { + compatible = "mediatek,mt7981-pcie", + "mediatek,mt7986-pcie"; + reg = <0 0x11280000 0 0x4000>; + reg-names = "pcie-mac"; + ranges = <0x82000000 0 0x20000000 + 0x0 0x20000000 0 0x10000000>; + device_type = "pci"; + interrupts = ; + bus-range = <0x00 0xff>; + clocks = <&infracfg CLK_INFRA_IPCIE_CK>, + <&infracfg CLK_INFRA_IPCIE_PIPE_CK>, + <&infracfg CLK_INFRA_IPCIER_CK>, + <&infracfg CLK_INFRA_IPCIEB_CK>; + phys = <&u3port0 PHY_TYPE_PCIE>; + phy-names = "pcie-phy"; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie_intc 0>, + <0 0 0 2 &pcie_intc 1>, + <0 0 0 3 &pcie_intc 2>, + <0 0 0 4 &pcie_intc 3>; + #interrupt-cells = <1>; + #address-cells = <3>; + #size-cells = <2>; + status = "disabled"; + + pcie_intc: interrupt-controller { + interrupt-controller; + #interrupt-cells = <1>; + #address-cells = <0>; + }; + }; + + pio: pinctrl@11d00000 { + compatible = "mediatek,mt7981-pinctrl"; + reg = <0 0x11d00000 0 0x1000>, + <0 0x11c00000 0 0x1000>, + <0 0x11c10000 0 0x1000>, + <0 0x11d20000 0 0x1000>, + <0 0x11e00000 0 0x1000>, + <0 0x11e20000 0 0x1000>, + <0 0x11f00000 0 0x1000>, + <0 0x11f10000 0 0x1000>, + <0 0x1000b000 0 0x1000>; + reg-names = "gpio", "iocfg_rt", "iocfg_rm", + "iocfg_rb", "iocfg_lb", "iocfg_bl", + "iocfg_tm", "iocfg_tl", "eint"; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pio 0 0 56>; + interrupt-controller; + interrupts = ; + interrupt-parent = <&gic>; + #interrupt-cells = <2>; + + mdio_pins: mdc-mdio-pins { + mux { + function = "eth"; + groups = "smi_mdc_mdio"; + }; + }; + + uart0_pins: uart0-pins { + mux { + function = "uart"; + groups = "uart0"; + }; + }; + + wifi_dbdc_pins: wifi-dbdc-pins { + mux { + function = "eth"; + groups = "wf0_mode1"; + }; + + conf { + pins = "WF_HB1", "WF_HB2", "WF_HB3", "WF_HB4", + "WF_HB0", "WF_HB0_B", "WF_HB5", "WF_HB6", + "WF_HB7", "WF_HB8", "WF_HB9", "WF_HB10", + "WF_TOP_CLK", "WF_TOP_DATA", "WF_XO_REQ", + "WF_CBA_RESETB", "WF_DIG_RESETB"; + drive-strength = <4>; + }; + }; + + gbe_led0_pins: gbe-led0-pins { + mux { + function = "led"; + groups = "gbe_led0"; + }; + }; + + gbe_led1_pins: gbe-led1-pins { + mux { + function = "led"; + groups = "gbe_led1"; + }; + }; + }; + + topmisc: topmisc@11d10000 { + compatible = "mediatek,mt7981-topmisc", "syscon"; + reg = <0 0x11d10000 0 0x10000>; + #clock-cells = <1>; + }; + + usb_phy: usb-phy@11e10000 { + compatible = "mediatek,mt7981", + "mediatek,generic-tphy-v2"; + ranges = <0 0 0x11e10000 0x1700>; + #address-cells = <1>; + #size-cells = <1>; + status = "disabled"; + + u2port0: usb-phy@0 { + reg = <0x0 0x700>; + clocks = <&topckgen CLK_TOP_USB_FRMCNT_SEL>; + clock-names = "ref"; + #phy-cells = <1>; + }; + + u3port0: usb-phy@700 { + reg = <0x700 0x900>; + clocks = <&topckgen CLK_TOP_USB3_PHY_SEL>; + clock-names = "ref"; + #phy-cells = <1>; + mediatek,syscon-type = <&topmisc 0x218 0>; + status = "okay"; + }; + }; + + efuse: efuse@11f20000 { + compatible = "mediatek,mt7981-efuse", + "mediatek,efuse"; + reg = <0 0x11f20000 0 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + status = "okay"; + + thermal_calibration: thermal-calib@274 { + reg = <0x274 0xc>; + }; + + phy_calibration: phy-calib@8dc { + reg = <0x8dc 0x10>; + }; + + comb_rx_imp_p0: usb3-rx-imp@8c8 { + reg = <0x8c8 1>; + bits = <0 5>; + }; + + comb_tx_imp_p0: usb3-tx-imp@8c8 { + reg = <0x8c8 2>; + bits = <5 5>; + }; + + comb_intr_p0: usb3-intr@8c9 { + reg = <0x8c9 1>; + bits = <2 6>; + }; + }; + + ethsys: clock-controller@15000000 { + compatible = "mediatek,mt7981-ethsys", + "syscon"; + reg = <0 0x15000000 0 0x1000>; + #clock-cells = <1>; + #reset-cells = <1>; + #address-cells = <1>; + #size-cells = <1>; + }; + + wed: wed@15010000 { + compatible = "mediatek,mt7981-wed", + "mediatek,mt7986-wed", + "syscon"; + reg = <0 0x15010000 0 0x1000>; + interrupt-parent = <&gic>; + interrupts = ; + memory-region = <&wo_emi0>, <&wo_data>; + memory-region-names = "wo-emi", "wo-data"; + mediatek,wo-ccif = <&wo_ccif0>; + mediatek,wo-ilm = <&wo_ilm0>; + mediatek,wo-dlm = <&wo_dlm0>; + mediatek,wo-cpuboot = <&wo_cpuboot>; + }; + + eth: ethernet@15100000 { + compatible = "mediatek,mt7981-eth"; + reg = <0 0x15100000 0 0x80000>; + interrupts = , + , + , + ; + clocks = <ðsys CLK_ETH_FE_EN>, + <ðsys CLK_ETH_GP2_EN>, + <ðsys CLK_ETH_GP1_EN>, + <ðsys CLK_ETH_WOCPU0_EN>, + <&sgmiisys0 CLK_SGM0_TX_EN>, + <&sgmiisys0 CLK_SGM0_RX_EN>, + <&sgmiisys0 CLK_SGM0_CK0_EN>, + <&sgmiisys0 CLK_SGM0_CDR_CK0_EN>, + <&sgmiisys1 CLK_SGM1_TX_EN>, + <&sgmiisys1 CLK_SGM1_RX_EN>, + <&sgmiisys1 CLK_SGM1_CK1_EN>, + <&sgmiisys1 CLK_SGM1_CDR_CK1_EN>, + <&topckgen CLK_TOP_SGM_REG>, + <&topckgen CLK_TOP_NETSYS_SEL>, + <&topckgen CLK_TOP_NETSYS_500M_SEL>; + clock-names = "fe", "gp2", "gp1", "wocpu0", + "sgmii_tx250m", "sgmii_rx250m", + "sgmii_cdr_ref", "sgmii_cdr_fb", + "sgmii2_tx250m", "sgmii2_rx250m", + "sgmii2_cdr_ref", "sgmii2_cdr_fb", + "sgmii_ck", "netsys0", "netsys1"; + assigned-clocks = <&topckgen CLK_TOP_NETSYS_2X_SEL>, + <&topckgen CLK_TOP_SGM_325M_SEL>; + assigned-clock-parents = <&topckgen CLK_TOP_CB_NET2_800M>, + <&topckgen CLK_TOP_CB_SGM_325M>; + mediatek,ethsys = <ðsys>; + mediatek,sgmiisys = <&sgmiisys0>, <&sgmiisys1>; + mediatek,infracfg = <&topmisc>; + mediatek,wed = <&wed>; + #reset-cells = <1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + mdio_bus: mdio-bus { + #address-cells = <1>; + #size-cells = <0>; + + int_gbe_phy: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + phy-mode = "gmii"; + phy-is-integrated; + nvmem-cells = <&phy_calibration>; + nvmem-cell-names = "phy-cal-data"; + + leds { + #address-cells = <1>; + #size-cells = <0>; + + int_gbe_phy_led0: int-gbe-phy-led0@0 { + reg = <0>; + function = LED_FUNCTION_LAN; + status = "disabled"; + }; + + int_gbe_phy_led1: int-gbe-phy-led1@1 { + reg = <1>; + function = LED_FUNCTION_LAN; + status = "disabled"; + }; + }; + }; + }; + }; + + wdma: wdma@15104800 { + compatible = "mediatek,wed-wdma"; + reg = <0 0x15104800 0 0x400>, + <0 0x15104c00 0 0x400>; + }; + + wo_cpuboot: syscon@15194000 { + compatible = "mediatek,mt7986-wo-cpuboot", "syscon"; + reg = <0 0x15194000 0 0x1000>; + }; + + ap2woccif: ap2woccif@151a5000 { + compatible = "mediatek,ap2woccif"; + reg = <0 0x151a5000 0 0x1000>, + <0 0x151ad000 0 0x1000>; + interrupt-parent = <&gic>; + interrupts = , + ; + }; + + wo_ccif0: syscon@151a5000 { + compatible = "mediatek,mt7986-wo-ccif", "syscon"; + reg = <0 0x151a5000 0 0x1000>; + interrupt-parent = <&gic>; + interrupts = ; + }; + + wo_ilm0: syscon@151e0000 { + compatible = "mediatek,mt7986-wo-ilm", "syscon"; + reg = <0 0x151e0000 0 0x8000>; + }; + + wo_dlm0: syscon@151e8000 { + compatible = "mediatek,mt7986-wo-dlm", "syscon"; + reg = <0 0x151e8000 0 0x2000>; + }; + + wifi: wifi@18000000 { + compatible = "mediatek,mt7981-wmac"; + reg = <0 0x18000000 0 0x1000000>, + <0 0x10003000 0 0x1000>, + <0 0x11d10000 0 0x1000>; + resets = <&watchdog MT7986_TOPRGU_CONSYS_SW_RST>; + reset-names = "consys"; + pinctrl-0 = <&wifi_dbdc_pins>; + pinctrl-names = "dbdc"; + clocks = <&topckgen CLK_TOP_NETSYS_MCU_SEL>, + <&topckgen CLK_TOP_AP2CNN_HOST_SEL>; + clock-names = "mcu", "ap2conn"; + interrupts = , + , + , + ; + memory-region = <&wmcpu_emi>; + status = "disabled"; + }; }; - trng { - compatible = "mediatek,mt7981-rng"; - }; + thermal-zones { + cpu_thermal: cpu-thermal { + polling-delay-passive = <1000>; + polling-delay = <1000>; + thermal-sensors = <&thermal 0>; - clk40m: oscillator@0 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <40000000>; - clock-output-names = "clkxtal"; - }; + trips { + cpu_trip_active_highest: active-highest { + temperature = <70000>; + hysteresis = <2000>; + type = "active"; + }; - infracfg: infracfg@10001000 { - compatible = "mediatek,mt7981-infracfg", "syscon"; - reg = <0 0x10001000 0 0x1000>; - #clock-cells = <1>; - }; + cpu_trip_active_high: active-high { + temperature = <60000>; + hysteresis = <2000>; + type = "active"; + }; - topckgen: topckgen@1001B000 { - compatible = "mediatek,mt7981-topckgen", "syscon"; - reg = <0 0x1001B000 0 0x1000>; - #clock-cells = <1>; - }; + cpu_trip_active_med: active-med { + temperature = <50000>; + hysteresis = <2000>; + type = "active"; + }; - apmixedsys: apmixedsys@1001E000 { - compatible = "mediatek,mt7981-apmixedsys", "mediatek,mt7986-apmixedsys", "syscon"; - reg = <0 0x1001E000 0 0x1000>; - #clock-cells = <1>; + cpu_trip_active_low: active-low { + temperature = <45000>; + hysteresis = <2000>; + type = "active"; + }; + + cpu_trip_active_lowest: active-lowest { + temperature = <40000>; + hysteresis = <2000>; + type = "active"; + }; + }; + + cooling-maps { + cpu-active-highest { + /* active: set fan to cooling level 7 */ + cooling-device = <&fan 7 7>; + trip = <&cpu_trip_active_highest>; + }; + + cpu-active-high { + /* active: set fan to cooling level 5 */ + cooling-device = <&fan 5 5>; + trip = <&cpu_trip_active_high>; + }; + + cpu-active-med { + /* active: set fan to cooling level 3 */ + cooling-device = <&fan 3 3>; + trip = <&cpu_trip_active_med>; + }; + + cpu-active-low { + /* active: set fan to cooling level 2 */ + cooling-device = <&fan 2 2>; + trip = <&cpu_trip_active_low>; + }; + + cpu-active-lowest { + /* active: set fan to cooling level 1 */ + cooling-device = <&fan 1 1>; + trip = <&cpu_trip_active_lowest>; + }; + }; + }; }; timer { @@ -239,570 +816,7 @@ }; - watchdog: watchdog@1001c000 { - compatible = "mediatek,mt7986-wdt", - "mediatek,mt6589-wdt"; - reg = <0 0x1001c000 0 0x1000>; - interrupts = ; - #reset-cells = <1>; - status = "disabled"; - }; - - gic: interrupt-controller@c000000 { - compatible = "arm,gic-v3"; - #interrupt-cells = <3>; - interrupt-parent = <&gic>; - interrupt-controller; - reg = <0 0x0c000000 0 0x40000>, /* GICD */ - <0 0x0c080000 0 0x200000>; /* GICR */ - - interrupts = ; - }; - - uart0: serial@11002000 { - compatible = "mediatek,mt6577-uart"; - reg = <0 0x11002000 0 0x400>; - interrupts = ; - clocks = <&infracfg CLK_INFRA_UART0_SEL>, - <&infracfg CLK_INFRA_UART0_CK>; - clock-names = "baud", "bus"; - assigned-clocks = <&topckgen CLK_TOP_UART_SEL>, - <&infracfg CLK_INFRA_UART0_SEL>; - assigned-clock-parents = <&topckgen CLK_TOP_CB_CKSQ_40M>, - <&topckgen CLK_TOP_UART_SEL>; - pinctrl-0 = <&uart0_pins>; - pinctrl-names = "default"; - status = "disabled"; - }; - - uart1: serial@11003000 { - compatible = "mediatek,mt6577-uart"; - reg = <0 0x11003000 0 0x400>; - interrupts = ; - clocks = <&infracfg CLK_INFRA_UART1_SEL>, - <&infracfg CLK_INFRA_UART1_CK>; - clock-names = "baud", "bus"; - assigned-clocks = <&topckgen CLK_TOP_UART_SEL>, - <&infracfg CLK_INFRA_UART1_SEL>; - assigned-clock-parents = <&topckgen CLK_TOP_CB_CKSQ_40M>, - <&topckgen CLK_TOP_UART_SEL>; - status = "disabled"; - }; - - uart2: serial@11004000 { - compatible = "mediatek,mt6577-uart"; - reg = <0 0x11004000 0 0x400>; - interrupts = ; - clocks = <&infracfg CLK_INFRA_UART2_SEL>, - <&infracfg CLK_INFRA_UART2_CK>; - clock-names = "baud", "bus"; - assigned-clocks = <&topckgen CLK_TOP_UART_SEL>, - <&infracfg CLK_INFRA_UART2_SEL>; - assigned-clock-parents = <&topckgen CLK_TOP_CB_CKSQ_40M>, - <&topckgen CLK_TOP_UART_SEL>; - status = "disabled"; - }; - - i2c0: i2c@11007000 { - compatible = "mediatek,mt7981-i2c"; - reg = <0 0x11007000 0 0x1000>, - <0 0x10217080 0 0x80>; - interrupts = ; - clock-div = <1>; - clocks = <&infracfg CLK_INFRA_I2C0_CK>, - <&infracfg CLK_INFRA_AP_DMA_CK>, - <&infracfg CLK_INFRA_I2C_MCK_CK>, - <&infracfg CLK_INFRA_I2C_PCK_CK>; - clock-names = "main", "dma", "arb", "pmic"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - pcie: pcie@11280000 { - compatible = "mediatek,mt7981-pcie", - "mediatek,mt7986-pcie"; - device_type = "pci"; - reg = <0 0x11280000 0 0x4000>; - reg-names = "pcie-mac"; - #address-cells = <3>; - #size-cells = <2>; - interrupts = ; - bus-range = <0x00 0xff>; - ranges = <0x82000000 0 0x20000000 - 0x0 0x20000000 0 0x10000000>; - status = "disabled"; - - clocks = <&infracfg CLK_INFRA_IPCIE_CK>, - <&infracfg CLK_INFRA_IPCIE_PIPE_CK>, - <&infracfg CLK_INFRA_IPCIER_CK>, - <&infracfg CLK_INFRA_IPCIEB_CK>; - - phys = <&u3port0 PHY_TYPE_PCIE>; - phy-names = "pcie-phy"; - - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 7>; - interrupt-map = <0 0 0 1 &pcie_intc 0>, - <0 0 0 2 &pcie_intc 1>, - <0 0 0 3 &pcie_intc 2>, - <0 0 0 4 &pcie_intc 3>; - pcie_intc: interrupt-controller { - interrupt-controller; - #address-cells = <0>; - #interrupt-cells = <1>; - }; - }; - - crypto: crypto@10320000 { - compatible = "inside-secure,safexcel-eip97"; - reg = <0 0x10320000 0 0x40000>; - interrupts = , - , - , - ; - interrupt-names = "ring0", "ring1", "ring2", "ring3"; - clocks = <&topckgen CLK_TOP_EIP97B>; - clock-names = "top_eip97_ck"; - assigned-clocks = <&topckgen CLK_TOP_EIP97B_SEL>; - assigned-clock-parents = <&topckgen CLK_TOP_CB_NET1_D5>; - }; - - pio: pinctrl@11d00000 { - compatible = "mediatek,mt7981-pinctrl"; - reg = <0 0x11d00000 0 0x1000>, - <0 0x11c00000 0 0x1000>, - <0 0x11c10000 0 0x1000>, - <0 0x11d20000 0 0x1000>, - <0 0x11e00000 0 0x1000>, - <0 0x11e20000 0 0x1000>, - <0 0x11f00000 0 0x1000>, - <0 0x11f10000 0 0x1000>, - <0 0x1000b000 0 0x1000>; - reg-names = "gpio", "iocfg_rt", "iocfg_rm", - "iocfg_rb", "iocfg_lb", "iocfg_bl", - "iocfg_tm", "iocfg_tl", "eint"; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pio 0 0 56>; - interrupt-controller; - interrupts = ; - interrupt-parent = <&gic>; - #interrupt-cells = <2>; - - mdio_pins: mdc-mdio-pins { - mux { - function = "eth"; - groups = "smi_mdc_mdio"; - }; - }; - - uart0_pins: uart0-pins { - mux { - function = "uart"; - groups = "uart0"; - }; - }; - - wifi_dbdc_pins: wifi-dbdc-pins { - mux { - function = "eth"; - groups = "wf0_mode1"; - }; - conf { - pins = "WF_HB1", "WF_HB2", "WF_HB3", "WF_HB4", - "WF_HB0", "WF_HB0_B", "WF_HB5", "WF_HB6", - "WF_HB7", "WF_HB8", "WF_HB9", "WF_HB10", - "WF_TOP_CLK", "WF_TOP_DATA", "WF_XO_REQ", - "WF_CBA_RESETB", "WF_DIG_RESETB"; - drive-strength = <4>; - }; - }; - - gbe_led0_pins: gbe-led0-pins { - mux { - function = "led"; - groups = "gbe_led0"; - }; - }; - - gbe_led1_pins: gbe-led1-pins { - mux { - function = "led"; - groups = "gbe_led1"; - }; - }; - }; - - ethsys: syscon@15000000 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "mediatek,mt7981-ethsys", - "mediatek,mt7986-ethsys", - "syscon"; - reg = <0 0x15000000 0 0x1000>; - #clock-cells = <1>; - #reset-cells = <1>; - }; - - wed: wed@15010000 { - compatible = "mediatek,mt7981-wed", - "mediatek,mt7986-wed", - "syscon"; - reg = <0 0x15010000 0 0x1000>; - interrupt-parent = <&gic>; - interrupts = ; - memory-region = <&wo_emi0>, <&wo_data>; - memory-region-names = "wo-emi", "wo-data"; - mediatek,wo-ccif = <&wo_ccif0>; - mediatek,wo-ilm = <&wo_ilm0>; - mediatek,wo-dlm = <&wo_dlm0>; - mediatek,wo-cpuboot = <&wo_cpuboot>; - }; - - eth: ethernet@15100000 { - compatible = "mediatek,mt7981-eth"; - reg = <0 0x15100000 0 0x80000>; - interrupts = , - , - , - ; - clocks = <ðsys CLK_ETH_FE_EN>, - <ðsys CLK_ETH_GP2_EN>, - <ðsys CLK_ETH_GP1_EN>, - <ðsys CLK_ETH_WOCPU0_EN>, - <&sgmiisys0 CLK_SGM0_TX_EN>, - <&sgmiisys0 CLK_SGM0_RX_EN>, - <&sgmiisys0 CLK_SGM0_CK0_EN>, - <&sgmiisys0 CLK_SGM0_CDR_CK0_EN>, - <&sgmiisys1 CLK_SGM1_TX_EN>, - <&sgmiisys1 CLK_SGM1_RX_EN>, - <&sgmiisys1 CLK_SGM1_CK1_EN>, - <&sgmiisys1 CLK_SGM1_CDR_CK1_EN>, - <&topckgen CLK_TOP_SGM_REG>, - <&topckgen CLK_TOP_NETSYS_SEL>, - <&topckgen CLK_TOP_NETSYS_500M_SEL>; - clock-names = "fe", "gp2", "gp1", "wocpu0", - "sgmii_tx250m", "sgmii_rx250m", - "sgmii_cdr_ref", "sgmii_cdr_fb", - "sgmii2_tx250m", "sgmii2_rx250m", - "sgmii2_cdr_ref", "sgmii2_cdr_fb", - "sgmii_ck", "netsys0", "netsys1"; - assigned-clocks = <&topckgen CLK_TOP_NETSYS_2X_SEL>, - <&topckgen CLK_TOP_SGM_325M_SEL>; - assigned-clock-parents = <&topckgen CLK_TOP_CB_NET2_800M>, - <&topckgen CLK_TOP_CB_SGM_325M>; - mediatek,ethsys = <ðsys>; - mediatek,sgmiisys = <&sgmiisys0>, <&sgmiisys1>; - mediatek,infracfg = <&topmisc>; - mediatek,wed = <&wed>; - #reset-cells = <1>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - - mdio_bus: mdio-bus { - #address-cells = <1>; - #size-cells = <0>; - - int_gbe_phy: ethernet-phy@0 { - reg = <0>; - compatible = "ethernet-phy-ieee802.3-c22"; - phy-mode = "gmii"; - phy-is-integrated; - nvmem-cells = <&phy_calibration>; - nvmem-cell-names = "phy-cal-data"; - - leds { - #address-cells = <1>; - #size-cells = <0>; - - int_gbe_phy_led0: int-gbe-phy-led0@0 { - reg = <0>; - function = LED_FUNCTION_LAN; - status = "disabled"; - }; - - int_gbe_phy_led1: int-gbe-phy-led1@1 { - reg = <1>; - function = LED_FUNCTION_LAN; - status = "disabled"; - }; - }; - }; - }; - }; - - wo_dlm0: syscon@151e8000 { - compatible = "mediatek,mt7986-wo-dlm", "syscon"; - reg = <0 0x151e8000 0 0x2000>; - }; - - wo_ilm0: syscon@151e0000 { - compatible = "mediatek,mt7986-wo-ilm", "syscon"; - reg = <0 0x151e0000 0 0x8000>; - }; - - wo_cpuboot: syscon@15194000 { - compatible = "mediatek,mt7986-wo-cpuboot", "syscon"; - reg = <0 0x15194000 0 0x1000>; - }; - - wo_ccif0: syscon@151a5000 { - compatible = "mediatek,mt7986-wo-ccif", "syscon"; - reg = <0 0x151a5000 0 0x1000>; - interrupt-parent = <&gic>; - interrupts = ; - }; - - sgmiisys0: syscon@10060000 { - compatible = "mediatek,mt7981-sgmiisys_0", "mediatek,mt7986-sgmiisys_0", "syscon"; - reg = <0 0x10060000 0 0x1000>; - mediatek,pnswap; - #clock-cells = <1>; - }; - - sgmiisys1: syscon@10070000 { - compatible = "mediatek,mt7981-sgmiisys_1", "mediatek,mt7986-sgmiisys_1", "syscon"; - reg = <0 0x10070000 0 0x1000>; - #clock-cells = <1>; - }; - - topmisc: topmisc@11d10000 { - compatible = "mediatek,mt7981-topmisc", "syscon"; - reg = <0 0x11d10000 0 0x10000>; - #clock-cells = <1>; - }; - - snand: snfi@11005000 { - compatible = "mediatek,mt7986-snand"; - reg = <0 0x11005000 0 0x1000>, <0 0x11006000 0 0x1000>; - reg-names = "nfi", "ecc"; - interrupts = ; - clocks = <&infracfg CLK_INFRA_SPINFI1_CK>, - <&infracfg CLK_INFRA_NFI1_CK>, - <&infracfg CLK_INFRA_NFI_HCK_CK>; - clock-names = "pad_clk", "nfi_clk", "nfi_hclk"; - assigned-clocks = <&topckgen CLK_TOP_SPINFI_SEL>, - <&topckgen CLK_TOP_NFI1X_SEL>; - assigned-clock-parents = <&topckgen CLK_TOP_CB_M_D8>, - <&topckgen CLK_TOP_CB_M_D8>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - mmc0: mmc@11230000 { - compatible = "mediatek,mt7986-mmc", - "mediatek,mt7981-mmc"; - reg = <0 0x11230000 0 0x1000>, <0 0x11c20000 0 0x1000>; - interrupts = ; - clocks = <&infracfg CLK_INFRA_MSDC_CK>, - <&infracfg CLK_INFRA_MSDC_HCK_CK>, - <&infracfg CLK_INFRA_MSDC_66M_CK>, - <&infracfg CLK_INFRA_MSDC_133M_CK>; - assigned-clocks = <&topckgen CLK_TOP_EMMC_208M_SEL>, - <&topckgen CLK_TOP_EMMC_400M_SEL>; - assigned-clock-parents = <&topckgen CLK_TOP_CB_M_D2>, - <&topckgen CLK_TOP_CB_NET2_D2>; - clock-names = "source", "hclk", "axi_cg", "ahb_cg"; - status = "disabled"; - }; - - wed_pcie: wed_pcie@10003000 { - compatible = "mediatek,wed_pcie"; - reg = <0 0x10003000 0 0x10>; - }; - - spi0: spi@1100a000 { - compatible = "mediatek,mt7986-spi-ipm", "mediatek,spi-ipm"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0 0x1100a000 0 0x100>; - interrupts = ; - clocks = <&topckgen CLK_TOP_CB_M_D2>, - <&topckgen CLK_TOP_SPI_SEL>, - <&infracfg CLK_INFRA_SPI0_CK>, - <&infracfg CLK_INFRA_SPI0_HCK_CK>; - - clock-names = "parent-clk", "sel-clk", "spi-clk", "hclk"; - status = "disabled"; - }; - - spi1: spi@1100b000 { - compatible = "mediatek,mt7986-spi-ipm", "mediatek,spi-ipm"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0 0x1100b000 0 0x100>; - interrupts = ; - clocks = <&topckgen CLK_TOP_CB_M_D2>, - <&topckgen CLK_TOP_SPIM_MST_SEL>, - <&infracfg CLK_INFRA_SPI1_CK>, - <&infracfg CLK_INFRA_SPI1_HCK_CK>; - clock-names = "parent-clk", "sel-clk", "spi-clk", "hclk"; - status = "disabled"; - }; - - spi2: spi@11009000 { - compatible = "mediatek,mt7986-spi-ipm", "mediatek,spi-ipm"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0 0x11009000 0 0x100>; - interrupts = ; - clocks = <&topckgen CLK_TOP_CB_M_D2>, - <&topckgen CLK_TOP_SPI_SEL>, - <&infracfg CLK_INFRA_SPI2_CK>, - <&infracfg CLK_INFRA_SPI2_HCK_CK>; - clock-names = "parent-clk", "sel-clk", "spi-clk", "hclk"; - status = "disabled"; - }; - - consys: consys@10000000 { - compatible = "mediatek,mt7981-consys"; - reg = <0 0x10000000 0 0x8600000>; - memory-region = <&wmcpu_emi>; - }; - - xhci: usb@11200000 { - compatible = "mediatek,mt7986-xhci", - "mediatek,mtk-xhci"; - reg = <0 0x11200000 0 0x2e00>, - <0 0x11203e00 0 0x0100>; - reg-names = "mac", "ippc"; - interrupts = ; - clocks = <&infracfg CLK_INFRA_IUSB_SYS_CK>, - <&infracfg CLK_INFRA_IUSB_CK>, - <&infracfg CLK_INFRA_IUSB_133_CK>, - <&infracfg CLK_INFRA_IUSB_66M_CK>, - <&topckgen CLK_TOP_U2U3_XHCI_SEL>; - clock-names = "sys_ck", - "ref_ck", - "mcu_ck", - "dma_ck", - "xhci_ck"; - phys = <&u2port0 PHY_TYPE_USB2>, - <&u3port0 PHY_TYPE_USB3>; - vusb33-supply = <®_3p3v>; - status = "disabled"; - }; - - usb_phy: usb-phy@11e10000 { - compatible = "mediatek,mt7981", - "mediatek,generic-tphy-v2"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0 0x11e10000 0x1700>; - status = "disabled"; - - u2port0: usb-phy@0 { - reg = <0x0 0x700>; - clocks = <&topckgen CLK_TOP_USB_FRMCNT_SEL>; - clock-names = "ref"; - #phy-cells = <1>; - }; - - u3port0: usb-phy@700 { - reg = <0x700 0x900>; - clocks = <&topckgen CLK_TOP_USB3_PHY_SEL>; - clock-names = "ref"; - #phy-cells = <1>; - mediatek,syscon-type = <&topmisc 0x218 0>; - status = "okay"; - }; - }; - - reg_3p3v: regulator-3p3v { - compatible = "regulator-fixed"; - regulator-name = "fixed-3.3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - efuse: efuse@11f20000 { - compatible = "mediatek,mt7981-efuse", - "mediatek,efuse"; - reg = <0 0x11f20000 0 0x1000>; - #address-cells = <1>; - #size-cells = <1>; - status = "okay"; - - thermal_calibration: thermal-calib@274 { - reg = <0x274 0xc>; - }; - - phy_calibration: phy-calib@8dc { - reg = <0x8dc 0x10>; - }; - - comb_rx_imp_p0: usb3-rx-imp@8c8 { - reg = <0x8c8 1>; - bits = <0 5>; - }; - - comb_tx_imp_p0: usb3-tx-imp@8c8 { - reg = <0x8c8 2>; - bits = <5 5>; - }; - - comb_intr_p0: usb3-intr@8c9 { - reg = <0x8c9 1>; - bits = <2 6>; - }; - }; - - afe: audio-controller@11210000 { - compatible = "mediatek,mt79xx-audio"; - reg = <0 0x11210000 0 0x9000>; - interrupts = ; - clocks = <&infracfg CLK_INFRA_AUD_BUS_CK>, - <&infracfg CLK_INFRA_AUD_26M_CK>, - <&infracfg CLK_INFRA_AUD_L_CK>, - <&infracfg CLK_INFRA_AUD_AUD_CK>, - <&infracfg CLK_INFRA_AUD_EG2_CK>, - <&topckgen CLK_TOP_AUD_SEL>; - clock-names = "aud_bus_ck", - "aud_26m_ck", - "aud_l_ck", - "aud_aud_ck", - "aud_eg2_ck", - "aud_sel"; - assigned-clocks = <&topckgen CLK_TOP_AUD_SEL>, - <&topckgen CLK_TOP_A1SYS_SEL>, - <&topckgen CLK_TOP_AUD_L_SEL>, - <&topckgen CLK_TOP_A_TUNER_SEL>; - assigned-clock-parents = <&topckgen CLK_TOP_CB_APLL2_196M>, - <&topckgen CLK_TOP_APLL2_D4>, - <&topckgen CLK_TOP_CB_APLL2_196M>, - <&topckgen CLK_TOP_APLL2_D4>; - status = "disabled"; - }; - - ice: ice_debug { - compatible = "mediatek,mt7981-ice_debug", - "mediatek,mt2701-ice_debug"; - clocks = <&infracfg CLK_INFRA_DBG_CK>; - clock-names = "ice_dbg"; - }; - - wifi: wifi@18000000 { - compatible = "mediatek,mt7981-wmac"; - resets = <&watchdog MT7986_TOPRGU_CONSYS_SW_RST>; - reset-names = "consys"; - pinctrl-0 = <&wifi_dbdc_pins>; - pinctrl-names = "dbdc"; - clocks = <&topckgen CLK_TOP_NETSYS_MCU_SEL>, - <&topckgen CLK_TOP_AP2CNN_HOST_SEL>; - clock-names = "mcu", "ap2conn"; - reg = <0 0x18000000 0 0x1000000>, - <0 0x10003000 0 0x1000>, - <0 0x11d10000 0 0x1000>; - interrupts = , - , - , - ; - memory-region = <&wmcpu_emi>; - status = "disabled"; + trng { + compatible = "mediatek,mt7981-rng"; }; }; diff --git a/lede/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7986a-rfb-spim-nand.dts b/lede/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7986a-rfb-spim-nand.dts index 83a37150cf..ce007099d2 100644 --- a/lede/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7986a-rfb-spim-nand.dts +++ b/lede/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7986a-rfb-spim-nand.dts @@ -15,8 +15,8 @@ compatible = "spi-nand"; reg = <1>; spi-max-frequency = <10000000>; - spi-tx-buswidth = <4>; - spi-rx-buswidth = <4>; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; partitions { compatible = "fixed-partitions"; diff --git a/lede/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7986a-rfb-spim-nor.dts b/lede/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7986a-rfb-spim-nor.dts index 868365a994..ea148315f0 100644 --- a/lede/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7986a-rfb-spim-nor.dts +++ b/lede/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7986a-rfb-spim-nor.dts @@ -15,8 +15,8 @@ compatible = "jedec,spi-nor"; reg = <0>; spi-max-frequency = <52000000>; - spi-tx-buswidth = <4>; - spi-rx-buswidth = <4>; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; partitions { compatible = "fixed-partitions"; #address-cells = <1>; diff --git a/lede/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dtsi b/lede/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dtsi index 1ab56e37f7..26d560bd4b 100644 --- a/lede/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dtsi +++ b/lede/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dtsi @@ -99,7 +99,7 @@ reg = <6>; }; - switch: switch@0 { + switch: switch@1f { compatible = "mediatek,mt7531"; reg = <31>; reset-gpios = <&pio 5 0>; diff --git a/lede/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts b/lede/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts index b4bf3400ff..68f30eba6d 100644 --- a/lede/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts +++ b/lede/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts @@ -14,9 +14,11 @@ / { model = "Bananapi BPI-R4"; compatible = "bananapi,bpi-r4", - "mediatek,mt7988"; + "mediatek,mt7988a"; aliases { + ethernet0 = &gmac0; + ethernet1 = &gmac1; serial0 = &uart0; led-boot = &led_green; led-failsafe = &led_green; @@ -26,7 +28,7 @@ chosen { stdout-path = &uart0; - bootargs = "console=ttyS0,115200n1 loglevel=8 pci=pcie_bus_perf ubi.block=0,fit root=/dev/fit0"; + bootargs = "console=ttyS0,115200n1 loglevel=8 pci=pcie_bus_perf ubi.block=0,fit root=/dev/fit0 rootwait"; rootdisk-spim-nand = <&ubi_rootfs>; }; @@ -320,6 +322,15 @@ status = "okay"; }; +&pwm { + status = "okay"; +}; + +&fan { + pwms = <&pwm 0 50000>; + status = "okay"; +}; + &ssusb1 { status = "okay"; }; @@ -386,6 +397,18 @@ status = "okay"; }; +&uart1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart1_2_lite_pins>; +}; + +&uart2 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart2_3_pins>; +}; + &watchdog { status = "okay"; }; diff --git a/lede/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a-rfb-snfi-nand.dtso b/lede/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a-rfb-snfi-nand.dtso index 6180165177..86b0042f64 100644 --- a/lede/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a-rfb-snfi-nand.dtso +++ b/lede/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a-rfb-snfi-nand.dtso @@ -19,8 +19,8 @@ compatible = "spi-nand"; reg = <0>; spi-max-frequency = <52000000>; - spi-tx-buswidth = <4>; - spi-rx-buswidth = <4>; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; mediatek,nmbm; mediatek,bmt-max-ratio = <1>; mediatek,bmt-max-reserved-blocks = <64>; diff --git a/lede/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a-rfb-spim-nand.dtso b/lede/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a-rfb-spim-nand.dtso index e63436fa55..a9eca00d44 100644 --- a/lede/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a-rfb-spim-nand.dtso +++ b/lede/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a-rfb-spim-nand.dtso @@ -21,8 +21,8 @@ compatible = "spi-nand"; reg = <0>; spi-max-frequency = <52000000>; - spi-tx-buswidth = <4>; - spi-rx-buswidth = <4>; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; mediatek,nmbm; mediatek,bmt-max-ratio = <1>; mediatek,bmt-max-reserved-blocks = <64>; diff --git a/lede/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a-rfb.dts b/lede/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a-rfb.dts index 11dbf98301..5012e7a498 100644 --- a/lede/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a-rfb.dts +++ b/lede/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a-rfb.dts @@ -13,7 +13,7 @@ / { model = "MediaTek MT7988A Reference Board"; compatible = "mediatek,mt7988a-rfb", - "mediatek,mt7988"; + "mediatek,mt7988a"; chosen { bootargs = "console=ttyS0,115200n1 loglevel=8 \ diff --git a/lede/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a.dtsi b/lede/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a.dtsi index 50b04e7773..3bc9f08c40 100644 --- a/lede/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a.dtsi +++ b/lede/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a.dtsi @@ -10,95 +10,24 @@ #include #include #include -#include +#include #include +/* TOPRGU resets */ +#define MT7988_TOPRGU_SGMII0_GRST 1 +#define MT7988_TOPRGU_SGMII1_GRST 2 +#define MT7988_TOPRGU_XFI0_GRST 12 +#define MT7988_TOPRGU_XFI1_GRST 13 +#define MT7988_TOPRGU_XFI_PEXTP0_GRST 14 +#define MT7988_TOPRGU_XFI_PEXTP1_GRST 15 +#define MT7988_TOPRGU_XFI_PLL_GRST 16 + / { - compatible = "mediatek,mt7988"; + compatible = "mediatek,mt7988a"; interrupt-parent = <&gic>; #address-cells = <2>; #size-cells = <2>; - clk40m: oscillator@0 { - compatible = "fixed-clock"; - clock-frequency = <40000000>; - #clock-cells = <0>; - clock-output-names = "clkxtal"; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - cpu0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a73"; - enable-method = "psci"; - reg = <0x0>; - clocks = <&mcusys CLK_MCU_ARM_DIV_SEL>, - <&topckgen CLK_TOP_XTAL>; - clock-names = "cpu", "intermediate"; - operating-points-v2 = <&cluster0_opp>; - mediatek,cci = <&cci>; - }; - - cpu1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a73"; - enable-method = "psci"; - reg = <0x1>; - clocks = <&mcusys CLK_MCU_ARM_DIV_SEL>, - <&topckgen CLK_TOP_XTAL>; - clock-names = "cpu", "intermediate"; - operating-points-v2 = <&cluster0_opp>; - mediatek,cci = <&cci>; - }; - - cpu2: cpu@2 { - device_type = "cpu"; - compatible = "arm,cortex-a73"; - enable-method = "psci"; - reg = <0x2>; - clocks = <&mcusys CLK_MCU_ARM_DIV_SEL>, - <&topckgen CLK_TOP_XTAL>; - clock-names = "cpu", "intermediate"; - operating-points-v2 = <&cluster0_opp>; - mediatek,cci = <&cci>; - }; - - cpu3: cpu@3 { - device_type = "cpu"; - compatible = "arm,cortex-a73"; - enable-method = "psci"; - reg = <0x3>; - clocks = <&mcusys CLK_MCU_ARM_DIV_SEL>, - <&topckgen CLK_TOP_XTAL>; - clock-names = "cpu", "intermediate"; - operating-points-v2 = <&cluster0_opp>; - mediatek,cci = <&cci>; - }; - - cluster0_opp: opp_table0 { - compatible = "operating-points-v2"; - opp-shared; - opp00 { - opp-hz = /bits/ 64 <800000000>; - opp-microvolt = <850000>; - }; - opp01 { - opp-hz = /bits/ 64 <1100000000>; - opp-microvolt = <850000>; - }; - opp02 { - opp-hz = /bits/ 64 <1500000000>; - opp-microvolt = <850000>; - }; - opp03 { - opp-hz = /bits/ 64 <1800000000>; - opp-microvolt = <900000>; - }; - }; - }; - cci: cci { compatible = "mediatek,mt7988-cci", "mediatek,mt8183-cci"; @@ -108,27 +37,125 @@ operating-points-v2 = <&cci_opp>; }; + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + compatible = "arm,cortex-a73"; + reg = <0x0>; + device_type = "cpu"; + enable-method = "psci"; + clocks = <&mcusys CLK_MCU_ARM_DIV_SEL>, + <&topckgen CLK_TOP_XTAL>; + clock-names = "cpu", "intermediate"; + operating-points-v2 = <&cluster0_opp>; + mediatek,cci = <&cci>; + }; + + cpu1: cpu@1 { + compatible = "arm,cortex-a73"; + reg = <0x1>; + device_type = "cpu"; + enable-method = "psci"; + clocks = <&mcusys CLK_MCU_ARM_DIV_SEL>, + <&topckgen CLK_TOP_XTAL>; + clock-names = "cpu", "intermediate"; + operating-points-v2 = <&cluster0_opp>; + mediatek,cci = <&cci>; + }; + + cpu2: cpu@2 { + compatible = "arm,cortex-a73"; + reg = <0x2>; + device_type = "cpu"; + enable-method = "psci"; + clocks = <&mcusys CLK_MCU_ARM_DIV_SEL>, + <&topckgen CLK_TOP_XTAL>; + clock-names = "cpu", "intermediate"; + operating-points-v2 = <&cluster0_opp>; + mediatek,cci = <&cci>; + }; + + cpu3: cpu@3 { + compatible = "arm,cortex-a73"; + reg = <0x3>; + device_type = "cpu"; + enable-method = "psci"; + clocks = <&mcusys CLK_MCU_ARM_DIV_SEL>, + <&topckgen CLK_TOP_XTAL>; + clock-names = "cpu", "intermediate"; + operating-points-v2 = <&cluster0_opp>; + mediatek,cci = <&cci>; + }; + + cluster0_opp: opp_table0 { + compatible = "operating-points-v2"; + opp-shared; + + opp00 { + opp-hz = /bits/ 64 <800000000>; + opp-microvolt = <850000>; + }; + + opp01 { + opp-hz = /bits/ 64 <1100000000>; + opp-microvolt = <850000>; + }; + + opp02 { + opp-hz = /bits/ 64 <1500000000>; + opp-microvolt = <850000>; + }; + + opp03 { + opp-hz = /bits/ 64 <1800000000>; + opp-microvolt = <900000>; + }; + }; + }; + cci_opp: opp_table_cci { compatible = "operating-points-v2"; opp-shared; + opp00 { opp-hz = /bits/ 64 <480000000>; opp-microvolt = <850000>; }; + opp01 { opp-hz = /bits/ 64 <660000000>; opp-microvolt = <850000>; }; + opp02 { opp-hz = /bits/ 64 <900000000>; opp-microvolt = <850000>; }; + opp03 { opp-hz = /bits/ 64 <1080000000>; opp-microvolt = <900000>; }; }; + clk40m: oscillator@0 { + compatible = "fixed-clock"; + clock-frequency = <40000000>; + #clock-cells = <0>; + clock-output-names = "clkxtal"; + }; + + fan: pwm-fan { + compatible = "pwm-fan"; + /* cooling level (0, 1, 2, 3) : (0% duty, 30% duty, 50% duty, 100% duty) */ + cooling-levels = <0 80 128 255>; + #cooling-cells = <2>; + #thermal-sensor-cells = <1>; + status = "disabled"; + }; + pmu { compatible = "arm,cortex-a73-pmu"; interrupt-parent = <&gic>; @@ -136,88 +163,8 @@ }; psci { - compatible = "arm,psci-0.2"; - method = "smc"; - }; - - reserved-memory { - #address-cells = <2>; - #size-cells = <2>; - ranges; - - /* 320 KiB reserved for ARM Trusted Firmware (BL31 and BL32) */ - secmon_reserved: secmon@43000000 { - reg = <0 0x43000000 0 0x50000>; - no-map; - }; - }; - - thermal-zones { - cpu_thermal: cpu-thermal { - polling-delay-passive = <1000>; - polling-delay = <1000>; - thermal-sensors = <&lvts 0>; - trips { - cpu_trip_crit: crit { - temperature = <125000>; - hysteresis = <2000>; - type = "critical"; - }; - - cpu_trip_hot: hot { - temperature = <120000>; - hysteresis = <2000>; - type = "hot"; - }; - - cpu_trip_active_high: active-high { - temperature = <115000>; - hysteresis = <2000>; - type = "active"; - }; - - cpu_trip_active_med: active-med { - temperature = <85000>; - hysteresis = <2000>; - type = "active"; - }; - - cpu_trip_active_low: active-low { - temperature = <40000>; - hysteresis = <2000>; - type = "active"; - }; - }; - - cooling-maps { - cpu-active-high { - /* active: set fan to cooling level 2 */ - cooling-device = <&fan 3 3>; - trip = <&cpu_trip_active_high>; - }; - - cpu-active-low { - /* active: set fan to cooling level 1 */ - cooling-device = <&fan 2 2>; - trip = <&cpu_trip_active_med>; - }; - - cpu-passive { - /* passive: set fan to cooling level 0 */ - cooling-device = <&fan 1 1>; - trip = <&cpu_trip_active_low>; - }; - }; - }; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupt-parent = <&gic>; - interrupts = , - , - , - ; + compatible = "arm,psci-0.2"; + method = "smc"; }; reg_1p8v: regulator-1p8v { @@ -238,37 +185,48 @@ regulator-always-on; }; - soc { + reserved-memory { + ranges; #address-cells = <2>; #size-cells = <2>; + + /* 320 KiB reserved for ARM Trusted Firmware (BL31 and BL32) */ + secmon_reserved: secmon@43000000 { + reg = <0 0x43000000 0 0x50000>; + no-map; + }; + }; + + soc { compatible = "simple-bus"; ranges; + #address-cells = <2>; + #size-cells = <2>; gic: interrupt-controller@c000000 { compatible = "arm,gic-v3"; - #interrupt-cells = <3>; - interrupt-parent = <&gic>; - interrupt-controller; reg = <0 0x0c000000 0 0x40000>, /* GICD */ <0 0x0c080000 0 0x200000>, /* GICR */ <0 0x0c400000 0 0x2000>, /* GICC */ <0 0x0c410000 0 0x1000>, /* GICH */ <0 0x0c420000 0 0x2000>; /* GICV */ - + interrupt-parent = <&gic>; interrupts = ; + interrupt-controller; + #interrupt-cells = <3>; }; phyfw: phy-firmware@f000000 { compatible = "mediatek,2p5gphy-fw"; - reg = <0 0x0f000000 0 0x8000>, - <0 0x0f100000 0 0x20000>, - <0 0x0f0f0000 0 0x200>; + reg = <0 0x0f100000 0 0x20000>, + <0 0x0f0f0018 0 0x20>; }; infracfg: infracfg@10001000 { compatible = "mediatek,mt7988-infracfg", "syscon"; reg = <0 0x10001000 0 0x1000>; #clock-cells = <1>; + #reset-cells = <1>; }; topckgen: topckgen@1001b000 { @@ -295,12 +253,12 @@ pio: pinctrl@1001f000 { compatible = "mediatek,mt7988-pinctrl", "syscon"; reg = <0 0x1001f000 0 0x1000>, - <0 0x11c10000 0 0x1000>, - <0 0x11d00000 0 0x1000>, - <0 0x11d20000 0 0x1000>, - <0 0x11e00000 0 0x1000>, - <0 0x11f00000 0 0x1000>, - <0 0x1000b000 0 0x1000>; + <0 0x11c10000 0 0x1000>, + <0 0x11d00000 0 0x1000>, + <0 0x11d20000 0 0x1000>, + <0 0x11e00000 0 0x1000>, + <0 0x11f00000 0 0x1000>, + <0 0x1000b000 0 0x1000>; reg-names = "gpio_base", "iocfg_tr_base", "iocfg_br_base", "iocfg_rb_base", "iocfg_lb_base", "iocfg_tl_base", "eint"; @@ -464,6 +422,69 @@ }; }; + uart1_0_pins: uart1-0-pins { + mux { + function = "uart"; + groups = "uart1_0"; + }; + }; + + uart1_1_pins: uart1-1-pins { + mux { + function = "uart"; + groups = "uart1_1"; + }; + }; + + uart1_2_pins: uart1-2-pins { + mux { + function = "uart"; + groups = "uart1_2"; + }; + }; + + uart1_2_lite_pins: uart1-2-lite-pins { + mux { + function = "uart"; + groups = "uart1_2_lite"; + }; + }; + + uart2_pins: uart2-pins { + mux { + function = "uart"; + groups = "uart2"; + }; + }; + + uart2_0_pins: uart2-0-pins { + mux { + function = "uart"; + groups = "uart2_0"; + }; + }; + + uart2_1_pins: uart2-1-pins { + mux { + function = "uart"; + groups = "uart2_1"; + }; + }; + + uart2_2_pins: uart2-2-pins { + mux { + function = "uart"; + groups = "uart2_2"; + }; + }; + + uart2_3_pins: uart2-3-pins { + mux { + function = "uart"; + groups = "uart2_3"; + }; + }; + snfi_pins: snfi-pins { mux { function = "flash"; @@ -539,58 +560,73 @@ }; }; + pwm: pwm@10048000 { + compatible = "mediatek,mt7988-pwm"; + reg = <0 0x10048000 0 0x1000>; + #pwm-cells = <2>; + clocks = <&infracfg CLK_INFRA_66M_PWM_BCK>, + <&infracfg CLK_INFRA_66M_PWM_HCK>, + <&infracfg CLK_INFRA_66M_PWM_CK1>, + <&infracfg CLK_INFRA_66M_PWM_CK2>, + <&infracfg CLK_INFRA_66M_PWM_CK3>, + <&infracfg CLK_INFRA_66M_PWM_CK4>, + <&infracfg CLK_INFRA_66M_PWM_CK5>, + <&infracfg CLK_INFRA_66M_PWM_CK6>, + <&infracfg CLK_INFRA_66M_PWM_CK7>, + <&infracfg CLK_INFRA_66M_PWM_CK8>; + clock-names = "top", "main", "pwm1", "pwm2", "pwm3", + "pwm4","pwm5","pwm6","pwm7","pwm8"; + status = "disabled"; + }; + sgmiisys0: syscon@10060000 { compatible = "mediatek,mt7988-sgmiisys", - "mediatek,mt7988-sgmiisys_0", - "syscon"; + "mediatek,mt7988-sgmiisys0", + "syscon", + "simple-mfd"; reg = <0 0x10060000 0 0x1000>; + resets = <&watchdog MT7988_TOPRGU_SGMII0_GRST>; #clock-cells = <1>; + + sgmiipcs0: pcs { + compatible = "mediatek,mt7988-sgmii"; + clocks = <&topckgen CLK_TOP_SGM_0_SEL>, + <&sgmiisys0 CLK_SGM0_TX_EN>, + <&sgmiisys0 CLK_SGM0_RX_EN>; + clock-names = "sgmii_sel", "sgmii_tx", "sgmii_rx"; + }; }; sgmiisys1: syscon@10070000 { compatible = "mediatek,mt7988-sgmiisys", - "mediatek,mt7988-sgmiisys_1", - "syscon"; + "mediatek,mt7988-sgmiisys1", + "syscon", + "simple-mfd"; reg = <0 0x10070000 0 0x1000>; + resets = <&watchdog MT7988_TOPRGU_SGMII1_GRST>; #clock-cells = <1>; + + sgmiipcs1: pcs { + compatible = "mediatek,mt7988-sgmii"; + clocks = <&topckgen CLK_TOP_SGM_1_SEL>, + <&sgmiisys1 CLK_SGM1_TX_EN>, + <&sgmiisys1 CLK_SGM1_RX_EN>; + clock-names = "sgmii_sel", "sgmii_tx", "sgmii_rx"; + }; }; - usxgmiisys0: usxgmiisys@10080000 { - compatible = "mediatek,mt7988-usxgmiisys", - "mediatek,mt7988-usxgmiisys_0", - "syscon"; + usxgmiisys0: pcs@10080000 { + compatible = "mediatek,mt7988-usxgmiisys"; reg = <0 0x10080000 0 0x1000>; - #clock-cells = <1>; + resets = <&watchdog MT7988_TOPRGU_XFI0_GRST>; + clocks = <&topckgen CLK_TOP_USXGMII_SBUS_0_SEL>; }; - usxgmiisys1: usxgmiisys@10081000 { - compatible = "mediatek,mt7988-usxgmiisys", - "mediatek,mt7988-usxgmiisys_1", - "syscon"; + usxgmiisys1: pcs@10081000 { + compatible = "mediatek,mt7988-usxgmiisys"; reg = <0 0x10081000 0 0x1000>; - #clock-cells = <1>; - }; - - xfi_pextp0: xfi-pextp@11f20000 { - compatible = "mediatek,mt7988-xfi-pextp", - "mediatek,mt7988-xfi-pextp_0", - "syscon"; - reg = <0 0x11f20000 0 0x10000>; - #clock-cells = <1>; - }; - - xfi_pextp1: xfi-pextp@11f30000 { - compatible = "mediatek,mt7988-xfi-pextp", - "mediatek,mt7988-xfi-pextp_1", - "syscon"; - reg = <0 0x11f30000 0 0x10000>; - #clock-cells = <1>; - }; - - xfi_pll: xfi-pll@11f40000 { - compatible = "mediatek,mt7988-xfi-pll", "syscon"; - reg = <0 0x11f40000 0 0x1000>; - #clock-cells = <1>; + resets = <&watchdog MT7988_TOPRGU_XFI1_GRST>; + clocks = <&topckgen CLK_TOP_USXGMII_SBUS_1_SEL>; }; mcusys: mcusys@100e0000 { @@ -621,6 +657,46 @@ status = "disabled"; }; + uart1: serial@11000100 { + compatible = "mediatek,mt7986-uart", + "mediatek,mt6577-uart"; + reg = <0 0x11000100 0 0x100>; + interrupts = ; + /* + * 8250-mtk driver don't control "baud" clock since commit + * e32a83c70cf9 (kernel v5.7), but both "baud" and "bus" clocks + * still need to be passed to the driver to prevent probe fail + */ + clocks = <&topckgen CLK_TOP_UART_SEL>, + <&infracfg CLK_INFRA_52M_UART1_CK>; + clock-names = "baud", "bus"; + assigned-clocks = <&topckgen CLK_TOP_UART_SEL>, + <&infracfg CLK_INFRA_MUX_UART1_SEL>; + assigned-clock-parents = <&topckgen CLK_TOP_XTAL>, + <&topckgen CLK_TOP_UART_SEL>; + status = "disabled"; + }; + + uart2: serial@11000200 { + compatible = "mediatek,mt7986-uart", + "mediatek,mt6577-uart"; + reg = <0 0x11000200 0 0x100>; + interrupts = ; + /* + * 8250-mtk driver don't control "baud" clock since commit + * e32a83c70cf9 (kernel v5.7), but both "baud" and "bus" clocks + * still need to be passed to the driver to prevent probe fail + */ + clocks = <&topckgen CLK_TOP_UART_SEL>, + <&infracfg CLK_INFRA_52M_UART2_CK>; + clock-names = "baud", "bus"; + assigned-clocks = <&topckgen CLK_TOP_UART_SEL>, + <&infracfg CLK_INFRA_MUX_UART2_SEL>; + assigned-clock-parents = <&topckgen CLK_TOP_XTAL>, + <&topckgen CLK_TOP_UART_SEL>; + status = "disabled"; + }; + snand: spi@11001000 { compatible = "mediatek,mt7986-snand"; reg = <0 0x11001000 0 0x1000>; @@ -742,241 +818,16 @@ status = "disabled"; }; - pwm: pwm@10048000 { - compatible = "mediatek,mt7988-pwm"; - reg = <0 0x10048000 0 0x1000>; - #pwm-cells = <2>; - clocks = <&infracfg CLK_INFRA_66M_PWM_BCK>, - <&infracfg CLK_INFRA_66M_PWM_HCK>, - <&infracfg CLK_INFRA_66M_PWM_CK1>, - <&infracfg CLK_INFRA_66M_PWM_CK2>, - <&infracfg CLK_INFRA_66M_PWM_CK3>, - <&infracfg CLK_INFRA_66M_PWM_CK4>, - <&infracfg CLK_INFRA_66M_PWM_CK5>, - <&infracfg CLK_INFRA_66M_PWM_CK6>, - <&infracfg CLK_INFRA_66M_PWM_CK7>, - <&infracfg CLK_INFRA_66M_PWM_CK8>; - clock-names = "top", "main", "pwm1", "pwm2", "pwm3", - "pwm4","pwm5","pwm6","pwm7","pwm8"; - status = "disabled"; - }; - - fan: pwm-fan { - compatible = "pwm-fan"; - /* cooling level (0, 1, 2) : (0% duty, 50% duty, 100% duty) */ - cooling-levels = <0 128 255>; - #cooling-cells = <2>; - #thermal-sensor-cells = <1>; - status = "disabled"; - }; - lvts: lvts@1100a000 { - compatible = "mediatek,mt7988-lvts"; - #thermal-sensor-cells = <1>; + compatible = "mediatek,mt7988-lvts-ap"; reg = <0 0x1100a000 0 0x1000>; clocks = <&infracfg CLK_INFRA_26M_THERM_SYSTEM>; clock-names = "lvts_clk"; + interrupts = ; + resets = <&infracfg MT7988_INFRA_RST1_THERM_CTRL_SWRST>; nvmem-cells = <&lvts_calibration>; - nvmem-cell-names = "e_data1"; - }; - - crypto: crypto@15600000 { - compatible = "inside-secure,safexcel-eip197b"; - reg = <0 0x15600000 0 0x180000>; - interrupts = , - , - , - ; - interrupt-names = "ring0", "ring1", "ring2", "ring3"; - status = "okay"; - }; - - afe: audio-controller@11210000 { - compatible = "mediatek,mt79xx-audio"; - reg = <0 0x11210000 0 0x9000>; - interrupts = ; - clocks = <&infracfg CLK_INFRA_66M_AUD_SLV_BCK>, - <&infracfg CLK_INFRA_AUD_26M>, - <&infracfg CLK_INFRA_AUD_L>, - <&infracfg CLK_INFRA_AUD_AUD>, - <&infracfg CLK_INFRA_AUD_EG2>, - <&topckgen CLK_TOP_AUD_SEL>, - <&topckgen CLK_TOP_AUD_I2S_M>; - clock-names = "aud_bus_ck", - "aud_26m_ck", - "aud_l_ck", - "aud_aud_ck", - "aud_eg2_ck", - "aud_sel", - "aud_i2s_m"; - assigned-clocks = <&topckgen CLK_TOP_AUD_SEL>, - <&topckgen CLK_TOP_A1SYS_SEL>, - <&topckgen CLK_TOP_AUD_L_SEL>, - <&topckgen CLK_TOP_A_TUNER_SEL>; - assigned-clock-parents = <&apmixedsys CLK_APMIXED_APLL2>, - <&topckgen CLK_TOP_APLL2_D4>, - <&apmixedsys CLK_APMIXED_APLL2>, - <&topckgen CLK_TOP_APLL2_D4>; - status = "disabled"; - }; - - pcie2: pcie@11280000 { - compatible = "mediatek,mt7988-pcie", - "mediatek,mt7986-pcie", - "mediatek,mt8192-pcie"; - device_type = "pci"; - #address-cells = <3>; - #size-cells = <2>; - reg = <0 0x11280000 0 0x2000>; - reg-names = "pcie-mac"; - linux,pci-domain = <3>; - interrupts = ; - bus-range = <0x00 0xff>; - ranges = <0x81000000 0x00 0x20000000 0x00 - 0x20000000 0x00 0x00200000>, - <0x82000000 0x00 0x20200000 0x00 - 0x20200000 0x00 0x07e00000>; - clocks = <&infracfg CLK_INFRA_PCIE_PIPE_P2>, - <&infracfg CLK_INFRA_PCIE_GFMUX_TL_P2>, - <&infracfg CLK_INFRA_PCIE_PERI_26M_CK_P2>, - <&infracfg CLK_INFRA_133M_PCIE_CK_P2>; - clock-names = "pl_250m", "tl_26m", "peri_26m", - "top_133m"; - pinctrl-names = "default"; - pinctrl-0 = <&pcie2_pins>; - status = "disabled"; - - phys = <&xphyu3port0 PHY_TYPE_PCIE>; - phy-names = "pcie-phy"; - - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0x7>; - interrupt-map = <0 0 0 1 &pcie_intc2 0>, - <0 0 0 2 &pcie_intc2 1>, - <0 0 0 3 &pcie_intc2 2>, - <0 0 0 4 &pcie_intc2 3>; - pcie_intc2: interrupt-controller { - #address-cells = <0>; - #interrupt-cells = <1>; - interrupt-controller; - }; - }; - - pcie3: pcie@11290000 { - compatible = "mediatek,mt7988-pcie", - "mediatek,mt7986-pcie", - "mediatek,mt8192-pcie"; - device_type = "pci"; - #address-cells = <3>; - #size-cells = <2>; - reg = <0 0x11290000 0 0x2000>; - reg-names = "pcie-mac"; - linux,pci-domain = <2>; - interrupts = ; - bus-range = <0x00 0xff>; - ranges = <0x81000000 0x00 0x28000000 0x00 - 0x28000000 0x00 0x00200000>, - <0x82000000 0x00 0x28200000 0x00 - 0x28200000 0x00 0x07e00000>; - clocks = <&infracfg CLK_INFRA_PCIE_PIPE_P3>, - <&infracfg CLK_INFRA_PCIE_GFMUX_TL_P3>, - <&infracfg CLK_INFRA_PCIE_PERI_26M_CK_P3>, - <&infracfg CLK_INFRA_133M_PCIE_CK_P3>; - clock-names = "pl_250m", "tl_26m", "peri_26m", - "top_133m"; - pinctrl-names = "default"; - pinctrl-0 = <&pcie3_pins>; - status = "disabled"; - - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0x7>; - interrupt-map = <0 0 0 1 &pcie_intc3 0>, - <0 0 0 2 &pcie_intc3 1>, - <0 0 0 3 &pcie_intc3 2>, - <0 0 0 4 &pcie_intc3 3>; - pcie_intc3: interrupt-controller { - #address-cells = <0>; - #interrupt-cells = <1>; - interrupt-controller; - }; - }; - - pcie0: pcie@11300000 { - compatible = "mediatek,mt7988-pcie", - "mediatek,mt7986-pcie", - "mediatek,mt8192-pcie"; - device_type = "pci"; - #address-cells = <3>; - #size-cells = <2>; - reg = <0 0x11300000 0 0x2000>; - reg-names = "pcie-mac"; - linux,pci-domain = <0>; - interrupts = ; - bus-range = <0x00 0xff>; - ranges = <0x81000000 0x00 0x30000000 0x00 - 0x30000000 0x00 0x00200000>, - <0x82000000 0x00 0x30200000 0x00 - 0x30200000 0x00 0x07e00000>; - clocks = <&infracfg CLK_INFRA_PCIE_PIPE_P0>, - <&infracfg CLK_INFRA_PCIE_GFMUX_TL_P0>, - <&infracfg CLK_INFRA_PCIE_PERI_26M_CK_P0>, - <&infracfg CLK_INFRA_133M_PCIE_CK_P0>; - clock-names = "pl_250m", "tl_26m", "peri_26m", - "top_133m"; - pinctrl-names = "default"; - pinctrl-0 = <&pcie0_pins>; - status = "disabled"; - - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0x7>; - interrupt-map = <0 0 0 1 &pcie_intc0 0>, - <0 0 0 2 &pcie_intc0 1>, - <0 0 0 3 &pcie_intc0 2>, - <0 0 0 4 &pcie_intc0 3>; - pcie_intc0: interrupt-controller { - #address-cells = <0>; - #interrupt-cells = <1>; - interrupt-controller; - }; - }; - - pcie1: pcie@11310000 { - compatible = "mediatek,mt7988-pcie", - "mediatek,mt7986-pcie", - "mediatek,mt8192-pcie"; - device_type = "pci"; - #address-cells = <3>; - #size-cells = <2>; - reg = <0 0x11310000 0 0x2000>; - reg-names = "pcie-mac"; - linux,pci-domain = <1>; - interrupts = ; - bus-range = <0x00 0xff>; - ranges = <0x81000000 0x00 0x38000000 0x00 - 0x38000000 0x00 0x00200000>, - <0x82000000 0x00 0x38200000 0x00 - 0x38200000 0x00 0x07e00000>; - clocks = <&infracfg CLK_INFRA_PCIE_PIPE_P1>, - <&infracfg CLK_INFRA_PCIE_GFMUX_TL_P1>, - <&infracfg CLK_INFRA_PCIE_PERI_26M_CK_P1>, - <&infracfg CLK_INFRA_133M_PCIE_CK_P1>; - clock-names = "pl_250m", "tl_26m", "peri_26m", - "top_133m"; - pinctrl-names = "default"; - pinctrl-0 = <&pcie1_pins>; - status = "disabled"; - - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0x7>; - interrupt-map = <0 0 0 1 &pcie_intc1 0>, - <0 0 0 2 &pcie_intc1 1>, - <0 0 0 3 &pcie_intc1 2>, - <0 0 0 4 &pcie_intc1 3>; - pcie_intc1: interrupt-controller { - #address-cells = <0>; - #interrupt-cells = <1>; - interrupt-controller; - }; + nvmem-cell-names = "lvts-calib-data-1"; + #thermal-sensor-cells = <1>; }; ssusb0: usb@11190000 { @@ -1028,6 +879,35 @@ status = "disabled"; }; + afe: audio-controller@11210000 { + compatible = "mediatek,mt79xx-audio"; + reg = <0 0x11210000 0 0x9000>; + interrupts = ; + clocks = <&infracfg CLK_INFRA_66M_AUD_SLV_BCK>, + <&infracfg CLK_INFRA_AUD_26M>, + <&infracfg CLK_INFRA_AUD_L>, + <&infracfg CLK_INFRA_AUD_AUD>, + <&infracfg CLK_INFRA_AUD_EG2>, + <&topckgen CLK_TOP_AUD_SEL>, + <&topckgen CLK_TOP_AUD_I2S_M>; + clock-names = "aud_bus_ck", + "aud_26m_ck", + "aud_l_ck", + "aud_aud_ck", + "aud_eg2_ck", + "aud_sel", + "aud_i2s_m"; + assigned-clocks = <&topckgen CLK_TOP_AUD_SEL>, + <&topckgen CLK_TOP_A1SYS_SEL>, + <&topckgen CLK_TOP_AUD_L_SEL>, + <&topckgen CLK_TOP_A_TUNER_SEL>; + assigned-clock-parents = <&apmixedsys CLK_APMIXED_APLL2>, + <&topckgen CLK_TOP_APLL2_D4>, + <&apmixedsys CLK_APMIXED_APLL2>, + <&topckgen CLK_TOP_APLL2_D4>; + status = "disabled"; + }; + mmc0: mmc@11230000 { compatible = "mediatek,mt7986-mmc", "mediatek,mt7981-mmc"; @@ -1051,19 +931,183 @@ status = "disabled"; }; + pcie2: pcie@11280000 { + compatible = "mediatek,mt7988-pcie", + "mediatek,mt7986-pcie", + "mediatek,mt8192-pcie"; + reg = <0 0x11280000 0 0x2000>; + reg-names = "pcie-mac"; + ranges = <0x81000000 0x00 0x20000000 0x00 + 0x20000000 0x00 0x00200000>, + <0x82000000 0x00 0x20200000 0x00 + 0x20200000 0x00 0x07e00000>; + device_type = "pci"; + linux,pci-domain = <3>; + interrupts = ; + bus-range = <0x00 0xff>; + clocks = <&infracfg CLK_INFRA_PCIE_PIPE_P2>, + <&infracfg CLK_INFRA_PCIE_GFMUX_TL_P2>, + <&infracfg CLK_INFRA_PCIE_PERI_26M_CK_P2>, + <&infracfg CLK_INFRA_133M_PCIE_CK_P2>, + <&topckgen CLK_TOP_PEXTP_P2_SEL>; + clock-names = "pl_250m", "tl_26m", "peri_26m", + "top_133m", "pextp_clk"; + pinctrl-names = "default"; + pinctrl-0 = <&pcie2_pins>; + phys = <&xphyu3port0 PHY_TYPE_PCIE>; + phy-names = "pcie-phy"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &pcie_intc2 0>, + <0 0 0 2 &pcie_intc2 1>, + <0 0 0 3 &pcie_intc2 2>, + <0 0 0 4 &pcie_intc2 3>; + #address-cells = <3>; + #size-cells = <2>; + status = "disabled"; + + pcie_intc2: interrupt-controller { + #address-cells = <0>; + #interrupt-cells = <1>; + interrupt-controller; + }; + }; + + pcie3: pcie@11290000 { + compatible = "mediatek,mt7988-pcie", + "mediatek,mt7986-pcie", + "mediatek,mt8192-pcie"; + reg = <0 0x11290000 0 0x2000>; + reg-names = "pcie-mac"; + ranges = <0x81000000 0x00 0x28000000 0x00 + 0x28000000 0x00 0x00200000>, + <0x82000000 0x00 0x28200000 0x00 + 0x28200000 0x00 0x07e00000>; + device_type = "pci"; + linux,pci-domain = <2>; + interrupts = ; + bus-range = <0x00 0xff>; + clocks = <&infracfg CLK_INFRA_PCIE_PIPE_P3>, + <&infracfg CLK_INFRA_PCIE_GFMUX_TL_P3>, + <&infracfg CLK_INFRA_PCIE_PERI_26M_CK_P3>, + <&infracfg CLK_INFRA_133M_PCIE_CK_P3>, + <&topckgen CLK_TOP_PEXTP_P3_SEL>; + clock-names = "pl_250m", "tl_26m", "peri_26m", + "top_133m", "pextp_clk"; + pinctrl-names = "default"; + pinctrl-0 = <&pcie3_pins>; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &pcie_intc3 0>, + <0 0 0 2 &pcie_intc3 1>, + <0 0 0 3 &pcie_intc3 2>, + <0 0 0 4 &pcie_intc3 3>; + #address-cells = <3>; + #size-cells = <2>; + status = "disabled"; + + pcie_intc3: interrupt-controller { + #address-cells = <0>; + #interrupt-cells = <1>; + interrupt-controller; + }; + }; + + pcie0: pcie@11300000 { + compatible = "mediatek,mt7988-pcie", + "mediatek,mt7986-pcie", + "mediatek,mt8192-pcie"; + reg = <0 0x11300000 0 0x2000>; + reg-names = "pcie-mac"; + ranges = <0x81000000 0x00 0x30000000 0x00 + 0x30000000 0x00 0x00200000>, + <0x82000000 0x00 0x30200000 0x00 + 0x30200000 0x00 0x07e00000>; + device_type = "pci"; + linux,pci-domain = <0>; + interrupts = ; + bus-range = <0x00 0xff>; + clocks = <&infracfg CLK_INFRA_PCIE_PIPE_P0>, + <&infracfg CLK_INFRA_PCIE_GFMUX_TL_P0>, + <&infracfg CLK_INFRA_PCIE_PERI_26M_CK_P0>, + <&infracfg CLK_INFRA_133M_PCIE_CK_P0>, + <&topckgen CLK_TOP_PEXTP_P0_SEL>; + clock-names = "pl_250m", "tl_26m", "peri_26m", + "top_133m", "pextp_clk"; + pinctrl-names = "default"; + pinctrl-0 = <&pcie0_pins>; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &pcie_intc0 0>, + <0 0 0 2 &pcie_intc0 1>, + <0 0 0 3 &pcie_intc0 2>, + <0 0 0 4 &pcie_intc0 3>; + #address-cells = <3>; + #size-cells = <2>; + status = "disabled"; + + pcie_intc0: interrupt-controller { + #address-cells = <0>; + #interrupt-cells = <1>; + interrupt-controller; + }; + }; + + pcie1: pcie@11310000 { + compatible = "mediatek,mt7988-pcie", + "mediatek,mt7986-pcie", + "mediatek,mt8192-pcie"; + reg = <0 0x11310000 0 0x2000>; + reg-names = "pcie-mac"; + ranges = <0x81000000 0x00 0x38000000 0x00 + 0x38000000 0x00 0x00200000>, + <0x82000000 0x00 0x38200000 0x00 + 0x38200000 0x00 0x07e00000>; + device_type = "pci"; + linux,pci-domain = <1>; + interrupts = ; + bus-range = <0x00 0xff>; + clocks = <&infracfg CLK_INFRA_PCIE_PIPE_P1>, + <&infracfg CLK_INFRA_PCIE_GFMUX_TL_P1>, + <&infracfg CLK_INFRA_PCIE_PERI_26M_CK_P1>, + <&infracfg CLK_INFRA_133M_PCIE_CK_P1>, + <&topckgen CLK_TOP_PEXTP_P1_SEL>; + clock-names = "pl_250m", "tl_26m", "peri_26m", + "top_133m", "pextp_clk"; + pinctrl-names = "default"; + pinctrl-0 = <&pcie1_pins>; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &pcie_intc1 0>, + <0 0 0 2 &pcie_intc1 1>, + <0 0 0 3 &pcie_intc1 2>, + <0 0 0 4 &pcie_intc1 3>; + #address-cells = <3>; + #size-cells = <2>; + status = "disabled"; + + pcie_intc1: interrupt-controller { + #address-cells = <0>; + #interrupt-cells = <1>; + interrupt-controller; + }; + }; + tphy: tphy@11c50000 { compatible = "mediatek,mt7988", "mediatek,generic-tphy-v2"; + ranges; #address-cells = <2>; #size-cells = <2>; - ranges; status = "disabled"; + tphyu2port0: usb-phy@11c50000 { reg = <0 0x11c50000 0 0x700>; clocks = <&infracfg CLK_INFRA_USB_UTMI_CK_P1>; clock-names = "ref"; #phy-cells = <1>; }; + tphyu3port0: usb-phy@11c50700 { reg = <0 0x11c50700 0 0x900>; clocks = <&infracfg CLK_INFRA_USB_PIPE_CK_P1>; @@ -1087,9 +1131,9 @@ xphy: xphy@11e10000 { compatible = "mediatek,mt7988", "mediatek,xsphy"; + ranges; #address-cells = <2>; #size-cells = <2>; - ranges; status = "disabled"; xphyu2port0: usb-phy@11e10000 { @@ -1108,6 +1152,32 @@ }; }; + xfi_tphy0: phy@11f20000 { + compatible = "mediatek,mt7988-xfi-tphy"; + reg = <0 0x11f20000 0 0x10000>; + resets = <&watchdog MT7988_TOPRGU_XFI_PEXTP0_GRST>; + clocks = <&xfi_pll CLK_XFIPLL_PLL_EN>, <&topckgen CLK_TOP_XFI_PHY_0_XTAL_SEL>; + clock-names = "xfipll", "topxtal"; + mediatek,usxgmii-performance-errata; + #phy-cells = <0>; + }; + + xfi_tphy1: phy@11f30000 { + compatible = "mediatek,mt7988-xfi-tphy"; + reg = <0 0x11f30000 0 0x10000>; + resets = <&watchdog MT7988_TOPRGU_XFI_PEXTP1_GRST>; + clocks = <&xfi_pll CLK_XFIPLL_PLL_EN>, <&topckgen CLK_TOP_XFI_PHY_1_XTAL_SEL>; + clock-names = "xfipll", "topxtal"; + #phy-cells = <0>; + }; + + xfi_pll: clock-controller@11f40000 { + compatible = "mediatek,mt7988-xfi-pll"; + reg = <0 0x11f40000 0 0x1000>; + resets = <&watchdog MT7988_TOPRGU_XFI_PLL_GRST>; + #clock-cells = <1>; + }; + efuse: efuse@11f50000 { compatible = "mediatek,efuse"; reg = <0 0x11f50000 0 0x1000>; @@ -1117,42 +1187,47 @@ lvts_calibration: calib@918 { reg = <0x918 0x28>; }; + phy_calibration_p0: calib@940 { reg = <0x940 0x10>; }; + phy_calibration_p1: calib@954 { reg = <0x954 0x10>; }; + phy_calibration_p2: calib@968 { reg = <0x968 0x10>; }; + phy_calibration_p3: calib@97c { reg = <0x97c 0x10>; }; + cpufreq_calibration: calib@278 { reg = <0x278 0x1>; }; }; ethsys: syscon@15000000 { - #address-cells = <1>; - #size-cells = <1>; compatible = "mediatek,mt7988-ethsys", "syscon"; reg = <0 0x15000000 0 0x1000>; #clock-cells = <1>; #reset-cells = <1>; + #address-cells = <1>; + #size-cells = <1>; }; switch: switch@15020000 { - #address-cells = <1>; - #size-cells = <1>; compatible = "mediatek,mt7988-switch"; reg = <0 0x15020000 0 0x8000>; interrupt-controller; #interrupt-cells = <1>; interrupt-parent = <&gic>; interrupts = ; - resets = <ðrst 0>; + resets = <ðwarp MT7988_ETHWARP_RST_SWITCH>; + #address-cells = <1>; + #size-cells = <1>; ports { #address-cells = <1>; @@ -1306,18 +1381,11 @@ }; }; - ethwarp: syscon@15031000 { - compatible = "mediatek,mt7988-ethwarp", "syscon", "simple-mfd"; + ethwarp: clock-controller@15031000 { + compatible = "mediatek,mt7988-ethwarp"; reg = <0 0x15031000 0 0x1000>; #clock-cells = <1>; - - ethrst: reset-controller { - compatible = "ti,syscon-reset"; - #reset-cells = <1>; - ti,reset-bits = < - 0x8 9 0x8 9 0 0 (ASSERT_SET | DEASSERT_CLEAR | STATUS_NONE) - >; - }; + #reset-cells = <1>; }; eth: ethernet@15100000 { @@ -1337,19 +1405,9 @@ <ðsys CLK_ETHDMA_GP3_EN>, <ðsys CLK_ETHDMA_ESW_EN>, <ðsys CLK_ETHDMA_CRYPT0_EN>, - <&sgmiisys0 CLK_SGM0_TX_EN>, - <&sgmiisys0 CLK_SGM0_RX_EN>, - <&sgmiisys1 CLK_SGM1_TX_EN>, - <&sgmiisys1 CLK_SGM1_RX_EN>, <ðwarp CLK_ETHWARP_WOCPU2_EN>, <ðwarp CLK_ETHWARP_WOCPU1_EN>, <ðwarp CLK_ETHWARP_WOCPU0_EN>, - <&topckgen CLK_TOP_USXGMII_SBUS_0_SEL>, - <&topckgen CLK_TOP_USXGMII_SBUS_1_SEL>, - <&topckgen CLK_TOP_SGM_0_SEL>, - <&topckgen CLK_TOP_SGM_1_SEL>, - <&topckgen CLK_TOP_XFI_PHY_0_XTAL_SEL>, - <&topckgen CLK_TOP_XFI_PHY_1_XTAL_SEL>, <&topckgen CLK_TOP_ETH_GMII_SEL>, <&topckgen CLK_TOP_ETH_REFCK_50M_SEL>, <&topckgen CLK_TOP_ETH_SYS_200M_SEL>, @@ -1363,13 +1421,9 @@ <&topckgen CLK_TOP_NETSYS_PPEFB_250M_SEL>, <&topckgen CLK_TOP_NETSYS_WARP_SEL>; clock-names = "xgp1", "xgp2", "xgp3", "fe", "gp2", "gp1", - "gp3", "esw", "crypto", "sgmii_tx250m", - "sgmii_rx250m", "sgmii2_tx250m", "sgmii2_rx250m", + "gp3", "esw", "crypto", "ethwarp_wocpu2", "ethwarp_wocpu1", - "ethwarp_wocpu0", "top_usxgmii0_sel", - "top_usxgmii1_sel", "top_sgm0_sel", - "top_sgm1_sel", "top_xfi_phy0_xtal_sel", - "top_xfi_phy1_xtal_sel", "top_eth_gmii_sel", + "ethwarp_wocpu0", "top_eth_gmii_sel", "top_eth_refck_50m_sel", "top_eth_sys_200m_sel", "top_eth_sys_sel", "top_eth_xgmii_sel", "top_eth_mii_sel", "top_netsys_sel", @@ -1390,13 +1444,7 @@ <&apmixedsys CLK_APMIXED_SGMPLL>, <&apmixedsys CLK_APMIXED_SGMPLL>; mediatek,ethsys = <ðsys>; - mediatek,sgmiisys = <&sgmiisys0>, <&sgmiisys1>; - mediatek,usxgmiisys = <&usxgmiisys0>, <&usxgmiisys1>; - mediatek,xfi-pextp = <&xfi_pextp0>, <&xfi_pextp1>; - mediatek,xfi-pll = <&xfi_pll>; mediatek,infracfg = <&topmisc>; - mediatek,toprgu = <&watchdog>; - #reset-cells = <1>; #address-cells = <1>; #size-cells = <0>; @@ -1417,12 +1465,16 @@ compatible = "mediatek,eth-mac"; reg = <1>; status = "disabled"; + pcs-handle = <&sgmiipcs1>, <&usxgmiisys1>; + phys = <&xfi_tphy1>; }; gmac2: mac@2 { compatible = "mediatek,eth-mac"; reg = <2>; status = "disabled"; + pcs-handle = <&sgmiipcs0>, <&usxgmiisys0>; + phys = <&xfi_tphy0>; }; mdio_bus: mdio-bus { @@ -1431,11 +1483,91 @@ /* internal 2.5G PHY */ int_2p5g_phy: ethernet-phy@15 { - reg = <15>; compatible = "ethernet-phy-ieee802.3-c45"; + reg = <15>; phy-mode = "internal"; }; }; }; + + crypto: crypto@15600000 { + compatible = "inside-secure,safexcel-eip197b"; + reg = <0 0x15600000 0 0x180000>; + interrupts = , + , + , + ; + interrupt-names = "ring0", "ring1", "ring2", "ring3"; + status = "okay"; + }; + }; + + thermal-zones { + cpu_thermal: cpu-thermal { + polling-delay-passive = <1000>; + polling-delay = <1000>; + thermal-sensors = <&lvts 0>; + + trips { + cpu_trip_crit: crit { + temperature = <125000>; + hysteresis = <2000>; + type = "critical"; + }; + + cpu_trip_hot: hot { + temperature = <120000>; + hysteresis = <2000>; + type = "hot"; + }; + + cpu_trip_active_high: active-high { + temperature = <115000>; + hysteresis = <2000>; + type = "active"; + }; + + cpu_trip_active_med: active-med { + temperature = <85000>; + hysteresis = <2000>; + type = "active"; + }; + + cpu_trip_active_low: active-low { + temperature = <40000>; + hysteresis = <2000>; + type = "active"; + }; + }; + + cooling-maps { + cpu-active-high { + /* active: set fan to cooling level 2 */ + cooling-device = <&fan 3 3>; + trip = <&cpu_trip_active_high>; + }; + + cpu-active-low { + /* active: set fan to cooling level 1 */ + cooling-device = <&fan 2 2>; + trip = <&cpu_trip_active_med>; + }; + + cpu-passive { + /* passive: set fan to cooling level 0 */ + cooling-device = <&fan 1 1>; + trip = <&cpu_trip_active_low>; + }; + }; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupt-parent = <&gic>; + interrupts = , + , + , + ; }; }; diff --git a/lede/target/linux/mediatek/files-6.1/drivers/clk/mediatek/clk-mt7988-apmixed.c b/lede/target/linux/mediatek/files-6.1/drivers/clk/mediatek/clk-mt7988-apmixed.c deleted file mode 100644 index 3f1edc231e..0000000000 --- a/lede/target/linux/mediatek/files-6.1/drivers/clk/mediatek/clk-mt7988-apmixed.c +++ /dev/null @@ -1,113 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (c) 2023 MediaTek Inc. - * Author: Sam Shih - * Author: Xiufeng Li - */ - -#include -#include -#include -#include -#include -#include "clk-mtk.h" -#include "clk-gate.h" -#include "clk-mux.h" -#include "clk-pll.h" -#include - -#define MT7988_PLL_FMAX (2500UL * MHZ) -#define MT7988_PCW_CHG_SHIFT 2 - -#define PLL_xtal(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _rst_bar_mask, \ - _pcwbits, _pd_reg, _pd_shift, _tuner_reg, _tuner_en_reg, \ - _tuner_en_bit, _pcw_reg, _pcw_shift, _pcw_chg_reg, \ - _div_table) \ - { \ - .id = _id, .name = _name, .reg = _reg, .pwr_reg = _pwr_reg, \ - .en_mask = _en_mask, .flags = _flags, \ - .rst_bar_mask = BIT(_rst_bar_mask), .fmax = MT7988_PLL_FMAX, \ - .pcwbits = _pcwbits, .pd_reg = _pd_reg, \ - .pd_shift = _pd_shift, .tuner_reg = _tuner_reg, \ - .tuner_en_reg = _tuner_en_reg, .tuner_en_bit = _tuner_en_bit, \ - .pcw_reg = _pcw_reg, .pcw_shift = _pcw_shift, \ - .pcw_chg_reg = _pcw_chg_reg, \ - .pcw_chg_shift = MT7988_PCW_CHG_SHIFT, \ - .div_table = _div_table, .parent_name = "clkxtal", \ - } - -#define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _rst_bar_mask, \ - _pcwbits, _pd_reg, _pd_shift, _tuner_reg, _tuner_en_reg, \ - _tuner_en_bit, _pcw_reg, _pcw_shift, _pcw_chg_reg) \ - PLL_xtal(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _rst_bar_mask, \ - _pcwbits, _pd_reg, _pd_shift, _tuner_reg, _tuner_en_reg, \ - _tuner_en_bit, _pcw_reg, _pcw_shift, _pcw_chg_reg, NULL) - -static const struct mtk_pll_data plls[] = { - PLL(CLK_APMIXED_NETSYSPLL, "netsyspll", 0x0104, 0x0110, 0x00000001, 0, - 0, 32, 0x0104, 4, 0, 0, 0, 0x0108, 0, 0x0104), - PLL(CLK_APMIXED_MPLL, "mpll", 0x0114, 0x0120, 0xff000001, HAVE_RST_BAR, - 23, 32, 0x0114, 4, 0, 0, 0, 0x0118, 0, 0x0114), - PLL(CLK_APMIXED_MMPLL, "mmpll", 0x0124, 0x0130, 0xff000001, - HAVE_RST_BAR, 23, 32, 0x0124, 4, 0, 0, 0, 0x0128, 0, 0x0124), - PLL(CLK_APMIXED_APLL2, "apll2", 0x0134, 0x0140, 0x00000001, 0, 0, 32, - 0x0134, 4, 0x0704, 0x0700, 1, 0x0138, 0, 0x0134), - PLL(CLK_APMIXED_NET1PLL, "net1pll", 0x0144, 0x0150, 0xff000001, - HAVE_RST_BAR, 23, 32, 0x0144, 4, 0, 0, 0, 0x0148, 0, 0x0144), - PLL(CLK_APMIXED_NET2PLL, "net2pll", 0x0154, 0x0160, 0xff000001, - (HAVE_RST_BAR | PLL_AO), 23, 32, 0x0154, 4, 0, 0, 0, 0x0158, 0, - 0x0154), - PLL(CLK_APMIXED_WEDMCUPLL, "wedmcupll", 0x0164, 0x0170, 0x00000001, 0, - 0, 32, 0x0164, 4, 0, 0, 0, 0x0168, 0, 0x0164), - PLL(CLK_APMIXED_SGMPLL, "sgmpll", 0x0174, 0x0180, 0x00000001, 0, 0, 32, - 0x0174, 4, 0, 0, 0, 0x0178, 0, 0x0174), - PLL(CLK_APMIXED_ARM_B, "arm_b", 0x0204, 0x0210, 0xff000001, - (HAVE_RST_BAR | PLL_AO), 23, 32, 0x0204, 4, 0, 0, 0, 0x0208, 0, - 0x0204), - PLL(CLK_APMIXED_CCIPLL2_B, "ccipll2_b", 0x0214, 0x0220, 0xff000001, - HAVE_RST_BAR, 23, 32, 0x0214, 4, 0, 0, 0, 0x0218, 0, 0x0214), - PLL(CLK_APMIXED_USXGMIIPLL, "usxgmiipll", 0x0304, 0x0310, 0xff000001, - HAVE_RST_BAR, 23, 32, 0x0304, 4, 0, 0, 0, 0x0308, 0, 0x0304), - PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x0314, 0x0320, 0x00000001, 0, 0, - 32, 0x0314, 4, 0, 0, 0, 0x0318, 0, 0x0314), -}; - -static const struct of_device_id of_match_clk_mt7988_apmixed[] = { - { .compatible = "mediatek,mt7988-apmixedsys", }, - { /* sentinel */ } -}; - -static int clk_mt7988_apmixed_probe(struct platform_device *pdev) -{ - struct clk_hw_onecell_data *clk_data; - struct device_node *node = pdev->dev.of_node; - int r; - - clk_data = mtk_alloc_clk_data(ARRAY_SIZE(plls)); - if (!clk_data) - return -ENOMEM; - - mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data); - - r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); - if (r) { - pr_err("%s(): could not register clock provider: %d\n", - __func__, r); - goto free_apmixed_data; - } - return r; - -free_apmixed_data: - mtk_free_clk_data(clk_data); - return r; -} - -static struct platform_driver clk_mt7988_apmixed_drv = { - .probe = clk_mt7988_apmixed_probe, - .driver = { - .name = "clk-mt7988-apmixed", - .of_match_table = of_match_clk_mt7988_apmixed, - }, -}; -builtin_platform_driver(clk_mt7988_apmixed_drv); -MODULE_LICENSE("GPL"); diff --git a/lede/target/linux/mediatek/files-6.1/drivers/clk/mediatek/clk-mt7988-eth.c b/lede/target/linux/mediatek/files-6.1/drivers/clk/mediatek/clk-mt7988-eth.c deleted file mode 100644 index 14b877f8cb..0000000000 --- a/lede/target/linux/mediatek/files-6.1/drivers/clk/mediatek/clk-mt7988-eth.c +++ /dev/null @@ -1,141 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (c) 2023 MediaTek Inc. - * Author: Sam Shih - * Author: Xiufeng Li - */ - -#include -#include -#include -#include -#include -#include "clk-mtk.h" -#include "clk-gate.h" -#include - -static const struct mtk_gate_regs ethdma_cg_regs = { - .set_ofs = 0x30, - .clr_ofs = 0x30, - .sta_ofs = 0x30, -}; - -#define GATE_ETHDMA(_id, _name, _parent, _shift) \ - { \ - .id = _id, .name = _name, .parent_name = _parent, \ - .regs = ðdma_cg_regs, .shift = _shift, \ - .ops = &mtk_clk_gate_ops_no_setclr_inv, \ - } - -static const struct mtk_gate ethdma_clks[] = { - GATE_ETHDMA(CLK_ETHDMA_XGP1_EN, "ethdma_xgp1_en", "top_xtal", 0), - GATE_ETHDMA(CLK_ETHDMA_XGP2_EN, "ethdma_xgp2_en", "top_xtal", 1), - GATE_ETHDMA(CLK_ETHDMA_XGP3_EN, "ethdma_xgp3_en", "top_xtal", 2), - GATE_ETHDMA(CLK_ETHDMA_FE_EN, "ethdma_fe_en", "netsys_2x_sel", 6), - GATE_ETHDMA(CLK_ETHDMA_GP2_EN, "ethdma_gp2_en", "top_xtal", 7), - GATE_ETHDMA(CLK_ETHDMA_GP1_EN, "ethdma_gp1_en", "top_xtal", 8), - GATE_ETHDMA(CLK_ETHDMA_GP3_EN, "ethdma_gp3_en", "top_xtal", 10), - GATE_ETHDMA(CLK_ETHDMA_ESW_EN, "ethdma_esw_en", "netsys_gsw_sel", 16), - GATE_ETHDMA(CLK_ETHDMA_CRYPT0_EN, "ethdma_crypt0_en", "eip197_sel", - 29), -}; - -static const struct mtk_clk_desc ethdma_desc = { - .clks = ethdma_clks, - .num_clks = ARRAY_SIZE(ethdma_clks), -}; - -static const struct mtk_gate_regs sgmii0_cg_regs = { - .set_ofs = 0xe4, - .clr_ofs = 0xe4, - .sta_ofs = 0xe4, -}; - -#define GATE_SGMII0(_id, _name, _parent, _shift) \ - { \ - .id = _id, .name = _name, .parent_name = _parent, \ - .regs = &sgmii0_cg_regs, .shift = _shift, \ - .ops = &mtk_clk_gate_ops_no_setclr_inv, \ - } - -static const struct mtk_gate sgmii0_clks[] = { - GATE_SGMII0(CLK_SGM0_TX_EN, "sgm0_tx_en", "top_xtal", 2), - GATE_SGMII0(CLK_SGM0_RX_EN, "sgm0_rx_en", "top_xtal", 3), -}; - -static const struct mtk_clk_desc sgmii0_desc = { - .clks = sgmii0_clks, - .num_clks = ARRAY_SIZE(sgmii0_clks), -}; - -static const struct mtk_gate_regs sgmii1_cg_regs = { - .set_ofs = 0xe4, - .clr_ofs = 0xe4, - .sta_ofs = 0xe4, -}; - -#define GATE_SGMII1(_id, _name, _parent, _shift) \ - { \ - .id = _id, .name = _name, .parent_name = _parent, \ - .regs = &sgmii1_cg_regs, .shift = _shift, \ - .ops = &mtk_clk_gate_ops_no_setclr_inv, \ - } - -static const struct mtk_gate sgmii1_clks[] = { - GATE_SGMII1(CLK_SGM1_TX_EN, "sgm1_tx_en", "top_xtal", 2), - GATE_SGMII1(CLK_SGM1_RX_EN, "sgm1_rx_en", "top_xtal", 3), -}; - -static const struct mtk_clk_desc sgmii1_desc = { - .clks = sgmii1_clks, - .num_clks = ARRAY_SIZE(sgmii1_clks), -}; - -static const struct mtk_gate_regs ethwarp_cg_regs = { - .set_ofs = 0x14, - .clr_ofs = 0x14, - .sta_ofs = 0x14, -}; - -#define GATE_ETHWARP(_id, _name, _parent, _shift) \ - { \ - .id = _id, .name = _name, .parent_name = _parent, \ - .regs = ðwarp_cg_regs, .shift = _shift, \ - .ops = &mtk_clk_gate_ops_no_setclr_inv, \ - } - -static const struct mtk_gate ethwarp_clks[] = { - GATE_ETHWARP(CLK_ETHWARP_WOCPU2_EN, "ethwarp_wocpu2_en", - "netsys_mcu_sel", 13), - GATE_ETHWARP(CLK_ETHWARP_WOCPU1_EN, "ethwarp_wocpu1_en", - "netsys_mcu_sel", 14), - GATE_ETHWARP(CLK_ETHWARP_WOCPU0_EN, "ethwarp_wocpu0_en", - "netsys_mcu_sel", 15), -}; - -static const struct mtk_clk_desc ethwarp_desc = { - .clks = ethwarp_clks, - .num_clks = ARRAY_SIZE(ethwarp_clks), -}; - -static const struct of_device_id of_match_clk_mt7986_eth[] = { - { .compatible = "mediatek,mt7988-ethsys", .data = ðdma_desc }, - { .compatible = "mediatek,mt7988-sgmiisys_0", .data = &sgmii0_desc }, - { .compatible = "mediatek,mt7988-sgmiisys_1", .data = &sgmii1_desc }, - { .compatible = "mediatek,mt7988-ethwarp", .data = ðwarp_desc }, - { /* sentinel */ } -}; -MODULE_DEVICE_TABLE(of, of_match_clk_mt7988_eth); - -static struct platform_driver clk_mt7988_eth_drv = { - .driver = { - .name = "clk-mt7988-eth", - .of_match_table = of_match_clk_mt7986_eth, - }, - .probe = mtk_clk_simple_probe, - .remove = mtk_clk_simple_remove, -}; -module_platform_driver(clk_mt7988_eth_drv); - -MODULE_DESCRIPTION("MediaTek MT7988 Ethernet clocks driver"); -MODULE_LICENSE("GPL"); diff --git a/lede/target/linux/mediatek/files-6.1/drivers/clk/mediatek/clk-mt7988-infracfg.c b/lede/target/linux/mediatek/files-6.1/drivers/clk/mediatek/clk-mt7988-infracfg.c deleted file mode 100644 index a5d21d756d..0000000000 --- a/lede/target/linux/mediatek/files-6.1/drivers/clk/mediatek/clk-mt7988-infracfg.c +++ /dev/null @@ -1,376 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (c) 2023 MediaTek Inc. - * Author: Sam Shih - * Author: Xiufeng Li - */ - -#include -#include -#include -#include -#include -#include "clk-mtk.h" -#include "clk-gate.h" -#include "clk-mux.h" -#include - -static DEFINE_SPINLOCK(mt7988_clk_lock); - -static const char *const infra_mux_uart0_parents[] __initconst = { - "csw_infra_f26m_sel", "uart_sel" -}; - -static const char *const infra_mux_uart1_parents[] __initconst = { - "csw_infra_f26m_sel", "uart_sel" -}; - -static const char *const infra_mux_uart2_parents[] __initconst = { - "csw_infra_f26m_sel", "uart_sel" -}; - -static const char *const infra_mux_spi0_parents[] __initconst = { "i2c_sel", - "spi_sel" }; - -static const char *const infra_mux_spi1_parents[] __initconst = { - "i2c_sel", "spim_mst_sel" -}; - -static const char *const infra_pwm_bck_parents[] __initconst = { - "top_rtc_32p7k", "csw_infra_f26m_sel", "sysaxi_sel", "pwm_sel" -}; - -static const char *const infra_pcie_gfmux_tl_ck_o_p0_parents[] __initconst = { - "top_rtc_32p7k", "csw_infra_f26m_sel", "csw_infra_f26m_sel", - "pextp_tl_sel" -}; - -static const char *const infra_pcie_gfmux_tl_ck_o_p1_parents[] __initconst = { - "top_rtc_32p7k", "csw_infra_f26m_sel", "csw_infra_f26m_sel", - "pextp_tl_p1_sel" -}; - -static const char *const infra_pcie_gfmux_tl_ck_o_p2_parents[] __initconst = { - "top_rtc_32p7k", "csw_infra_f26m_sel", "csw_infra_f26m_sel", - "pextp_tl_p2_sel" -}; - -static const char *const infra_pcie_gfmux_tl_ck_o_p3_parents[] __initconst = { - "top_rtc_32p7k", "csw_infra_f26m_sel", "csw_infra_f26m_sel", - "pextp_tl_p3_sel" -}; - -static const struct mtk_mux infra_muxes[] = { - /* MODULE_CLK_SEL_0 */ - MUX_GATE_CLR_SET_UPD(CLK_INFRA_MUX_UART0_SEL, "infra_mux_uart0_sel", - infra_mux_uart0_parents, 0x0018, 0x0010, 0x0014, - 0, 1, -1, -1, -1), - MUX_GATE_CLR_SET_UPD(CLK_INFRA_MUX_UART1_SEL, "infra_mux_uart1_sel", - infra_mux_uart1_parents, 0x0018, 0x0010, 0x0014, - 1, 1, -1, -1, -1), - MUX_GATE_CLR_SET_UPD(CLK_INFRA_MUX_UART2_SEL, "infra_mux_uart2_sel", - infra_mux_uart2_parents, 0x0018, 0x0010, 0x0014, - 2, 1, -1, -1, -1), - MUX_GATE_CLR_SET_UPD(CLK_INFRA_MUX_SPI0_SEL, "infra_mux_spi0_sel", - infra_mux_spi0_parents, 0x0018, 0x0010, 0x0014, 4, - 1, -1, -1, -1), - MUX_GATE_CLR_SET_UPD(CLK_INFRA_MUX_SPI1_SEL, "infra_mux_spi1_sel", - infra_mux_spi1_parents, 0x0018, 0x0010, 0x0014, 5, - 1, -1, -1, -1), - MUX_GATE_CLR_SET_UPD(CLK_INFRA_MUX_SPI2_SEL, "infra_mux_spi2_sel", - infra_mux_spi0_parents, 0x0018, 0x0010, 0x0014, 6, - 1, -1, -1, -1), - MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM_SEL, "infra_pwm_sel", - infra_pwm_bck_parents, 0x0018, 0x0010, 0x0014, 14, - 2, -1, -1, -1), - MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM_CK1_SEL, "infra_pwm_ck1_sel", - infra_pwm_bck_parents, 0x0018, 0x0010, 0x0014, 16, - 2, -1, -1, -1), - MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM_CK2_SEL, "infra_pwm_ck2_sel", - infra_pwm_bck_parents, 0x0018, 0x0010, 0x0014, 18, - 2, -1, -1, -1), - MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM_CK3_SEL, "infra_pwm_ck3_sel", - infra_pwm_bck_parents, 0x0018, 0x0010, 0x0014, 20, - 2, -1, -1, -1), - MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM_CK4_SEL, "infra_pwm_ck4_sel", - infra_pwm_bck_parents, 0x0018, 0x0010, 0x0014, 22, - 2, -1, -1, -1), - MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM_CK5_SEL, "infra_pwm_ck5_sel", - infra_pwm_bck_parents, 0x0018, 0x0010, 0x0014, 24, - 2, -1, -1, -1), - MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM_CK6_SEL, "infra_pwm_ck6_sel", - infra_pwm_bck_parents, 0x0018, 0x0010, 0x0014, 26, - 2, -1, -1, -1), - MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM_CK7_SEL, "infra_pwm_ck7_sel", - infra_pwm_bck_parents, 0x0018, 0x0010, 0x0014, 28, - 2, -1, -1, -1), - MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM_CK8_SEL, "infra_pwm_ck8_sel", - infra_pwm_bck_parents, 0x0018, 0x0010, 0x0014, 30, - 2, -1, -1, -1), - /* MODULE_CLK_SEL_1 */ - MUX_GATE_CLR_SET_UPD(CLK_INFRA_PCIE_GFMUX_TL_O_P0_SEL, - "infra_pcie_gfmux_tl_o_p0_sel", - infra_pcie_gfmux_tl_ck_o_p0_parents, 0x0028, - 0x0020, 0x0024, 0, 2, -1, -1, -1), - MUX_GATE_CLR_SET_UPD(CLK_INFRA_PCIE_GFMUX_TL_O_P1_SEL, - "infra_pcie_gfmux_tl_o_p1_sel", - infra_pcie_gfmux_tl_ck_o_p1_parents, 0x0028, - 0x0020, 0x0024, 2, 2, -1, -1, -1), - MUX_GATE_CLR_SET_UPD(CLK_INFRA_PCIE_GFMUX_TL_O_P2_SEL, - "infra_pcie_gfmux_tl_o_p2_sel", - infra_pcie_gfmux_tl_ck_o_p2_parents, 0x0028, - 0x0020, 0x0024, 4, 2, -1, -1, -1), - MUX_GATE_CLR_SET_UPD(CLK_INFRA_PCIE_GFMUX_TL_O_P3_SEL, - "infra_pcie_gfmux_tl_o_p3_sel", - infra_pcie_gfmux_tl_ck_o_p3_parents, 0x0028, - 0x0020, 0x0024, 6, 2, -1, -1, -1), -}; - -static const struct mtk_gate_regs infra0_cg_regs = { - .set_ofs = 0x10, - .clr_ofs = 0x14, - .sta_ofs = 0x18, -}; - -static const struct mtk_gate_regs infra1_cg_regs = { - .set_ofs = 0x40, - .clr_ofs = 0x44, - .sta_ofs = 0x48, -}; - -static const struct mtk_gate_regs infra2_cg_regs = { - .set_ofs = 0x50, - .clr_ofs = 0x54, - .sta_ofs = 0x58, -}; - -static const struct mtk_gate_regs infra3_cg_regs = { - .set_ofs = 0x60, - .clr_ofs = 0x64, - .sta_ofs = 0x68, -}; - -#define GATE_INFRA0_FLAGS(_id, _name, _parent, _shift, _flags) \ - { \ - .id = _id, .name = _name, .parent_name = _parent, \ - .regs = &infra0_cg_regs, .shift = _shift, \ - .ops = &mtk_clk_gate_ops_setclr, .flags = _flags, \ - } - -#define GATE_INFRA1_FLAGS(_id, _name, _parent, _shift, _flags) \ - { \ - .id = _id, .name = _name, .parent_name = _parent, \ - .regs = &infra1_cg_regs, .shift = _shift, \ - .ops = &mtk_clk_gate_ops_setclr, .flags = _flags, \ - } - -#define GATE_INFRA2_FLAGS(_id, _name, _parent, _shift, _flags) \ - { \ - .id = _id, .name = _name, .parent_name = _parent, \ - .regs = &infra2_cg_regs, .shift = _shift, \ - .ops = &mtk_clk_gate_ops_setclr, .flags = _flags, \ - } - -#define GATE_INFRA3_FLAGS(_id, _name, _parent, _shift, _flags) \ - { \ - .id = _id, .name = _name, .parent_name = _parent, \ - .regs = &infra3_cg_regs, .shift = _shift, \ - .ops = &mtk_clk_gate_ops_setclr, .flags = _flags, \ - } - -#define GATE_INFRA0(_id, _name, _parent, _shift) \ - GATE_INFRA0_FLAGS(_id, _name, _parent, _shift, 0) - -#define GATE_INFRA1(_id, _name, _parent, _shift) \ - GATE_INFRA1_FLAGS(_id, _name, _parent, _shift, 0) - -#define GATE_INFRA2(_id, _name, _parent, _shift) \ - GATE_INFRA2_FLAGS(_id, _name, _parent, _shift, 0) - -#define GATE_INFRA3(_id, _name, _parent, _shift) \ - GATE_INFRA3_FLAGS(_id, _name, _parent, _shift, 0) - -#define GATE_CRITICAL(_id, _name, _parent, _regs, _shift) { \ - .id = _id, .name = _name, .parent_name = _parent, \ - .regs = _regs, .shift = _shift, \ - .flags = CLK_IS_CRITICAL, \ - .ops = &mtk_clk_gate_ops_setclr, \ - } - -static const struct mtk_gate infra_clks[] = { - /* INFRA0 */ - GATE_INFRA0(CLK_INFRA_PCIE_PERI_26M_CK_P0, - "infra_pcie_peri_ck_26m_ck_p0", "csw_infra_f26m_sel", 7), - GATE_INFRA0(CLK_INFRA_PCIE_PERI_26M_CK_P1, - "infra_pcie_peri_ck_26m_ck_p1", "csw_infra_f26m_sel", 8), - GATE_INFRA0(CLK_INFRA_PCIE_PERI_26M_CK_P2, - "infra_pcie_peri_ck_26m_ck_p2", "csw_infra_f26m_sel", 9), - GATE_INFRA0(CLK_INFRA_PCIE_PERI_26M_CK_P3, - "infra_pcie_peri_ck_26m_ck_p3", "csw_infra_f26m_sel", 10), - /* INFRA1 */ - GATE_INFRA1(CLK_INFRA_66M_GPT_BCK, "infra_hf_66m_gpt_bck", - "sysaxi_sel", 0), - GATE_INFRA1(CLK_INFRA_66M_PWM_HCK, "infra_hf_66m_pwm_hck", - "sysaxi_sel", 1), - GATE_INFRA1(CLK_INFRA_66M_PWM_BCK, "infra_hf_66m_pwm_bck", - "infra_pwm_sel", 2), - GATE_INFRA1(CLK_INFRA_66M_PWM_CK1, "infra_hf_66m_pwm_ck1", - "infra_pwm_ck1_sel", 3), - GATE_INFRA1(CLK_INFRA_66M_PWM_CK2, "infra_hf_66m_pwm_ck2", - "infra_pwm_ck2_sel", 4), - GATE_INFRA1(CLK_INFRA_66M_PWM_CK3, "infra_hf_66m_pwm_ck3", - "infra_pwm_ck3_sel", 5), - GATE_INFRA1(CLK_INFRA_66M_PWM_CK4, "infra_hf_66m_pwm_ck4", - "infra_pwm_ck4_sel", 6), - GATE_INFRA1(CLK_INFRA_66M_PWM_CK5, "infra_hf_66m_pwm_ck5", - "infra_pwm_ck5_sel", 7), - GATE_INFRA1(CLK_INFRA_66M_PWM_CK6, "infra_hf_66m_pwm_ck6", - "infra_pwm_ck6_sel", 8), - GATE_INFRA1(CLK_INFRA_66M_PWM_CK7, "infra_hf_66m_pwm_ck7", - "infra_pwm_ck7_sel", 9), - GATE_INFRA1(CLK_INFRA_66M_PWM_CK8, "infra_hf_66m_pwm_ck8", - "infra_pwm_ck8_sel", 10), - GATE_INFRA1(CLK_INFRA_133M_CQDMA_BCK, "infra_hf_133m_cqdma_bck", - "sysaxi_sel", 12), - GATE_INFRA1(CLK_INFRA_66M_AUD_SLV_BCK, "infra_66m_aud_slv_bck", - "sysaxi_sel", 13), - GATE_INFRA1(CLK_INFRA_AUD_26M, "infra_f_faud_26m", - "csw_infra_f26m_sel", 14), - GATE_INFRA1(CLK_INFRA_AUD_L, "infra_f_faud_l", "aud_l_sel", 15), - GATE_INFRA1(CLK_INFRA_AUD_AUD, "infra_f_aud_aud", "a1sys_sel", 16), - GATE_INFRA1(CLK_INFRA_AUD_EG2, "infra_f_faud_eg2", "a_tuner_sel", 18), - GATE_INFRA1_FLAGS(CLK_INFRA_DRAMC_F26M, "infra_dramc_f26m", - "csw_infra_f26m_sel", 19, CLK_IS_CRITICAL), - // JTAG - GATE_INFRA1_FLAGS(CLK_INFRA_133M_DBG_ACKM, "infra_hf_133m_dbg_ackm", - "sysaxi_sel", 20, CLK_IS_CRITICAL), - GATE_INFRA1(CLK_INFRA_66M_AP_DMA_BCK, "infra_66m_ap_dma_bck", - "sysaxi_sel", 21), - GATE_INFRA1(CLK_INFRA_66M_SEJ_BCK, "infra_hf_66m_sej_bck", - "sysaxi_sel", 29), - GATE_INFRA1(CLK_INFRA_PRE_CK_SEJ_F13M, "infra_pre_ck_sej_f13m", - "csw_infra_f26m_sel", 30), - /* INFRA2 */ - GATE_INFRA2(CLK_INFRA_26M_THERM_SYSTEM, "infra_hf_26m_therm_system", - "csw_infra_f26m_sel", 0), - GATE_INFRA2(CLK_INFRA_I2C_BCK, "infra_i2c_bck", "i2c_sel", 1), - GATE_INFRA2(CLK_INFRA_52M_UART0_CK, "infra_f_52m_uart0", - "infra_mux_uart0_sel", 3), - GATE_INFRA2(CLK_INFRA_52M_UART1_CK, "infra_f_52m_uart1", - "infra_mux_uart1_sel", 4), - GATE_INFRA2(CLK_INFRA_52M_UART2_CK, "infra_f_52m_uart2", - "infra_mux_uart2_sel", 5), - GATE_INFRA2(CLK_INFRA_NFI, "infra_f_fnfi", "nfi1x_sel", 9), - GATE_INFRA2(CLK_INFRA_SPINFI, "infra_f_fspinfi", "spinfi_sel", 10), - GATE_INFRA2_FLAGS(CLK_INFRA_66M_NFI_HCK, "infra_hf_66m_nfi_hck", - "sysaxi_sel", 11, CLK_IS_CRITICAL), - GATE_INFRA2_FLAGS(CLK_INFRA_104M_SPI0, "infra_hf_104m_spi0", - "infra_mux_spi0_sel", 12, CLK_IS_CRITICAL), - GATE_INFRA2(CLK_INFRA_104M_SPI1, "infra_hf_104m_spi1", - "infra_mux_spi1_sel", 13), - GATE_INFRA2(CLK_INFRA_104M_SPI2_BCK, "infra_hf_104m_spi2_bck", - "infra_mux_spi2_sel", 14), - GATE_INFRA2_FLAGS(CLK_INFRA_66M_SPI0_HCK, "infra_hf_66m_spi0_hck", - "sysaxi_sel", 15, CLK_IS_CRITICAL), - GATE_INFRA2(CLK_INFRA_66M_SPI1_HCK, "infra_hf_66m_spi1_hck", - "sysaxi_sel", 16), - GATE_INFRA2(CLK_INFRA_66M_SPI2_HCK, "infra_hf_66m_spi2_hck", - "sysaxi_sel", 17), - GATE_INFRA2(CLK_INFRA_66M_FLASHIF_AXI, "infra_hf_66m_flashif_axi", - "sysaxi_sel", 18), - GATE_CRITICAL(CLK_INFRA_RTC, "infra_f_frtc", "top_rtc_32k", &infra2_cg_regs, 19), - GATE_INFRA2(CLK_INFRA_26M_ADC_BCK, "infra_f_26m_adc_bck", - "csw_infra_f26m_sel", 20), - GATE_INFRA2(CLK_INFRA_RC_ADC, "infra_f_frc_adc", "infra_f_26m_adc_bck", - 21), - GATE_INFRA2(CLK_INFRA_MSDC400, "infra_f_fmsdc400", "emmc_400m_sel", - 22), - GATE_INFRA2(CLK_INFRA_MSDC2_HCK, "infra_f_fmsdc2_hck", "emmc_250m_sel", - 23), - GATE_INFRA2(CLK_INFRA_133M_MSDC_0_HCK, "infra_hf_133m_msdc_0_hck", - "sysaxi_sel", 24), - GATE_INFRA2(CLK_INFRA_66M_MSDC_0_HCK, "infra_66m_msdc_0_hck", - "sysaxi_sel", 25), - GATE_INFRA2(CLK_INFRA_133M_CPUM_BCK, "infra_hf_133m_cpum_bck", - "sysaxi_sel", 26), - GATE_INFRA2(CLK_INFRA_BIST2FPC, "infra_hf_fbist2fpc", "nfi1x_sel", 27), - GATE_INFRA2(CLK_INFRA_I2C_X16W_MCK_CK_P1, - "infra_hf_i2c_x16w_mck_ck_p1", "sysaxi_sel", 29), - GATE_INFRA2(CLK_INFRA_I2C_X16W_PCK_CK_P1, - "infra_hf_i2c_x16w_pck_ck_p1", "sysaxi_sel", 31), - /* INFRA3 */ - GATE_INFRA3(CLK_INFRA_133M_USB_HCK, "infra_133m_usb_hck", "sysaxi_sel", - 0), - GATE_INFRA3(CLK_INFRA_133M_USB_HCK_CK_P1, "infra_133m_usb_hck_ck_p1", - "sysaxi_sel", 1), - GATE_INFRA3(CLK_INFRA_66M_USB_HCK, "infra_66m_usb_hck", "sysaxi_sel", - 2), - GATE_INFRA3(CLK_INFRA_66M_USB_HCK_CK_P1, "infra_66m_usb_hck_ck_p1", - "sysaxi_sel", 3), - GATE_INFRA3(CLK_INFRA_USB_SYS, "infra_usb_sys", "usb_sys_sel", 4), - GATE_INFRA3(CLK_INFRA_USB_SYS_CK_P1, "infra_usb_sys_ck_p1", - "usb_sys_p1_sel", 5), - GATE_INFRA3(CLK_INFRA_USB_REF, "infra_usb_ref", "top_xtal", 6), - GATE_INFRA3(CLK_INFRA_USB_CK_P1, "infra_usb_ck_p1", "top_xtal", 7), - GATE_INFRA3_FLAGS(CLK_INFRA_USB_FRMCNT, "infra_usb_frmcnt", - "usb_frmcnt_sel", 8, CLK_IS_CRITICAL), - GATE_INFRA3_FLAGS(CLK_INFRA_USB_FRMCNT_CK_P1, "infra_usb_frmcnt_ck_p1", - "usb_frmcnt_p1_sel", 9, CLK_IS_CRITICAL), - GATE_INFRA3(CLK_INFRA_USB_PIPE, "infra_usb_pipe", "sspxtp_sel", 10), - GATE_INFRA3(CLK_INFRA_USB_PIPE_CK_P1, "infra_usb_pipe_ck_p1", - "usb_phy_sel", 11), - GATE_INFRA3(CLK_INFRA_USB_UTMI, "infra_usb_utmi", "top_xtal", 12), - GATE_INFRA3(CLK_INFRA_USB_UTMI_CK_P1, "infra_usb_utmi_ck_p1", - "top_xtal", 13), - GATE_INFRA3(CLK_INFRA_USB_XHCI, "infra_usb_xhci", "usb_xhci_sel", 14), - GATE_INFRA3(CLK_INFRA_USB_XHCI_CK_P1, "infra_usb_xhci_ck_p1", - "usb_xhci_p1_sel", 15), - GATE_INFRA3(CLK_INFRA_PCIE_GFMUX_TL_P0, "infra_pcie_gfmux_tl_ck_p0", - "infra_pcie_gfmux_tl_o_p0_sel", 20), - GATE_INFRA3(CLK_INFRA_PCIE_GFMUX_TL_P1, "infra_pcie_gfmux_tl_ck_p1", - "infra_pcie_gfmux_tl_o_p1_sel", 21), - GATE_INFRA3(CLK_INFRA_PCIE_GFMUX_TL_P2, "infra_pcie_gfmux_tl_ck_p2", - "infra_pcie_gfmux_tl_o_p2_sel", 22), - GATE_INFRA3(CLK_INFRA_PCIE_GFMUX_TL_P3, "infra_pcie_gfmux_tl_ck_p3", - "infra_pcie_gfmux_tl_o_p3_sel", 23), - GATE_INFRA3(CLK_INFRA_PCIE_PIPE_P0, "infra_pcie_pipe_ck_p0", - "top_xtal", 24), - GATE_INFRA3(CLK_INFRA_PCIE_PIPE_P1, "infra_pcie_pipe_ck_p1", - "top_xtal", 25), - GATE_INFRA3(CLK_INFRA_PCIE_PIPE_P2, "infra_pcie_pipe_ck_p2", - "top_xtal", 26), - GATE_INFRA3(CLK_INFRA_PCIE_PIPE_P3, "infra_pcie_pipe_ck_p3", - "top_xtal", 27), - GATE_INFRA3(CLK_INFRA_133M_PCIE_CK_P0, "infra_133m_pcie_ck_p0", - "sysaxi_sel", 28), - GATE_INFRA3(CLK_INFRA_133M_PCIE_CK_P1, "infra_133m_pcie_ck_p1", - "sysaxi_sel", 29), - GATE_INFRA3(CLK_INFRA_133M_PCIE_CK_P2, "infra_133m_pcie_ck_p2", - "sysaxi_sel", 30), - GATE_INFRA3(CLK_INFRA_133M_PCIE_CK_P3, "infra_133m_pcie_ck_p3", - "sysaxi_sel", 31), -}; - -static const struct mtk_clk_desc infra_desc = { - .clks = infra_clks, - .num_clks = ARRAY_SIZE(infra_clks), - .mux_clks = infra_muxes, - .num_mux_clks = ARRAY_SIZE(infra_muxes), - .clk_lock = &mt7988_clk_lock, -}; - -static const struct of_device_id of_match_clk_mt7988_infracfg[] = { - { .compatible = "mediatek,mt7988-infracfg", .data = &infra_desc }, - { /* sentinel */ } -}; -MODULE_DEVICE_TABLE(of, of_match_clk_mt7988_infracfg); - -static struct platform_driver clk_mt7988_infracfg_drv = { - .driver = { - .name = "clk-mt7988-infracfg", - .of_match_table = of_match_clk_mt7988_infracfg, - }, - .probe = mtk_clk_simple_probe, - .remove = mtk_clk_simple_remove, -}; -module_platform_driver(clk_mt7988_infracfg_drv); diff --git a/lede/target/linux/mediatek/files-6.1/drivers/clk/mediatek/clk-mt7988-topckgen.c b/lede/target/linux/mediatek/files-6.1/drivers/clk/mediatek/clk-mt7988-topckgen.c deleted file mode 100644 index b0745d6508..0000000000 --- a/lede/target/linux/mediatek/files-6.1/drivers/clk/mediatek/clk-mt7988-topckgen.c +++ /dev/null @@ -1,446 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (c) 2023 MediaTek Inc. - * Author: Sam Shih - * Author: Xiufeng Li - */ - -#include -#include -#include -#include -#include -#include "clk-mtk.h" -#include "clk-gate.h" -#include "clk-mux.h" -#include - -static DEFINE_SPINLOCK(mt7988_clk_lock); - -static const struct mtk_fixed_clk top_fixed_clks[] = { - FIXED_CLK(CLK_TOP_XTAL, "top_xtal", "clkxtal", 40000000), -}; - -static const struct mtk_fixed_factor top_divs[] = { - FACTOR(CLK_TOP_XTAL_D2, "top_xtal_d2", "top_xtal", 1, 2), - FACTOR(CLK_TOP_RTC_32K, "top_rtc_32k", "top_xtal", 1, 1250), - FACTOR(CLK_TOP_RTC_32P7K, "top_rtc_32p7k", "top_xtal", 1, 1220), - FACTOR(CLK_TOP_MPLL_D2, "mpll_d2", "mpll", 1, 2), - FACTOR(CLK_TOP_MPLL_D3_D2, "mpll_d3_d2", "mpll", 1, 2), - FACTOR(CLK_TOP_MPLL_D4, "mpll_d4", "mpll", 1, 4), - FACTOR(CLK_TOP_MPLL_D8, "mpll_d8", "mpll", 1, 8), - FACTOR(CLK_TOP_MPLL_D8_D2, "mpll_d8_d2", "mpll", 1, 16), - FACTOR(CLK_TOP_MMPLL_D2, "mmpll_d2", "mmpll", 1, 2), - FACTOR(CLK_TOP_MMPLL_D3_D5, "mmpll_d3_d5", "mmpll", 1, 15), - FACTOR(CLK_TOP_MMPLL_D4, "mmpll_d4", "mmpll", 1, 4), - FACTOR(CLK_TOP_MMPLL_D6_D2, "mmpll_d6_d2", "mmpll", 1, 12), - FACTOR(CLK_TOP_MMPLL_D8, "mmpll_d8", "mmpll", 1, 8), - FACTOR(CLK_TOP_APLL2_D4, "apll2_d4", "apll2", 1, 4), - FACTOR(CLK_TOP_NET1PLL_D4, "net1pll_d4", "net1pll", 1, 4), - FACTOR(CLK_TOP_NET1PLL_D5, "net1pll_d5", "net1pll", 1, 5), - FACTOR(CLK_TOP_NET1PLL_D5_D2, "net1pll_d5_d2", "net1pll", 1, 10), - FACTOR(CLK_TOP_NET1PLL_D5_D4, "net1pll_d5_d4", "net1pll", 1, 20), - FACTOR(CLK_TOP_NET1PLL_D8, "net1pll_d8", "net1pll", 1, 8), - FACTOR(CLK_TOP_NET1PLL_D8_D2, "net1pll_d8_d2", "net1pll", 1, 16), - FACTOR(CLK_TOP_NET1PLL_D8_D4, "net1pll_d8_d4", "net1pll", 1, 32), - FACTOR(CLK_TOP_NET1PLL_D8_D8, "net1pll_d8_d8", "net1pll", 1, 64), - FACTOR(CLK_TOP_NET1PLL_D8_D16, "net1pll_d8_d16", "net1pll", 1, 128), - FACTOR(CLK_TOP_NET2PLL_D2, "net2pll_d2", "net2pll", 1, 2), - FACTOR(CLK_TOP_NET2PLL_D4, "net2pll_d4", "net2pll", 1, 4), - FACTOR(CLK_TOP_NET2PLL_D4_D4, "net2pll_d4_d4", "net2pll", 1, 16), - FACTOR(CLK_TOP_NET2PLL_D4_D8, "net2pll_d4_d8", "net2pll", 1, 32), - FACTOR(CLK_TOP_NET2PLL_D6, "net2pll_d6", "net2pll", 1, 6), - FACTOR(CLK_TOP_NET2PLL_D8, "net2pll_d8", "net2pll", 1, 8), -}; - -static const char *const netsys_parents[] = { "top_xtal", "net2pll_d2", - "mmpll_d2" }; - -static const char *const netsys_500m_parents[] = { "top_xtal", "net1pll_d5", - "net1pll_d5_d2" }; - -static const char *const netsys_2x_parents[] = { "top_xtal", "net2pll", - "mmpll" }; - -static const char *const netsys_gsw_parents[] = { "top_xtal", "net1pll_d4", - "net1pll_d5" }; - -static const char *const eth_gmii_parents[] = { "top_xtal", "net1pll_d5_d4" }; - -static const char *const netsys_mcu_parents[] = { "top_xtal", "net2pll", - "mmpll", "net1pll_d4", - "net1pll_d5", "mpll" }; - -static const char *const eip197_parents[] = { "top_xtal", "netsyspll", - "net2pll", "mmpll", - "net1pll_d4", "net1pll_d5" }; - -static const char *const axi_infra_parents[] = { "top_xtal", "net1pll_d8_d2" }; - -static const char *const uart_parents[] = { "top_xtal", "mpll_d8", - "mpll_d8_d2" }; - -static const char *const emmc_250m_parents[] = { "top_xtal", "net1pll_d5_d2", - "mmpll_d4" }; - -static const char *const emmc_400m_parents[] = { "top_xtal", "msdcpll", - "mmpll_d2", "mpll_d2", - "mmpll_d4", "net1pll_d8_d2" }; - -static const char *const spi_parents[] = { "top_xtal", "mpll_d2", - "mmpll_d4", "net1pll_d8_d2", - "net2pll_d6", "net1pll_d5_d4", - "mpll_d4", "net1pll_d8_d4" }; - -static const char *const nfi1x_parents[] = { "top_xtal", "mmpll_d4", - "net1pll_d8_d2", "net2pll_d6", - "mpll_d4", "mmpll_d8", - "net1pll_d8_d4", "mpll_d8" }; - -static const char *const spinfi_parents[] = { "top_xtal_d2", "top_xtal", - "net1pll_d5_d4", "mpll_d4", - "mmpll_d8", "net1pll_d8_d4", - "mmpll_d6_d2", "mpll_d8" }; - -static const char *const pwm_parents[] = { "top_xtal", "net1pll_d8_d2", - "net1pll_d5_d4", "mpll_d4", - "mpll_d8_d2", "top_rtc_32k" }; - -static const char *const i2c_parents[] = { "top_xtal", "net1pll_d5_d4", - "mpll_d4", "net1pll_d8_d4" }; - -static const char *const pcie_mbist_250m_parents[] = { "top_xtal", - "net1pll_d5_d2" }; - -static const char *const pextp_tl_ck_parents[] = { "top_xtal", "net2pll_d6", - "mmpll_d8", "mpll_d8_d2", - "top_rtc_32k" }; - -static const char *const usb_frmcnt_parents[] = { "top_xtal", "mmpll_d3_d5" }; - -static const char *const aud_parents[] = { "top_xtal", "apll2" }; - -static const char *const a1sys_parents[] = { "top_xtal", "apll2_d4" }; - -static const char *const aud_l_parents[] = { "top_xtal", "apll2", - "mpll_d8_d2" }; - -static const char *const sspxtp_parents[] = { "top_xtal_d2", "mpll_d8_d2" }; - -static const char *const usxgmii_sbus_0_parents[] = { "top_xtal", - "net1pll_d8_d4" }; - -static const char *const sgm_0_parents[] = { "top_xtal", "sgmpll" }; - -static const char *const sysapb_parents[] = { "top_xtal", "mpll_d3_d2" }; - -static const char *const eth_refck_50m_parents[] = { "top_xtal", - "net2pll_d4_d4" }; - -static const char *const eth_sys_200m_parents[] = { "top_xtal", "net2pll_d4" }; - -static const char *const eth_xgmii_parents[] = { "top_xtal_d2", - "net1pll_d8_d8", - "net1pll_d8_d16" }; - -static const char *const bus_tops_parents[] = { "top_xtal", "net1pll_d5", - "net2pll_d2" }; - -static const char *const npu_tops_parents[] = { "top_xtal", "net2pll" }; - -static const char *const dramc_md32_parents[] = { "top_xtal", "mpll_d2", - "wedmcupll" }; - -static const char *const da_xtp_glb_p0_parents[] = { "top_xtal", - "net2pll_d8" }; - -static const char *const mcusys_backup_625m_parents[] = { "top_xtal", - "net1pll_d4" }; - -static const char *const macsec_parents[] = { "top_xtal", "sgmpll", - "net1pll_d8" }; - -static const char *const netsys_tops_400m_parents[] = { "top_xtal", - "net2pll_d2" }; - -static const char *const eth_mii_parents[] = { "top_xtal_d2", - "net2pll_d4_d8" }; - -static const struct mtk_mux top_muxes[] = { - /* CLK_CFG_0 */ - MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_SEL, "netsys_sel", netsys_parents, - 0x000, 0x004, 0x008, 0, 2, 7, 0x1c0, 0), - MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_500M_SEL, "netsys_500m_sel", - netsys_500m_parents, 0x000, 0x004, 0x008, 8, 2, - 15, 0x1C0, 1), - MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_2X_SEL, "netsys_2x_sel", - netsys_2x_parents, 0x000, 0x004, 0x008, 16, 2, 23, - 0x1C0, 2), - MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_GSW_SEL, "netsys_gsw_sel", - netsys_gsw_parents, 0x000, 0x004, 0x008, 24, 2, - 31, 0x1C0, 3), - /* CLK_CFG_1 */ - MUX_GATE_CLR_SET_UPD(CLK_TOP_ETH_GMII_SEL, "eth_gmii_sel", - eth_gmii_parents, 0x010, 0x014, 0x018, 0, 1, 7, - 0x1C0, 4), - MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_MCU_SEL, "netsys_mcu_sel", - netsys_mcu_parents, 0x010, 0x014, 0x018, 8, 3, 15, - 0x1C0, 5), - MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_PAO_2X_SEL, "netsys_pao_2x_sel", - netsys_mcu_parents, 0x010, 0x014, 0x018, 16, 3, - 23, 0x1C0, 6), - MUX_GATE_CLR_SET_UPD(CLK_TOP_EIP197_SEL, "eip197_sel", eip197_parents, - 0x010, 0x014, 0x018, 24, 3, 31, 0x1c0, 7), - /* CLK_CFG_2 */ - MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_AXI_INFRA_SEL, "axi_infra_sel", - axi_infra_parents, 0x020, 0x024, 0x028, 0, - 1, 7, 0x1C0, 8, CLK_IS_CRITICAL), - MUX_GATE_CLR_SET_UPD(CLK_TOP_UART_SEL, "uart_sel", uart_parents, 0x020, - 0x024, 0x028, 8, 2, 15, 0x1c0, 9), - MUX_GATE_CLR_SET_UPD(CLK_TOP_EMMC_250M_SEL, "emmc_250m_sel", - emmc_250m_parents, 0x020, 0x024, 0x028, 16, 2, 23, - 0x1C0, 10), - MUX_GATE_CLR_SET_UPD(CLK_TOP_EMMC_400M_SEL, "emmc_400m_sel", - emmc_400m_parents, 0x020, 0x024, 0x028, 24, 3, 31, - 0x1C0, 11), - /* CLK_CFG_3 */ - MUX_GATE_CLR_SET_UPD(CLK_TOP_SPI_SEL, "spi_sel", spi_parents, 0x030, - 0x034, 0x038, 0, 3, 7, 0x1c0, 12), - MUX_GATE_CLR_SET_UPD(CLK_TOP_SPIM_MST_SEL, "spim_mst_sel", spi_parents, - 0x030, 0x034, 0x038, 8, 3, 15, 0x1c0, 13), - MUX_GATE_CLR_SET_UPD(CLK_TOP_NFI1X_SEL, "nfi1x_sel", nfi1x_parents, - 0x030, 0x034, 0x038, 16, 3, 23, 0x1c0, 14), - MUX_GATE_CLR_SET_UPD(CLK_TOP_SPINFI_SEL, "spinfi_sel", spinfi_parents, - 0x030, 0x034, 0x038, 24, 3, 31, 0x1c0, 15), - /* CLK_CFG_4 */ - MUX_GATE_CLR_SET_UPD(CLK_TOP_PWM_SEL, "pwm_sel", pwm_parents, 0x040, - 0x044, 0x048, 0, 3, 7, 0x1c0, 16), - MUX_GATE_CLR_SET_UPD(CLK_TOP_I2C_SEL, "i2c_sel", i2c_parents, 0x040, - 0x044, 0x048, 8, 2, 15, 0x1c0, 17), - MUX_GATE_CLR_SET_UPD(CLK_TOP_PCIE_MBIST_250M_SEL, - "pcie_mbist_250m_sel", pcie_mbist_250m_parents, - 0x040, 0x044, 0x048, 16, 1, 23, 0x1C0, 18), - MUX_GATE_CLR_SET_UPD(CLK_TOP_PEXTP_TL_SEL, "pextp_tl_sel", - pextp_tl_ck_parents, 0x040, 0x044, 0x048, 24, 3, - 31, 0x1C0, 19), - /* CLK_CFG_5 */ - MUX_GATE_CLR_SET_UPD(CLK_TOP_PEXTP_TL_P1_SEL, "pextp_tl_p1_sel", - pextp_tl_ck_parents, 0x050, 0x054, 0x058, 0, 3, 7, - 0x1C0, 20), - MUX_GATE_CLR_SET_UPD(CLK_TOP_PEXTP_TL_P2_SEL, "pextp_tl_p2_sel", - pextp_tl_ck_parents, 0x050, 0x054, 0x058, 8, 3, - 15, 0x1C0, 21), - MUX_GATE_CLR_SET_UPD(CLK_TOP_PEXTP_TL_P3_SEL, "pextp_tl_p3_sel", - pextp_tl_ck_parents, 0x050, 0x054, 0x058, 16, 3, - 23, 0x1C0, 22), - MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_SYS_SEL, "usb_sys_sel", - eth_gmii_parents, 0x050, 0x054, 0x058, 24, 1, 31, - 0x1C0, 23), - /* CLK_CFG_6 */ - MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_SYS_P1_SEL, "usb_sys_p1_sel", - eth_gmii_parents, 0x060, 0x064, 0x068, 0, 1, 7, - 0x1C0, 24), - MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_XHCI_SEL, "usb_xhci_sel", - eth_gmii_parents, 0x060, 0x064, 0x068, 8, 1, 15, - 0x1C0, 25), - MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_XHCI_P1_SEL, "usb_xhci_p1_sel", - eth_gmii_parents, 0x060, 0x064, 0x068, 16, 1, 23, - 0x1C0, 26), - MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_FRMCNT_SEL, "usb_frmcnt_sel", - usb_frmcnt_parents, 0x060, 0x064, 0x068, 24, 1, - 31, 0x1C0, 27), - /* CLK_CFG_7 */ - MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_FRMCNT_P1_SEL, "usb_frmcnt_p1_sel", - usb_frmcnt_parents, 0x070, 0x074, 0x078, 0, 1, 7, - 0x1C0, 28), - MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_SEL, "aud_sel", aud_parents, 0x070, - 0x074, 0x078, 8, 1, 15, 0x1c0, 29), - MUX_GATE_CLR_SET_UPD(CLK_TOP_A1SYS_SEL, "a1sys_sel", a1sys_parents, - 0x070, 0x074, 0x078, 16, 1, 23, 0x1c0, 30), - MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_L_SEL, "aud_l_sel", aud_l_parents, - 0x070, 0x074, 0x078, 24, 2, 31, 0x1c4, 0), - /* CLK_CFG_8 */ - MUX_GATE_CLR_SET_UPD(CLK_TOP_A_TUNER_SEL, "a_tuner_sel", a1sys_parents, - 0x080, 0x084, 0x088, 0, 1, 7, 0x1c4, 1), - MUX_GATE_CLR_SET_UPD(CLK_TOP_SSPXTP_SEL, "sspxtp_sel", sspxtp_parents, - 0x080, 0x084, 0x088, 8, 1, 15, 0x1c4, 2), - MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_PHY_SEL, "usb_phy_sel", - sspxtp_parents, 0x080, 0x084, 0x088, 16, 1, 23, - 0x1c4, 3), - MUX_GATE_CLR_SET_UPD(CLK_TOP_USXGMII_SBUS_0_SEL, "usxgmii_sbus_0_sel", - usxgmii_sbus_0_parents, 0x080, 0x084, 0x088, 24, - 1, 31, 0x1C4, 4), - /* CLK_CFG_9 */ - MUX_GATE_CLR_SET_UPD(CLK_TOP_USXGMII_SBUS_1_SEL, "usxgmii_sbus_1_sel", - usxgmii_sbus_0_parents, 0x090, 0x094, 0x098, 0, 1, - 7, 0x1C4, 5), - MUX_GATE_CLR_SET_UPD(CLK_TOP_SGM_0_SEL, "sgm_0_sel", sgm_0_parents, - 0x090, 0x094, 0x098, 8, 1, 15, 0x1c4, 6), - MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SGM_SBUS_0_SEL, "sgm_sbus_0_sel", - usxgmii_sbus_0_parents, 0x090, 0x094, 0x098, - 16, 1, 23, 0x1C4, 7, CLK_IS_CRITICAL), - MUX_GATE_CLR_SET_UPD(CLK_TOP_SGM_1_SEL, "sgm_1_sel", sgm_0_parents, - 0x090, 0x094, 0x098, 24, 1, 31, 0x1c4, 8), - /* CLK_CFG_10 */ - MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SGM_SBUS_1_SEL, "sgm_sbus_1_sel", - usxgmii_sbus_0_parents, 0x0a0, 0x0a4, 0x0a8, - 0, 1, 7, 0x1C4, 9, CLK_IS_CRITICAL), - MUX_GATE_CLR_SET_UPD(CLK_TOP_XFI_PHY_0_XTAL_SEL, "xfi_phy_0_xtal_sel", - sspxtp_parents, 0x0a0, 0x0a4, 0x0a8, 8, 1, 15, - 0x1C4, 10), - MUX_GATE_CLR_SET_UPD(CLK_TOP_XFI_PHY_1_XTAL_SEL, "xfi_phy_1_xtal_sel", - sspxtp_parents, 0x0a0, 0x0a4, 0x0a8, 16, 1, 23, - 0x1C4, 11), - /* CLK_CFG_11 */ - MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SYSAXI_SEL, "sysaxi_sel", - axi_infra_parents, 0x0a0, 0x0a4, 0x0a8, 24, - 1, 31, 0x1C4, 12, CLK_IS_CRITICAL), - MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SYSAPB_SEL, "sysapb_sel", - sysapb_parents, 0x0b0, 0x0b4, 0x0b8, 0, 1, - 7, 0x1c4, 13, CLK_IS_CRITICAL), - MUX_GATE_CLR_SET_UPD(CLK_TOP_ETH_REFCK_50M_SEL, "eth_refck_50m_sel", - eth_refck_50m_parents, 0x0b0, 0x0b4, 0x0b8, 8, 1, - 15, 0x1C4, 14), - MUX_GATE_CLR_SET_UPD(CLK_TOP_ETH_SYS_200M_SEL, "eth_sys_200m_sel", - eth_sys_200m_parents, 0x0b0, 0x0b4, 0x0b8, 16, 1, - 23, 0x1C4, 15), - MUX_GATE_CLR_SET_UPD(CLK_TOP_ETH_SYS_SEL, "eth_sys_sel", - pcie_mbist_250m_parents, 0x0b0, 0x0b4, 0x0b8, 24, - 1, 31, 0x1C4, 16), - /* CLK_CFG_12 */ - MUX_GATE_CLR_SET_UPD(CLK_TOP_ETH_XGMII_SEL, "eth_xgmii_sel", - eth_xgmii_parents, 0x0c0, 0x0c4, 0x0c8, 0, 2, 7, - 0x1C4, 17), - MUX_GATE_CLR_SET_UPD(CLK_TOP_BUS_TOPS_SEL, "bus_tops_sel", - bus_tops_parents, 0x0c0, 0x0c4, 0x0c8, 8, 2, 15, - 0x1C4, 18), - MUX_GATE_CLR_SET_UPD(CLK_TOP_NPU_TOPS_SEL, "npu_tops_sel", - npu_tops_parents, 0x0c0, 0x0c4, 0x0c8, 16, 1, 23, - 0x1C4, 19), - MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_DRAMC_SEL, "dramc_sel", - sspxtp_parents, 0x0c0, 0x0c4, 0x0c8, 24, 1, - 31, 0x1C4, 20, CLK_IS_CRITICAL), - /* CLK_CFG_13 */ - MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_DRAMC_MD32_SEL, "dramc_md32_sel", - dramc_md32_parents, 0x0d0, 0x0d4, 0x0d8, 0, - 2, 7, 0x1C4, 21, CLK_IS_CRITICAL), - MUX_GATE_CLR_SET_UPD_FLAGS( - CLK_TOP_INFRA_F26M_SEL, "csw_infra_f26m_sel", sspxtp_parents, - 0x0d0, 0x0d4, 0x0d8, 8, 1, 15, 0x1C4, 22, CLK_IS_CRITICAL), - MUX_GATE_CLR_SET_UPD(CLK_TOP_PEXTP_P0_SEL, "pextp_p0_sel", - sspxtp_parents, 0x0d0, 0x0d4, 0x0d8, 16, 1, 23, - 0x1C4, 23), - MUX_GATE_CLR_SET_UPD(CLK_TOP_PEXTP_P1_SEL, "pextp_p1_sel", - sspxtp_parents, 0x0d0, 0x0d4, 0x0d8, 24, 1, 31, - 0x1C4, 24), - /* CLK_CFG_14 */ - MUX_GATE_CLR_SET_UPD(CLK_TOP_PEXTP_P2_SEL, "pextp_p2_sel", - sspxtp_parents, 0x0e0, 0x0e4, 0x0e8, 0, 1, 7, - 0x1C4, 25), - MUX_GATE_CLR_SET_UPD(CLK_TOP_PEXTP_P3_SEL, "pextp_p3_sel", - sspxtp_parents, 0x0e0, 0x0e4, 0x0e8, 8, 1, 15, - 0x1C4, 26), - MUX_GATE_CLR_SET_UPD(CLK_TOP_DA_XTP_GLB_P0_SEL, "da_xtp_glb_p0_sel", - da_xtp_glb_p0_parents, 0x0e0, 0x0e4, 0x0e8, 16, 1, - 23, 0x1C4, 27), - MUX_GATE_CLR_SET_UPD(CLK_TOP_DA_XTP_GLB_P1_SEL, "da_xtp_glb_p1_sel", - da_xtp_glb_p0_parents, 0x0e0, 0x0e4, 0x0e8, 24, 1, - 31, 0x1C4, 28), - /* CLK_CFG_15 */ - MUX_GATE_CLR_SET_UPD(CLK_TOP_DA_XTP_GLB_P2_SEL, "da_xtp_glb_p2_sel", - da_xtp_glb_p0_parents, 0x0f0, 0x0f4, 0x0f8, 0, 1, - 7, 0x1C4, 29), - MUX_GATE_CLR_SET_UPD(CLK_TOP_DA_XTP_GLB_P3_SEL, "da_xtp_glb_p3_sel", - da_xtp_glb_p0_parents, 0x0f0, 0x0f4, 0x0f8, 8, 1, - 15, 0x1C4, 30), - MUX_GATE_CLR_SET_UPD(CLK_TOP_CKM_SEL, "ckm_sel", sspxtp_parents, 0x0F0, - 0x0f4, 0x0f8, 16, 1, 23, 0x1c8, 0), - MUX_GATE_CLR_SET_UPD(CLK_TOP_DA_SEL, "da_sel", sspxtp_parents, 0x0f0, - 0x0f4, 0x0f8, 24, 1, 31, 0x1C8, 1), - /* CLK_CFG_16 */ - MUX_GATE_CLR_SET_UPD(CLK_TOP_PEXTP_SEL, "pextp_sel", sspxtp_parents, - 0x0100, 0x104, 0x108, 0, 1, 7, 0x1c8, 2), - MUX_GATE_CLR_SET_UPD(CLK_TOP_TOPS_P2_26M_SEL, "tops_p2_26m_sel", - sspxtp_parents, 0x0100, 0x104, 0x108, 8, 1, 15, - 0x1C8, 3), - MUX_GATE_CLR_SET_UPD(CLK_TOP_MCUSYS_BACKUP_625M_SEL, - "mcusys_backup_625m_sel", - mcusys_backup_625m_parents, 0x0100, 0x104, 0x108, - 16, 1, 23, 0x1C8, 4), - MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_SYNC_250M_SEL, - "netsys_sync_250m_sel", pcie_mbist_250m_parents, - 0x0100, 0x104, 0x108, 24, 1, 31, 0x1c8, 5), - /* CLK_CFG_17 */ - MUX_GATE_CLR_SET_UPD(CLK_TOP_MACSEC_SEL, "macsec_sel", macsec_parents, - 0x0110, 0x114, 0x118, 0, 2, 7, 0x1c8, 6), - MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_TOPS_400M_SEL, - "netsys_tops_400m_sel", netsys_tops_400m_parents, - 0x0110, 0x114, 0x118, 8, 1, 15, 0x1c8, 7), - MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_PPEFB_250M_SEL, - "netsys_ppefb_250m_sel", pcie_mbist_250m_parents, - 0x0110, 0x114, 0x118, 16, 1, 23, 0x1c8, 8), - MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_WARP_SEL, "netsys_warp_sel", - netsys_parents, 0x0110, 0x114, 0x118, 24, 2, 31, - 0x1C8, 9), - /* CLK_CFG_18 */ - MUX_GATE_CLR_SET_UPD(CLK_TOP_ETH_MII_SEL, "eth_mii_sel", - eth_mii_parents, 0x0120, 0x124, 0x128, 0, 1, 7, - 0x1c8, 10), - MUX_GATE_CLR_SET_UPD(CLK_TOP_NPU_SEL, "ck_npu_sel", netsys_2x_parents, - 0x0120, 0x124, 0x128, 8, 2, 15, 0x1c8, 11), -}; - -static const struct mtk_composite top_aud_divs[] = { - DIV_GATE(CLK_TOP_AUD_I2S_M, "aud_i2s_m", "aud_sel", 0x0420, 0, 0x0420, - 8, 8), -}; - -static const struct mtk_clk_desc topck_desc = { - .fixed_clks = top_fixed_clks, - .num_fixed_clks = ARRAY_SIZE(top_fixed_clks), - .factor_clks = top_divs, - .num_factor_clks = ARRAY_SIZE(top_divs), - .mux_clks = top_muxes, - .num_mux_clks = ARRAY_SIZE(top_muxes), - .composite_clks = top_aud_divs, - .num_composite_clks = ARRAY_SIZE(top_aud_divs), - .clk_lock = &mt7988_clk_lock, -}; - -static const char *const mcu_bus_div_parents[] = { "top_xtal", "ccipll2_b", - "net1pll_d4" }; - -static const char *const mcu_arm_div_parents[] = { "top_xtal", "arm_b", - "net1pll_d4" }; - -static struct mtk_composite mcu_muxes[] = { - /* bus_pll_divider_cfg */ - MUX_GATE_FLAGS(CLK_MCU_BUS_DIV_SEL, "mcu_bus_div_sel", - mcu_bus_div_parents, 0x7C0, 9, 2, -1, CLK_IS_CRITICAL), - /* mp2_pll_divider_cfg */ - MUX_GATE_FLAGS(CLK_MCU_ARM_DIV_SEL, "mcu_arm_div_sel", - mcu_arm_div_parents, 0x7A8, 9, 2, -1, CLK_IS_CRITICAL), -}; - -static const struct mtk_clk_desc mcusys_desc = { - .composite_clks = mcu_muxes, - .num_composite_clks = ARRAY_SIZE(mcu_muxes), -}; - -static const struct of_device_id of_match_clk_mt7988_topckgen[] = { - { .compatible = "mediatek,mt7988-topckgen", .data = &topck_desc }, - { .compatible = "mediatek,mt7988-mcusys", .data = &mcusys_desc }, - { /* sentinel */ } -}; -MODULE_DEVICE_TABLE(of, of_match_clk_mt7988_topckgen); - -static struct platform_driver clk_mt7988_topckgen_drv = { - .probe = mtk_clk_simple_probe, - .remove = mtk_clk_simple_remove, - .driver = { - .name = "clk-mt7988-topckgen", - .of_match_table = of_match_clk_mt7988_topckgen, - }, -}; -module_platform_driver(clk_mt7988_topckgen_drv); -MODULE_LICENSE("GPL"); diff --git a/lede/target/linux/mediatek/files-6.1/drivers/net/phy/mediatek-2p5ge.c b/lede/target/linux/mediatek/files-6.1/drivers/net/phy/mediatek-2p5ge.c index c12e6b8eb6..e2e06d1eca 100644 --- a/lede/target/linux/mediatek/files-6.1/drivers/net/phy/mediatek-2p5ge.c +++ b/lede/target/linux/mediatek/files-6.1/drivers/net/phy/mediatek-2p5ge.c @@ -7,37 +7,50 @@ #include #include #include +#include +#include -#define MEDAITEK_2P5GE_PHY_DMB_FW "mediatek/mediatek-2p5ge-phy-dmb.bin" -#define MEDIATEK_2P5GE_PHY_PMB_FW "mediatek/mediatek-2p5ge-phy-pmb.bin" +#define MT7988_2P5GE_PMB "mediatek/mt7988/i2p5ge-phy-pmb.bin" -#define MD32_EN_CFG 0x18 -#define MD32_EN BIT(0) +#define MD32_EN BIT(0) +#define PMEM_PRIORITY BIT(8) +#define DMEM_PRIORITY BIT(16) -#define BASE100T_STATUS_EXTEND 0x10 -#define BASE1000T_STATUS_EXTEND 0x11 -#define EXTEND_CTRL_AND_STATUS 0x16 +#define BASE100T_STATUS_EXTEND 0x10 +#define BASE1000T_STATUS_EXTEND 0x11 +#define EXTEND_CTRL_AND_STATUS 0x16 -#define PHY_AUX_CTRL_STATUS 0x1d -#define PHY_AUX_DPX_MASK GENMASK(5, 5) -#define PHY_AUX_SPEED_MASK GENMASK(4, 2) +#define PHY_AUX_CTRL_STATUS 0x1d +#define PHY_AUX_DPX_MASK GENMASK(5, 5) +#define PHY_AUX_SPEED_MASK GENMASK(4, 2) /* Registers on MDIO_MMD_VEND1 */ -#define MTK_PHY_LINK_STATUS_MISC 0xa2 -#define MTK_PHY_FDX_ENABLE BIT(5) +#define MTK_PHY_LINK_STATUS_MISC 0xa2 +#define MTK_PHY_FDX_ENABLE BIT(5) + +#define MTK_PHY_LPI_PCS_DSP_CTRL 0x121 +#define MTK_PHY_LPI_SIG_EN_LO_THRESH100_MASK GENMASK(12, 8) /* Registers on MDIO_MMD_VEND2 */ -#define MTK_PHY_LED0_ON_CTRL 0x24 -#define MTK_PHY_LED0_ON_LINK1000 BIT(0) -#define MTK_PHY_LED0_ON_LINK100 BIT(1) -#define MTK_PHY_LED0_ON_LINK10 BIT(2) -#define MTK_PHY_LED0_ON_LINK2500 BIT(7) -#define MTK_PHY_LED0_POLARITY BIT(14) +#define MTK_PHY_LED0_ON_CTRL 0x24 +#define MTK_PHY_LED0_ON_LINK1000 BIT(0) +#define MTK_PHY_LED0_ON_LINK100 BIT(1) +#define MTK_PHY_LED0_ON_LINK10 BIT(2) +#define MTK_PHY_LED0_ON_LINK2500 BIT(7) +#define MTK_PHY_LED0_POLARITY BIT(14) -#define MTK_PHY_LED1_ON_CTRL 0x26 -#define MTK_PHY_LED1_ON_FDX BIT(4) -#define MTK_PHY_LED1_ON_HDX BIT(5) -#define MTK_PHY_LED1_POLARITY BIT(14) +#define MTK_PHY_LED1_ON_CTRL 0x26 +#define MTK_PHY_LED1_ON_FDX BIT(4) +#define MTK_PHY_LED1_ON_HDX BIT(5) +#define MTK_PHY_LED1_POLARITY BIT(14) + +#define MTK_EXT_PAGE_ACCESS 0x1f +#define MTK_PHY_PAGE_STANDARD 0x0000 +#define MTK_PHY_PAGE_EXTENDED_52B5 0x52b5 + +struct mtk_i2p5ge_phy_priv { + bool fw_loaded; +}; enum { PHY_AUX_SPD_10 = 0, @@ -46,67 +59,89 @@ enum { PHY_AUX_SPD_2500, }; -static int mt798x_2p5ge_phy_config_init(struct phy_device *phydev) +static int mtk_2p5ge_phy_read_page(struct phy_device *phydev) { - int ret; - int i; + return __phy_read(phydev, MTK_EXT_PAGE_ACCESS); +} + +static int mtk_2p5ge_phy_write_page(struct phy_device *phydev, int page) +{ + return __phy_write(phydev, MTK_EXT_PAGE_ACCESS, page); +} + +static int mt7988_2p5ge_phy_probe(struct phy_device *phydev) +{ + struct mtk_i2p5ge_phy_priv *phy_priv; + + phy_priv = devm_kzalloc(&phydev->mdio.dev, + sizeof(struct mtk_i2p5ge_phy_priv), GFP_KERNEL); + if (!phy_priv) + return -ENOMEM; + + phydev->priv = phy_priv; + + return 0; +} + +static int mt7988_2p5ge_phy_config_init(struct phy_device *phydev) +{ + int ret, i; const struct firmware *fw; struct device *dev = &phydev->mdio.dev; struct device_node *np; - void __iomem *dmb_addr; void __iomem *pmb_addr; - void __iomem *mcucsr_base; + void __iomem *md32_en_cfg_base; + struct mtk_i2p5ge_phy_priv *phy_priv = phydev->priv; u16 reg; struct pinctrl *pinctrl; - np = of_find_compatible_node(NULL, NULL, "mediatek,2p5gphy-fw"); - if (!np) - return -ENOENT; + if (!phy_priv->fw_loaded) { + np = of_find_compatible_node(NULL, NULL, "mediatek,2p5gphy-fw"); + if (!np) + return -ENOENT; + pmb_addr = of_iomap(np, 0); + if (!pmb_addr) + return -ENOMEM; + md32_en_cfg_base = of_iomap(np, 1); + if (!md32_en_cfg_base) + return -ENOMEM; - dmb_addr = of_iomap(np, 0); - if (!dmb_addr) - return -ENOMEM; - pmb_addr = of_iomap(np, 1); - if (!pmb_addr) - return -ENOMEM; - mcucsr_base = of_iomap(np, 2); - if (!mcucsr_base) - return -ENOMEM; + ret = request_firmware(&fw, MT7988_2P5GE_PMB, dev); + if (ret) { + dev_err(dev, "failed to load firmware: %s, ret: %d\n", + MT7988_2P5GE_PMB, ret); + return ret; + } - ret = request_firmware(&fw, MEDAITEK_2P5GE_PHY_DMB_FW, dev); - if (ret) { - dev_err(dev, "failed to load firmware: %s, ret: %d\n", - MEDAITEK_2P5GE_PHY_DMB_FW, ret); - return ret; + reg = readw(md32_en_cfg_base); + if (reg & MD32_EN) { + phy_set_bits(phydev, 0, BIT(15)); + usleep_range(10000, 11000); + } + phy_set_bits(phydev, 0, BIT(11)); + + /* Write magic number to safely stall MCU */ + phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x800e, 0x1100); + phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x800f, 0x00df); + + for (i = 0; i < fw->size - 1; i += 4) + writel(*((uint32_t *)(fw->data + i)), pmb_addr + i); + release_firmware(fw); + + writew(reg & ~MD32_EN, md32_en_cfg_base); + writew(reg | MD32_EN, md32_en_cfg_base); + phy_set_bits(phydev, 0, BIT(15)); + dev_info(dev, "Firmware loading/trigger ok.\n"); + + phy_priv->fw_loaded = true; } - for (i = 0; i < fw->size - 1; i += 4) - writel(*((uint32_t *)(fw->data + i)), dmb_addr + i); - release_firmware(fw); - - ret = request_firmware(&fw, MEDIATEK_2P5GE_PHY_PMB_FW, dev); - if (ret) { - dev_err(dev, "failed to load firmware: %s, ret: %d\n", - MEDIATEK_2P5GE_PHY_PMB_FW, ret); - return ret; - } - for (i = 0; i < fw->size - 1; i += 4) - writel(*((uint32_t *)(fw->data + i)), pmb_addr + i); - release_firmware(fw); - - reg = readw(mcucsr_base + MD32_EN_CFG); - writew(reg | MD32_EN, mcucsr_base + MD32_EN_CFG); - dev_dbg(dev, "Firmware loading/trigger ok.\n"); /* Setup LED */ - phy_clear_bits_mmd(phydev, MDIO_MMD_VEND2, MTK_PHY_LED0_ON_CTRL, - MTK_PHY_LED0_POLARITY); - phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, MTK_PHY_LED0_ON_CTRL, MTK_PHY_LED0_ON_LINK10 | MTK_PHY_LED0_ON_LINK100 | MTK_PHY_LED0_ON_LINK1000 | MTK_PHY_LED0_ON_LINK2500); - phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, MTK_PHY_LED1_ON_CTRL, MTK_PHY_LED1_ON_FDX | MTK_PHY_LED1_ON_HDX); @@ -116,10 +151,20 @@ static int mt798x_2p5ge_phy_config_init(struct phy_device *phydev) return PTR_ERR(pinctrl); } + phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_LPI_PCS_DSP_CTRL, + MTK_PHY_LPI_SIG_EN_LO_THRESH100_MASK, 0); + + /* Enable 16-bit next page exchange bit if 1000-BT isn't advertizing */ + phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_52B5); + __phy_write(phydev, 0x11, 0xfbfa); + __phy_write(phydev, 0x12, 0xc3); + __phy_write(phydev, 0x10, 0x87f8); + phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0); + return 0; } -static int mt798x_2p5ge_phy_config_aneg(struct phy_device *phydev) +static int mt7988_2p5ge_phy_config_aneg(struct phy_device *phydev) { bool changed = false; u32 adv; @@ -152,7 +197,7 @@ static int mt798x_2p5ge_phy_config_aneg(struct phy_device *phydev) return genphy_c45_check_and_restart_aneg(phydev, changed); } -static int mt798x_2p5ge_phy_get_features(struct phy_device *phydev) +static int mt7988_2p5ge_phy_get_features(struct phy_device *phydev) { int ret; @@ -160,7 +205,7 @@ static int mt798x_2p5ge_phy_get_features(struct phy_device *phydev) if (ret) return ret; - /* We don't support HDX at MAC layer on mt798x. + /* We don't support HDX at MAC layer on mt7988. * So mask phy's HDX capabilities, too. */ linkmode_set_bit(ETHTOOL_LINK_MODE_10baseT_Full_BIT, @@ -176,7 +221,7 @@ static int mt798x_2p5ge_phy_get_features(struct phy_device *phydev) return 0; } -static int mt798x_2p5ge_phy_read_status(struct phy_device *phydev) +static int mt7988_2p5ge_phy_read_status(struct phy_device *phydev) { int ret; @@ -189,9 +234,6 @@ static int mt798x_2p5ge_phy_read_status(struct phy_device *phydev) phydev->pause = 0; phydev->asym_pause = 0; - if (!phydev->link) - return 0; - if (phydev->autoneg == AUTONEG_ENABLE && phydev->autoneg_complete) { ret = genphy_c45_read_lpa(phydev); if (ret < 0) @@ -222,7 +264,6 @@ static int mt798x_2p5ge_phy_read_status(struct phy_device *phydev) break; case PHY_AUX_SPD_2500: phydev->speed = SPEED_2500; - phydev->duplex = DUPLEX_FULL; /* 2.5G must be FDX */ break; } @@ -231,18 +272,32 @@ static int mt798x_2p5ge_phy_read_status(struct phy_device *phydev) return ret; phydev->duplex = (ret & MTK_PHY_FDX_ENABLE) ? DUPLEX_FULL : DUPLEX_HALF; + /* FIXME: The current firmware always enables rate adaptation mode. */ + phydev->rate_matching = RATE_MATCH_PAUSE; return 0; } +static int mt7988_2p5ge_phy_get_rate_matching(struct phy_device *phydev, + phy_interface_t iface) +{ + return RATE_MATCH_PAUSE; +} + static struct phy_driver mtk_gephy_driver[] = { { - PHY_ID_MATCH_EXACT(0x00339c11), + PHY_ID_MATCH_MODEL(0x00339c11), .name = "MediaTek MT798x 2.5GbE PHY", - .config_init = mt798x_2p5ge_phy_config_init, - .config_aneg = mt798x_2p5ge_phy_config_aneg, - .get_features = mt798x_2p5ge_phy_get_features, - .read_status = mt798x_2p5ge_phy_read_status, + .probe = mt7988_2p5ge_phy_probe, + .config_init = mt7988_2p5ge_phy_config_init, + .config_aneg = mt7988_2p5ge_phy_config_aneg, + .get_features = mt7988_2p5ge_phy_get_features, + .read_status = mt7988_2p5ge_phy_read_status, + .get_rate_matching = mt7988_2p5ge_phy_get_rate_matching, + .suspend = genphy_suspend, + .resume = genphy_resume, + .read_page = mtk_2p5ge_phy_read_page, + .write_page = mtk_2p5ge_phy_write_page, }, }; @@ -258,5 +313,4 @@ MODULE_AUTHOR("SkyLake Huang "); MODULE_LICENSE("GPL"); MODULE_DEVICE_TABLE(mdio, mtk_2p5ge_phy_tbl); -MODULE_FIRMWARE(MEDAITEK_2P5GE_PHY_DMB_FW); -MODULE_FIRMWARE(MEDIATEK_2P5GE_PHY_PMB_FW); +MODULE_FIRMWARE(MT7988_2P5GE_PMB); diff --git a/lede/target/linux/mediatek/files-6.1/drivers/pinctrl/mediatek/pinctrl-mt7988.c b/lede/target/linux/mediatek/files-6.1/drivers/pinctrl/mediatek/pinctrl-mt7988.c index 49c0be1bba..9f92911245 100644 --- a/lede/target/linux/mediatek/files-6.1/drivers/pinctrl/mediatek/pinctrl-mt7988.c +++ b/lede/target/linux/mediatek/files-6.1/drivers/pinctrl/mediatek/pinctrl-mt7988.c @@ -596,6 +596,51 @@ static const struct mtk_pin_field_calc mt7988_pin_r1_range[] = { PIN_FIELD_BASE(83, 83, 1, 0x90, 0x10, 15, 1), }; +static const unsigned int mt7988_pull_type[] = { + MTK_PULL_PUPD_R1R0_TYPE,/*0*/ MTK_PULL_PUPD_R1R0_TYPE,/*1*/ + MTK_PULL_PUPD_R1R0_TYPE,/*2*/ MTK_PULL_PUPD_R1R0_TYPE,/*3*/ + MTK_PULL_PUPD_R1R0_TYPE,/*4*/ MTK_PULL_PUPD_R1R0_TYPE,/*5*/ + MTK_PULL_PUPD_R1R0_TYPE,/*6*/ MTK_PULL_PU_PD_TYPE, /*7*/ + MTK_PULL_PU_PD_TYPE, /*8*/ MTK_PULL_PU_PD_TYPE, /*9*/ + MTK_PULL_PU_PD_TYPE, /*10*/ MTK_PULL_PUPD_R1R0_TYPE,/*11*/ + MTK_PULL_PUPD_R1R0_TYPE,/*12*/ MTK_PULL_PU_PD_TYPE, /*13*/ + MTK_PULL_PU_PD_TYPE, /*14*/ MTK_PULL_PD_TYPE, /*15*/ + MTK_PULL_PD_TYPE, /*16*/ MTK_PULL_PD_TYPE, /*17*/ + MTK_PULL_PD_TYPE, /*18*/ MTK_PULL_PUPD_R1R0_TYPE,/*19*/ + MTK_PULL_PUPD_R1R0_TYPE,/*20*/ MTK_PULL_PUPD_R1R0_TYPE,/*21*/ + MTK_PULL_PUPD_R1R0_TYPE,/*22*/ MTK_PULL_PUPD_R1R0_TYPE,/*23*/ + MTK_PULL_PUPD_R1R0_TYPE,/*24*/ MTK_PULL_PUPD_R1R0_TYPE,/*25*/ + MTK_PULL_PUPD_R1R0_TYPE,/*26*/ MTK_PULL_PUPD_R1R0_TYPE,/*27*/ + MTK_PULL_PUPD_R1R0_TYPE,/*28*/ MTK_PULL_PUPD_R1R0_TYPE,/*29*/ + MTK_PULL_PUPD_R1R0_TYPE,/*30*/ MTK_PULL_PUPD_R1R0_TYPE,/*31*/ + MTK_PULL_PUPD_R1R0_TYPE,/*32*/ MTK_PULL_PUPD_R1R0_TYPE,/*33*/ + MTK_PULL_PUPD_R1R0_TYPE,/*34*/ MTK_PULL_PUPD_R1R0_TYPE,/*35*/ + MTK_PULL_PUPD_R1R0_TYPE,/*36*/ MTK_PULL_PUPD_R1R0_TYPE,/*37*/ + MTK_PULL_PUPD_R1R0_TYPE,/*38*/ MTK_PULL_PUPD_R1R0_TYPE,/*39*/ + MTK_PULL_PUPD_R1R0_TYPE,/*40*/ MTK_PULL_PUPD_R1R0_TYPE,/*41*/ + MTK_PULL_PUPD_R1R0_TYPE,/*42*/ MTK_PULL_PUPD_R1R0_TYPE,/*43*/ + MTK_PULL_PUPD_R1R0_TYPE,/*44*/ MTK_PULL_PUPD_R1R0_TYPE,/*45*/ + MTK_PULL_PUPD_R1R0_TYPE,/*46*/ MTK_PULL_PUPD_R1R0_TYPE,/*47*/ + MTK_PULL_PUPD_R1R0_TYPE,/*48*/ MTK_PULL_PUPD_R1R0_TYPE,/*49*/ + MTK_PULL_PUPD_R1R0_TYPE,/*50*/ MTK_PULL_PUPD_R1R0_TYPE,/*51*/ + MTK_PULL_PUPD_R1R0_TYPE,/*52*/ MTK_PULL_PUPD_R1R0_TYPE,/*53*/ + MTK_PULL_PUPD_R1R0_TYPE,/*54*/ MTK_PULL_PUPD_R1R0_TYPE,/*55*/ + MTK_PULL_PUPD_R1R0_TYPE,/*56*/ MTK_PULL_PUPD_R1R0_TYPE,/*57*/ + MTK_PULL_PUPD_R1R0_TYPE,/*58*/ MTK_PULL_PUPD_R1R0_TYPE,/*59*/ + MTK_PULL_PUPD_R1R0_TYPE,/*60*/ MTK_PULL_PUPD_R1R0_TYPE,/*61*/ + MTK_PULL_PUPD_R1R0_TYPE,/*62*/ MTK_PULL_PU_PD_TYPE, /*63*/ + MTK_PULL_PUPD_R1R0_TYPE,/*64*/ MTK_PULL_PUPD_R1R0_TYPE,/*65*/ + MTK_PULL_PUPD_R1R0_TYPE,/*66*/ MTK_PULL_PUPD_R1R0_TYPE,/*67*/ + MTK_PULL_PUPD_R1R0_TYPE,/*68*/ MTK_PULL_PUPD_R1R0_TYPE,/*69*/ + MTK_PULL_PUPD_R1R0_TYPE,/*70*/ MTK_PULL_PD_TYPE, /*71*/ + MTK_PULL_PD_TYPE, /*72*/ MTK_PULL_PUPD_R1R0_TYPE,/*73*/ + MTK_PULL_PUPD_R1R0_TYPE,/*74*/ MTK_PULL_PU_PD_TYPE, /*75*/ + MTK_PULL_PU_PD_TYPE, /*76*/ MTK_PULL_PU_PD_TYPE, /*77*/ + MTK_PULL_PU_PD_TYPE, /*78*/ MTK_PULL_PU_PD_TYPE, /*79*/ + MTK_PULL_PUPD_R1R0_TYPE,/*80*/ MTK_PULL_PUPD_R1R0_TYPE,/*81*/ + MTK_PULL_PUPD_R1R0_TYPE,/*82*/ MTK_PULL_PUPD_R1R0_TYPE,/*83*/ +}; + static const struct mtk_pin_reg_calc mt7988_reg_cals[] = { [PINCTRL_PIN_REG_MODE] = MTK_RANGE(mt7988_pin_mode_range), [PINCTRL_PIN_REG_DIR] = MTK_RANGE(mt7988_pin_dir_range), @@ -992,11 +1037,11 @@ static int mt7988_uart2_3_funcs[] = { 3, 3, 3, 3 }; static int mt7988_uart1_2_pins[] = { 80, 81, 82, 83 }; static int mt7988_uart1_2_funcs[] = { 1, 1, 1, 1 }; +static int mt7988_uart1_2_lite_pins[] = { 80, 81 }; +static int mt7988_uart1_2_lite_funcs[] = { 1, 1 }; + static int mt7988_tops_uart1_2_pins[] = { 80, 81 }; -static int mt7988_tops_uart1_2_funcs[] = { - 4, - 4, -}; +static int mt7988_tops_uart1_2_funcs[] = { 4, 4, }; static int mt7988_net_wo0_uart_txd_1_pins[] = { 80 }; static int mt7988_net_wo0_uart_txd_1_funcs[] = { 3 }; @@ -1254,6 +1299,8 @@ static const struct group_desc mt7988_groups[] = { PINCTRL_PIN_GROUP("pcie_wake_n2_1", mt7988_pcie_wake_n2_1), /* @GPIO(80,81,82,83) uart1_2 */ PINCTRL_PIN_GROUP("uart1_2", mt7988_uart1_2), + /* @GPIO(80,81) uart1_2_lite */ + PINCTRL_PIN_GROUP("uart1_2_lite", mt7988_uart1_2_lite), /* @GPIO(80) pwm2 */ PINCTRL_PIN_GROUP("pwm2", mt7988_pwm2), /* @GPIO(81) pwm3 */ @@ -1363,6 +1410,7 @@ static const char * const mt7988_uart_groups[] = { "uart1_1", "uart2_3", "uart1_2", + "uart1_2_lite", "tops_uart1_2", "net_wo0_uart_txd_1", "net_wo1_uart_txd_1", @@ -1433,6 +1481,9 @@ static struct mtk_pin_soc mt7988_data = { .bias_disable_get = mtk_pinconf_bias_disable_get, .bias_set = mtk_pinconf_bias_set, .bias_get = mtk_pinconf_bias_get, + .pull_type = mt7988_pull_type, + .bias_set_combo = mtk_pinconf_bias_set_combo, + .bias_get_combo = mtk_pinconf_bias_get_combo, .drive_set = mtk_pinconf_drive_set_rev1, .drive_get = mtk_pinconf_drive_get_rev1, .adv_pull_get = mtk_pinconf_adv_pull_get, diff --git a/lede/target/linux/mediatek/files-6.1/include/dt-bindings/clock/mediatek,mt7988-clk.h b/lede/target/linux/mediatek/files-6.1/include/dt-bindings/clock/mediatek,mt7988-clk.h deleted file mode 100644 index 77cfea4a8e..0000000000 --- a/lede/target/linux/mediatek/files-6.1/include/dt-bindings/clock/mediatek,mt7988-clk.h +++ /dev/null @@ -1,276 +0,0 @@ -/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ -/* - * Copyright (c) 2023 MediaTek Inc. - * Author: Sam Shih - * Author: Xiufeng Li - */ - -#ifndef _DT_BINDINGS_CLK_MT7988_H -#define _DT_BINDINGS_CLK_MT7988_H - -/* APMIXEDSYS */ - -#define CLK_APMIXED_NETSYSPLL 0 -#define CLK_APMIXED_MPLL 1 -#define CLK_APMIXED_MMPLL 2 -#define CLK_APMIXED_APLL2 3 -#define CLK_APMIXED_NET1PLL 4 -#define CLK_APMIXED_NET2PLL 5 -#define CLK_APMIXED_WEDMCUPLL 6 -#define CLK_APMIXED_SGMPLL 7 -#define CLK_APMIXED_ARM_B 8 -#define CLK_APMIXED_CCIPLL2_B 9 -#define CLK_APMIXED_USXGMIIPLL 10 -#define CLK_APMIXED_MSDCPLL 11 - -/* TOPCKGEN */ - -#define CLK_TOP_XTAL 0 -#define CLK_TOP_XTAL_D2 1 -#define CLK_TOP_RTC_32K 2 -#define CLK_TOP_RTC_32P7K 3 -#define CLK_TOP_MPLL_D2 4 -#define CLK_TOP_MPLL_D3_D2 5 -#define CLK_TOP_MPLL_D4 6 -#define CLK_TOP_MPLL_D8 7 -#define CLK_TOP_MPLL_D8_D2 8 -#define CLK_TOP_MMPLL_D2 9 -#define CLK_TOP_MMPLL_D3_D5 10 -#define CLK_TOP_MMPLL_D4 11 -#define CLK_TOP_MMPLL_D6_D2 12 -#define CLK_TOP_MMPLL_D8 13 -#define CLK_TOP_APLL2_D4 14 -#define CLK_TOP_NET1PLL_D4 15 -#define CLK_TOP_NET1PLL_D5 16 -#define CLK_TOP_NET1PLL_D5_D2 17 -#define CLK_TOP_NET1PLL_D5_D4 18 -#define CLK_TOP_NET1PLL_D8 19 -#define CLK_TOP_NET1PLL_D8_D2 20 -#define CLK_TOP_NET1PLL_D8_D4 21 -#define CLK_TOP_NET1PLL_D8_D8 22 -#define CLK_TOP_NET1PLL_D8_D16 23 -#define CLK_TOP_NET2PLL_D2 24 -#define CLK_TOP_NET2PLL_D4 25 -#define CLK_TOP_NET2PLL_D4_D4 26 -#define CLK_TOP_NET2PLL_D4_D8 27 -#define CLK_TOP_NET2PLL_D6 28 -#define CLK_TOP_NET2PLL_D8 29 -#define CLK_TOP_NETSYS_SEL 30 -#define CLK_TOP_NETSYS_500M_SEL 31 -#define CLK_TOP_NETSYS_2X_SEL 32 -#define CLK_TOP_NETSYS_GSW_SEL 33 -#define CLK_TOP_ETH_GMII_SEL 34 -#define CLK_TOP_NETSYS_MCU_SEL 35 -#define CLK_TOP_NETSYS_PAO_2X_SEL 36 -#define CLK_TOP_EIP197_SEL 37 -#define CLK_TOP_AXI_INFRA_SEL 38 -#define CLK_TOP_UART_SEL 39 -#define CLK_TOP_EMMC_250M_SEL 40 -#define CLK_TOP_EMMC_400M_SEL 41 -#define CLK_TOP_SPI_SEL 42 -#define CLK_TOP_SPIM_MST_SEL 43 -#define CLK_TOP_NFI1X_SEL 44 -#define CLK_TOP_SPINFI_SEL 45 -#define CLK_TOP_PWM_SEL 46 -#define CLK_TOP_I2C_SEL 47 -#define CLK_TOP_PCIE_MBIST_250M_SEL 48 -#define CLK_TOP_PEXTP_TL_SEL 49 -#define CLK_TOP_PEXTP_TL_P1_SEL 50 -#define CLK_TOP_PEXTP_TL_P2_SEL 51 -#define CLK_TOP_PEXTP_TL_P3_SEL 52 -#define CLK_TOP_USB_SYS_SEL 53 -#define CLK_TOP_USB_SYS_P1_SEL 54 -#define CLK_TOP_USB_XHCI_SEL 55 -#define CLK_TOP_USB_XHCI_P1_SEL 56 -#define CLK_TOP_USB_FRMCNT_SEL 57 -#define CLK_TOP_USB_FRMCNT_P1_SEL 58 -#define CLK_TOP_AUD_SEL 59 -#define CLK_TOP_A1SYS_SEL 60 -#define CLK_TOP_AUD_L_SEL 61 -#define CLK_TOP_A_TUNER_SEL 62 -#define CLK_TOP_SSPXTP_SEL 63 -#define CLK_TOP_USB_PHY_SEL 64 -#define CLK_TOP_USXGMII_SBUS_0_SEL 65 -#define CLK_TOP_USXGMII_SBUS_1_SEL 66 -#define CLK_TOP_SGM_0_SEL 67 -#define CLK_TOP_SGM_SBUS_0_SEL 68 -#define CLK_TOP_SGM_1_SEL 69 -#define CLK_TOP_SGM_SBUS_1_SEL 70 -#define CLK_TOP_XFI_PHY_0_XTAL_SEL 71 -#define CLK_TOP_XFI_PHY_1_XTAL_SEL 72 -#define CLK_TOP_SYSAXI_SEL 73 -#define CLK_TOP_SYSAPB_SEL 74 -#define CLK_TOP_ETH_REFCK_50M_SEL 75 -#define CLK_TOP_ETH_SYS_200M_SEL 76 -#define CLK_TOP_ETH_SYS_SEL 77 -#define CLK_TOP_ETH_XGMII_SEL 78 -#define CLK_TOP_BUS_TOPS_SEL 79 -#define CLK_TOP_NPU_TOPS_SEL 80 -#define CLK_TOP_DRAMC_SEL 81 -#define CLK_TOP_DRAMC_MD32_SEL 82 -#define CLK_TOP_INFRA_F26M_SEL 83 -#define CLK_TOP_PEXTP_P0_SEL 84 -#define CLK_TOP_PEXTP_P1_SEL 85 -#define CLK_TOP_PEXTP_P2_SEL 86 -#define CLK_TOP_PEXTP_P3_SEL 87 -#define CLK_TOP_DA_XTP_GLB_P0_SEL 88 -#define CLK_TOP_DA_XTP_GLB_P1_SEL 89 -#define CLK_TOP_DA_XTP_GLB_P2_SEL 90 -#define CLK_TOP_DA_XTP_GLB_P3_SEL 91 -#define CLK_TOP_CKM_SEL 92 -#define CLK_TOP_DA_SEL 93 -#define CLK_TOP_PEXTP_SEL 94 -#define CLK_TOP_TOPS_P2_26M_SEL 95 -#define CLK_TOP_MCUSYS_BACKUP_625M_SEL 96 -#define CLK_TOP_NETSYS_SYNC_250M_SEL 97 -#define CLK_TOP_MACSEC_SEL 98 -#define CLK_TOP_NETSYS_TOPS_400M_SEL 99 -#define CLK_TOP_NETSYS_PPEFB_250M_SEL 100 -#define CLK_TOP_NETSYS_WARP_SEL 101 -#define CLK_TOP_ETH_MII_SEL 102 -#define CLK_TOP_NPU_SEL 103 -#define CLK_TOP_AUD_I2S_M 104 - -/* MCUSYS */ - -#define CLK_MCU_BUS_DIV_SEL 0 -#define CLK_MCU_ARM_DIV_SEL 1 - -/* INFRACFG_AO */ - -#define CLK_INFRA_MUX_UART0_SEL 0 -#define CLK_INFRA_MUX_UART1_SEL 1 -#define CLK_INFRA_MUX_UART2_SEL 2 -#define CLK_INFRA_MUX_SPI0_SEL 3 -#define CLK_INFRA_MUX_SPI1_SEL 4 -#define CLK_INFRA_MUX_SPI2_SEL 5 -#define CLK_INFRA_PWM_SEL 6 -#define CLK_INFRA_PWM_CK1_SEL 7 -#define CLK_INFRA_PWM_CK2_SEL 8 -#define CLK_INFRA_PWM_CK3_SEL 9 -#define CLK_INFRA_PWM_CK4_SEL 10 -#define CLK_INFRA_PWM_CK5_SEL 11 -#define CLK_INFRA_PWM_CK6_SEL 12 -#define CLK_INFRA_PWM_CK7_SEL 13 -#define CLK_INFRA_PWM_CK8_SEL 14 -#define CLK_INFRA_PCIE_GFMUX_TL_O_P0_SEL 15 -#define CLK_INFRA_PCIE_GFMUX_TL_O_P1_SEL 16 -#define CLK_INFRA_PCIE_GFMUX_TL_O_P2_SEL 17 -#define CLK_INFRA_PCIE_GFMUX_TL_O_P3_SEL 18 - -/* INFRACFG */ - -#define CLK_INFRA_PCIE_PERI_26M_CK_P0 19 -#define CLK_INFRA_PCIE_PERI_26M_CK_P1 20 -#define CLK_INFRA_PCIE_PERI_26M_CK_P2 21 -#define CLK_INFRA_PCIE_PERI_26M_CK_P3 22 -#define CLK_INFRA_66M_GPT_BCK 23 -#define CLK_INFRA_66M_PWM_HCK 24 -#define CLK_INFRA_66M_PWM_BCK 25 -#define CLK_INFRA_66M_PWM_CK1 26 -#define CLK_INFRA_66M_PWM_CK2 27 -#define CLK_INFRA_66M_PWM_CK3 28 -#define CLK_INFRA_66M_PWM_CK4 29 -#define CLK_INFRA_66M_PWM_CK5 30 -#define CLK_INFRA_66M_PWM_CK6 31 -#define CLK_INFRA_66M_PWM_CK7 32 -#define CLK_INFRA_66M_PWM_CK8 33 -#define CLK_INFRA_133M_CQDMA_BCK 34 -#define CLK_INFRA_66M_AUD_SLV_BCK 35 -#define CLK_INFRA_AUD_26M 36 -#define CLK_INFRA_AUD_L 37 -#define CLK_INFRA_AUD_AUD 38 -#define CLK_INFRA_AUD_EG2 39 -#define CLK_INFRA_DRAMC_F26M 40 -#define CLK_INFRA_133M_DBG_ACKM 41 -#define CLK_INFRA_66M_AP_DMA_BCK 42 -#define CLK_INFRA_66M_SEJ_BCK 43 -#define CLK_INFRA_PRE_CK_SEJ_F13M 44 -#define CLK_INFRA_26M_THERM_SYSTEM 45 -#define CLK_INFRA_I2C_BCK 46 -#define CLK_INFRA_52M_UART0_CK 47 -#define CLK_INFRA_52M_UART1_CK 48 -#define CLK_INFRA_52M_UART2_CK 49 -#define CLK_INFRA_NFI 50 -#define CLK_INFRA_SPINFI 51 -#define CLK_INFRA_66M_NFI_HCK 52 -#define CLK_INFRA_104M_SPI0 53 -#define CLK_INFRA_104M_SPI1 54 -#define CLK_INFRA_104M_SPI2_BCK 55 -#define CLK_INFRA_66M_SPI0_HCK 56 -#define CLK_INFRA_66M_SPI1_HCK 57 -#define CLK_INFRA_66M_SPI2_HCK 58 -#define CLK_INFRA_66M_FLASHIF_AXI 59 -#define CLK_INFRA_RTC 60 -#define CLK_INFRA_26M_ADC_BCK 61 -#define CLK_INFRA_RC_ADC 62 -#define CLK_INFRA_MSDC400 63 -#define CLK_INFRA_MSDC2_HCK 64 -#define CLK_INFRA_133M_MSDC_0_HCK 65 -#define CLK_INFRA_66M_MSDC_0_HCK 66 -#define CLK_INFRA_133M_CPUM_BCK 67 -#define CLK_INFRA_BIST2FPC 68 -#define CLK_INFRA_I2C_X16W_MCK_CK_P1 69 -#define CLK_INFRA_I2C_X16W_PCK_CK_P1 70 -#define CLK_INFRA_133M_USB_HCK 71 -#define CLK_INFRA_133M_USB_HCK_CK_P1 72 -#define CLK_INFRA_66M_USB_HCK 73 -#define CLK_INFRA_66M_USB_HCK_CK_P1 74 -#define CLK_INFRA_USB_SYS 75 -#define CLK_INFRA_USB_SYS_CK_P1 76 -#define CLK_INFRA_USB_REF 77 -#define CLK_INFRA_USB_CK_P1 78 -#define CLK_INFRA_USB_FRMCNT 79 -#define CLK_INFRA_USB_FRMCNT_CK_P1 80 -#define CLK_INFRA_USB_PIPE 81 -#define CLK_INFRA_USB_PIPE_CK_P1 82 -#define CLK_INFRA_USB_UTMI 83 -#define CLK_INFRA_USB_UTMI_CK_P1 84 -#define CLK_INFRA_USB_XHCI 85 -#define CLK_INFRA_USB_XHCI_CK_P1 86 -#define CLK_INFRA_PCIE_GFMUX_TL_P0 87 -#define CLK_INFRA_PCIE_GFMUX_TL_P1 88 -#define CLK_INFRA_PCIE_GFMUX_TL_P2 89 -#define CLK_INFRA_PCIE_GFMUX_TL_P3 90 -#define CLK_INFRA_PCIE_PIPE_P0 91 -#define CLK_INFRA_PCIE_PIPE_P1 92 -#define CLK_INFRA_PCIE_PIPE_P2 93 -#define CLK_INFRA_PCIE_PIPE_P3 94 -#define CLK_INFRA_133M_PCIE_CK_P0 95 -#define CLK_INFRA_133M_PCIE_CK_P1 96 -#define CLK_INFRA_133M_PCIE_CK_P2 97 -#define CLK_INFRA_133M_PCIE_CK_P3 98 - -/* ETHDMA */ - -#define CLK_ETHDMA_XGP1_EN 0 -#define CLK_ETHDMA_XGP2_EN 1 -#define CLK_ETHDMA_XGP3_EN 2 -#define CLK_ETHDMA_FE_EN 3 -#define CLK_ETHDMA_GP2_EN 4 -#define CLK_ETHDMA_GP1_EN 5 -#define CLK_ETHDMA_GP3_EN 6 -#define CLK_ETHDMA_ESW_EN 7 -#define CLK_ETHDMA_CRYPT0_EN 8 -#define CLK_ETHDMA_NR_CLK 9 - -/* SGMIISYS_0 */ - -#define CLK_SGM0_TX_EN 0 -#define CLK_SGM0_RX_EN 1 -#define CLK_SGMII0_NR_CLK 2 - -/* SGMIISYS_1 */ - -#define CLK_SGM1_TX_EN 0 -#define CLK_SGM1_RX_EN 1 -#define CLK_SGMII1_NR_CLK 2 - -/* ETHWARP */ - -#define CLK_ETHWARP_WOCPU2_EN 0 -#define CLK_ETHWARP_WOCPU1_EN 1 -#define CLK_ETHWARP_WOCPU0_EN 2 -#define CLK_ETHWARP_NR_CLK 3 - -#endif /* _DT_BINDINGS_CLK_MT7988_H */ diff --git a/lede/target/linux/mediatek/files/block/partitions/fit.c b/lede/target/linux/mediatek/files/block/partitions/fit.c index 0d531f49a3..463cd4e9ab 100644 --- a/lede/target/linux/mediatek/files/block/partitions/fit.c +++ b/lede/target/linux/mediatek/files/block/partitions/fit.c @@ -73,11 +73,7 @@ int parse_fit_partitions(struct parsed_partitions *state, u64 fit_start_sector, u64 sectors, int *slot, int add_remain) { -#if LINUX_VERSION_CODE >= KERNEL_VERSION(5, 11, 0) struct block_device *bdev = state->disk->part0; -#else - struct block_device *bdev = state->bdev; -#endif struct address_space *mapping = bdev->bd_inode->i_mapping; struct page *page; void *fit, *init_fit; @@ -104,8 +100,11 @@ int parse_fit_partitions(struct parsed_partitions *state, u64 fit_start_sector, return -ERANGE; page = read_mapping_page(mapping, fit_start_sector >> (PAGE_SHIFT - SECTOR_SHIFT), NULL); - if (!page) - return -ENOMEM; + if (IS_ERR(page)) + return -EFAULT; + + if (PageError(page)) + return -EFAULT; init_fit = page_address(page); @@ -224,8 +223,8 @@ int parse_fit_partitions(struct parsed_partitions *state, u64 fit_start_sector, image_description = fdt_getprop(fit, node, FIT_DESC_PROP, &image_description_len); - printk(KERN_DEBUG "FIT: %16s sub-image 0x%08x - 0x%08x \"%s\" %s%s%s\n", - image_type, image_pos, image_pos + image_len, image_name, + printk(KERN_DEBUG "FIT: %16s sub-image 0x%08x..0x%08x \"%s\" %s%s%s\n", + image_type, image_pos, image_pos + image_len - 1, image_name, image_description?"(":"", image_description?:"", image_description?") ":""); if (strcmp(image_type, FIT_FILESYSTEM_PROP)) diff --git a/lede/target/linux/mediatek/files/drivers/leds/leds-smartrg-system.c b/lede/target/linux/mediatek/files/drivers/leds/leds-smartrg-system.c index 5e1e3a3542..7736905704 100644 --- a/lede/target/linux/mediatek/files/drivers/leds/leds-smartrg-system.c +++ b/lede/target/linux/mediatek/files/drivers/leds/leds-smartrg-system.c @@ -7,6 +7,7 @@ #include #include #include +#include /** * Driver for SmartRG RGBW LED microcontroller. @@ -159,7 +160,11 @@ srg_led_init_led(struct srg_led_ctrl *sysled_ctrl, struct device_node *np) static int +#if LINUX_VERSION_CODE < KERNEL_VERSION(6,6,0) +srg_led_probe(struct i2c_client *client, const struct i2c_device_id *id) +#else srg_led_probe(struct i2c_client *client) +#endif { struct device_node *np = client->dev.of_node, *child; struct srg_led_ctrl *sysled_ctrl; @@ -193,13 +198,21 @@ static void srg_led_disable(struct i2c_client *client) srg_led_i2c_write(sysled_ctrl, i, 0); } +#if LINUX_VERSION_CODE >= KERNEL_VERSION(5,16,0) static void +#else +static int +#endif srg_led_remove(struct i2c_client *client) { struct srg_led_ctrl *sysled_ctrl = i2c_get_clientdata(client); srg_led_disable(client); mutex_destroy(&sysled_ctrl->lock); + +#if LINUX_VERSION_CODE < KERNEL_VERSION(5,16,0) + return 0; +#endif } static const struct i2c_device_id srg_led_id[] = { diff --git a/lede/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/acl.c b/lede/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/acl.c index 75e5a5e740..85c12b000f 100644 --- a/lede/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/acl.c +++ b/lede/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/acl.c @@ -144,7 +144,7 @@ static rtk_api_ret_t _rtk_filter_igrAcl_writeDataField(rtl8367c_aclrule *aclRule * RT_ERR_SMI - SMI access error * RT_ERR_NULL_POINTER - Pointer pFilter_field or pFilter_cfg point to NULL. * Note: - * This function enable and intialize ACL function + * This function enable and initialize ACL function */ rtk_api_ret_t rtk_filter_igrAcl_init(void) { @@ -204,7 +204,7 @@ rtk_api_ret_t rtk_filter_igrAcl_init(void) * This function add a comparison rule (*pFilter_field) to an ACL configuration (*pFilter_cfg). * Pointer pFilter_cfg points to an ACL configuration structure, this structure keeps multiple ACL * comparison rules by means of linked list. Pointer pFilter_field will be added to linked - * list keeped by structure that pFilter_cfg points to. + * list kept by structure that pFilter_cfg points to. */ rtk_api_ret_t rtk_filter_igrAcl_field_add(rtk_filter_cfg_t* pFilter_cfg, rtk_filter_field_t* pFilter_field) { @@ -348,7 +348,7 @@ static rtk_api_ret_t _rtk_filter_igrAcl_writeDataField(rtl8367c_aclrule *aclRule } else { - /*default acl template for ipv6 address supports MSB 32-bits and LSB 32-bits only*/ + /*default ACL template for ipv6 address supports MSB 32-bits and LSB 32-bits only*/ aclRule[tempIdx].data_bits.field[fieldIdx] = ((ip6addr[3] & (0xFFFF << ((i&1) * 16))) >> ((i&1) * 16)); aclRule[tempIdx].care_bits.field[fieldIdx] = ((ip6mask[3] & (0xFFFF << ((i&1) * 16))) >> ((i&1) * 16)); } @@ -557,7 +557,7 @@ static rtk_api_ret_t _rtk_filter_igrAcl_writeDataField(rtl8367c_aclrule *aclRule * pFilter_cfg - The ACL configuration that this function will add comparison rule * pFilter_action - Action(s) of ACL configuration. * Output: - * ruleNum - number of rules written in acl table + * ruleNum - number of rules written in ACL table * Return: * RT_ERR_OK - OK * RT_ERR_FAILED - Failed @@ -1140,12 +1140,12 @@ rtk_api_ret_t rtk_filter_igrAcl_cfg_delAll(void) /* Function Name: * rtk_filter_igrAcl_cfg_get * Description: - * Get one ingress acl configuration from ASIC. + * Get one ingress ACL configuration from ASIC. * Input: * filter_id - Start index of ACL configuration. * Output: - * pFilter_cfg - buffer pointer of ingress acl data - * pFilter_action - buffer pointer of ingress acl action + * pFilter_cfg - buffer pointer of ingress ACL data + * pFilter_action - buffer pointer of ingress ACL action * Return: * RT_ERR_OK - OK * RT_ERR_FAILED - Failed @@ -1462,7 +1462,7 @@ rtk_api_ret_t rtk_filter_igrAcl_cfg_get(rtk_filter_id_t filter_id, rtk_filter_cf * RT_ERR_PORT_ID - Invalid port id. * RT_ERR_INPUT - Invalid input parameters. * Note: - * This function sets action of packets when no ACL configruation matches. + * This function sets action of packets when no ACL configuration matches. */ rtk_api_ret_t rtk_filter_igrAcl_unmatchAction_set(rtk_port_t port, rtk_filter_unmatch_action_t action) { @@ -1535,7 +1535,7 @@ rtk_api_ret_t rtk_filter_igrAcl_unmatchAction_get(rtk_port_t port, rtk_filter_un * RT_ERR_PORT_ID - Invalid port id. * RT_ERR_INPUT - Invalid input parameters. * Note: - * This function gets action of packets when no ACL configruation matches. + * This function gets action of packets when no ACL configuration matches. */ rtk_api_ret_t rtk_filter_igrAcl_state_set(rtk_port_t port, rtk_filter_state_t state) { @@ -1571,7 +1571,7 @@ rtk_api_ret_t rtk_filter_igrAcl_state_set(rtk_port_t port, rtk_filter_state_t st * RT_ERR_PORT_ID - Invalid port id. * RT_ERR_INPUT - Invalid input parameters. * Note: - * This function gets action of packets when no ACL configruation matches. + * This function gets action of packets when no ACL configuration matches. */ rtk_api_ret_t rtk_filter_igrAcl_state_get(rtk_port_t port, rtk_filter_state_t* pState) { @@ -1699,7 +1699,7 @@ rtk_api_ret_t rtk_filter_igrAcl_template_get(rtk_filter_template_t *aclTemplate) * RT_ERR_FAILED - Failed * RT_ERR_SMI - SMI access error * Note: - * System support 16 user defined field selctors. + * System support 16 user defined field selectors. * Each selector can be enabled or disable. * User can defined retrieving 16-bits in many predefiend * standard l2/l3/l4 payload. @@ -1928,7 +1928,7 @@ rtk_api_ret_t rtk_filter_vidrange_get(rtk_uint32 index, rtk_filter_vidrange_t *p * Set Port Range check * Input: * index - index of Port Range 0-15 - * type - IP Range check type, 0:Delete a entry, 1: Source Port, 2: Destnation Port + * type - IP Range check type, 0:Delete a entry, 1: Source Port, 2: Destination Port * upperPort - The upper bound of Port range * lowerPort - The lower Bound of Port range * Output: @@ -1977,7 +1977,7 @@ rtk_api_ret_t rtk_filter_portrange_set(rtk_uint32 index, rtk_filter_portrange_t * Input: * index - index of Port Range 0-15 * Output: - * pType - IP Range check type, 0:Delete a entry, 1: Source Port, 2: Destnation Port + * pType - IP Range check type, 0:Delete a entry, 1: Source Port, 2: Destination Port * pUpperPort - The upper bound of Port range * pLowerPort - The lower Bound of Port range * Return: @@ -2011,7 +2011,7 @@ rtk_api_ret_t rtk_filter_portrange_get(rtk_uint32 index, rtk_filter_portrange_t /* Function Name: * rtk_filter_igrAclPolarity_set * Description: - * Set ACL Goip control palarity + * Set ACL Goip control polarity * Input: * polarity - 1: High, 0: Low * Output: @@ -2034,7 +2034,7 @@ rtk_api_ret_t rtk_filter_igrAclPolarity_set(rtk_uint32 polarity) /* Function Name: * rtk_filter_igrAclPolarity_get * Description: - * Get ACL Goip control palarity + * Get ACL Goip control polarity * Input: * pPolarity - 1: High, 0: Low * Output: diff --git a/lede/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/cpu.c b/lede/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/cpu.c index d1cd95b37a..b031cbe920 100644 --- a/lede/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/cpu.c +++ b/lede/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/cpu.c @@ -113,7 +113,7 @@ rtk_api_ret_t rtk_cpu_enable_get(rtk_enable_t *pEnable) * Note: * The API can set CPU port and inserting proprietary CPU tag mode (Length/Type 0x8899) * to the frame that transmitting to CPU port. - * The inset cpu tag mode is as following: + * The insert CPU tag mode is as following: * - CPU_INSERT_TO_ALL * - CPU_INSERT_TO_TRAPPING * - CPU_INSERT_TO_NONE @@ -160,7 +160,7 @@ rtk_api_ret_t rtk_cpu_tagPort_set(rtk_port_t port, rtk_cpu_insert_t mode) * RT_ERR_L2_NO_CPU_PORT - CPU port is not exist * Note: * The API can get configured CPU port and its setting. - * The inset cpu tag mode is as following: + * The insert CPU tag mode is as following: * - CPU_INSERT_TO_ALL * - CPU_INSERT_TO_TRAPPING * - CPU_INSERT_TO_NONE diff --git a/lede/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/igmp.c b/lede/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/igmp.c index 170cbdaaf0..18e145a21c 100644 --- a/lede/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/igmp.c +++ b/lede/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/igmp.c @@ -233,7 +233,7 @@ rtk_api_ret_t rtk_igmp_static_router_port_get(rtk_portmask_t *pPortmask) * Input: * port - Port ID * protocol - IGMP/MLD protocol - * action - Per-port and per-protocol IGMP action seeting + * action - Per-port and per-protocol IGMP action setting * Output: * None. * Return: @@ -321,7 +321,7 @@ rtk_api_ret_t rtk_igmp_protocol_set(rtk_port_t port, rtk_igmp_protocol_t protoco * Input: * port - Port ID * protocol - IGMP/MLD protocol - * action - Per-port and per-protocol IGMP action seeting + * action - Per-port and per-protocol IGMP action setting * Output: * None. * Return: @@ -1217,7 +1217,7 @@ rtk_api_ret_t rtk_igmp_portRxPktEnable_get(rtk_port_t port, rtk_igmp_rxPktEnable * Description: * Get IGMP/MLD Group database * Input: - * indes - Index (0~255) + * index - Index (0~255) * Output: * pGroup - Group database information. * Return: @@ -1418,7 +1418,7 @@ rtk_api_ret_t rtk_igmp_ReportLeaveFwdAction_get(rtk_igmp_ReportLeaveFwdAct_t *pA /* Function Name: * rtk_igmp_dropLeaveZeroEnable_set * Description: - * Set the function of droppping Leave packet with group IP = 0.0.0.0 + * Set the function of dropping Leave packet with group IP = 0.0.0.0 * Input: * enabled - Action 1: drop, 0:pass * Output: @@ -1451,7 +1451,7 @@ rtk_api_ret_t rtk_igmp_dropLeaveZeroEnable_set(rtk_enable_t enabled) /* Function Name: * rtk_igmp_dropLeaveZeroEnable_get * Description: - * Get the function of droppping Leave packet with group IP = 0.0.0.0 + * Get the function of dropping Leave packet with group IP = 0.0.0.0 * Input: * None * Output: diff --git a/lede/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/include/acl.h b/lede/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/include/acl.h index 6308da8d42..634e7325d6 100644 --- a/lede/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/include/acl.h +++ b/lede/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/include/acl.h @@ -9,7 +9,7 @@ * * Purpose : RTL8367/RTL8367C switch high-level API * - * Feature : The file includes ACL module high-layer API defination + * Feature : The file includes ACL module high-layer API definition * */ @@ -566,7 +566,7 @@ typedef enum rtk_filter_portrange_e * RT_ERR_SMI - SMI access error * RT_ERR_NULL_POINTER - Pointer pFilter_field or pFilter_cfg point to NULL. * Note: - * This function enable and intialize ACL function + * This function enable and initialize ACL function */ extern rtk_api_ret_t rtk_filter_igrAcl_init(void); @@ -589,7 +589,7 @@ extern rtk_api_ret_t rtk_filter_igrAcl_init(void); * This function add a comparison rule (*pFilter_field) to an ACL configuration (*pFilter_cfg). * Pointer pFilter_cfg points to an ACL configuration structure, this structure keeps multiple ACL * comparison rules by means of linked list. Pointer pFilter_field will be added to linked - * list keeped by structure that pFilter_cfg points to. + * list kept by structure that pFilter_cfg points to. */ extern rtk_api_ret_t rtk_filter_igrAcl_field_add(rtk_filter_cfg_t *pFilter_cfg, rtk_filter_field_t *pFilter_field); @@ -602,7 +602,7 @@ extern rtk_api_ret_t rtk_filter_igrAcl_field_add(rtk_filter_cfg_t *pFilter_cfg, * pFilter_cfg - The ACL configuration that this function will add comparison rule * pFilter_action - Action(s) of ACL configuration. * Output: - * ruleNum - number of rules written in acl table + * ruleNum - number of rules written in ACL table * Return: * RT_ERR_OK - OK * RT_ERR_FAILED - Failed @@ -657,12 +657,12 @@ extern rtk_api_ret_t rtk_filter_igrAcl_cfg_delAll(void); /* Function Name: * rtk_filter_igrAcl_cfg_get * Description: - * Get one ingress acl configuration from ASIC. + * Get one ingress ACL configuration from ASIC. * Input: * filter_id - Start index of ACL configuration. * Output: - * pFilter_cfg - buffer pointer of ingress acl data - * pFilter_action - buffer pointer of ingress acl action + * pFilter_cfg - buffer pointer of ingress ACL data + * pFilter_action - buffer pointer of ingress ACL action * Return: * RT_ERR_OK - OK * RT_ERR_FAILED - Failed @@ -690,7 +690,7 @@ extern rtk_api_ret_t rtk_filter_igrAcl_cfg_get(rtk_filter_id_t filter_id, rtk_fi * RT_ERR_PORT_ID - Invalid port id. * RT_ERR_INPUT - Invalid input parameters. * Note: - * This function sets action of packets when no ACL configruation matches. + * This function sets action of packets when no ACL configuration matches. */ extern rtk_api_ret_t rtk_filter_igrAcl_unmatchAction_set(rtk_port_t port, rtk_filter_unmatch_action_t action); @@ -709,7 +709,7 @@ extern rtk_api_ret_t rtk_filter_igrAcl_unmatchAction_set(rtk_port_t port, rtk_fi * RT_ERR_PORT_ID - Invalid port id. * RT_ERR_INPUT - Invalid input parameters. * Note: - * This function gets action of packets when no ACL configruation matches. + * This function gets action of packets when no ACL configuration matches. */ extern rtk_api_ret_t rtk_filter_igrAcl_unmatchAction_get(rtk_port_t port, rtk_filter_unmatch_action_t* action); @@ -729,7 +729,7 @@ extern rtk_api_ret_t rtk_filter_igrAcl_unmatchAction_get(rtk_port_t port, rtk_fi * RT_ERR_PORT_ID - Invalid port id. * RT_ERR_INPUT - Invalid input parameters. * Note: - * This function gets action of packets when no ACL configruation matches. + * This function gets action of packets when no ACL configuration matches. */ extern rtk_api_ret_t rtk_filter_igrAcl_state_set(rtk_port_t port, rtk_filter_state_t state); @@ -748,7 +748,7 @@ extern rtk_api_ret_t rtk_filter_igrAcl_state_set(rtk_port_t port, rtk_filter_sta * RT_ERR_PORT_ID - Invalid port id. * RT_ERR_INPUT - Invalid input parameters. * Note: - * This function gets action of packets when no ACL configruation matches. + * This function gets action of packets when no ACL configuration matches. */ extern rtk_api_ret_t rtk_filter_igrAcl_state_get(rtk_port_t port, rtk_filter_state_t* state); @@ -802,7 +802,7 @@ extern rtk_api_ret_t rtk_filter_igrAcl_template_get(rtk_filter_template_t *aclTe * RT_ERR_FAILED - Failed * RT_ERR_SMI - SMI access error * Note: - * System support 16 user defined field selctors. + * System support 16 user defined field selectors. * Each selector can be enabled or disable. * User can defined retrieving 16-bits in many predefiend * standard l2/l3/l4 payload. @@ -917,7 +917,7 @@ extern rtk_api_ret_t rtk_filter_vidrange_get(rtk_uint32 index, rtk_filter_vidran * Set Port Range check * Input: * index - index of Port Range 0-15 - * type - IP Range check type, 0:Delete a entry, 1: Source Port, 2: Destnation Port + * type - IP Range check type, 0:Delete a entry, 1: Source Port, 2: Destination Port * upperPort - The upper bound of Port range * lowerPort - The lower Bound of Port range * Output: @@ -940,7 +940,7 @@ extern rtk_api_ret_t rtk_filter_portrange_set(rtk_uint32 index, rtk_filter_portr * Input: * index - index of Port Range 0-15 * Output: - * pType - IP Range check type, 0:Delete a entry, 1: Source Port, 2: Destnation Port + * pType - IP Range check type, 0:Delete a entry, 1: Source Port, 2: Destination Port * pUpperPort - The upper bound of Port range * pLowerPort - The lower Bound of Port range * Return: @@ -957,7 +957,7 @@ extern rtk_api_ret_t rtk_filter_portrange_get(rtk_uint32 index, rtk_filter_portr /* Function Name: * rtk_filter_igrAclPolarity_set * Description: - * Set ACL Goip control palarity + * Set ACL Goip control polarity * Input: * polarity - 1: High, 0: Low * Output: @@ -973,7 +973,7 @@ extern rtk_api_ret_t rtk_filter_igrAclPolarity_set(rtk_uint32 polarity); /* Function Name: * rtk_filter_igrAclPolarity_get * Description: - * Get ACL Goip control palarity + * Get ACL Goip control polarity * Input: * pPolarity - 1: High, 0: Low * Output: diff --git a/lede/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/include/cpu.h b/lede/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/include/cpu.h index 5544aca7b2..67aa1e3d88 100644 --- a/lede/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/include/cpu.h +++ b/lede/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/include/cpu.h @@ -9,7 +9,7 @@ * * Purpose : RTL8367/RTL8367C switch high-level API * - * Feature : The file includes CPU module high-layer API defination + * Feature : The file includes CPU module high-layer API definition * */ @@ -107,7 +107,7 @@ extern rtk_api_ret_t rtk_cpu_enable_get(rtk_enable_t *pEnable); * Note: * The API can set CPU port and inserting proprietary CPU tag mode (Length/Type 0x8899) * to the frame that transmitting to CPU port. - * The inset cpu tag mode is as following: + * The insert CPU tag mode is as following: * - CPU_INSERT_TO_ALL * - CPU_INSERT_TO_TRAPPING * - CPU_INSERT_TO_NONE @@ -131,7 +131,7 @@ extern rtk_api_ret_t rtk_cpu_tagPort_set(rtk_port_t port, rtk_cpu_insert_t mode) * RT_ERR_L2_NO_CPU_PORT - CPU port is not exist * Note: * The API can get configured CPU port and its setting. - * The inset cpu tag mode is as following: + * The insert CPU tag mode is as following: * - CPU_INSERT_TO_ALL * - CPU_INSERT_TO_TRAPPING * - CPU_INSERT_TO_NONE diff --git a/lede/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/include/dot1x.h b/lede/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/include/dot1x.h index ef0a05a04b..082ee2569e 100644 --- a/lede/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/include/dot1x.h +++ b/lede/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/include/dot1x.h @@ -9,7 +9,7 @@ * * Purpose : RTL8367/RTL8367C switch high-level API * - * Feature : The file includes 1X module high-layer API defination + * Feature : The file includes 1X module high-layer API definition * */ diff --git a/lede/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/include/eee.h b/lede/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/include/eee.h index b670998c8c..e3920363d1 100644 --- a/lede/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/include/eee.h +++ b/lede/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/include/eee.h @@ -9,7 +9,7 @@ * * Purpose : RTL8367/RTL8367C switch high-level API * - * Feature : The file includes EEE module high-layer API defination + * Feature : The file includes EEE module high-layer API definition * */ diff --git a/lede/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/include/i2c.h b/lede/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/include/i2c.h index 2c7f0756ae..110f41e818 100644 --- a/lede/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/include/i2c.h +++ b/lede/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/include/i2c.h @@ -9,7 +9,7 @@ * * Purpose : RTL8367/RTL8367C switch high-level API * - * Feature : The file includes I2C module high-layer API defination + * Feature : The file includes I2C module high-layer API definition * */ diff --git a/lede/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/include/igmp.h b/lede/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/include/igmp.h index f088b0ccdd..b36db43d83 100644 --- a/lede/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/include/igmp.h +++ b/lede/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/include/igmp.h @@ -9,7 +9,7 @@ * * Purpose : RTL8367/RTL8367C switch high-level API * - * Feature : The file includes IGMP module high-layer API defination + * Feature : The file includes IGMP module high-layer API definition * */ @@ -205,7 +205,7 @@ extern rtk_api_ret_t rtk_igmp_static_router_port_get(rtk_portmask_t *pPortmask); * Input: * port - Port ID * protocol - IGMP/MLD protocol - * action - Per-port and per-protocol IGMP action seeting + * action - Per-port and per-protocol IGMP action setting * Output: * None. * Return: @@ -225,7 +225,7 @@ extern rtk_api_ret_t rtk_igmp_protocol_set(rtk_port_t port, rtk_igmp_protocol_t * Input: * port - Port ID * protocol - IGMP/MLD protocol - * action - Per-port and per-protocol IGMP action seeting + * action - Per-port and per-protocol IGMP action setting * Output: * None. * Return: @@ -640,7 +640,7 @@ extern rtk_api_ret_t rtk_igmp_portRxPktEnable_get(rtk_port_t port, rtk_igmp_rxPk * Description: * Get IGMP/MLD Group database * Input: - * indes - Index (0~255) + * index - Index (0~255) * Output: * pGroup - Group database information. * Return: @@ -694,7 +694,7 @@ extern rtk_api_ret_t rtk_igmp_ReportLeaveFwdAction_get(rtk_igmp_ReportLeaveFwdAc /* Function Name: * rtk_igmp_dropLeaveZeroEnable_set * Description: - * Set the function of droppping Leave packet with group IP = 0.0.0.0 + * Set the function of dropping Leave packet with group IP = 0.0.0.0 * Input: * enabled - Action 1: drop, 0:pass * Output: @@ -712,7 +712,7 @@ extern rtk_api_ret_t rtk_igmp_dropLeaveZeroEnable_set(rtk_enable_t enabled); /* Function Name: * rtk_igmp_dropLeaveZeroEnable_get * Description: - * Get the function of droppping Leave packet with group IP = 0.0.0.0 + * Get the function of dropping Leave packet with group IP = 0.0.0.0 * Input: * None * Output: diff --git a/lede/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/include/interrupt.h b/lede/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/include/interrupt.h index f2689ebc70..20625fff52 100644 --- a/lede/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/include/interrupt.h +++ b/lede/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/include/interrupt.h @@ -9,7 +9,7 @@ * * Purpose : RTL8367/RTL8367C switch high-level API * - * Feature : The file includes Interrupt module high-layer API defination + * Feature : The file includes Interrupt module high-layer API definition * */ diff --git a/lede/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/include/l2.h b/lede/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/include/l2.h index e0ccdbe3d7..ec5aad2e30 100644 --- a/lede/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/include/l2.h +++ b/lede/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/include/l2.h @@ -9,7 +9,7 @@ * * Purpose : RTL8367/RTL8367C switch high-level API * - * Feature : The file includes L2 module high-layer API defination + * Feature : The file includes L2 module high-layer API definition * */ @@ -209,7 +209,7 @@ extern rtk_api_ret_t rtk_l2_init(void); * RT_ERR_L2_INDEXTBL_FULL - hashed index is full of entries. * RT_ERR_INPUT - Invalid input parameters. * Note: - * If the unicast mac address already existed in LUT, it will udpate the status of the entry. + * If the unicast mac address already existed in LUT, it will update the status of the entry. * Otherwise, it will find an empty or asic auto learned entry to write. If all the entries * with the same hash value can't be replaced, ASIC will return a RT_ERR_L2_INDEXTBL_FULL error. */ @@ -307,7 +307,7 @@ extern rtk_api_ret_t rtk_l2_addr_del(rtk_mac_t *pMac, rtk_l2_ucastAddr_t *pL2_da * RT_ERR_PORT_MASK - Invalid portmask. * RT_ERR_INPUT - Invalid input parameters. * Note: - * If the multicast mac address already existed in the LUT, it will udpate the + * If the multicast mac address already existed in the LUT, it will update the * port mask of the entry. Otherwise, it will find an empty or asic auto learned * entry to write. If all the entries with the same hash value can't be replaced, * ASIC will return a RT_ERR_L2_INDEXTBL_FULL error. @@ -383,7 +383,7 @@ extern rtk_api_ret_t rtk_l2_mcastAddr_del(rtk_l2_mcastAddr_t *pMcastAddr); /* Function Name: * rtk_l2_ipMcastAddr_add * Description: - * Add Lut IP multicast entry + * Add LUT IP multicast entry * Input: * pIpMcastAddr - IP Multicast entry * Output: @@ -418,7 +418,7 @@ extern rtk_api_ret_t rtk_l2_ipMcastAddr_add(rtk_l2_ipMcastAddr_t *pIpMcastAddr); * RT_ERR_L2_ENTRY_NOTFOUND - No such LUT entry. * RT_ERR_INPUT - Invalid input parameters. * Note: - * The API can get Lut table of IP multicast entry. + * The API can get LUT table of IP multicast entry. */ extern rtk_api_ret_t rtk_l2_ipMcastAddr_get(rtk_l2_ipMcastAddr_t *pIpMcastAddr); @@ -465,7 +465,7 @@ extern rtk_api_ret_t rtk_l2_ipMcastAddr_del(rtk_l2_ipMcastAddr_t *pIpMcastAddr); /* Function Name: * rtk_l2_ipVidMcastAddr_add * Description: - * Add Lut IP multicast+VID entry + * Add LUT IP multicast+VID entry * Input: * pIpVidMcastAddr - IP & VID multicast Entry * Output: @@ -913,7 +913,7 @@ extern rtk_api_ret_t rtk_l2_learningCnt_get(rtk_port_t port, rtk_mac_cnt_t *pMac * Set flooding portmask * Input: * type - flooding type. - * pFlood_portmask - flooding porkmask + * pFlood_portmask - flooding portmask * Output: * None * Return: @@ -938,7 +938,7 @@ extern rtk_api_ret_t rtk_l2_floodPortMask_set(rtk_l2_flood_type_t floood_type, r * Input: * type - flooding type. * Output: - * pFlood_portmask - flooding porkmask + * pFlood_portmask - flooding portmask * Return: * RT_ERR_OK - OK * RT_ERR_FAILED - Failed @@ -956,10 +956,10 @@ extern rtk_api_ret_t rtk_l2_floodPortMask_get(rtk_l2_flood_type_t floood_type, r /* Function Name: * rtk_l2_localPktPermit_set * Description: - * Set permittion of frames if source port and destination port are the same. + * Set permission of frames if source port and destination port are the same. * Input: * port - Port id. - * permit - permittion status + * permit - permission status * Output: * None * Return: @@ -969,34 +969,34 @@ extern rtk_api_ret_t rtk_l2_floodPortMask_get(rtk_l2_flood_type_t floood_type, r * RT_ERR_PORT_ID - Invalid port number. * RT_ERR_ENABLE - Invalid permit value. * Note: - * This API is setted to permit frame if its source port is equal to destination port. + * This API is set to permit frame if its source port is equal to destination port. */ extern rtk_api_ret_t rtk_l2_localPktPermit_set(rtk_port_t port, rtk_enable_t permit); /* Function Name: * rtk_l2_localPktPermit_get * Description: - * Get permittion of frames if source port and destination port are the same. + * Get permission of frames if source port and destination port are the same. * Input: * port - Port id. * Output: - * pPermit - permittion status + * pPermit - permission status * Return: * RT_ERR_OK - OK * RT_ERR_FAILED - Failed * RT_ERR_SMI - SMI access error * RT_ERR_PORT_ID - Invalid port number. * Note: - * This API is to get permittion status for frames if its source port is equal to destination port. + * This API is to get permission status for frames if its source port is equal to destination port. */ extern rtk_api_ret_t rtk_l2_localPktPermit_get(rtk_port_t port, rtk_enable_t *pPermit); /* Function Name: * rtk_l2_aging_set * Description: - * Set LUT agging out speed + * Set LUT ageing out speed * Input: - * aging_time - Agging out time. + * aging_time - Ageing out time. * Output: * None * Return: @@ -1005,14 +1005,14 @@ extern rtk_api_ret_t rtk_l2_localPktPermit_get(rtk_port_t port, rtk_enable_t *pP * RT_ERR_SMI - SMI access error * RT_ERR_OUT_OF_RANGE - input out of range. * Note: - * The API can set LUT agging out period for each entry and the range is from 14s to 800s. + * The API can set LUT ageing out period for each entry and the range is from 14s to 800s. */ extern rtk_api_ret_t rtk_l2_aging_set(rtk_l2_age_time_t aging_time); /* Function Name: * rtk_l2_aging_get * Description: - * Get LUT agging out time + * Get LUT ageing out time * Input: * None * Output: @@ -1023,14 +1023,14 @@ extern rtk_api_ret_t rtk_l2_aging_set(rtk_l2_age_time_t aging_time); * RT_ERR_SMI - SMI access error * RT_ERR_PORT_ID - Invalid port number. * Note: - * The API can get LUT agging out period for each entry. + * The API can get LUT ageing out period for each entry. */ extern rtk_api_ret_t rtk_l2_aging_get(rtk_l2_age_time_t *pAging_time); /* Function Name: * rtk_l2_ipMcastAddrLookup_set * Description: - * Set Lut IP multicast lookup function + * Set LUT IP multicast lookup function * Input: * type - Lookup type for IPMC packet. * Output: @@ -1051,7 +1051,7 @@ extern rtk_api_ret_t rtk_l2_ipMcastAddrLookup_set(rtk_l2_ipmc_lookup_type_t type /* Function Name: * rtk_l2_ipMcastAddrLookup_get * Description: - * Get Lut IP multicast lookup function + * Get LUT IP multicast lookup function * Input: * None. * Output: @@ -1068,9 +1068,9 @@ extern rtk_api_ret_t rtk_l2_ipMcastAddrLookup_get(rtk_l2_ipmc_lookup_type_t *pTy /* Function Name: * rtk_l2_ipMcastForwardRouterPort_set * Description: - * Set IPMC packet forward to rounter port also or not + * Set IPMC packet forward to router port also or not * Input: - * enabled - 1: Inlcude router port, 0, exclude router port + * enabled - 1: Include router port, 0, exclude router port * Output: * None. * Return: @@ -1085,11 +1085,11 @@ extern rtk_api_ret_t rtk_l2_ipMcastForwardRouterPort_set(rtk_enable_t enabled); /* Function Name: * rtk_l2_ipMcastForwardRouterPort_get * Description: - * Get IPMC packet forward to rounter port also or not + * Get IPMC packet forward to router port also or not * Input: * None. * Output: - * pEnabled - 1: Inlcude router port, 0, exclude router port + * pEnabled - 1: Include router port, 0, exclude router port * Return: * RT_ERR_OK - OK * RT_ERR_FAILED - Failed diff --git a/lede/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/include/leaky.h b/lede/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/include/leaky.h index 13ef60df83..e5b22e2878 100644 --- a/lede/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/include/leaky.h +++ b/lede/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/include/leaky.h @@ -9,7 +9,7 @@ * * Purpose : RTL8367/RTL8367C switch high-level API * - * Feature : The file includes Leaky module high-layer API defination + * Feature : The file includes Leaky module high-layer API definition * */ diff --git a/lede/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/include/led.h b/lede/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/include/led.h index 71acc7c92c..7706107ef4 100644 --- a/lede/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/include/led.h +++ b/lede/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/include/led.h @@ -9,7 +9,7 @@ * * Purpose : RTL8367/RTL8367C switch high-level API * - * Feature : The file includes LED module high-layer API defination + * Feature : The file includes LED module high-layer API definition * */ @@ -107,7 +107,7 @@ typedef enum rtk_led_serialOutput_e /* Function Name: * rtk_led_enable_set * Description: - * Set Led enable congiuration + * Set Led enable configuration * Input: * group - LED group id. * pPortmask - LED enable port mask. @@ -126,7 +126,7 @@ extern rtk_api_ret_t rtk_led_enable_set(rtk_led_group_t group, rtk_portmask_t *p /* Function Name: * rtk_led_enable_get * Description: - * Get Led enable congiuration + * Get Led enable configuration * Input: * group - LED group id. * Output: @@ -188,7 +188,7 @@ extern rtk_api_ret_t rtk_led_operation_get(rtk_led_operation_t *pMode); /* Function Name: * rtk_led_modeForce_set * Description: - * Set Led group to congiuration force mode + * Set Led group to configuration force mode * Input: * port - port ID * group - Support LED group id. @@ -214,7 +214,7 @@ extern rtk_api_ret_t rtk_led_modeForce_set(rtk_port_t port, rtk_led_group_t grou /* Function Name: * rtk_led_modeForce_get * Description: - * Get Led group to congiuration force mode + * Get Led group to configuration force mode * Input: * port - port ID * group - Support LED group id. @@ -276,7 +276,7 @@ extern rtk_api_ret_t rtk_led_blinkRate_get(rtk_led_blink_rate_t *pBlinkRate); /* Function Name: * rtk_led_groupConfig_set * Description: - * Set per group Led to congiuration mode + * Set per group Led to configuration mode * Input: * group - LED group. * config - LED configuration @@ -312,7 +312,7 @@ extern rtk_api_ret_t rtk_led_groupConfig_set(rtk_led_group_t group, rtk_led_cong /* Function Name: * rtk_led_groupConfig_get * Description: - * Get Led group congiuration mode + * Get Led group configuration mode * Input: * group - LED group. * Output: @@ -370,7 +370,7 @@ extern rtk_api_ret_t rtk_led_groupAbility_get(rtk_led_group_t group, rtk_led_abi /* Function Name: * rtk_led_serialMode_set * Description: - * Set Led serial mode active congiuration + * Set Led serial mode active configuration * Input: * active - LED group. * Output: @@ -381,14 +381,14 @@ extern rtk_api_ret_t rtk_led_groupAbility_get(rtk_led_group_t group, rtk_led_abi * RT_ERR_SMI - SMI access error * RT_ERR_INPUT - Invalid input parameters. * Note: - * The API can set LED serial mode active congiuration. + * The API can set LED serial mode active configuration. */ extern rtk_api_ret_t rtk_led_serialMode_set(rtk_led_active_t active); /* Function Name: * rtk_led_serialMode_get * Description: - * Get Led group congiuration mode + * Get Led group configuration mode * Input: * group - LED group. * Output: diff --git a/lede/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/include/mirror.h b/lede/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/include/mirror.h index 1e984b7d80..8d179ce2df 100644 --- a/lede/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/include/mirror.h +++ b/lede/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/include/mirror.h @@ -9,7 +9,7 @@ * * Purpose : RTL8367/RTL8367C switch high-level API * - * Feature : The file includes Mirror module high-layer API defination + * Feature : The file includes Mirror module high-layer API definition * */ @@ -81,7 +81,7 @@ extern rtk_api_ret_t rtk_mirror_portBased_get(rtk_port_t* pMirroring_port, rtk_p * RT_ERR_SMI - SMI access error * RT_ERR_ENABLE - Invalid enable input * Note: - * The API is to set mirror isolation function that prevent normal forwarding packets to miror port. + * The API is to set mirror isolation function that prevent normal forwarding packets to mirror port. */ extern rtk_api_ret_t rtk_mirror_portIso_set(rtk_enable_t enable); @@ -118,7 +118,7 @@ extern rtk_api_ret_t rtk_mirror_portIso_get(rtk_enable_t *pEnable); * RT_ERR_SMI - SMI access error * RT_ERR_ENABLE - Invalid enable input * Note: - * The API is to set mirror VLAN leaky function forwarding packets to miror port. + * The API is to set mirror VLAN leaky function forwarding packets to mirror port. */ extern rtk_api_ret_t rtk_mirror_vlanLeaky_set(rtk_enable_t txenable, rtk_enable_t rxenable); @@ -157,7 +157,7 @@ extern rtk_api_ret_t rtk_mirror_vlanLeaky_get(rtk_enable_t *pTxenable, rtk_enabl * RT_ERR_SMI - SMI access error * RT_ERR_ENABLE - Invalid enable input * Note: - * The API is to set mirror VLAN leaky function forwarding packets to miror port. + * The API is to set mirror VLAN leaky function forwarding packets to mirror port. */ extern rtk_api_ret_t rtk_mirror_isolationLeaky_set(rtk_enable_t txenable, rtk_enable_t rxenable); diff --git a/lede/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/include/port.h b/lede/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/include/port.h index fcac1bcb84..458f16bf6d 100644 --- a/lede/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/include/port.h +++ b/lede/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/include/port.h @@ -9,7 +9,7 @@ * * Purpose : RTL8367/RTL8367C switch high-level API * - * Feature : The file includes port module high-layer API defination + * Feature : The file includes port module high-layer API definition * */ @@ -222,7 +222,7 @@ typedef struct rtk_rtctResult_s /* Function Name: * rtk_port_phyAutoNegoAbility_set * Description: - * Set ethernet PHY auto-negotiation desired ability. + * Set Ethernet PHY auto-negotiation desired ability. * Input: * port - port id. * pAbility - Ability structure @@ -259,7 +259,7 @@ extern rtk_api_ret_t rtk_port_phyAutoNegoAbility_set(rtk_port_t port, rtk_port_p * RT_ERR_INPUT - Invalid input parameters. * RT_ERR_BUSYWAIT_TIMEOUT - PHY access busy * Note: - * Get the capablity of specified PHY. + * Get the capability of specified PHY. */ extern rtk_api_ret_t rtk_port_phyAutoNegoAbility_get(rtk_port_t port, rtk_port_phy_ability_t *pAbility); @@ -303,14 +303,14 @@ extern rtk_api_ret_t rtk_port_phyForceModeAbility_set(rtk_port_t port, rtk_port_ * RT_ERR_INPUT - Invalid input parameters. * RT_ERR_BUSYWAIT_TIMEOUT - PHY access busy * Note: - * Get the capablity of specified PHY. + * Get the capability of specified PHY. */ extern rtk_api_ret_t rtk_port_phyForceModeAbility_get(rtk_port_t port, rtk_port_phy_ability_t *pAbility); /* Function Name: * rtk_port_phyStatus_get * Description: - * Get ethernet PHY linking status + * Get Ethernet PHY linking status * Input: * port - Port id. * Output: @@ -459,7 +459,7 @@ extern rtk_api_ret_t rtk_port_macStatus_get(rtk_port_t port, rtk_port_mac_abilit * For UTP port, This API will also enable the digital * loopback bit in PHY register for sync of speed between * PHY and MAC. For EXT port, users need to force the - * link state by themself. + * link state by themselves. */ extern rtk_api_ret_t rtk_port_macLocalLoopbackEnable_set(rtk_port_t port, rtk_enable_t enable); @@ -527,7 +527,7 @@ extern rtk_api_ret_t rtk_port_phyReg_get(rtk_port_t port, rtk_port_phy_reg_t reg /* Function Name: * rtk_port_backpressureEnable_set * Description: - * Set the half duplex backpressure enable status of the specific port. + * Set the half duplex back-pressure enable status of the specific port. * Input: * port - port id. * enable - Back pressure status. @@ -540,8 +540,8 @@ extern rtk_api_ret_t rtk_port_phyReg_get(rtk_port_t port, rtk_port_phy_reg_t reg * RT_ERR_PORT_ID - Invalid port number. * RT_ERR_ENABLE - Invalid enable input. * Note: - * This API can set the half duplex backpressure enable status of the specific port. - * The half duplex backpressure enable status of the port is as following: + * This API can set the half duplex back-pressure enable status of the specific port. + * The half duplex back-pressure enable status of the port is as following: * - DISABLE * - ENABLE */ @@ -550,7 +550,7 @@ extern rtk_api_ret_t rtk_port_backpressureEnable_set(rtk_port_t port, rtk_enable /* Function Name: * rtk_port_backpressureEnable_get * Description: - * Get the half duplex backpressure enable status of the specific port. + * Get the half duplex back-pressure enable status of the specific port. * Input: * port - Port id. * Output: @@ -561,8 +561,8 @@ extern rtk_api_ret_t rtk_port_backpressureEnable_set(rtk_port_t port, rtk_enable * RT_ERR_SMI - SMI access error * RT_ERR_PORT_ID - Invalid port number. * Note: - * This API can get the half duplex backpressure enable status of the specific port. - * The half duplex backpressure enable status of the port is as following: + * This API can get the half duplex back-pressure enable status of the specific port. + * The half duplex back-pressure enable status of the port is as following: * - DISABLE * - ENABLE */ @@ -594,7 +594,7 @@ extern rtk_api_ret_t rtk_port_adminEnable_set(rtk_port_t port, rtk_enable_t enab /* Function Name: * rtk_port_adminEnable_get * Description: - * Get port admin configurationof the specific port. + * Get port admin configuration of the specific port. * Input: * port - Port id. * Output: @@ -628,7 +628,7 @@ extern rtk_api_ret_t rtk_port_adminEnable_get(rtk_port_t port, rtk_enable_t *pEn * RT_ERR_PORT_ID - Invalid port number. * RT_ERR_PORT_MASK - Invalid portmask. * Note: - * This API set the port mask that a port can trasmit packet to of each port + * This API set the port mask that a port can transmit packet to of each port * A port can only transmit packet to ports included in permitted portmask */ extern rtk_api_ret_t rtk_port_isolation_set(rtk_port_t port, rtk_portmask_t *pPortmask); @@ -647,7 +647,7 @@ extern rtk_api_ret_t rtk_port_isolation_set(rtk_port_t port, rtk_portmask_t *pPo * RT_ERR_SMI - SMI access error * RT_ERR_PORT_ID - Invalid port number. * Note: - * This API get the port mask that a port can trasmit packet to of each port + * This API get the port mask that a port can transmit packet to of each port * A port can only transmit packet to ports included in permitted portmask */ extern rtk_api_ret_t rtk_port_isolation_get(rtk_port_t port, rtk_portmask_t *pPortmask); @@ -669,7 +669,7 @@ extern rtk_api_ret_t rtk_port_isolation_get(rtk_port_t port, rtk_portmask_t *pPo * Note: * This API can set external interface 2 RGMII delay. * In TX delay, there are 2 selection: no-delay and 2ns delay. - * In RX dekay, there are 8 steps for delay tunning. 0 for no-delay, and 7 for maximum delay. + * In RX delay, there are 8 steps for delay tuning. 0 for no-delay, and 7 for maximum delay. */ extern rtk_api_ret_t rtk_port_rgmiiDelayExt_set(rtk_port_t port, rtk_data_t txDelay, rtk_data_t rxDelay); @@ -690,7 +690,7 @@ extern rtk_api_ret_t rtk_port_rgmiiDelayExt_set(rtk_port_t port, rtk_data_t txDe * Note: * This API can set external interface 2 RGMII delay. * In TX delay, there are 2 selection: no-delay and 2ns delay. - * In RX dekay, there are 8 steps for delay tunning. 0 for n0-delay, and 7 for maximum delay. + * In RX delay, there are 8 steps for delay tuning. 0 for n0-delay, and 7 for maximum delay. */ extern rtk_api_ret_t rtk_port_rgmiiDelayExt_get(rtk_port_t port, rtk_data_t *pTxDelay, rtk_data_t *pRxDelay); diff --git a/lede/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/include/ptp.h b/lede/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/include/ptp.h index 6c4aca5a58..d18c4a01ed 100644 --- a/lede/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/include/ptp.h +++ b/lede/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/include/ptp.h @@ -9,7 +9,7 @@ * * Purpose : RTL8367/RTL8367C switch high-level API * - * Feature : The file includes time module high-layer API defination + * Feature : The file includes time module high-layer API definition * */ @@ -310,7 +310,7 @@ extern rtk_api_ret_t rtk_ptp_portEnable_get(rtk_port_t port, rtk_enable_t *pEnab /* Function Name: * rtk_ptp_portTimestamp_get * Description: - * Get PTP timstamp according to the PTP identifier on the dedicated port from the specified device. + * Get PTP timestamp according to the PTP identifier on the dedicated port from the specified device. * Input: * unit - unit id * port - port id diff --git a/lede/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/include/qos.h b/lede/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/include/qos.h index 4be417486f..d2d8fac24a 100644 --- a/lede/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/include/qos.h +++ b/lede/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/include/qos.h @@ -9,7 +9,7 @@ * * Purpose : RTL8367/RTL8367C switch high-level API * - * Feature : The file includes QoS module high-layer API defination + * Feature : The file includes QoS module high-layer API definition * */ @@ -123,7 +123,7 @@ typedef rtk_uint32 rtk_queue_num_t; /* queue number*/ /* Function Name: * rtk_qos_init * Description: - * Configure Qos default settings with queue number assigment to each port. + * Configure QoS default settings with queue number assignment to each port. * Input: * queueNum - Queue number of each port. * Output: @@ -135,7 +135,7 @@ typedef rtk_uint32 rtk_queue_num_t; /* queue number*/ * RT_ERR_QUEUE_NUM - Invalid queue number. * RT_ERR_INPUT - Invalid input parameters. * Note: - * This API will initialize related Qos setting with queue number assigment. + * This API will initialize related QoS setting with queue number assignment. * The queue number is from 1 to 8. */ extern rtk_api_ret_t rtk_qos_init(rtk_queue_num_t queueNum); @@ -235,7 +235,7 @@ extern rtk_api_ret_t rtk_qos_1pPriRemap_set(rtk_pri_t dot1p_pri, rtk_pri_t int_p * RT_ERR_VLAN_PRIORITY - Invalid priority. * RT_ERR_QOS_INT_PRIORITY - Invalid priority. * Note: - * Priority of 802.1Q assigment for internal asic priority, and it is uesed for queue usage and packet scheduling. + * Priority of 802.1Q assignment for internal asic priority, and it is used for queue usage and packet scheduling. */ extern rtk_api_ret_t rtk_qos_1pPriRemap_get(rtk_pri_t dot1p_pri, rtk_pri_t *pInt_pri); diff --git a/lede/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/include/rate.h b/lede/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/include/rate.h index 231ed01bb0..b3cdf432f7 100644 --- a/lede/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/include/rate.h +++ b/lede/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/include/rate.h @@ -9,7 +9,7 @@ * * Purpose : RTL8367/RTL8367C switch high-level API * - * Feature : The file includes rate module high-layer API defination + * Feature : The file includes rate module high-layer API definition * */ diff --git a/lede/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/include/rtk_error.h b/lede/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/include/rtk_error.h index dc9c0bed35..54d1a13f3b 100644 --- a/lede/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/include/rtk_error.h +++ b/lede/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/include/rtk_error.h @@ -40,7 +40,7 @@ typedef enum rt_error_code_e RT_ERR_NULL_POINTER, /* 0x00000007, input parameter is null pointer */ RT_ERR_QUEUE_ID, /* 0x00000008, invalid queue id */ RT_ERR_QUEUE_NUM, /* 0x00000009, invalid queue number */ - RT_ERR_BUSYWAIT_TIMEOUT, /* 0x0000000a, busy watting time out */ + RT_ERR_BUSYWAIT_TIMEOUT, /* 0x0000000a, busy waiting time out */ RT_ERR_MAC, /* 0x0000000b, invalid mac address */ RT_ERR_OUT_OF_RANGE, /* 0x0000000c, input parameter out of range */ RT_ERR_CHIP_NOT_SUPPORTED, /* 0x0000000d, functions not supported by this chip model */ @@ -57,7 +57,7 @@ typedef enum rt_error_code_e /* 0x0001xxxx for vlan */ RT_ERR_VLAN_VID = 0x00010000, /* 0x00010000, invalid vid */ RT_ERR_VLAN_PRIORITY, /* 0x00010001, invalid 1p priority */ - RT_ERR_VLAN_EMPTY_ENTRY, /* 0x00010002, emtpy entry of vlan table */ + RT_ERR_VLAN_EMPTY_ENTRY, /* 0x00010002, empty entry of vlan table */ RT_ERR_VLAN_ACCEPT_FRAME_TYPE, /* 0x00010003, invalid accept frame type */ RT_ERR_VLAN_EXIST, /* 0x00010004, vlan is exist */ RT_ERR_VLAN_ENTRY_NOT_FOUND, /* 0x00010005, specified vlan entry not found */ @@ -165,7 +165,7 @@ typedef enum rt_error_code_e RT_ERR_INBW_TOKEN_AMOUNT, /* 0x000c0001, invalid amount of token for input bandwidth control */ RT_ERR_INBW_FCON_VALUE, /* 0x000c0002, invalid flow control ON threshold value for input bandwidth control */ RT_ERR_INBW_FCOFF_VALUE, /* 0x000c0003, invalid flow control OFF threshold value for input bandwidth control */ - RT_ERR_INBW_FC_ALLOWANCE, /* 0x000c0004, invalid allowance of incomming packet for input bandwidth control */ + RT_ERR_INBW_FC_ALLOWANCE, /* 0x000c0004, invalid allowance of incoming packet for input bandwidth control */ RT_ERR_INBW_RATE, /* 0x000c0005, invalid input bandwidth */ /* 0x000dxxxx for QoS */ @@ -220,7 +220,7 @@ typedef enum rt_error_code_e RT_ERR_DOT1X_PROC, /* 0x00110006, unauthorized behavior error */ RT_ERR_DOT1X_GVLANIDX, /* 0x00110007, guest vlan index error */ RT_ERR_DOT1X_GVLANTALK, /* 0x00110008, guest vlan OPDIR error */ - RT_ERR_DOT1X_MAC_PORT_MISMATCH, /* 0x00110009, Auth MAC and port mismatch eror */ + RT_ERR_DOT1X_MAC_PORT_MISMATCH, /* 0x00110009, Auth MAC and port mismatch error */ RT_ERR_END /* The symbol is the latest symbol */ } rt_error_code_t; diff --git a/lede/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/include/rtk_switch.h b/lede/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/include/rtk_switch.h index b0ca13682c..0a43c0dbd3 100644 --- a/lede/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/include/rtk_switch.h +++ b/lede/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/include/rtk_switch.h @@ -185,10 +185,10 @@ typedef enum rtk_switch_maxPktLen_linkSpeed_e { #define RTK_SCAN_ALL_LOG_PORT(__port__) for(__port__ = 0; __port__ < RTK_SWITCH_PORT_NUM; __port__++) if( rtk_switch_logicalPortCheck(__port__) == RT_ERR_OK) #define RTK_SCAN_ALL_LOG_PORTMASK(__portmask__) for((__portmask__).bits[0] = 0; (__portmask__).bits[0] < 0x7FFFF; (__portmask__).bits[0]++) if( rtk_switch_isPortMaskValid(&__portmask__) == RT_ERR_OK) -/* Port mask defination */ +/* Port mask definition */ #define RTK_PHY_PORTMASK_ALL (rtk_switch_phyPortMask_get()) -/* Port defination*/ +/* Port definition*/ #define RTK_MAX_LOGICAL_PORT_ID (rtk_switch_maxLogicalPort_get()) /* Function Name: @@ -477,7 +477,7 @@ extern rtk_api_ret_t rtk_switch_isPortMaskExt(rtk_portmask_t *pPmask); /* Function Name: * rtk_switch_portmask_L2P_get * Description: - * Get physicl portmask from logical portmask + * Get physical portmask from logical portmask * Input: * pLogicalPmask - logical port mask * Output: @@ -546,7 +546,7 @@ rtk_api_ret_t rtk_switch_logPortMask_get(rtk_portmask_t *pPortmask); /* Function Name: * rtk_switch_init * Description: - * Set chip to default configuration enviroment + * Set chip to default configuration environment * Input: * None * Output: diff --git a/lede/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/include/rtk_types.h b/lede/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/include/rtk_types.h index 589ecb7811..cafc7ff9da 100644 --- a/lede/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/include/rtk_types.h +++ b/lede/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/include/rtk_types.h @@ -56,13 +56,13 @@ typedef enum rtk_enable_e #define ETHER_ADDR_LEN 6 #endif -/* ethernet address type */ +/* Ethernet address type */ typedef struct rtk_mac_s { rtk_uint8 octet[ETHER_ADDR_LEN]; } rtk_mac_t; -typedef rtk_uint32 rtk_pri_t; /* priority vlaue */ +typedef rtk_uint32 rtk_pri_t; /* priority value */ typedef rtk_uint32 rtk_qid_t; /* queue id type */ typedef rtk_uint32 rtk_data_t; typedef rtk_uint32 rtk_dscp_t; /* dscp vlaue */ diff --git a/lede/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/include/rtl8367c_asicdrv_cputag.h b/lede/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/include/rtl8367c_asicdrv_cputag.h index f7a460145e..982e2c4bfc 100644 --- a/lede/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/include/rtl8367c_asicdrv_cputag.h +++ b/lede/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/include/rtl8367c_asicdrv_cputag.h @@ -38,7 +38,7 @@ extern ret_t rtl8367c_setAsicCputagInsertMode(rtk_uint32 mode); extern ret_t rtl8367c_getAsicCputagInsertMode(rtk_uint32 *pMode); extern ret_t rtl8367c_setAsicCputagPriorityRemapping(rtk_uint32 srcPri, rtk_uint32 newPri); extern ret_t rtl8367c_getAsicCputagPriorityRemapping(rtk_uint32 srcPri, rtk_uint32 *pNewPri); -extern ret_t rtl8367c_setAsicCputagPosition(rtk_uint32 postion); +extern ret_t rtl8367c_setAsicCputagPosition(rtk_uint32 position); extern ret_t rtl8367c_getAsicCputagPosition(rtk_uint32* pPostion); extern ret_t rtl8367c_setAsicCputagMode(rtk_uint32 mode); extern ret_t rtl8367c_getAsicCputagMode(rtk_uint32 *pMode); diff --git a/lede/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/include/rtl8367c_asicdrv_green.h b/lede/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/include/rtl8367c_asicdrv_green.h index 38fd085d06..95c1b20bd4 100644 --- a/lede/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/include/rtl8367c_asicdrv_green.h +++ b/lede/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/include/rtl8367c_asicdrv_green.h @@ -11,7 +11,7 @@ * $Date: 2017-03-08 15:13:58 +0800 (gT, 08 T 2017) $ * * Purpose : RTL8367C switch high-level API for RTL8367C - * Feature : Green ethernet related functions + * Feature : Green Ethernet related functions * */ diff --git a/lede/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/include/rtl8367c_asicdrv_qos.h b/lede/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/include/rtl8367c_asicdrv_qos.h index 26042bfa13..d0a8995879 100644 --- a/lede/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/include/rtl8367c_asicdrv_qos.h +++ b/lede/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/include/rtl8367c_asicdrv_qos.h @@ -11,7 +11,7 @@ * $Date: 2017-03-08 15:13:58 +0800 (gT, 08 T 2017) $ * * Purpose : RTL8367C switch high-level API for RTL8367C - * Feature : Qos related functions + * Feature : QoS related functions * */ diff --git a/lede/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/include/rtl8367c_asicdrv_unknownMulticast.h b/lede/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/include/rtl8367c_asicdrv_unknownMulticast.h index d142d25cff..e492e715b3 100644 --- a/lede/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/include/rtl8367c_asicdrv_unknownMulticast.h +++ b/lede/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/include/rtl8367c_asicdrv_unknownMulticast.h @@ -11,7 +11,7 @@ * $Date: 2017-03-08 15:13:58 +0800 (gT, 08 T 2017) $ * * Purpose : RTL8367C switch high-level API for RTL8367C - * Feature : Unkown multicast related functions + * Feature : Unknown multicast related functions * */ diff --git a/lede/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/include/rtl8367c_base.h b/lede/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/include/rtl8367c_base.h index 676ca8ed74..7a70e158fa 100644 --- a/lede/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/include/rtl8367c_base.h +++ b/lede/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/include/rtl8367c_base.h @@ -11,7 +11,7 @@ * $Date: 2017-03-08 15:13:58 +0800 (gT, 08 T 2017) $ * * Purpose : RTL8367C switch high-level API for RTL8367C - * Feature : Regsiter MACRO related definition + * Feature : Register MACRO related definition * */ diff --git a/lede/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/include/rtl8367c_reg.h b/lede/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/include/rtl8367c_reg.h index eb4f48b83e..f973c7bcb6 100644 --- a/lede/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/include/rtl8367c_reg.h +++ b/lede/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/include/rtl8367c_reg.h @@ -20357,8 +20357,8 @@ auto-generated register address and field data #define RTL8367C_IGMP_MLD_DISCARD_STORM_FILTER_MASK 0x2000 #define RTL8367C_REPORT_FORWARD_OFFSET 12 #define RTL8367C_REPORT_FORWARD_MASK 0x1000 -#define RTL8367C_ROBURSTNESS_VAR_OFFSET 9 -#define RTL8367C_ROBURSTNESS_VAR_MASK 0xE00 +#define RTL8367C_ROBUSTNESS_VAR_OFFSET 9 +#define RTL8367C_ROBUSTNESS_VAR_MASK 0xE00 #define RTL8367C_LEAVE_SUPPRESSION_OFFSET 8 #define RTL8367C_LEAVE_SUPPRESSION_MASK 0x100 #define RTL8367C_REPORT_SUPPRESSION_OFFSET 7 diff --git a/lede/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/l2.c b/lede/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/l2.c index feff0b240b..e73199a4e9 100644 --- a/lede/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/l2.c +++ b/lede/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/l2.c @@ -86,7 +86,7 @@ rtk_api_ret_t rtk_l2_init(void) * RT_ERR_L2_INDEXTBL_FULL - hashed index is full of entries. * RT_ERR_INPUT - Invalid input parameters. * Note: - * If the unicast mac address already existed in LUT, it will udpate the status of the entry. + * If the unicast mac address already existed in LUT, it will update the status of the entry. * Otherwise, it will find an empty or asic auto learned entry to write. If all the entries * with the same hash value can't be replaced, ASIC will return a RT_ERR_L2_INDEXTBL_FULL error. */ @@ -453,7 +453,7 @@ rtk_api_ret_t rtk_l2_addr_del(rtk_mac_t *pMac, rtk_l2_ucastAddr_t *pL2_data) * RT_ERR_PORT_MASK - Invalid portmask. * RT_ERR_INPUT - Invalid input parameters. * Note: - * If the multicast mac address already existed in the LUT, it will udpate the + * If the multicast mac address already existed in the LUT, it will update the * port mask of the entry. Otherwise, it will find an empty or asic auto learned * entry to write. If all the entries with the same hash value can't be replaced, * ASIC will return a RT_ERR_L2_INDEXTBL_FULL error. @@ -800,7 +800,7 @@ rtk_api_ret_t rtk_l2_mcastAddr_del(rtk_l2_mcastAddr_t *pMcastAddr) /* Function Name: * rtk_l2_ipMcastAddr_add * Description: - * Add Lut IP multicast entry + * Add LUT IP multicast entry * Input: * pIpMcastAddr - IP Multicast entry * Output: @@ -914,7 +914,7 @@ rtk_api_ret_t rtk_l2_ipMcastAddr_add(rtk_l2_ipMcastAddr_t *pIpMcastAddr) * RT_ERR_L2_ENTRY_NOTFOUND - No such LUT entry. * RT_ERR_INPUT - Invalid input parameters. * Note: - * The API can get Lut table of IP multicast entry. + * The API can get LUT table of IP multicast entry. */ rtk_api_ret_t rtk_l2_ipMcastAddr_get(rtk_l2_ipMcastAddr_t *pIpMcastAddr) { @@ -1080,7 +1080,7 @@ rtk_api_ret_t rtk_l2_ipMcastAddr_del(rtk_l2_ipMcastAddr_t *pIpMcastAddr) /* Function Name: * rtk_l2_ipVidMcastAddr_add * Description: - * Add Lut IP multicast+VID entry + * Add LUT IP multicast+VID entry * Input: * pIpVidMcastAddr - IP & VID multicast Entry * Output: @@ -2143,7 +2143,7 @@ rtk_api_ret_t rtk_l2_learningCnt_get(rtk_port_t port, rtk_mac_cnt_t *pMac_cnt) * Set flooding portmask * Input: * type - flooding type. - * pFlood_portmask - flooding porkmask + * pFlood_portmask - flooding portmask * Output: * None * Return: @@ -2204,7 +2204,7 @@ rtk_api_ret_t rtk_l2_floodPortMask_set(rtk_l2_flood_type_t floood_type, rtk_port * Input: * type - flooding type. * Output: - * pFlood_portmask - flooding porkmask + * pFlood_portmask - flooding portmask * Return: * RT_ERR_OK - OK * RT_ERR_FAILED - Failed @@ -2259,10 +2259,10 @@ rtk_api_ret_t rtk_l2_floodPortMask_get(rtk_l2_flood_type_t floood_type, rtk_port /* Function Name: * rtk_l2_localPktPermit_set * Description: - * Set permittion of frames if source port and destination port are the same. + * Set permission of frames if source port and destination port are the same. * Input: * port - Port id. - * permit - permittion status + * permit - permission status * Output: * None * Return: @@ -2272,7 +2272,7 @@ rtk_api_ret_t rtk_l2_floodPortMask_get(rtk_l2_flood_type_t floood_type, rtk_port * RT_ERR_PORT_ID - Invalid port number. * RT_ERR_ENABLE - Invalid permit value. * Note: - * This API is setted to permit frame if its source port is equal to destination port. + * This API is set to permit frame if its source port is equal to destination port. */ rtk_api_ret_t rtk_l2_localPktPermit_set(rtk_port_t port, rtk_enable_t permit) { @@ -2296,18 +2296,18 @@ rtk_api_ret_t rtk_l2_localPktPermit_set(rtk_port_t port, rtk_enable_t permit) /* Function Name: * rtk_l2_localPktPermit_get * Description: - * Get permittion of frames if source port and destination port are the same. + * Get permission of frames if source port and destination port are the same. * Input: * port - Port id. * Output: - * pPermit - permittion status + * pPermit - permission status * Return: * RT_ERR_OK - OK * RT_ERR_FAILED - Failed * RT_ERR_SMI - SMI access error * RT_ERR_PORT_ID - Invalid port number. * Note: - * This API is to get permittion status for frames if its source port is equal to destination port. + * This API is to get permission status for frames if its source port is equal to destination port. */ rtk_api_ret_t rtk_l2_localPktPermit_get(rtk_port_t port, rtk_enable_t *pPermit) { @@ -2331,9 +2331,9 @@ rtk_api_ret_t rtk_l2_localPktPermit_get(rtk_port_t port, rtk_enable_t *pPermit) /* Function Name: * rtk_l2_aging_set * Description: - * Set LUT agging out speed + * Set LUT ageing out speed * Input: - * aging_time - Agging out time. + * aging_time - Ageing out time. * Output: * None * Return: @@ -2342,7 +2342,7 @@ rtk_api_ret_t rtk_l2_localPktPermit_get(rtk_port_t port, rtk_enable_t *pPermit) * RT_ERR_SMI - SMI access error * RT_ERR_OUT_OF_RANGE - input out of range. * Note: - * The API can set LUT agging out period for each entry and the range is from 45s to 458s. + * The API can set LUT ageing out period for each entry and the range is from 45s to 458s. */ rtk_api_ret_t rtk_l2_aging_set(rtk_l2_age_time_t aging_time) { @@ -2371,7 +2371,7 @@ rtk_api_ret_t rtk_l2_aging_set(rtk_l2_age_time_t aging_time) /* Function Name: * rtk_l2_aging_get * Description: - * Get LUT agging out time + * Get LUT ageing out time * Input: * None * Output: @@ -2382,7 +2382,7 @@ rtk_api_ret_t rtk_l2_aging_set(rtk_l2_age_time_t aging_time) * RT_ERR_SMI - SMI access error * RT_ERR_PORT_ID - Invalid port number. * Note: - * The API can get LUT agging out period for each entry. + * The API can get LUT ageing out period for each entry. */ rtk_api_ret_t rtk_l2_aging_get(rtk_l2_age_time_t *pAging_time) { @@ -2416,7 +2416,7 @@ rtk_api_ret_t rtk_l2_aging_get(rtk_l2_age_time_t *pAging_time) /* Function Name: * rtk_l2_ipMcastAddrLookup_set * Description: - * Set Lut IP multicast lookup function + * Set LUT IP multicast lookup function * Input: * type - Lookup type for IPMC packet. * Output: @@ -2473,7 +2473,7 @@ rtk_api_ret_t rtk_l2_ipMcastAddrLookup_set(rtk_l2_ipmc_lookup_type_t type) /* Function Name: * rtk_l2_ipMcastAddrLookup_get * Description: - * Get Lut IP multicast lookup function + * Get LUT IP multicast lookup function * Input: * None. * Output: @@ -2518,9 +2518,9 @@ rtk_api_ret_t rtk_l2_ipMcastAddrLookup_get(rtk_l2_ipmc_lookup_type_t *pType) /* Function Name: * rtk_l2_ipMcastForwardRouterPort_set * Description: - * Set IPMC packet forward to rounter port also or not + * Set IPMC packet forward to router port also or not * Input: - * enabled - 1: Inlcude router port, 0, exclude router port + * enabled - 1: Include router port, 0, exclude router port * Output: * None. * Return: @@ -2549,11 +2549,11 @@ rtk_api_ret_t rtk_l2_ipMcastForwardRouterPort_set(rtk_enable_t enabled) /* Function Name: * rtk_l2_ipMcastForwardRouterPort_get * Description: - * Get IPMC packet forward to rounter port also or not + * Get IPMC packet forward to router port also or not * Input: * None. * Output: - * pEnabled - 1: Inlcude router port, 0, exclude router port + * pEnabled - 1: Include router port, 0, exclude router port * Return: * RT_ERR_OK - OK * RT_ERR_FAILED - Failed diff --git a/lede/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/led.c b/lede/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/led.c index c00c331d8a..02e0829dc6 100644 --- a/lede/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/led.c +++ b/lede/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/led.c @@ -27,7 +27,7 @@ /* Function Name: * rtk_led_enable_set * Description: - * Set Led enable congiuration + * Set Led enable configuration * Input: * group - LED group id. * pPortmask - LED enable port mask. @@ -74,7 +74,7 @@ rtk_api_ret_t rtk_led_enable_set(rtk_led_group_t group, rtk_portmask_t *pPortmas /* Function Name: * rtk_led_enable_get * Description: - * Get Led enable congiuration + * Get Led enable configuration * Input: * group - LED group id. * Output: @@ -205,7 +205,7 @@ rtk_api_ret_t rtk_led_operation_get(rtk_led_operation_t *pMode) /* Function Name: * rtk_led_modeForce_set * Description: - * Set Led group to congiuration force mode + * Set Led group to configuration force mode * Input: * port - port ID * group - Support LED group id. @@ -255,7 +255,7 @@ rtk_api_ret_t rtk_led_modeForce_set(rtk_port_t port, rtk_led_group_t group, rtk_ /* Function Name: * rtk_led_modeForce_get * Description: - * Get Led group to congiuration force mode + * Get Led group to configuration force mode * Input: * port - port ID * group - Support LED group id. @@ -369,7 +369,7 @@ rtk_api_ret_t rtk_led_blinkRate_get(rtk_led_blink_rate_t *pBlinkRate) /* Function Name: * rtk_led_groupConfig_set * Description: - * Set per group Led to congiuration mode + * Set per group Led to configuration mode * Input: * group - LED group. * config - LED configuration @@ -422,7 +422,7 @@ rtk_api_ret_t rtk_led_groupConfig_set(rtk_led_group_t group, rtk_led_congig_t co /* Function Name: * rtk_led_groupConfig_get * Description: - * Get Led group congiuration mode + * Get Led group configuration mode * Input: * group - LED group. * Output: @@ -583,7 +583,7 @@ rtk_api_ret_t rtk_led_groupAbility_get(rtk_led_group_t group, rtk_led_ability_t /* Function Name: * rtk_led_serialMode_set * Description: - * Set Led serial mode active congiuration + * Set Led serial mode active configuration * Input: * active - LED group. * Output: @@ -594,7 +594,7 @@ rtk_api_ret_t rtk_led_groupAbility_get(rtk_led_group_t group, rtk_led_ability_t * RT_ERR_SMI - SMI access error * RT_ERR_INPUT - Invalid input parameters. * Note: - * The API can set LED serial mode active congiuration. + * The API can set LED serial mode active configuration. */ rtk_api_ret_t rtk_led_serialMode_set(rtk_led_active_t active) { diff --git a/lede/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/mirror.c b/lede/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/mirror.c index 1921d1a5af..3bbad8adb6 100644 --- a/lede/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/mirror.c +++ b/lede/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/mirror.c @@ -66,7 +66,7 @@ rtk_api_ret_t rtk_mirror_portBased_set(rtk_port_t mirroring_port, rtk_portmask_t RTK_CHK_PORTMASK_VALID(pMirrored_tx_portmask); - /*Mirror Sorce Port Mask Check*/ + /*Mirror Source Port Mask Check*/ if (pMirrored_tx_portmask->bits[0]!=pMirrored_rx_portmask->bits[0]&&pMirrored_tx_portmask->bits[0]!=0&&pMirrored_rx_portmask->bits[0]!=0) return RT_ERR_PORT_MASK; @@ -353,7 +353,7 @@ rtk_api_ret_t rtk_mirror_vlanLeaky_get(rtk_enable_t *pTxenable, rtk_enable_t *pR * RT_ERR_SMI - SMI access error * RT_ERR_ENABLE - Invalid enable input * Note: - * The API is to set mirror VLAN leaky function forwarding packets to miror port. + * The API is to set mirror VLAN leaky function forwarding packets to mirror port. */ rtk_api_ret_t rtk_mirror_isolationLeaky_set(rtk_enable_t txenable, rtk_enable_t rxenable) { diff --git a/lede/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/port.c b/lede/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/port.c index 9f99d1b3dc..9c7bcd0e38 100644 --- a/lede/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/port.c +++ b/lede/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/port.c @@ -410,7 +410,7 @@ static rtk_api_ret_t _rtk_port_FiberModeAbility_get(rtk_port_t port, rtk_port_ph /* Function Name: * rtk_port_phyAutoNegoAbility_set * Description: - * Set ethernet PHY auto-negotiation desired ability. + * Set Ethernet PHY auto-negotiation desired ability. * Input: * port - port id. * pAbility - Ability structure @@ -618,7 +618,7 @@ rtk_api_ret_t rtk_port_phyAutoNegoAbility_set(rtk_port_t port, rtk_port_phy_abil * RT_ERR_INPUT - Invalid input parameters. * RT_ERR_BUSYWAIT_TIMEOUT - PHY access busy * Note: - * Get the capablity of specified PHY. + * Get the capability of specified PHY. */ rtk_api_ret_t rtk_port_phyAutoNegoAbility_get(rtk_port_t port, rtk_port_phy_ability_t *pAbility) { @@ -836,7 +836,7 @@ rtk_api_ret_t rtk_port_phyForceModeAbility_set(rtk_port_t port, rtk_port_phy_abi if (1 == pAbility->AsyFC) { - /*Asymetric flow control in reg 4.11*/ + /*Asymmetric flow control in reg 4.11*/ phyEnMsk4 = phyEnMsk4 | (1 << 11); } if (1 == pAbility->FC) @@ -892,7 +892,7 @@ rtk_api_ret_t rtk_port_phyForceModeAbility_set(rtk_port_t port, rtk_port_phy_abi * RT_ERR_INPUT - Invalid input parameters. * RT_ERR_BUSYWAIT_TIMEOUT - PHY access busy * Note: - * Get the capablity of specified PHY. + * Get the capability of specified PHY. */ rtk_api_ret_t rtk_port_phyForceModeAbility_get(rtk_port_t port, rtk_port_phy_ability_t *pAbility) { @@ -982,7 +982,7 @@ rtk_api_ret_t rtk_port_phyForceModeAbility_get(rtk_port_t port, rtk_port_phy_abi /* Function Name: * rtk_port_phyStatus_get * Description: - * Get ethernet PHY linking status + * Get Ethernet PHY linking status * Input: * port - Port id. * Output: @@ -1363,7 +1363,7 @@ rtk_api_ret_t rtk_port_macStatus_get(rtk_port_t port, rtk_port_mac_ability_t *pP * For UTP port, This API will also enable the digital * loopback bit in PHY register for sync of speed between * PHY and MAC. For EXT port, users need to force the - * link state by themself. + * link state by themselves. */ rtk_api_ret_t rtk_port_macLocalLoopbackEnable_set(rtk_port_t port, rtk_enable_t enable) { @@ -1508,7 +1508,7 @@ rtk_api_ret_t rtk_port_phyReg_get(rtk_port_t port, rtk_port_phy_reg_t reg, rtk_p /* Function Name: * rtk_port_backpressureEnable_set * Description: - * Set the half duplex backpressure enable status of the specific port. + * Set the half duplex back-pressure enable status of the specific port. * Input: * port - port id. * enable - Back pressure status. @@ -1521,10 +1521,10 @@ rtk_api_ret_t rtk_port_phyReg_get(rtk_port_t port, rtk_port_phy_reg_t reg, rtk_p * RT_ERR_PORT_ID - Invalid port number. * RT_ERR_ENABLE - Invalid enable input. * Note: - * This API can set the half duplex backpressure enable status of the specific port. - * The half duplex backpressure enable status of the port is as following: + * This API can set the half duplex back-pressure enable status of the specific port. + * The half duplex back-pressure enable status of the port is as following: * - DISABLE(Defer) - * - ENABLE (Backpressure) + * - ENABLE (Back-pressure) */ rtk_api_ret_t rtk_port_backpressureEnable_set(rtk_port_t port, rtk_enable_t enable) { @@ -1548,7 +1548,7 @@ rtk_api_ret_t rtk_port_backpressureEnable_set(rtk_port_t port, rtk_enable_t enab /* Function Name: * rtk_port_backpressureEnable_get * Description: - * Get the half duplex backpressure enable status of the specific port. + * Get the half duplex back-pressure enable status of the specific port. * Input: * port - Port id. * Output: @@ -1559,10 +1559,10 @@ rtk_api_ret_t rtk_port_backpressureEnable_set(rtk_port_t port, rtk_enable_t enab * RT_ERR_SMI - SMI access error * RT_ERR_PORT_ID - Invalid port number. * Note: - * This API can get the half duplex backpressure enable status of the specific port. - * The half duplex backpressure enable status of the port is as following: + * This API can get the half duplex back-pressure enable status of the specific port. + * The half duplex back-pressure enable status of the port is as following: * - DISABLE(Defer) - * - ENABLE (Backpressure) + * - ENABLE (Back-pressure) */ rtk_api_ret_t rtk_port_backpressureEnable_get(rtk_port_t port, rtk_enable_t *pEnable) { @@ -1643,7 +1643,7 @@ rtk_api_ret_t rtk_port_adminEnable_set(rtk_port_t port, rtk_enable_t enable) /* Function Name: * rtk_port_adminEnable_get * Description: - * Get port admin configurationof the specific port. + * Get port admin configuration of the specific port. * Input: * port - Port id. * Output: @@ -1704,7 +1704,7 @@ rtk_api_ret_t rtk_port_adminEnable_get(rtk_port_t port, rtk_enable_t *pEnable) * RT_ERR_PORT_ID - Invalid port number. * RT_ERR_PORT_MASK - Invalid portmask. * Note: - * This API set the port mask that a port can trasmit packet to of each port + * This API set the port mask that a port can transmit packet to of each port * A port can only transmit packet to ports included in permitted portmask */ rtk_api_ret_t rtk_port_isolation_set(rtk_port_t port, rtk_portmask_t *pPortmask) @@ -1747,7 +1747,7 @@ rtk_api_ret_t rtk_port_isolation_set(rtk_port_t port, rtk_portmask_t *pPortmask) * RT_ERR_SMI - SMI access error * RT_ERR_PORT_ID - Invalid port number. * Note: - * This API get the port mask that a port can trasmit packet to of each port + * This API get the port mask that a port can transmit packet to of each port * A port can only transmit packet to ports included in permitted portmask */ rtk_api_ret_t rtk_port_isolation_get(rtk_port_t port, rtk_portmask_t *pPortmask) @@ -1790,7 +1790,7 @@ rtk_api_ret_t rtk_port_isolation_get(rtk_port_t port, rtk_portmask_t *pPortmask) * Note: * This API can set external interface 2 RGMII delay. * In TX delay, there are 2 selection: no-delay and 2ns delay. - * In RX dekay, there are 8 steps for delay tunning. 0 for no-delay, and 7 for maximum delay. + * In RX delay, there are 8 steps for delay tuning. 0 for no-delay, and 7 for maximum delay. */ rtk_api_ret_t rtk_port_rgmiiDelayExt_set(rtk_port_t port, rtk_data_t txDelay, rtk_data_t rxDelay) { @@ -1841,7 +1841,7 @@ rtk_api_ret_t rtk_port_rgmiiDelayExt_set(rtk_port_t port, rtk_data_t txDelay, rt * Note: * This API can set external interface 2 RGMII delay. * In TX delay, there are 2 selection: no-delay and 2ns delay. - * In RX dekay, there are 8 steps for delay tunning. 0 for n0-delay, and 7 for maximum delay. + * In RX delay, there are 8 steps for delay tuning. 0 for n0-delay, and 7 for maximum delay. */ rtk_api_ret_t rtk_port_rgmiiDelayExt_get(rtk_port_t port, rtk_data_t *pTxDelay, rtk_data_t *pRxDelay) { diff --git a/lede/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/ptp.c b/lede/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/ptp.c index 40962a0e69..af8ce30912 100644 --- a/lede/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/ptp.c +++ b/lede/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/ptp.c @@ -401,7 +401,7 @@ rtk_api_ret_t rtk_ptp_portEnable_get(rtk_port_t port, rtk_enable_t *pEnable) /* Function Name: * rtk_ptp_portTimestamp_get * Description: - * Get PTP timstamp according to the PTP identifier on the dedicated port from the specified device. + * Get PTP timestamp according to the PTP identifier on the dedicated port from the specified device. * Input: * unit - unit id * port - port id diff --git a/lede/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/qos.c b/lede/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/qos.c index 70067a3016..9bcb49cfbd 100644 --- a/lede/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/qos.c +++ b/lede/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/qos.c @@ -28,7 +28,7 @@ /* Function Name: * rtk_qos_init * Description: - * Configure Qos default settings with queue number assigment to each port. + * Configure QoS default settings with queue number assignment to each port. * Input: * queueNum - Queue number of each port. * Output: @@ -40,7 +40,7 @@ * RT_ERR_QUEUE_NUM - Invalid queue number. * RT_ERR_INPUT - Invalid input parameters. * Note: - * This API will initialize related Qos setting with queue number assigment. + * This API will initialize related QoS setting with queue number assignment. * The queue number is from 1 to 8. */ rtk_api_ret_t rtk_qos_init(rtk_queue_num_t queueNum) @@ -143,7 +143,7 @@ rtk_api_ret_t rtk_qos_init(rtk_queue_num_t queueNum) return retVal; } - /* Finetune B/T value */ + /* Fine-tune B/T value */ if((retVal = rtl8367c_setAsicReg(0x1722, 0x1158)) != RT_ERR_OK) return retVal; @@ -455,7 +455,7 @@ rtk_api_ret_t rtk_qos_1pPriRemap_set(rtk_pri_t dot1p_pri, rtk_pri_t int_pri) * RT_ERR_VLAN_PRIORITY - Invalid priority. * RT_ERR_QOS_INT_PRIORITY - Invalid priority. * Note: - * Priority of 802.1Q assigment for internal asic priority, and it is uesed for queue usage and packet scheduling. + * Priority of 802.1Q assignment for internal asic priority, and it is used for queue usage and packet scheduling. */ rtk_api_ret_t rtk_qos_1pPriRemap_get(rtk_pri_t dot1p_pri, rtk_pri_t *pInt_pri) { diff --git a/lede/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/rldp.c b/lede/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/rldp.c index d3ca029751..0ecc32a6b5 100644 --- a/lede/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/rldp.c +++ b/lede/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/rldp.c @@ -8,7 +8,7 @@ * available at https://www.gnu.org/licenses/old-licenses/gpl-2.0.txt * * $Revision: 76306 $ - * $Date: 2017-03-08 15:13:58 +0800 (gT, 08 T 2017) $ + * $Date: 2017-03-08 15:13:58 +0800 (週三, 08 三月 2017) $ * * Purpose : Declaration of RLDP and RLPP API * @@ -404,7 +404,7 @@ rtk_api_ret_t rtk_rldp_portStatus_get(rtk_port_t port, rtk_rldp_portStatus_t *pP * RT_ERR_NULL_POINTER * Note: * Clear operation effect loop_enter and loop_leave only, other field in - * the structure are don't care. Loop status cab't be clean. + * the structure are don't care. Loop status can't be clean. */ rtk_api_ret_t rtk_rldp_portStatus_set(rtk_port_t port, rtk_rldp_portStatus_t *pPortStatus) { diff --git a/lede/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/rtk_switch.c b/lede/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/rtk_switch.c index 0bb0db0776..20542f259f 100644 --- a/lede/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/rtk_switch.c +++ b/lede/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/rtk_switch.c @@ -152,7 +152,7 @@ static rtk_switch_halCtrl_t rtl8370b_hal_Ctrl = /* Minimum physical port number */ 0, - /* Maxmum physical port number */ + /* Maximum physical port number */ 10, /* Physical port mask */ @@ -221,7 +221,7 @@ static rtk_switch_halCtrl_t rtl8364b_hal_Ctrl = /* Minimum physical port number */ 0, - /* Maxmum physical port number */ + /* Maximum physical port number */ 7, /* Physical port mask */ @@ -290,7 +290,7 @@ static rtk_switch_halCtrl_t rtl8363sc_vb_hal_Ctrl = /* Minimum physical port number */ 0, - /* Maxmum physical port number */ + /* Maximum physical port number */ 7, /* Physical port mask */ @@ -1215,7 +1215,7 @@ rtk_api_ret_t rtk_switch_isPortMaskExt(rtk_portmask_t *pPmask) /* Function Name: * rtk_switch_portmask_L2P_get * Description: - * Get physicl portmask from logical portmask + * Get physical portmask from logical portmask * Input: * pLogicalPmask - logical port mask * Output: @@ -1351,7 +1351,7 @@ rtk_api_ret_t rtk_switch_logPortMask_get(rtk_portmask_t *pPortmask) /* Function Name: * rtk_switch_init * Description: - * Set chip to default configuration enviroment + * Set chip to default configuration environment * Input: * None * Output: diff --git a/lede/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/rtl8367c_asicdrv_acl.c b/lede/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/rtl8367c_asicdrv_acl.c index d9ccd97118..1e4d2961e7 100644 --- a/lede/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/rtl8367c_asicdrv_acl.c +++ b/lede/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/rtl8367c_asicdrv_acl.c @@ -173,7 +173,7 @@ static void _rtl8367c_aclActStUser2Smi(rtl8367c_acl_act_t *pAclUser, rtk_uint16 /* Function Name: * rtl8367c_setAsicAcl * Description: - * Set port acl function enable/disable + * Set port ACL function enable/disable * Input: * port - Physical port number (0~10) * enabled - 1: enabled, 0: disabled @@ -196,7 +196,7 @@ ret_t rtl8367c_setAsicAcl(rtk_uint32 port, rtk_uint32 enabled) /* Function Name: * rtl8367c_getAsicAcl * Description: - * Get port acl function enable/disable + * Get port ACL function enable/disable * Input: * port - Physical port number (0~10) * enabled - 1: enabled, 0: disabled @@ -219,7 +219,7 @@ ret_t rtl8367c_getAsicAcl(rtk_uint32 port, rtk_uint32* pEnabled) /* Function Name: * rtl8367c_setAsicAclUnmatchedPermit * Description: - * Set port acl function unmatched permit action + * Set port ACL function unmatched permit action * Input: * port - Physical port number (0~10) * enabled - 1: enabled, 0: disabled @@ -242,7 +242,7 @@ ret_t rtl8367c_setAsicAclUnmatchedPermit(rtk_uint32 port, rtk_uint32 enabled) /* Function Name: * rtl8367c_getAsicAclUnmatchedPermit * Description: - * Get port acl function unmatched permit action + * Get port ACL function unmatched permit action * Input: * port - Physical port number (0~10) * enabled - 1: enabled, 0: disabled @@ -266,10 +266,10 @@ ret_t rtl8367c_getAsicAclUnmatchedPermit(rtk_uint32 port, rtk_uint32* pEnabled) /* Function Name: * rtl8367c_setAsicAclRule * Description: - * Set acl rule content + * Set ACL rule content * Input: * index - ACL rule index (0-95) of 96 ACL rules - * pAclRule - ACL rule stucture for setting + * pAclRule - ACL rule structure for setting * Output: * None * Return: @@ -278,8 +278,8 @@ ret_t rtl8367c_getAsicAclUnmatchedPermit(rtk_uint32 port, rtk_uint32* pEnabled) * RT_ERR_OUT_OF_RANGE - Invalid ACL rule index (0-95) * Note: * System supported 95 shared 289-bit ACL ingress rule. Index was available at range 0-95 only. - * If software want to modify ACL rule, the ACL function should be disable at first or unspecify - * acl action will be executed. + * If software want to modify ACL rule, the ACL function should be disabled at first or unspecified + * ACL action will be executed. * One ACL rule structure has three parts setting: * Bit 0-147 Data Bits of this Rule * Bit 148 Valid Bit @@ -410,10 +410,10 @@ ret_t rtl8367c_setAsicAclRule(rtk_uint32 index, rtl8367c_aclrule* pAclRule) /* Function Name: * rtl8367c_getAsicAclRule * Description: - * Get acl rule content + * Get ACL rule content * Input: * index - ACL rule index (0-63) of 64 ACL rules - * pAclRule - ACL rule stucture for setting + * pAclRule - ACL rule structure for setting * Output: * None * Return: @@ -588,7 +588,7 @@ ret_t rtl8367c_getAsicAclNot(rtk_uint32 index, rtk_uint32* pNot) * Set fields of a ACL Template * Input: * index - ACL template index(0~4) - * pAclType - ACL type stucture for setting + * pAclType - ACL type structure for setting * Output: * None * Return: @@ -598,7 +598,7 @@ ret_t rtl8367c_getAsicAclNot(rtk_uint32 index, rtk_uint32* pNot) * Note: * The API can set type field of the 5 ACL rule templates. * Each type has 8 fields. One field means what data in one field of a ACL rule means - * 8 fields of ACL rule 0~95 is descripted by one type in ACL group + * 8 fields of ACL rule 0~95 is described by one type in ACL group */ ret_t rtl8367c_setAsicAclTemplate(rtk_uint32 index, rtl8367c_acltemplate_t* pAclType) { @@ -630,7 +630,7 @@ ret_t rtl8367c_setAsicAclTemplate(rtk_uint32 index, rtl8367c_acltemplate_t* pAcl * Get fields of a ACL Template * Input: * index - ACL template index(0~4) - * pAclType - ACL type stucture for setting + * pAclType - ACL type structure for setting * Output: * None * Return: @@ -669,7 +669,7 @@ ret_t rtl8367c_getAsicAclTemplate(rtk_uint32 index, rtl8367c_acltemplate_t *pAcl * Set ACL rule matched Action * Input: * index - ACL rule index (0-95) of 96 ACL rules - * pAclAct - ACL action stucture for setting + * pAclAct - ACL action structure for setting * Output: * None * Return: @@ -734,7 +734,7 @@ ret_t rtl8367c_setAsicAclAct(rtk_uint32 index, rtl8367c_acl_act_t* pAclAct) * Get ACL rule matched Action * Input: * index - ACL rule index (0-95) of 96 ACL rules - * pAclAct - ACL action stucture for setting + * pAclAct - ACL action structure for setting * Output: * None * Return: @@ -1137,7 +1137,7 @@ ret_t rtl8367c_getAsicAclIpRange(rtk_uint32 index, rtk_uint32* pType, ipaddr_t* /* Function Name: * rtl8367c_setAsicAclGpioPolarity * Description: - * Set ACL Goip control palarity + * Set ACL Goip control polarity * Input: * polarity - 1: High, 0: Low * Output: @@ -1155,7 +1155,7 @@ ret_t rtl8367c_setAsicAclGpioPolarity(rtk_uint32 polarity) /* Function Name: * rtl8367c_getAsicAclGpioPolarity * Description: - * Get ACL Goip control palarity + * Get ACL Goip control polarity * Input: * pPolarity - 1: High, 0: Low * Output: diff --git a/lede/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/rtl8367c_asicdrv_cputag.c b/lede/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/rtl8367c_asicdrv_cputag.c index d22bf65eaa..ec9c332e16 100644 --- a/lede/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/rtl8367c_asicdrv_cputag.c +++ b/lede/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/rtl8367c_asicdrv_cputag.c @@ -18,7 +18,7 @@ /* Function Name: * rtl8367c_setAsicCputagEnable * Description: - * Set cpu tag function enable/disable + * Set CPU tag function enable/disable * Input: * enabled - 1: enabled, 0: disabled * Output: @@ -41,7 +41,7 @@ ret_t rtl8367c_setAsicCputagEnable(rtk_uint32 enabled) /* Function Name: * rtl8367c_getAsicCputagEnable * Description: - * Get cpu tag function enable/disable + * Get CPU tag function enable/disable * Input: * pEnabled - 1: enabled, 0: disabled * Output: @@ -59,7 +59,7 @@ ret_t rtl8367c_getAsicCputagEnable(rtk_uint32 *pEnabled) /* Function Name: * rtl8367c_setAsicCputagTrapPort * Description: - * Set cpu tag trap port + * Set CPU tag trap port * Input: * port - port number * Output: @@ -91,7 +91,7 @@ ret_t rtl8367c_setAsicCputagTrapPort(rtk_uint32 port) /* Function Name: * rtl8367c_getAsicCputagTrapPort * Description: - * Get cpu tag trap port + * Get CPU tag trap port * Input: * pPort - port number * Output: @@ -248,9 +248,9 @@ ret_t rtl8367c_getAsicCputagPriorityRemapping(rtk_uint32 srcPri, rtk_uint32 *pNe /* Function Name: * rtl8367c_setAsicCputagPosition * Description: - * Set cpu tag insert position + * Set CPU tag insert position * Input: - * postion - 1: After entire packet(before CRC field), 0: After MAC_SA (Default) + * position - 1: After entire packet(before CRC field), 0: After MAC_SA (Default) * Output: * None * Return: @@ -259,14 +259,14 @@ ret_t rtl8367c_getAsicCputagPriorityRemapping(rtk_uint32 srcPri, rtk_uint32 *pNe * Note: * None */ -ret_t rtl8367c_setAsicCputagPosition(rtk_uint32 postion) +ret_t rtl8367c_setAsicCputagPosition(rtk_uint32 position) { - return rtl8367c_setAsicRegBit(RTL8367C_REG_CPU_CTRL, RTL8367C_CPU_TAG_POSITION_OFFSET, postion); + return rtl8367c_setAsicRegBit(RTL8367C_REG_CPU_CTRL, RTL8367C_CPU_TAG_POSITION_OFFSET, position); } /* Function Name: * rtl8367c_getAsicCputagPosition * Description: - * Get cpu tag insert position + * Get CPU tag insert position * Input: * pPostion - 1: After entire packet(before CRC field), 0: After MAC_SA (Default) * Output: @@ -285,7 +285,7 @@ ret_t rtl8367c_getAsicCputagPosition(rtk_uint32* pPostion) /* Function Name: * rtl8367c_setAsicCputagMode * Description: - * Set cpu tag mode + * Set CPU tag mode * Input: * mode - 1: 4bytes mode, 0: 8bytes mode * Output: @@ -308,7 +308,7 @@ ret_t rtl8367c_setAsicCputagMode(rtk_uint32 mode) /* Function Name: * rtl8367c_getAsicCputagMode * Description: - * Get cpu tag mode + * Get CPU tag mode * Input: * pMode - 1: 4bytes mode, 0: 8bytes mode * Output: @@ -326,7 +326,7 @@ ret_t rtl8367c_getAsicCputagMode(rtk_uint32 *pMode) /* Function Name: * rtl8367c_setAsicCputagRxMinLength * Description: - * Set cpu tag mode + * Set CPU tag mode * Input: * mode - 1: 64bytes, 0: 72bytes * Output: @@ -349,7 +349,7 @@ ret_t rtl8367c_setAsicCputagRxMinLength(rtk_uint32 mode) /* Function Name: * rtl8367c_getAsicCputagRxMinLength * Description: - * Get cpu tag mode + * Get CPU tag mode * Input: * pMode - 1: 64bytes, 0: 72bytes * Output: diff --git a/lede/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/rtl8367c_asicdrv_eav.c b/lede/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/rtl8367c_asicdrv_eav.c index 370b7c6f3a..811ee47954 100644 --- a/lede/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/rtl8367c_asicdrv_eav.c +++ b/lede/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/rtl8367c_asicdrv_eav.c @@ -100,7 +100,7 @@ ret_t rtl8367c_getAsicEavMacAddress(ether_addr_t *pMac) * Description: * Set PTP parser tag TPID. * Input: - * outerTag - outter tag TPID + * outerTag - outer tag TPID * innerTag - inner tag TPID * Output: * None @@ -128,7 +128,7 @@ ret_t rtl8367c_setAsicEavTpid(rtk_uint32 outerTag, rtk_uint32 innerTag) * Input: * None * Output: - * pOuterTag - outter tag TPID + * pOuterTag - outer tag TPID * pInnerTag - inner tag TPID * Return: * RT_ERR_OK - Success @@ -161,7 +161,7 @@ ret_t rtl8367c_getAsicEavTpid(rtk_uint32* pOuterTag, rtk_uint32* pInnerTag) * RT_ERR_OK - Success * RT_ERR_SMI - SMI access error * Note: - * The time granuality is 8 nano seconds. + * The time granularity is 8 nano seconds. */ ret_t rtl8367c_setAsicEavSysTime(rtk_uint32 second, rtk_uint32 nanoSecond) { @@ -218,7 +218,7 @@ ret_t rtl8367c_setAsicEavSysTime(rtk_uint32 second, rtk_uint32 nanoSecond) * RT_ERR_OK - Success * RT_ERR_SMI - SMI access error * Note: - * The time granuality is 8 nano seconds. + * The time granularity is 8 nano seconds. */ ret_t rtl8367c_getAsicEavSysTime(rtk_uint32* pSecond, rtk_uint32* pNanoSecond) { @@ -265,7 +265,7 @@ ret_t rtl8367c_getAsicEavSysTime(rtk_uint32* pSecond, rtk_uint32* pNanoSecond) * Description: * Set PTP system time adjust * Input: - * type - incresae or decrease + * type - increase or decrease * second - seconds * nanoSecond - nano seconds * Output: @@ -481,7 +481,7 @@ ret_t rtl8367c_getAsicEavInterruptStatus(rtk_uint32* pIms) * RT_ERR_OK - Success * RT_ERR_SMI - SMI access error * Note: - * This API can be used to clear ASIC interrupt status and register will be cleared by writting 1. + * This API can be used to clear ASIC interrupt status and register will be cleared by writing 1. * [0]:TX_SYNC, * [1]:TX_DELAY, * [2]:TX_PDELAY_REQ, @@ -570,7 +570,7 @@ ret_t rtl8367c_getAsicEavPortInterruptStatus(rtk_uint32 port, rtk_uint32* pIms) * RT_ERR_SMI - SMI access error * RT_ERR_PORT_ID - Invalid port number * Note: - * If EAV function is enabled, PTP event messgae packet will be attached PTP timestamp for trapping + * If EAV function is enabled, PTP event message packet will be attached PTP timestamp for trapping */ ret_t rtl8367c_setAsicEavPortEnable(rtk_uint32 port, rtk_uint32 enabled) { @@ -646,7 +646,7 @@ ret_t rtl8367c_getAsicEavPortEnable(rtk_uint32 port, rtk_uint32 *pEnabled) * RT_ERR_OK - Success * RT_ERR_SMI - SMI access error * Note: - * The time granuality is 8 nano seconds. + * The time granularity is 8 nano seconds. */ ret_t rtl8367c_getAsicEavPortTimeStamp(rtk_uint32 port, rtk_uint32 type, rtl8367c_ptp_time_stamp_t* timeStamp) { @@ -796,7 +796,7 @@ ret_t rtl8367c_getAsicEavTrap(rtk_uint32 port, rtk_uint32 *pEnabled) * RT_ERR_SMI - SMI access error * RT_ERR_PORT_ID - Invalid port number * Note: - * If EAV function is enabled, PTP event messgae packet will be attached PTP timestamp for trapping + * If EAV function is enabled, PTP event message packet will be attached PTP timestamp for trapping */ ret_t rtl8367c_setAsicEavEnable(rtk_uint32 port, rtk_uint32 enabled) { diff --git a/lede/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/rtl8367c_asicdrv_fc.c b/lede/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/rtl8367c_asicdrv_fc.c index 28f49b1ba7..b7b1022439 100644 --- a/lede/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/rtl8367c_asicdrv_fc.c +++ b/lede/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/rtl8367c_asicdrv_fc.c @@ -55,7 +55,7 @@ ret_t rtl8367c_getAsicFlowControlSelect(rtk_uint32 *pSelect) /* Function Name: * rtl8367c_setAsicFlowControlJumboMode * Description: - * Set Jumbo threhsold for flow control + * Set Jumbo threshold for flow control * Input: * enabled - Jumbo mode flow control 1: Enable 0:Disable * Output: @@ -73,7 +73,7 @@ ret_t rtl8367c_setAsicFlowControlJumboMode(rtk_uint32 enabled) /* Function Name: * rtl8367c_getAsicFlowControlJumboMode * Description: - * Get Jumbo threhsold for flow control + * Get Jumbo threshold for flow control * Input: * pEnabled - Jumbo mode flow control 1: Enable 0:Disable * Output: diff --git a/lede/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/rtl8367c_asicdrv_green.c b/lede/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/rtl8367c_asicdrv_green.c index a38623850b..3fb5f57b91 100644 --- a/lede/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/rtl8367c_asicdrv_green.c +++ b/lede/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/rtl8367c_asicdrv_green.c @@ -11,7 +11,7 @@ * $Date: 2017-03-08 15:13:58 +0800 (週三, 08 三月 2017) $ * * Purpose : RTL8367C switch high-level API for RTL8367C - * Feature : Green ethernet related functions + * Feature : Green Ethernet related functions * */ #include @@ -22,7 +22,7 @@ * Get per-Port ingress page usage per second * Input: * port - Physical port number (0~7) - * pPage - page number of ingress packet occuping per second + * pPage - page number of ingress packet occurring per second * Output: * None * Return: @@ -30,7 +30,7 @@ * RT_ERR_SMI - SMI access error * RT_ERR_PORT_ID - Invalid port number * Note: - * Ingress traffic occuping page number per second for high layer green feature usage + * Ingress traffic occurring page number per second for high layer green feature usage */ ret_t rtl8367c_getAsicGreenPortPage(rtk_uint32 port, rtk_uint32* pPage) { @@ -134,7 +134,7 @@ ret_t rtl8367c_setAsicGreenHighPriorityTraffic(rtk_uint32 port) * Get indicator which ASIC had received high priority traffic or not * Input: * port - Physical port number (0~7) - * pIndicator - Have received high priority traffic indicator. If 1 means ASCI had received high priority in 1second checking priod + * pIndicator - Have received high priority traffic indicator. If 1 means ASCI had received high priority in 1second checking period * Output: * None * Return: @@ -153,14 +153,14 @@ ret_t rtl8367c_getAsicGreenHighPriorityTraffic(rtk_uint32 port, rtk_uint32* pInd } /* -@func rtk_int32 | rtl8367c_setAsicGreenEthernet | Set green ethernet function. +@func rtk_int32 | rtl8367c_setAsicGreenEthernet | Set green Ethernet function. @parm rtk_uint32 | green | Green feature function usage 1:enable 0:disable. @rvalue RT_ERR_OK | Success. @rvalue RT_ERR_SMI | SMI access error. @comm The API can set Green Ethernet function to reduce power consumption. While green feature is enabled, ASIC will automatic detect the cable length and then select different power mode for best performance with minimums power consumption. Link down - ports will enter power savining mode in 10 seconds after the cable disconnected if power saving function is enabled. + ports will enter power saving mode in 10 seconds after the cable disconnected if power saving function is enabled. */ ret_t rtl8367c_setAsicGreenEthernet(rtk_uint32 port, rtk_uint32 green) { @@ -286,14 +286,14 @@ ret_t rtl8367c_setAsicGreenEthernet(rtk_uint32 port, rtk_uint32 green) } /* -@func rtk_int32 | rtl8367c_getAsicGreenEthernet | Get green ethernet function. +@func rtk_int32 | rtl8367c_getAsicGreenEthernet | Get green Ethernet function. @parm rtk_uint32 | *green | Green feature function usage 1:enable 0:disable. @rvalue RT_ERR_OK | Success. @rvalue RT_ERR_SMI | SMI access error. @comm The API can set Green Ethernet function to reduce power consumption. While green feature is enabled, ASIC will automatic detect the cable length and then select different power mode for best performance with minimums power consumption. Link down - ports will enter power savining mode in 10 seconds after the cable disconnected if power saving function is enabled. + ports will enter power saving mode in 10 seconds after the cable disconnected if power saving function is enabled. */ ret_t rtl8367c_getAsicGreenEthernet(rtk_uint32 port, rtk_uint32* green) { diff --git a/lede/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/rtl8367c_asicdrv_hsb.c b/lede/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/rtl8367c_asicdrv_hsb.c index 435368d51b..1b8ef59d95 100644 --- a/lede/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/rtl8367c_asicdrv_hsb.c +++ b/lede/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/rtl8367c_asicdrv_hsb.c @@ -30,7 +30,7 @@ * RT_ERR_SMI - SMI access error * RT_ERR_OUT_OF_RANGE - input parameter out of range * Note: - * System support 16 user defined field selctors. + * System support 16 user defined field selectors. * Each selector can be enabled or disable. User can defined retrieving 16-bits in many predefiend * standard l2/l3/l4 payload. */ diff --git a/lede/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/rtl8367c_asicdrv_igmp.c b/lede/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/rtl8367c_asicdrv_igmp.c index e0e734d61e..c915d2d618 100644 --- a/lede/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/rtl8367c_asicdrv_igmp.c +++ b/lede/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/rtl8367c_asicdrv_igmp.c @@ -429,8 +429,8 @@ ret_t rtl8367c_setAsicIGMPRobVar(rtk_uint32 rob_var) if(rob_var > RTL8367C_MAX_ROB_VAR) return RT_ERR_OUT_OF_RANGE; - /* Bourstness variable */ - retVal = rtl8367c_setAsicRegBits(RTL8367C_REG_IGMP_MLD_CFG0, RTL8367C_ROBURSTNESS_VAR_MASK, rob_var); + /* Robustness variable */ + retVal = rtl8367c_setAsicRegBits(RTL8367C_REG_IGMP_MLD_CFG0, RTL8367C_ROBUSTNESS_VAR_MASK, rob_var); if(retVal != RT_ERR_OK) return retVal; @@ -456,8 +456,8 @@ ret_t rtl8367c_getAsicIGMPRobVar(rtk_uint32 *prob_var) ret_t retVal; rtk_uint32 value; - /* Bourstness variable */ - retVal = rtl8367c_getAsicRegBits(RTL8367C_REG_IGMP_MLD_CFG0, RTL8367C_ROBURSTNESS_VAR_MASK, &value); + /* Robustness variable */ + retVal = rtl8367c_getAsicRegBits(RTL8367C_REG_IGMP_MLD_CFG0, RTL8367C_ROBUSTNESS_VAR_MASK, &value); if(retVal != RT_ERR_OK) return retVal; @@ -1813,7 +1813,7 @@ ret_t rtl8367c_getAsicIGMPReportLeaveFlood(rtk_uint32 *pFlood) /* Function Name: * rtl8367c_setAsicIGMPDropLeaveZero * Description: - * Set the function of droppping Leave packet with group IP = 0.0.0.0 + * Set the function of dropping Leave packet with group IP = 0.0.0.0 * Input: * drop - 1: Drop, 0:Bypass * Output: @@ -1838,7 +1838,7 @@ ret_t rtl8367c_setAsicIGMPDropLeaveZero(rtk_uint32 drop) /* Function Name: * rtl8367c_getAsicIGMPDropLeaveZero * Description: - * Get the function of droppping Leave packet with group IP = 0.0.0.0 + * Get the function of dropping Leave packet with group IP = 0.0.0.0 * Input: * None * Output: @@ -1865,7 +1865,7 @@ ret_t rtl8367c_getAsicIGMPDropLeaveZero(rtk_uint32 *pDrop) /* Function Name: * rtl8367c_setAsicIGMPBypassStormCTRL * Description: - * Set the function of bypass strom control for IGMP/MLD packet + * Set the function of bypass storm control for IGMP/MLD packet * Input: * bypass - 1: Bypass, 0:not bypass * Output: @@ -1890,7 +1890,7 @@ ret_t rtl8367c_setAsicIGMPBypassStormCTRL(rtk_uint32 bypass) /* Function Name: * rtl8367c_getAsicIGMPBypassStormCTRL * Description: - * Set the function of bypass strom control for IGMP/MLD packet + * Set the function of bypass storm control for IGMP/MLD packet * Input: * None * Output: @@ -1944,7 +1944,7 @@ ret_t rtl8367c_setAsicIGMPIsoLeaky(rtk_uint32 leaky) * Description: * Get Port Isolation leaky for IGMP/MLD packet * Input: - * Noen + * None * Output: * pLeaky - 1: Leaky, 0:not leaky * Return: @@ -1996,7 +1996,7 @@ ret_t rtl8367c_setAsicIGMPVLANLeaky(rtk_uint32 leaky) * Description: * Get VLAN leaky for IGMP/MLD packet * Input: - * Noen + * None * Output: * pLeaky - 1: Leaky, 0:not leaky * Return: diff --git a/lede/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/rtl8367c_asicdrv_inbwctrl.c b/lede/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/rtl8367c_asicdrv_inbwctrl.c index abb36bec2d..13a7b14246 100644 --- a/lede/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/rtl8367c_asicdrv_inbwctrl.c +++ b/lede/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/rtl8367c_asicdrv_inbwctrl.c @@ -128,7 +128,7 @@ ret_t rtl8367c_getAsicPortIngressBandwidth(rtk_uint32 port, rtk_uint32* pBandwid /* Function Name: * rtl8367c_setAsicPortIngressBandwidthBypass * Description: - * Set ingress bandwidth control bypasss 8899, RMA 01-80-C2-00-00-xx and IGMP + * Set ingress bandwidth control bypass 8899, RMA 01-80-C2-00-00-xx and IGMP * Input: * enabled - 1: enabled, 0: disabled * Output: @@ -146,7 +146,7 @@ ret_t rtl8367c_setAsicPortIngressBandwidthBypass(rtk_uint32 enabled) /* Function Name: * rtl8367c_getAsicPortIngressBandwidthBypass * Description: - * Set ingress bandwidth control bypasss 8899, RMA 01-80-C2-00-00-xx and IGMP + * Set ingress bandwidth control bypass 8899, RMA 01-80-C2-00-00-xx and IGMP * Input: * pEnabled - 1: enabled, 0: disabled * Output: diff --git a/lede/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/rtl8367c_asicdrv_interrupt.c b/lede/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/rtl8367c_asicdrv_interrupt.c index fb6cbcdf1f..1d5ccfc904 100644 --- a/lede/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/rtl8367c_asicdrv_interrupt.c +++ b/lede/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/rtl8367c_asicdrv_interrupt.c @@ -99,10 +99,10 @@ ret_t rtl8367c_getAsicInterruptMask(rtk_uint32* pImr) * RT_ERR_OK - Success * RT_ERR_SMI - SMI access error * Note: - * This API can be used to clear ASIC interrupt status and register will be cleared by writting 1. + * This API can be used to clear ASIC interrupt status and register will be cleared by writing 1. * [0]:Link change, * [1]:Share meter exceed, - * [2]:Learn number overed, + * [2]:Learn number over, * [3]:Speed Change, * [4]:Tx special congestion * [5]:1 second green feature diff --git a/lede/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/rtl8367c_asicdrv_led.c b/lede/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/rtl8367c_asicdrv_led.c index 1189028161..6f2617f5aa 100644 --- a/lede/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/rtl8367c_asicdrv_led.c +++ b/lede/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/rtl8367c_asicdrv_led.c @@ -607,7 +607,7 @@ ret_t rtl8367c_getAsicLedSerialModeConfig(rtk_uint32 *active, rtk_uint32 *serimo /* @func ret_t | rtl8367c_setAsicLedOutputEnable | Set LED output enable -@parm rtk_uint32 | enabled | enable or disalbe. +@parm rtk_uint32 | enabled | enable or disable. @rvalue RT_ERR_OK | Success. @rvalue RT_ERR_SMI | SMI access error. @rvalue RT_ERR_INPUT | Invalid input value. diff --git a/lede/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/rtl8367c_asicdrv_lut.c b/lede/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/rtl8367c_asicdrv_lut.c index 343a6f159c..1521467aa8 100644 --- a/lede/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/rtl8367c_asicdrv_lut.c +++ b/lede/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/rtl8367c_asicdrv_lut.c @@ -207,7 +207,7 @@ static void _rtl8367c_fdbStSmi2User( rtl8367c_luttb *pLutSt, rtk_uint16 *pFdbSmi /* Function Name: * rtl8367c_setAsicLutIpMulticastLookup * Description: - * Set Lut IP multicast lookup function + * Set LUT IP multicast lookup function * Input: * enabled - 1: enabled, 0: disabled * Output: @@ -225,7 +225,7 @@ ret_t rtl8367c_setAsicLutIpMulticastLookup(rtk_uint32 enabled) /* Function Name: * rtl8367c_getAsicLutIpMulticastLookup * Description: - * Get Lut IP multicast lookup function + * Get LUT IP multicast lookup function * Input: * pEnabled - 1: enabled, 0: disabled * Output: @@ -244,7 +244,7 @@ ret_t rtl8367c_getAsicLutIpMulticastLookup(rtk_uint32* pEnabled) /* Function Name: * rtl8367c_setAsicLutIpMulticastLookup * Description: - * Set Lut IP multicast + VID lookup function + * Set LUT IP multicast + VID lookup function * Input: * enabled - 1: enabled, 0: disabled * Output: @@ -263,7 +263,7 @@ ret_t rtl8367c_setAsicLutIpMulticastVidLookup(rtk_uint32 enabled) /* Function Name: * rtl8367c_getAsicLutIpMulticastVidLookup * Description: - * Get Lut IP multicast lookup function + * Get LUT IP multicast lookup function * Input: * pEnabled - 1: enabled, 0: disabled * Output: @@ -282,7 +282,7 @@ ret_t rtl8367c_getAsicLutIpMulticastVidLookup(rtk_uint32* pEnabled) /* Function Name: * rtl8367c_setAsicLutIpLookupMethod * Description: - * Set Lut IP lookup hash with DIP or {DIP,SIP} pair + * Set LUT IP lookup hash with DIP or {DIP,SIP} pair * Input: * type - 1: When DIP can be found in IPMC_GROUP_TABLE, use DIP+SIP Hash, otherwise, use DIP+(SIP=0.0.0.0) Hash. * 0: When DIP can be found in IPMC_GROUP_TABLE, use DIP+(SIP=0.0.0.0) Hash, otherwise use DIP+SIP Hash. @@ -301,7 +301,7 @@ ret_t rtl8367c_setAsicLutIpLookupMethod(rtk_uint32 type) /* Function Name: * rtl8367c_getAsicLutIpLookupMethod * Description: - * Get Lut IP lookup hash with DIP or {DIP,SIP} pair + * Get LUT IP lookup hash with DIP or {DIP,SIP} pair * Input: * pType - 1: When DIP can be found in IPMC_GROUP_TABLE, use DIP+SIP Hash, otherwise, use DIP+(SIP=0.0.0.0) Hash. * 0: When DIP can be found in IPMC_GROUP_TABLE, use DIP+(SIP=0.0.0.0) Hash, otherwise use DIP+SIP Hash. @@ -320,10 +320,10 @@ ret_t rtl8367c_getAsicLutIpLookupMethod(rtk_uint32* pType) /* Function Name: * rtl8367c_setAsicLutAgeTimerSpeed * Description: - * Set LUT agging out speed + * Set LUT ageing out speed * Input: - * timer - Agging out timer 0:Has been aged out - * speed - Agging out speed 0-fastest 3-slowest + * timer - Ageing out timer 0:Has been aged out + * speed - Ageing out speed 0-fastest 3-slowest * Output: * None * Return: @@ -346,10 +346,10 @@ ret_t rtl8367c_setAsicLutAgeTimerSpeed(rtk_uint32 timer, rtk_uint32 speed) /* Function Name: * rtl8367c_getAsicLutAgeTimerSpeed * Description: - * Get LUT agging out speed + * Get LUT ageing out speed * Input: - * pTimer - Agging out timer 0:Has been aged out - * pSpeed - Agging out speed 0-fastest 3-slowest + * pTimer - Ageing out timer 0:Has been aged out + * pSpeed - Ageing out speed 0-fastest 3-slowest * Output: * None * Return: @@ -378,7 +378,7 @@ ret_t rtl8367c_getAsicLutAgeTimerSpeed(rtk_uint32* pTimer, rtk_uint32* pSpeed) /* Function Name: * rtl8367c_setAsicLutCamTbUsage * Description: - * Configure Lut CAM table usage + * Configure LUT CAM table usage * Input: * enabled - L2 CAM table usage 1: enabled, 0: disabled * Output: @@ -400,7 +400,7 @@ ret_t rtl8367c_setAsicLutCamTbUsage(rtk_uint32 enabled) /* Function Name: * rtl8367c_getAsicLutCamTbUsage * Description: - * Get Lut CAM table usage + * Get LUT CAM table usage * Input: * pEnabled - L2 CAM table usage 1: enabled, 0: disabled * Output: @@ -439,7 +439,7 @@ ret_t rtl8367c_getAsicLutCamTbUsage(rtk_uint32* pEnabled) * Note: * None */ - /*޸: RTL8367C_PORTIDMAX, RTL8367C_LUT_LEARNLIMITMAX, RTL8367C_LUT_PORT_LEARN_LIMITNO_REG*/ + /*modification: RTL8367C_PORTIDMAX, RTL8367C_LUT_LEARNLIMITMAX, RTL8367C_LUT_PORT_LEARN_LIMITNO_REG*/ ret_t rtl8367c_setAsicLutLearnLimitNo(rtk_uint32 port, rtk_uint32 number) { if(port > RTL8367C_PORTIDMAX) @@ -470,7 +470,7 @@ ret_t rtl8367c_setAsicLutLearnLimitNo(rtk_uint32 port, rtk_uint32 number) * Note: * None */ - /*޸: RTL8367C_PORTIDMAX, RTL8367C_LUT_PORT_LEARN_LIMITNO_REG*/ + /*modification: RTL8367C_PORTIDMAX, RTL8367C_LUT_PORT_LEARN_LIMITNO_REG*/ ret_t rtl8367c_getAsicLutLearnLimitNo(rtk_uint32 port, rtk_uint32* pNumber) { if(port > RTL8367C_PORTIDMAX) @@ -498,7 +498,7 @@ ret_t rtl8367c_getAsicLutLearnLimitNo(rtk_uint32 port, rtk_uint32* pNumber) * Note: * None */ - /*޸: RTL8367C_LUT_LEARNLIMITMAX*/ + /*modification: RTL8367C_LUT_LEARNLIMITMAX*/ ret_t rtl8367c_setAsicSystemLutLearnLimitNo(rtk_uint32 number) { if(number > RTL8367C_LUT_LEARNLIMITMAX) @@ -632,7 +632,7 @@ ret_t rtl8367c_getAsicSystemLutLearnOverAct(rtk_uint32 *pAction) * Note: * None */ - /*޸: RTL8367C_LUT_SYSTEM_LEARN_PMASK_MASK*/ + /*modification: RTL8367C_LUT_SYSTEM_LEARN_PMASK_MASK*/ ret_t rtl8367c_setAsicSystemLutLearnPortMask(rtk_uint32 portmask) { ret_t retVal; @@ -666,7 +666,7 @@ ret_t rtl8367c_setAsicSystemLutLearnPortMask(rtk_uint32 portmask) * Note: * None */ - /*޸: RTL8367C_LUT_SYSTEM_LEARN_PMASK_MASK*/ + /*modification: RTL8367C_LUT_SYSTEM_LEARN_PMASK_MASK*/ ret_t rtl8367c_getAsicSystemLutLearnPortMask(rtk_uint32 *pPortmask) { rtk_uint32 tmpmask; @@ -966,7 +966,7 @@ ret_t rtl8367c_getAsicL2LookupTb(rtk_uint32 method, rtl8367c_luttb *pL2Table) * Note: * None */ - /*޸RTL8367C_PORTIDMAX, RTL8367C_REG_L2_LRN_CNT_REG, port10 reg is not contnious, wait for updating of base.h*/ + /*modification:RTL8367C_PORTIDMAX, RTL8367C_REG_L2_LRN_CNT_REG, port10 reg is not continuous, wait for updating of base.h*/ ret_t rtl8367c_getAsicLutLearnNo(rtk_uint32 port, rtk_uint32* pNumber) { ret_t retVal; @@ -1047,7 +1047,7 @@ ret_t rtl8367c_getAsicLutFlushAllStatus(rtk_uint32 *pBusyStatus) * Note: * None */ - /*port8~port10һregister, wait for updating of base.h, reg.h*/ + /*port8~port10 setup is done in a separate register, wait for updating of base.h, reg.h*/ ret_t rtl8367c_setAsicLutForceFlush(rtk_uint32 portmask) { ret_t retVal; @@ -1079,7 +1079,7 @@ ret_t rtl8367c_setAsicLutForceFlush(rtk_uint32 portmask) * Note: * None */ - /*port8~port10һregister, wait for updating of base.h, reg.h*/ + /*port8~port10 setup is done in a separate register, wait for updating of base.h, reg.h*/ ret_t rtl8367c_getAsicLutForceFlushStatus(rtk_uint32 *pPortmask) { rtk_uint32 tmpMask; @@ -1142,7 +1142,7 @@ ret_t rtl8367c_getAsicLutFlushMode(rtk_uint32* pMode) * Description: * Get L2 LUT flush type * Input: - * type - 0: dynamice unicast; 1: both dynamic and static unicast entry + * type - 0: dynamic unicast; 1: both dynamic and static unicast entry * Output: * None * Return: @@ -1160,7 +1160,7 @@ ret_t rtl8367c_setAsicLutFlushType(rtk_uint32 type) * Description: * Set L2 LUT flush type * Input: - * pType - 0: dynamice unicast; 1: both dynamic and static unicast entry + * pType - 0: dynamic unicast; 1: both dynamic and static unicast entry * Output: * None * Return: @@ -1271,7 +1271,7 @@ ret_t rtl8367c_getAsicLutFlushFid(rtk_uint32* pFid) * Note: * None */ - /*޸RTL8367C_PORTIDMAX*/ + /*modification:RTL8367C_PORTIDMAX*/ ret_t rtl8367c_setAsicLutDisableAging(rtk_uint32 port, rtk_uint32 disabled) { if(port > RTL8367C_PORTIDMAX) @@ -1295,7 +1295,7 @@ ret_t rtl8367c_setAsicLutDisableAging(rtk_uint32 port, rtk_uint32 disabled) * Note: * None */ - /*޸RTL8367C_PORTIDMAX*/ + /*modification:RTL8367C_PORTIDMAX*/ ret_t rtl8367c_getAsicLutDisableAging(rtk_uint32 port, rtk_uint32 *pDisabled) { if(port > RTL8367C_PORTIDMAX) @@ -1504,9 +1504,9 @@ ret_t rtl8367c_getAsicLutLinkDownForceAging(rtk_uint32 *pEnable) /* Function Name: * rtl8367c_setAsicLutIpmcFwdRouterPort * Description: - * Set IPMC packet forward to rounter port also or not + * Set IPMC packet forward to router port also or not * Input: - * enable - 1: Inlcude router port, 0, exclude router port + * enable - 1: Include router port, 0, exclude router port * Output: * None * Return: @@ -1527,11 +1527,11 @@ ret_t rtl8367c_setAsicLutIpmcFwdRouterPort(rtk_uint32 enable) /* Function Name: * rtl8367c_getAsicLutIpmcFwdRouterPort * Description: - * Get IPMC packet forward to rounter port also or not + * Get IPMC packet forward to router port also or not * Input: * None * Output: - * pEnable - 1: Inlcude router port, 0, exclude router port + * pEnable - 1: Include router port, 0, exclude router port * Return: * RT_ERR_OK - Success * RT_ERR_SMI - SMI access error diff --git a/lede/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/rtl8367c_asicdrv_mib.c b/lede/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/rtl8367c_asicdrv_mib.c index c9aaa01d3e..7da098c49f 100644 --- a/lede/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/rtl8367c_asicdrv_mib.c +++ b/lede/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/rtl8367c_asicdrv_mib.c @@ -22,7 +22,7 @@ * Reset global/queue manage or per-port MIB counter * Input: * greset - Global reset - * qmreset - Queue maganement reset + * qmreset - Queue management reset * portmask - Port reset mask * Output: * None @@ -59,7 +59,7 @@ ret_t rtl8367c_setAsicMIBsCounterReset(rtk_uint32 greset, rtk_uint32 qmreset, rt * Input: * port - Physical port number (0~7) * mibIdx - MIB counter index - * pCounter - MIB retrived counter + * pCounter - MIB retrieved counter * Output: * None * Return: @@ -69,9 +69,9 @@ ret_t rtl8367c_setAsicMIBsCounterReset(rtk_uint32 greset, rtk_uint32 qmreset, rt * RT_ERR_BUSYWAIT_TIMEOUT - MIB is busy at retrieving * RT_ERR_STAT_CNTR_FAIL - MIB is resetting * Note: - * Before MIBs counter retrieving, writting accessing address to ASIC at first and check the MIB + * Before MIBs counter retrieving, writing accessing address to ASIC at first and check the MIB * control register status. If busy bit of MIB control is set, that means MIB counter have been - * waiting for preparing, then software must wait atfer this busy flag reset by ASIC. This driver + * waiting for preparing, then software must wait after this busy flag reset by ASIC. This driver * did not recycle reading user desired counter. Software must use driver again to get MIB counter * if return value is not RT_ERR_OK. */ @@ -124,7 +124,7 @@ ret_t rtl8367c_getAsicMIBsCounter(rtk_uint32 port, RTL8367C_MIBCOUNTER mibIdx, r /*writing access counter address first*/ /*This address is SRAM address, and SRAM address = MIB register address >> 2*/ - /*then ASIC will prepare 64bits counter wait for being retrived*/ + /*then ASIC will prepare 64bits counter wait for being retrieved*/ /*Write Mib related address to access control register*/ retVal = rtl8367c_setAsicReg(RTL8367C_REG_MIB_ADDRESS, (mibAddr >> 2)); if(retVal != RT_ERR_OK) @@ -183,7 +183,7 @@ ret_t rtl8367c_getAsicMIBsCounter(rtk_uint32 port, RTL8367C_MIBCOUNTER mibIdx, r /* Function Name: * rtl8367c_getAsicMIBsLogCounter * Description: - * Get MIBs Loggin counter + * Get MIBs Logging counter * Input: * index - The index of 32 logging counter (0 ~ 31) * Output: @@ -260,7 +260,7 @@ ret_t rtl8367c_getAsicMIBsLogCounter(rtk_uint32 index, rtk_uint32 *pCounter) * RT_ERR_OK - Success * RT_ERR_SMI - SMI access error * Note: - * Software need to check this control register atfer doing port resetting or global resetting + * Software need to check this control register after doing port resetting or global resetting */ ret_t rtl8367c_getAsicMIBsControl(rtk_uint32* pMask) { @@ -513,7 +513,7 @@ ret_t rtl8367c_setAsicMIBsResetLoggingCounter(rtk_uint32 index) /* Function Name: * rtl8367c_setAsicMIBsLength * Description: - * Set MIB length couting mode + * Set MIB length counting mode * Input: * txLengthMode - 0: tag length doesn't be counted. 1: tag length is counted. * rxLengthMode - 0: tag length doesn't be counted. 1: tag length is counted. @@ -542,7 +542,7 @@ ret_t rtl8367c_setAsicMIBsLength(rtk_uint32 txLengthMode, rtk_uint32 rxLengthMod /* Function Name: * rtl8367c_setAsicMIBsLength * Description: - * Set MIB length couting mode + * Set MIB length counting mode * Input: * None. * Output: diff --git a/lede/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/rtl8367c_asicdrv_port.c b/lede/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/rtl8367c_asicdrv_port.c index 78e80a0b20..fae046639d 100644 --- a/lede/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/rtl8367c_asicdrv_port.c +++ b/lede/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/rtl8367c_asicdrv_port.c @@ -951,7 +951,7 @@ rtk_uint8 Sgmii_Init[SGMII_INIT_SIZE] = { * Set UNDA behavior * Input: * port - port ID - * behavior - 0: flooding to unknwon DA portmask; 1: drop; 2:trap; 3: flooding + * behavior - 0: flooding to unknown DA portmask; 1: drop; 2:trap; 3: flooding * Output: * None * Return: @@ -981,7 +981,7 @@ ret_t rtl8367c_setAsicPortUnknownDaBehavior(rtk_uint32 port, rtk_uint32 behavior * Input: * port - port ID * Output: - * pBehavior - 0: flooding to unknwon DA portmask; 1: drop; 2:trap; 3: flooding + * pBehavior - 0: flooding to unknown DA portmask; 1: drop; 2:trap; 3: flooding * Return: * RT_ERR_OK - Success * RT_ERR_SMI - SMI access error @@ -3724,7 +3724,7 @@ ret_t rtl8367c_setAsicPortExtMode(rtk_uint32 id, rtk_uint32 mode) return retVal; /* 1: MAC link = SGMII SerDes link - 0: MAC link = SGMII config link cfg_sgmii_link + 0: MAC link = SGMII config link (cfg_sgmii_link) */ if ((retVal = rtl8367c_setAsicRegBit(0x1d95, 2, 0)) != RT_ERR_OK) return retVal; @@ -4032,7 +4032,7 @@ ret_t rtl8367c_setAsicPortExtMode(rtk_uint32 id, rtk_uint32 mode) if ((retVal = rtl8367c_setAsicRegBits(0x1d95, 0x1f00, 0x2)) != RT_ERR_OK) return retVal; - /*select MAC link source when port6/7 be set sgmii mode cfg_sgmii_link*/ + /*select MAC link source when port6/7 be set sgmii mode (cfg_sgmii_link)*/ if ((retVal = rtl8367c_setAsicRegBit(0x1d95, 2, 0)) != RT_ERR_OK) return retVal; } diff --git a/lede/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/rtl8367c_asicdrv_qos.c b/lede/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/rtl8367c_asicdrv_qos.c index 89c3c3e02e..69081049e3 100644 --- a/lede/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/rtl8367c_asicdrv_qos.c +++ b/lede/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/rtl8367c_asicdrv_qos.c @@ -11,7 +11,7 @@ * $Date: 2017-03-08 15:13:58 +0800 (週三, 08 三月 2017) $ * * Purpose : RTL8367C switch high-level API for RTL8367C - * Feature : Qos related functions + * Feature : QoS related functions * */ diff --git a/lede/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/rtl8367c_asicdrv_scheduling.c b/lede/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/rtl8367c_asicdrv_scheduling.c index 8ebd6796dc..32d9b20840 100644 --- a/lede/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/rtl8367c_asicdrv_scheduling.c +++ b/lede/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/rtl8367c_asicdrv_scheduling.c @@ -19,7 +19,7 @@ /* Function Name: * rtl8367c_setAsicLeakyBucketParameter * Description: - * Set Leaky Bucket Paramters + * Set Leaky Bucket Parameters * Input: * tick - Tick is used for time slot size unit * token - Token is used for adding budget in each time slot @@ -55,7 +55,7 @@ ret_t rtl8367c_setAsicLeakyBucketParameter(rtk_uint32 tick, rtk_uint32 token) /* Function Name: * rtl8367c_getAsicLeakyBucketParameter * Description: - * Get Leaky Bucket Paramters + * Get Leaky Bucket Parameters * Input: * tick - Tick is used for time slot size unit * token - Token is used for adding budget in each time slot @@ -166,7 +166,7 @@ ret_t rtl8367c_getAsicAprMeter(rtk_uint32 port, rtk_uint32 qid, rtk_uint32 *apri * Set per-port APR enable * Input: * port - Physical port number (0~7) - * aprEnable - APR enable seting 1:enable 0:disable + * aprEnable - APR enable setting 1:enable 0:disable * Output: * None * Return: @@ -193,7 +193,7 @@ ret_t rtl8367c_setAsicAprEnable(rtk_uint32 port, rtk_uint32 aprEnable) * Get per-port APR enable * Input: * port - Physical port number (0~7) - * aprEnable - APR enable seting 1:enable 0:disable + * aprEnable - APR enable setting 1:enable 0:disable * Output: * None * Return: diff --git a/lede/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/rtl8367c_asicdrv_svlan.c b/lede/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/rtl8367c_asicdrv_svlan.c index f19ceba5a9..e199664b5e 100644 --- a/lede/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/rtl8367c_asicdrv_svlan.c +++ b/lede/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/rtl8367c_asicdrv_svlan.c @@ -140,7 +140,7 @@ ret_t rtl8367c_getAsicSvlanUplinkPortMask(rtk_uint32* pPortmask) * RT_ERR_SMI - SMI access error * Note: * Ether type of S-tag in 802.1ad is 0x88a8 and there are existed ether type 0x9100 and 0x9200 - * for Q-in-Q SLAN design. User can set mathced ether type as service provider supported protocol + * for Q-in-Q SLAN design. User can set matched ether type as service provider supported protocol */ ret_t rtl8367c_setAsicSvlanTpid(rtk_uint32 protocolType) { @@ -344,7 +344,7 @@ ret_t rtl8367c_getAsicSvlanDefaultVlan(rtk_uint32 port, rtk_uint32* pIndex) /* Function Name: * rtl8367c_setAsicSvlanIngressUntag * Description: - * Set action received un-Stag frame from unplink port + * Set action received un-Stag frame from uplink port * Input: * mode - 0:Drop 1:Trap 2:Assign SVLAN * Output: @@ -362,7 +362,7 @@ ret_t rtl8367c_setAsicSvlanIngressUntag(rtk_uint32 mode) /* Function Name: * rtl8367c_getAsicSvlanIngressUntag * Description: - * Get action received un-Stag frame from unplink port + * Get action received un-Stag frame from uplink port * Input: * pMode - 0:Drop 1:Trap 2:Assign SVLAN * Output: @@ -380,7 +380,7 @@ ret_t rtl8367c_getAsicSvlanIngressUntag(rtk_uint32* pMode) /* Function Name: * rtl8367c_setAsicSvlanIngressUnmatch * Description: - * Set action received unmatched Stag frame from unplink port + * Set action received unmatched Stag frame from uplink port * Input: * mode - 0:Drop 1:Trap 2:Assign SVLAN * Output: @@ -398,7 +398,7 @@ ret_t rtl8367c_setAsicSvlanIngressUnmatch(rtk_uint32 mode) /* Function Name: * rtl8367c_getAsicSvlanIngressUnmatch * Description: - * Get action received unmatched Stag frame from unplink port + * Get action received unmatched Stag frame from uplink port * Input: * pMode - 0:Drop 1:Trap 2:Assign SVLAN * Output: @@ -417,7 +417,7 @@ ret_t rtl8367c_getAsicSvlanIngressUnmatch(rtk_uint32* pMode) /* Function Name: * rtl8367c_setAsicSvlanEgressUnassign * Description: - * Set unplink stream without egress SVID action + * Set uplink stream without egress SVID action * Input: * enabled - 1:Trap egress unassigned frames to CPU, 0: Use SVLAN setup in VS_CPSVIDX as egress SVID * Output: @@ -435,7 +435,7 @@ ret_t rtl8367c_setAsicSvlanEgressUnassign(rtk_uint32 enabled) /* Function Name: * rtl8367c_getAsicSvlanEgressUnassign * Description: - * Get unplink stream without egress SVID action + * Get uplink stream without egress SVID action * Input: * pEnabled - 1:Trap egress unassigned frames to CPU, 0: Use SVLAN setup in VS_CPSVIDX as egress SVID * Output: @@ -580,7 +580,7 @@ ret_t rtl8367c_getAsicSvlanMemberConfiguration(rtk_uint32 index,rtl8367c_svlan_m * RT_ERR_SMI - SMI access error * RT_ERR_ENTRY_INDEX - Invalid entry index * Note: - * ASIC will check upstream's VID and assign related SVID to mathed packet + * ASIC will check upstream's VID and assign related SVID to matched packet */ ret_t rtl8367c_setAsicSvlanC2SConf(rtk_uint32 index, rtk_uint32 evid, rtk_uint32 portmask, rtk_uint32 svidx) { diff --git a/lede/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/rtl8367c_asicdrv_unknownMulticast.c b/lede/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/rtl8367c_asicdrv_unknownMulticast.c index fcebd1b7f7..a3455bbebd 100644 --- a/lede/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/rtl8367c_asicdrv_unknownMulticast.c +++ b/lede/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/rtl8367c_asicdrv_unknownMulticast.c @@ -11,7 +11,7 @@ * $Date: 2017-03-08 15:13:58 +0800 (週三, 08 三月 2017) $ * * Purpose : RTL8367C switch high-level API for RTL8367C - * Feature : Unkown multicast related functions + * Feature : Unknown multicast related functions * */ diff --git a/lede/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/smi.c b/lede/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/smi.c index c272cad48e..70e767f422 100644 --- a/lede/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/smi.c +++ b/lede/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/smi.c @@ -421,7 +421,7 @@ rtk_int32 smi_write(rtk_uint32 mAddrs, rtk_uint32 rData) con = 0; do { con++; - _smi_readBit(1, &ACK); /* ACK for writting data [7:0] */ + _smi_readBit(1, &ACK); /* ACK for writing data [7:0] */ } while ((ACK != 0) && (con < ack_timer)); if (ACK != 0) ret = RT_ERR_FAILED; @@ -430,7 +430,7 @@ rtk_int32 smi_write(rtk_uint32 mAddrs, rtk_uint32 rData) con = 0; do { con++; - _smi_readBit(1, &ACK); /* ACK for writting data [15:8] */ + _smi_readBit(1, &ACK); /* ACK for writing data [15:8] */ } while ((ACK != 0) && (con < ack_timer)); if (ACK != 0) ret = RT_ERR_FAILED; diff --git a/lede/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/stat.c b/lede/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/stat.c index 3a328b0ca4..3fd028a296 100644 --- a/lede/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/stat.c +++ b/lede/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/stat.c @@ -140,7 +140,7 @@ rtk_api_ret_t rtk_stat_global_get(rtk_stat_global_type_t cntr_idx, rtk_stat_coun if (cntr_idx!=DOT1D_TP_LEARNED_ENTRY_DISCARDS_INDEX) return RT_ERR_STAT_INVALID_GLOBAL_CNTR; - if ((retVal = rtl8367c_getAsicMIBsCounter(0, cntr_idx, pCntr)) != RT_ERR_OK) + if ((retVal = rtl8367c_getAsicMIBsCounter(0, (RTL8367C_MIBCOUNTER)cntr_idx, pCntr)) != RT_ERR_OK) return retVal; return RT_ERR_OK; @@ -172,7 +172,7 @@ rtk_api_ret_t rtk_stat_global_getAll(rtk_stat_global_cntr_t *pGlobal_cntrs) if(NULL == pGlobal_cntrs) return RT_ERR_NULL_POINTER; - if ((retVal = rtl8367c_getAsicMIBsCounter(0,DOT1D_TP_LEARNED_ENTRY_DISCARDS_INDEX, &pGlobal_cntrs->dot1dTpLearnedEntryDiscards)) != RT_ERR_OK) + if ((retVal = rtl8367c_getAsicMIBsCounter(0, dot1dTpLearnedEntryDiscards, &pGlobal_cntrs->dot1dTpLearnedEntryDiscards)) != RT_ERR_OK) return retVal; return RT_ERR_OK; @@ -265,7 +265,7 @@ static rtk_api_ret_t _get_asic_mib_idx(rtk_stat_port_type_t cnt_idx, RTL8367C_MI * port - port id. * cntr_idx - port counter index. * Output: - * pCntr - MIB retrived counter. + * pCntr - MIB retrieved counter. * Return: * RT_ERR_OK - OK * RT_ERR_FAILED - Failed @@ -592,7 +592,7 @@ rtk_api_ret_t rtk_stat_lengthMode_set(rtk_stat_lengthMode_t txMode, rtk_stat_len /* Function Name: * rtk_stat_lengthMode_get * Description: - * Get Legnth mode. + * Get Length mode. * Input: * None. * Output: diff --git a/lede/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/storm.c b/lede/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/storm.c index 13cf4e3cb4..68063cdfa7 100644 --- a/lede/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/storm.c +++ b/lede/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/storm.c @@ -279,7 +279,7 @@ rtk_api_ret_t rtk_rate_stormControlPortEnable_get(rtk_port_t port, rtk_rate_stor * RT_ERR_ENABLE - Invalid IFG parameter * Note: * - * This API can set per-port bypass stomr filter control frame type including RMA and igmp. + * This API can set per-port bypass storm filter control frame type including RMA and IGMP. * The bypass frame type is as following: * - BYPASS_BRG_GROUP, * - BYPASS_FD_PAUSE, @@ -414,7 +414,7 @@ rtk_api_ret_t rtk_storm_bypass_set(rtk_storm_bypass_t type, rtk_enable_t enable) * RT_ERR_SMI - SMI access error * RT_ERR_INPUT - Invalid input parameters. * Note: - * This API can get per-port bypass stomr filter control frame type including RMA and igmp. + * This API can get per-port bypass storm filter control frame type including RMA and IGMP. * The bypass frame type is as following: * - BYPASS_BRG_GROUP, * - BYPASS_FD_PAUSE, @@ -526,7 +526,7 @@ rtk_api_ret_t rtk_storm_bypass_get(rtk_storm_bypass_t type, rtk_enable_t *pEnabl /* Function Name: * rtk_rate_stormControlExtPortmask_set * Description: - * Set externsion storm control port mask + * Set extension storm control port mask * Input: * pPortmask - port mask * Output: @@ -562,7 +562,7 @@ rtk_api_ret_t rtk_rate_stormControlExtPortmask_set(rtk_portmask_t *pPortmask) /* Function Name: * rtk_rate_stormControlExtPortmask_get * Description: - * Set externsion storm control port mask + * Set extension storm control port mask * Input: * None * Output: @@ -598,10 +598,10 @@ rtk_api_ret_t rtk_rate_stormControlExtPortmask_get(rtk_portmask_t *pPortmask) /* Function Name: * rtk_rate_stormControlExtEnable_set * Description: - * Set externsion storm control state + * Set extension storm control state * Input: * stormType - storm group type - * enable - externsion storm control state + * enable - extension storm control state * Output: * None * Return: @@ -653,11 +653,11 @@ rtk_api_ret_t rtk_rate_stormControlExtEnable_set(rtk_rate_storm_group_t stormTyp /* Function Name: * rtk_rate_stormControlExtEnable_get * Description: - * Get externsion storm control state + * Get extension storm control state * Input: * stormType - storm group type * Output: - * pEnable - externsion storm control state + * pEnable - extension storm control state * Return: * RT_ERR_OK * RT_ERR_FAILED @@ -707,10 +707,10 @@ rtk_api_ret_t rtk_rate_stormControlExtEnable_get(rtk_rate_storm_group_t stormTyp /* Function Name: * rtk_rate_stormControlExtMeterIdx_set * Description: - * Set externsion storm control meter index + * Set extension storm control meter index * Input: * stormType - storm group type - * index - externsion storm control state + * index - extension storm control state * Output: * None * Return: @@ -762,10 +762,10 @@ rtk_api_ret_t rtk_rate_stormControlExtMeterIdx_set(rtk_rate_storm_group_t stormT /* Function Name: * rtk_rate_stormControlExtMeterIdx_get * Description: - * Get externsion storm control meter index + * Get extension storm control meter index * Input: * stormType - storm group type - * pIndex - externsion storm control state + * pIndex - extension storm control state * Output: * None * Return: diff --git a/lede/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/svlan.c b/lede/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/svlan.c index bf4ef044d1..067291526a 100644 --- a/lede/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/svlan.c +++ b/lede/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/svlan.c @@ -41,7 +41,7 @@ rtk_svlan_lookupType_t svlan_lookupType; * RT_ERR_SMI - SMI access error * Note: * Ether type of S-tag in 802.1ad is 0x88a8 and there are existed ether type 0x9100 and 0x9200 for Q-in-Q SLAN design. - * User can set mathced ether type as service provider supported protocol. + * User can set matched ether type as service provider supported protocol. */ rtk_api_ret_t rtk_svlan_init(void) { @@ -250,7 +250,7 @@ rtk_api_ret_t rtk_svlan_servicePort_del(rtk_port_t port) * RT_ERR_INPUT - Invalid input parameter. * Note: * Ether type of S-tag in 802.1ad is 0x88a8 and there are existed ether type 0x9100 and 0x9200 for Q-in-Q SLAN design. - * User can set mathced ether type as service provider supported protocol. + * User can set matched ether type as service provider supported protocol. */ rtk_api_ret_t rtk_svlan_tpidEntry_set(rtk_svlan_tpid_t svlan_tag_id) { @@ -391,8 +391,8 @@ rtk_api_ret_t rtk_svlan_priorityRef_get(rtk_svlan_pri_ref_t *pRef) * RT_ERR_PORT_MASK - Invalid portmask. * RT_ERR_SVLAN_TABLE_FULL - SVLAN configuration is full. * Note: - * The API can set system 64 accepted s-tag frame format. Only 64 SVID S-tag frame will be accpeted - * to receiving from uplink ports. Other SVID S-tag frame or S-untagged frame will be droped by default setup. + * The API can set system 64 accepted s-tag frame format. Only 64 SVID S-tag frame will be accepted + * to receiving from uplink ports. Other SVID S-tag frame or S-untagged frame will be dropped by default setup. * - rtk_svlan_memberCfg_t->svid is SVID of SVLAN member configuration. * - rtk_svlan_memberCfg_t->memberport is member port mask of SVLAN member configuration. * - rtk_svlan_memberCfg_t->fid is filtering database of SVLAN member configuration. @@ -626,8 +626,8 @@ rtk_api_ret_t rtk_svlan_memberPortEntry_set(rtk_vlan_t svid, rtk_svlan_memberCfg * RT_ERR_SVLAN_ENTRY_NOT_FOUND - specified svlan entry not found. * RT_ERR_INPUT - Invalid input parameters. * Note: - * The API can get system 64 accepted s-tag frame format. Only 64 SVID S-tag frame will be accpeted - * to receiving from uplink ports. Other SVID S-tag frame or S-untagged frame will be droped. + * The API can get system 64 accepted s-tag frame format. Only 64 SVID S-tag frame will be accepted + * to receiving from uplink ports. Other SVID S-tag frame or S-untagged frame will be dropped. */ rtk_api_ret_t rtk_svlan_memberPortEntry_get(rtk_vlan_t svid, rtk_svlan_memberCfg_t *pSvlan_cfg) { @@ -794,8 +794,8 @@ rtk_api_ret_t rtk_svlan_memberPortEntry_adv_set(rtk_uint32 idx, rtk_svlan_member * RT_ERR_SVLAN_ENTRY_NOT_FOUND - specified svlan entry not found. * RT_ERR_INPUT - Invalid input parameters. * Note: - * The API can get system 64 accepted s-tag frame format. Only 64 SVID S-tag frame will be accpeted - * to receiving from uplink ports. Other SVID S-tag frame or S-untagged frame will be droped. + * The API can get system 64 accepted s-tag frame format. Only 64 SVID S-tag frame will be accepted + * to receiving from uplink ports. Other SVID S-tag frame or S-untagged frame will be dropped. */ rtk_api_ret_t rtk_svlan_memberPortEntry_adv_get(rtk_uint32 idx, rtk_svlan_memberCfg_t *pSvlan_cfg) { @@ -948,7 +948,7 @@ rtk_api_ret_t rtk_svlan_defaultSvlan_get(rtk_port_t port, rtk_vlan_t *pSvid) * RT_ERR_INPUT - Invalid input parameters. * Note: * The API can set system C2S configuration. ASIC will check upstream's VID and assign related - * SVID to mathed packet. There are 128 SVLAN C2S configurations. + * SVID to matched packet. There are 128 SVLAN C2S configurations. */ rtk_api_ret_t rtk_svlan_c2s_add(rtk_vlan_t vid, rtk_port_t src_port, rtk_vlan_t svid) { @@ -1011,7 +1011,7 @@ rtk_api_ret_t rtk_svlan_c2s_add(rtk_vlan_t vid, rtk_port_t src_port, rtk_vlan_t } else { - /* New svidx, remove src_port and find a new slot to add a new enrty */ + /* New svidx, remove src_port and find a new slot to add a new entry */ pmsk = pmsk & ~(1 << phyPort); if(pmsk == 0) c2s_svidx = 0; @@ -1263,7 +1263,7 @@ rtk_api_ret_t rtk_svlan_untag_action_set(rtk_svlan_untag_action_t action, rtk_vl * Note: * The API can Get action of downstream Un-Stag packet. A SVID assigned * to the un-stag is also retrieved by this API. The parameter pSvid is - * only refernced when the action is UNTAG_ASSIGN + * only referenced when the action is UNTAG_ASSIGN */ rtk_api_ret_t rtk_svlan_untag_action_get(rtk_svlan_untag_action_t *pAction, rtk_vlan_t *pSvid) { @@ -1313,8 +1313,8 @@ rtk_api_ret_t rtk_svlan_untag_action_get(rtk_svlan_untag_action_t *pAction, rtk_ * RT_ERR_INPUT - Invalid input parameters. * Note: * The API can configure action of downstream Un-match packet. A SVID assigned - * to the un-match is also supported by this API. The parameter od svid is - * only refernced when the action is set to UNMATCH_ASSIGN + * to the un-match is also supported by this API. The parameter of svid is + * only referenced when the action is set to UNMATCH_ASSIGN */ rtk_api_ret_t rtk_svlan_unmatch_action_set(rtk_svlan_unmatch_action_t action, rtk_vlan_t svid) { @@ -1379,7 +1379,7 @@ rtk_api_ret_t rtk_svlan_unmatch_action_set(rtk_svlan_unmatch_action_t action, rt * Note: * The API can Get action of downstream Un-match packet. A SVID assigned * to the un-match is also retrieved by this API. The parameter pSvid is - * only refernced when the action is UNMATCH_ASSIGN + * only referenced when the action is UNMATCH_ASSIGN */ rtk_api_ret_t rtk_svlan_unmatch_action_get(rtk_svlan_unmatch_action_t *pAction, rtk_vlan_t *pSvid) { @@ -1567,7 +1567,7 @@ rtk_api_ret_t rtk_svlan_dmac_vidsel_get(rtk_port_t port, rtk_enable_t *pEnable) * RT_ERR_OUT_OF_RANGE - input out of range. * RT_ERR_INPUT - Invalid input parameters. * Note: - * The API can set IP mutlicast to SVID configuration. If upstream packet is IPv4 multicast + * The API can set IP multicast to SVID configuration. If upstream packet is IPv4 multicast * packet and DIP is matched MC2S configuration, ASIC will assign egress SVID to the packet. * There are 32 SVLAN multicast configurations for IP and L2 multicast. */ @@ -1662,7 +1662,7 @@ rtk_api_ret_t rtk_svlan_ipmc2s_add(ipaddr_t ipmc, ipaddr_t ipmcMsk,rtk_vlan_t sv * RT_ERR_SVLAN_VID - Invalid SVLAN VID parameter. * RT_ERR_OUT_OF_RANGE - input out of range. * Note: - * The API can delete IP mutlicast to SVID configuration. There are 32 SVLAN multicast configurations for IP and L2 multicast. + * The API can delete IP multicast to SVID configuration. There are 32 SVLAN multicast configurations for IP and L2 multicast. */ rtk_api_ret_t rtk_svlan_ipmc2s_del(ipaddr_t ipmc, ipaddr_t ipmcMsk) { @@ -1714,7 +1714,7 @@ rtk_api_ret_t rtk_svlan_ipmc2s_del(ipaddr_t ipmc, ipaddr_t ipmcMsk) * RT_ERR_INPUT - Invalid input parameters. * RT_ERR_OUT_OF_RANGE - input out of range. * Note: - * The API can get IP mutlicast to SVID configuration. There are 32 SVLAN multicast configurations for IP and L2 multicast. + * The API can get IP multicast to SVID configuration. There are 32 SVLAN multicast configurations for IP and L2 multicast. */ rtk_api_ret_t rtk_svlan_ipmc2s_get(ipaddr_t ipmc, ipaddr_t ipmcMsk, rtk_vlan_t *pSvid) { @@ -1771,7 +1771,7 @@ rtk_api_ret_t rtk_svlan_ipmc2s_get(ipaddr_t ipmc, ipaddr_t ipmcMsk, rtk_vlan_t * * RT_ERR_OUT_OF_RANGE - input out of range. * RT_ERR_INPUT - Invalid input parameters. * Note: - * The API can set L2 Mutlicast to SVID configuration. If upstream packet is L2 multicast + * The API can set L2 Multicast to SVID configuration. If upstream packet is L2 multicast * packet and DMAC is matched, ASIC will assign egress SVID to the packet. There are 32 * SVLAN multicast configurations for IP and L2 multicast. */ @@ -1868,7 +1868,7 @@ rtk_api_ret_t rtk_svlan_l2mc2s_add(rtk_mac_t mac, rtk_mac_t macMsk, rtk_vlan_t s * RT_ERR_SVLAN_VID - Invalid SVLAN VID parameter. * RT_ERR_OUT_OF_RANGE - input out of range. * Note: - * The API can delete Mutlicast to SVID configuration. There are 32 SVLAN multicast configurations for IP and L2 multicast. + * The API can delete Multicast to SVID configuration. There are 32 SVLAN multicast configurations for IP and L2 multicast. */ rtk_api_ret_t rtk_svlan_l2mc2s_del(rtk_mac_t mac, rtk_mac_t macMsk) { @@ -1924,7 +1924,7 @@ rtk_api_ret_t rtk_svlan_l2mc2s_del(rtk_mac_t mac, rtk_mac_t macMsk) * RT_ERR_INPUT - Invalid input parameters. * RT_ERR_OUT_OF_RANGE - input out of range. * Note: - * The API can get L2 mutlicast to SVID configuration. There are 32 SVLAN multicast configurations for IP and L2 multicast. + * The API can get L2 multicast to SVID configuration. There are 32 SVLAN multicast configurations for IP and L2 multicast. */ rtk_api_ret_t rtk_svlan_l2mc2s_get(rtk_mac_t mac, rtk_mac_t macMsk, rtk_vlan_t *pSvid) { diff --git a/lede/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/vlan.c b/lede/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/vlan.c index f7480c4906..b407c3008c 100644 --- a/lede/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/vlan.c +++ b/lede/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/vlan.c @@ -106,7 +106,7 @@ rtk_api_ret_t rtk_vlan_init(void) return retVal; } - /* Updata Databse */ + /* Update Database */ vlan_mbrCfgUsage[0] = MBRCFG_USED_BY_VLAN; vlan_mbrCfgVid[0] = 1; @@ -950,7 +950,7 @@ rtk_api_ret_t rtk_vlan_protoAndPortBasedVlan_add(rtk_port_t port, rtk_vlan_proto { if ((retVal = rtl8367c_getAsicVlanProtocolBasedGroupData(i, &ppb_data_cfg)) != RT_ERR_OK) return retVal; - tmp = pInfo->frame_type; + tmp = (rtl8367c_provlan_frametype)pInfo->frame_type; if (ppb_data_cfg.etherType == pInfo->proto_type && ppb_data_cfg.frameType == tmp) { /*Already exist*/ @@ -976,7 +976,7 @@ rtk_api_ret_t rtk_vlan_protoAndPortBasedVlan_add(rtk_port_t port, rtk_vlan_proto else if (emptyframe_type; + ppb_data_cfg.frameType = (rtl8367c_provlan_frametype)pInfo->frame_type; ppb_data_cfg.etherType = pInfo->proto_type; if ((retVal = rtl8367c_setAsicVlanProtocolBasedGroupData(empty, &ppb_data_cfg)) != RT_ERR_OK) return retVal; @@ -1267,7 +1267,7 @@ rtk_api_ret_t rtk_vlan_tagMode_set(rtk_port_t port, rtk_vlan_tagMode_t tag_mode) if (tag_mode >= VLAN_TAG_MODE_END) return RT_ERR_PORT_ID; - if ((retVal = rtl8367c_setAsicVlanEgressTagMode(rtk_switch_port_L2P_get(port), tag_mode)) != RT_ERR_OK) + if ((retVal = rtl8367c_setAsicVlanEgressTagMode(rtk_switch_port_L2P_get(port), (rtl8367c_egtagmode)tag_mode)) != RT_ERR_OK) return retVal; return RT_ERR_OK; @@ -1576,7 +1576,7 @@ rtk_api_ret_t rtk_vlan_stg_get(rtk_vlan_t vid, rtk_stp_msti_id_t *pStg) * Set port-based filtering database * Input: * port - Port id. - * enable - ebable port-based FID + * enable - enable port-based FID * fid - Specified filtering database. * Output: * None @@ -1624,7 +1624,7 @@ rtk_api_ret_t rtk_vlan_portFid_set(rtk_port_t port, rtk_enable_t enable, rtk_fid * Input: * port - Port id. * Output: - * pEnable - ebable port-based FID + * pEnable - enable port-based FID * pFid - Specified filtering database. * Return: * RT_ERR_OK - OK diff --git a/lede/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367s_mdio.c b/lede/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367s_mdio.c index 08d2b57d43..b4d4554d4f 100644 --- a/lede/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367s_mdio.c +++ b/lede/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367s_mdio.c @@ -211,7 +211,7 @@ void init_gsw(void) set_rtl8367s_rgmii(); } -// bleow are platform driver +// below are platform driver static const struct of_device_id rtk_gsw_match[] = { { .compatible = "mediatek,rtk-gsw" }, {}, @@ -258,7 +258,7 @@ static int rtk_gsw_probe(struct platform_device *pdev) init_gsw(); - //init default vlan or init swocnfig + //init default vlan or init swconfig if(!of_property_read_string(pdev->dev.of_node, "mediatek,port_map", &pm)) { diff --git a/lede/target/linux/mediatek/filogic/config-6.1 b/lede/target/linux/mediatek/filogic/config-6.1 index c66bba9c9d..f3ebe7980f 100644 --- a/lede/target/linux/mediatek/filogic/config-6.1 +++ b/lede/target/linux/mediatek/filogic/config-6.1 @@ -82,7 +82,7 @@ CONFIG_CONTEXT_TRACKING_IDLE=y # CONFIG_CPUFREQ_DT is not set CONFIG_CPU_FREQ=y # CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set -CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE=y +CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y CONFIG_CPU_FREQ_GOV_ATTR_SET=y CONFIG_CPU_FREQ_GOV_COMMON=y CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y @@ -189,6 +189,8 @@ CONFIG_GENERIC_STRNLEN_USER=y CONFIG_GENERIC_TIME_VSYSCALL=y CONFIG_GLOB=y CONFIG_GPIO_CDEV=y +CONFIG_GPIO_WATCHDOG=y +CONFIG_GPIO_WATCHDOG_ARCH_INITCALL=y CONFIG_GRO_CELLS=y CONFIG_HARDIRQS_SW_RESEND=y CONFIG_HAS_DMA=y @@ -212,6 +214,7 @@ CONFIG_IRQ_TIME_ACCOUNTING=y CONFIG_IRQ_WORK=y CONFIG_JBD2=y CONFIG_JUMP_LABEL=y +CONFIG_LEDS_SMARTRG_LED=y CONFIG_LIBFDT=y CONFIG_LOCK_DEBUGGING_SUPPORT=y CONFIG_LOCK_SPIN_ON_OWNER=y @@ -230,6 +233,7 @@ CONFIG_MEMFD_CREATE=y CONFIG_MESSAGE_LOGLEVEL_DEFAULT=7 CONFIG_MFD_SYSCON=y CONFIG_MIGRATION=y +# CONFIG_MITIGATE_SPECTRE_BRANCH_HISTORY is not set CONFIG_MMC=y CONFIG_MMC_BLOCK=y CONFIG_MMC_CQHCI=y @@ -263,6 +267,9 @@ CONFIG_MTK_SCPSYS=y CONFIG_MTK_SCPSYS_PM_DOMAINS=y # CONFIG_MTK_SVS is not set CONFIG_MTK_THERMAL=y +CONFIG_MTK_SOC_THERMAL=y +CONFIG_MTK_LVTS_THERMAL=y +CONFIG_MTK_LVTS_THERMAL_DEBUGFS=y CONFIG_MTK_TIMER=y # CONFIG_MTK_UART_APDMA is not set CONFIG_MUTEX_SPIN_ON_OWNER=y @@ -276,7 +283,6 @@ CONFIG_NET_DSA_MT7530_MMIO=y CONFIG_NET_DSA_TAG_MTK=y CONFIG_NET_FLOW_LIMIT=y CONFIG_NET_MEDIATEK_SOC=y -CONFIG_NET_MEDIATEK_SOC_USXGMII=y CONFIG_NET_MEDIATEK_SOC_WED=y CONFIG_NET_SELFTESTS=y CONFIG_NET_SWITCHDEV=y @@ -323,6 +329,7 @@ CONFIG_PCI_DOMAINS_GENERIC=y CONFIG_PCI_MSI=y CONFIG_PCI_MSI_IRQ_DOMAIN=y CONFIG_PCS_MTK_LYNXI=y +CONFIG_PCS_MTK_USXGMII=y CONFIG_PERF_EVENTS=y CONFIG_PGTABLE_LEVELS=3 CONFIG_PHYLIB=y @@ -333,6 +340,7 @@ CONFIG_PHYS_ADDR_T_64BIT=y # CONFIG_PHY_MTK_PCIE is not set CONFIG_PHY_MTK_TPHY=y # CONFIG_PHY_MTK_UFS is not set +CONFIG_PHY_MTK_XFI_TPHY=y CONFIG_PHY_MTK_XSPHY=y CONFIG_PINCTRL=y # CONFIG_PINCTRL_MT2712 is not set diff --git a/lede/target/linux/mediatek/filogic/target.mk b/lede/target/linux/mediatek/filogic/target.mk index 4e5cde3d6b..1c4843a98c 100644 --- a/lede/target/linux/mediatek/filogic/target.mk +++ b/lede/target/linux/mediatek/filogic/target.mk @@ -2,7 +2,7 @@ ARCH:=aarch64 SUBTARGET:=filogic BOARDNAME:=Filogic 8x0 (MT798x) CPU_TYPE:=cortex-a53 -DEFAULT_PACKAGES += kmod-crypto-hw-safexcel kmod-mt7915e wpad-openssl uboot-envtools +DEFAULT_PACKAGES += fitblk kmod-crypto-hw-safexcel kmod-mt7915e wpad-openssl uboot-envtools KERNELNAME:=Image dtbs define Target/Description diff --git a/lede/target/linux/mediatek/patches-6.1/006-v6.2-arm64-dts-mt7986-add-spi-related-device-nodes.patch b/lede/target/linux/mediatek/patches-6.1/006-v6.2-arm64-dts-mt7986-add-spi-related-device-nodes.patch index 619bfec092..c45f183dc7 100644 --- a/lede/target/linux/mediatek/patches-6.1/006-v6.2-arm64-dts-mt7986-add-spi-related-device-nodes.patch +++ b/lede/target/linux/mediatek/patches-6.1/006-v6.2-arm64-dts-mt7986-add-spi-related-device-nodes.patch @@ -52,8 +52,8 @@ Signed-off-by: Matthias Brugger + compatible = "spi-nand"; + reg = <0>; + spi-max-frequency = <10000000>; -+ spi-tx-buswidth = <4>; -+ spi-rx-buswidth = <4>; ++ spi-tx-bus-width = <4>; ++ spi-rx-bus-width = <4>; + }; +}; + @@ -140,8 +140,8 @@ Signed-off-by: Matthias Brugger + compatible = "spi-nand"; + reg = <0>; + spi-max-frequency = <10000000>; -+ spi-tx-buswidth = <4>; -+ spi-rx-buswidth = <4>; ++ spi-tx-bus-width = <4>; ++ spi-rx-bus-width = <4>; + }; +}; + diff --git a/lede/target/linux/mediatek/patches-6.1/010-v6.3-arm64-dts-mt7986-add-Bananapi-R3.patch b/lede/target/linux/mediatek/patches-6.1/010-v6.3-arm64-dts-mt7986-add-Bananapi-R3.patch index abe0b6e9bc..38f159c74e 100644 --- a/lede/target/linux/mediatek/patches-6.1/010-v6.3-arm64-dts-mt7986-add-Bananapi-R3.patch +++ b/lede/target/linux/mediatek/patches-6.1/010-v6.3-arm64-dts-mt7986-add-Bananapi-R3.patch @@ -103,8 +103,8 @@ Signed-off-by: Matthias Brugger + compatible = "spi-nand"; + reg = <0>; + spi-max-frequency = <10000000>; -+ spi-tx-buswidth = <4>; -+ spi-rx-buswidth = <4>; ++ spi-tx-bus-width = <4>; ++ spi-rx-bus-width = <4>; + + partitions { + compatible = "fixed-partitions"; @@ -405,7 +405,7 @@ Signed-off-by: Matthias Brugger +}; + +&mdio { -+ switch: switch@31 { ++ switch: switch@1f { + compatible = "mediatek,mt7531"; + reg = <31>; + interrupt-controller; diff --git a/lede/target/linux/mediatek/patches-6.1/020-arm64-dts-mt7986-define-3W-max-power-to-both-SFP-on-.patch b/lede/target/linux/mediatek/patches-6.1/020-v6.7-arm64-dts-mt7986-define-3W-max-power-to-both-SFP-on-.patch similarity index 100% rename from lede/target/linux/mediatek/patches-6.1/020-arm64-dts-mt7986-define-3W-max-power-to-both-SFP-on-.patch rename to lede/target/linux/mediatek/patches-6.1/020-v6.7-arm64-dts-mt7986-define-3W-max-power-to-both-SFP-on-.patch diff --git a/lede/target/linux/mediatek/patches-6.1/021-arm64-dts-mt7986-change-cooling-trips.patch b/lede/target/linux/mediatek/patches-6.1/021-v6.7-arm64-dts-mt7986-change-cooling-trips.patch similarity index 100% rename from lede/target/linux/mediatek/patches-6.1/021-arm64-dts-mt7986-change-cooling-trips.patch rename to lede/target/linux/mediatek/patches-6.1/021-v6.7-arm64-dts-mt7986-change-cooling-trips.patch diff --git a/lede/target/linux/mediatek/patches-6.1/022-arm64-dts-mt7986-change-thermal-trips-on-BPI-R3.patch b/lede/target/linux/mediatek/patches-6.1/022-v6.7-arm64-dts-mt7986-change-thermal-trips-on-BPI-R3.patch similarity index 100% rename from lede/target/linux/mediatek/patches-6.1/022-arm64-dts-mt7986-change-thermal-trips-on-BPI-R3.patch rename to lede/target/linux/mediatek/patches-6.1/022-v6.7-arm64-dts-mt7986-change-thermal-trips-on-BPI-R3.patch diff --git a/lede/target/linux/mediatek/patches-6.1/041-block-fit-partition-parser.patch b/lede/target/linux/mediatek/patches-6.1/041-block-fit-partition-parser.patch index 3cef80d836..bb87c20a91 100644 --- a/lede/target/linux/mediatek/patches-6.1/041-block-fit-partition-parser.patch +++ b/lede/target/linux/mediatek/patches-6.1/041-block-fit-partition-parser.patch @@ -19,7 +19,7 @@ Subject: [PATCH] kernel: add block fit partition parser --- a/block/blk.h +++ b/block/blk.h -@@ -415,6 +415,8 @@ void blk_free_ext_minor(unsigned int min +@@ -414,6 +414,8 @@ void blk_free_ext_minor(unsigned int min #define ADDPART_FLAG_NONE 0 #define ADDPART_FLAG_RAID 1 #define ADDPART_FLAG_WHOLEDISK 2 diff --git a/lede/target/linux/mediatek/patches-6.1/104-mt7622-add-snor-irq.patch b/lede/target/linux/mediatek/patches-6.1/104-mt7622-add-snor-irq.patch index d15d989e97..0d9c91f44d 100644 --- a/lede/target/linux/mediatek/patches-6.1/104-mt7622-add-snor-irq.patch +++ b/lede/target/linux/mediatek/patches-6.1/104-mt7622-add-snor-irq.patch @@ -1,6 +1,6 @@ --- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi -@@ -575,6 +575,7 @@ +@@ -578,6 +578,7 @@ compatible = "mediatek,mt7622-nor", "mediatek,mt8173-nor"; reg = <0 0x11014000 0 0xe0>; diff --git a/lede/target/linux/mediatek/patches-6.1/106-dts-mt7622-disable_btif.patch b/lede/target/linux/mediatek/patches-6.1/106-dts-mt7622-disable_btif.patch new file mode 100644 index 0000000000..ac8594b396 --- /dev/null +++ b/lede/target/linux/mediatek/patches-6.1/106-dts-mt7622-disable_btif.patch @@ -0,0 +1,26 @@ +--- a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts ++++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts +@@ -109,10 +109,6 @@ + status = "disabled"; + }; + +-&btif { +- status = "okay"; +-}; +- + &cir { + pinctrl-names = "default"; + pinctrl-0 = <&irrx_pins>; +--- a/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts ++++ b/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts +@@ -90,10 +90,6 @@ + status = "disabled"; + }; + +-&btif { +- status = "okay"; +-}; +- + &cir { + pinctrl-names = "default"; + pinctrl-0 = <&irrx_pins>; diff --git a/lede/target/linux/mediatek/patches-6.1/112-dts-fix-bpi64-lan-names.patch b/lede/target/linux/mediatek/patches-6.1/112-dts-fix-bpi64-lan-names.patch index 7f97ef4aef..2cc0efdade 100644 --- a/lede/target/linux/mediatek/patches-6.1/112-dts-fix-bpi64-lan-names.patch +++ b/lede/target/linux/mediatek/patches-6.1/112-dts-fix-bpi64-lan-names.patch @@ -8,7 +8,7 @@ }; chosen { -@@ -165,22 +166,22 @@ +@@ -161,22 +162,22 @@ port@1 { reg = <1>; diff --git a/lede/target/linux/mediatek/patches-6.1/113-dts-fix-bpi64-leds-and-buttons.patch b/lede/target/linux/mediatek/patches-6.1/113-dts-fix-bpi64-leds-and-buttons.patch index bf1912a916..1cca6f3534 100644 --- a/lede/target/linux/mediatek/patches-6.1/113-dts-fix-bpi64-leds-and-buttons.patch +++ b/lede/target/linux/mediatek/patches-6.1/113-dts-fix-bpi64-leds-and-buttons.patch @@ -1,6 +1,6 @@ --- a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts +++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts -@@ -21,6 +21,10 @@ +@@ -21,6 +21,12 @@ aliases { serial0 = &uart0; ethernet0 = &gmac0; @@ -8,10 +8,12 @@ + led-failsafe = &led_system_blue; + led-running = &led_system_green; + led-upgrade = &led_system_blue; ++ mmc0 = &mmc0; ++ mmc1 = &mmc1; }; chosen { -@@ -44,8 +48,8 @@ +@@ -44,8 +50,8 @@ compatible = "gpio-keys"; factory-key { @@ -22,7 +24,7 @@ gpios = <&pio 0 GPIO_ACTIVE_HIGH>; }; -@@ -59,17 +63,17 @@ +@@ -59,17 +65,17 @@ leds { compatible = "gpio-leds"; diff --git a/lede/target/linux/mediatek/patches-6.1/114-dts-bpi64-disable-rtc.patch b/lede/target/linux/mediatek/patches-6.1/114-dts-bpi64-disable-rtc.patch index 261579bf37..119de1c457 100644 --- a/lede/target/linux/mediatek/patches-6.1/114-dts-bpi64-disable-rtc.patch +++ b/lede/target/linux/mediatek/patches-6.1/114-dts-bpi64-disable-rtc.patch @@ -1,6 +1,6 @@ --- a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts +++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts -@@ -559,12 +559,16 @@ +@@ -557,12 +557,16 @@ status = "okay"; }; diff --git a/lede/target/linux/mediatek/patches-6.1/115-dts-bpi64-add-snand-support.patch b/lede/target/linux/mediatek/patches-6.1/115-dts-bpi64-add-snand-support.patch deleted file mode 100644 index 20b0d90b22..0000000000 --- a/lede/target/linux/mediatek/patches-6.1/115-dts-bpi64-add-snand-support.patch +++ /dev/null @@ -1,50 +0,0 @@ ---- a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts -+++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts -@@ -256,14 +256,42 @@ - status = "disabled"; - }; - --&nor_flash { -- pinctrl-names = "default"; -- pinctrl-0 = <&spi_nor_pins>; -- status = "disabled"; -+&bch { -+ status = "okay"; -+}; - -+&snfi { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&serial_nand_pins>; -+ status = "okay"; - flash@0 { -- compatible = "jedec,spi-nor"; -+ compatible = "spi-nand"; - reg = <0>; -+ spi-tx-bus-width = <4>; -+ spi-rx-bus-width = <4>; -+ nand-ecc-engine = <&snfi>; -+ partitions { -+ compatible = "fixed-partitions"; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ -+ partition@0 { -+ label = "bl2"; -+ reg = <0x0 0x80000>; -+ read-only; -+ }; -+ -+ partition@80000 { -+ label = "fip"; -+ reg = <0x80000 0x200000>; -+ read-only; -+ }; -+ -+ partition@280000 { -+ label = "ubi"; -+ reg = <0x280000 0x7d80000>; -+ }; -+ }; - }; - }; - diff --git a/lede/target/linux/mediatek/patches-6.1/115-v6.5-arm64-dts-mt7622-declare-SPI-NAND-present-on-BPI-R64.patch b/lede/target/linux/mediatek/patches-6.1/115-v6.5-arm64-dts-mt7622-declare-SPI-NAND-present-on-BPI-R64.patch new file mode 100644 index 0000000000..6eac51f825 --- /dev/null +++ b/lede/target/linux/mediatek/patches-6.1/115-v6.5-arm64-dts-mt7622-declare-SPI-NAND-present-on-BPI-R64.patch @@ -0,0 +1,70 @@ +From d278f43f25beedfd0cb784d1dd0a9e7e8c8f123f Mon Sep 17 00:00:00 2001 +From: Daniel Golle +Date: Wed, 19 Apr 2023 20:15:53 +0100 +Subject: [PATCH] arm64: dts: mt7622: declare SPI-NAND present on BPI-R64 + +The SPI-NOR node in the device tree of the BananaPi R64 has most likely +been copied from the reference board's device tree even though the R64 +comes with an SPI-NAND chip rather than SPI-NOR. + +Setup the Serial NAND Flash Interface (SNFI) controller, enable +hardware BCH error detection and correction engine and add the SPI-NAND +chip including basic partitions, + +Signed-off-by: Daniel Golle +Link: https://lore.kernel.org/r/ZEA96dmaXqTpk8u8@makrotopia.org +Signed-off-by: Matthias Brugger +--- + .../dts/mediatek/mt7622-bananapi-bpi-r64.dts | 38 ++++++++++++++++--- + 1 file changed, 33 insertions(+), 5 deletions(-) + +--- a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts ++++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts +@@ -254,14 +254,42 @@ + status = "disabled"; + }; + +-&nor_flash { +- pinctrl-names = "default"; +- pinctrl-0 = <&spi_nor_pins>; +- status = "disabled"; ++&bch { ++ status = "okay"; ++}; + ++&snfi { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&serial_nand_pins>; ++ status = "okay"; + flash@0 { +- compatible = "jedec,spi-nor"; ++ compatible = "spi-nand"; + reg = <0>; ++ spi-tx-bus-width = <4>; ++ spi-rx-bus-width = <4>; ++ nand-ecc-engine = <&snfi>; ++ partitions { ++ compatible = "fixed-partitions"; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ++ partition@0 { ++ label = "bl2"; ++ reg = <0x0 0x80000>; ++ read-only; ++ }; ++ ++ partition@80000 { ++ label = "fip"; ++ reg = <0x80000 0x200000>; ++ read-only; ++ }; ++ ++ ubi: partition@280000 { ++ label = "ubi"; ++ reg = <0x280000 0x7d80000>; ++ }; ++ }; + }; + }; + diff --git a/lede/target/linux/mediatek/patches-6.1/131-dts-mt7622-add-snand-support.patch b/lede/target/linux/mediatek/patches-6.1/131-dts-mt7622-add-snand-support.patch index 134e5997e2..1a0e3237c8 100644 --- a/lede/target/linux/mediatek/patches-6.1/131-dts-mt7622-add-snand-support.patch +++ b/lede/target/linux/mediatek/patches-6.1/131-dts-mt7622-add-snand-support.patch @@ -1,6 +1,6 @@ --- a/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts +++ b/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts -@@ -539,6 +539,65 @@ +@@ -535,6 +535,65 @@ status = "disabled"; }; diff --git a/lede/target/linux/mediatek/patches-6.1/140-dts-fix-wmac-support-for-mt7622-rfb1.patch b/lede/target/linux/mediatek/patches-6.1/140-dts-fix-wmac-support-for-mt7622-rfb1.patch index 8e6935b434..208046ad16 100644 --- a/lede/target/linux/mediatek/patches-6.1/140-dts-fix-wmac-support-for-mt7622-rfb1.patch +++ b/lede/target/linux/mediatek/patches-6.1/140-dts-fix-wmac-support-for-mt7622-rfb1.patch @@ -1,6 +1,6 @@ --- a/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts +++ b/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts -@@ -580,7 +580,7 @@ +@@ -576,7 +576,7 @@ reg = <0x140000 0x0080000>; }; @@ -9,7 +9,7 @@ label = "Factory"; reg = <0x1c0000 0x0100000>; }; -@@ -641,5 +641,6 @@ +@@ -637,5 +637,6 @@ &wmac { pinctrl-names = "default"; pinctrl-0 = <&wmac_pins>; diff --git a/lede/target/linux/mediatek/patches-6.1/164-dts-mt7623-bpi-r2-rootdisk-for-fitblk.patch b/lede/target/linux/mediatek/patches-6.1/164-dts-mt7623-bpi-r2-rootdisk-for-fitblk.patch new file mode 100644 index 0000000000..f617211c9a --- /dev/null +++ b/lede/target/linux/mediatek/patches-6.1/164-dts-mt7623-bpi-r2-rootdisk-for-fitblk.patch @@ -0,0 +1,55 @@ +--- a/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts ++++ b/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts +@@ -26,7 +26,9 @@ + + chosen { + stdout-path = "serial2:115200n8"; +- bootargs = "earlycon=uart8250,mmio32,0x11004000 console=ttyS2,115200n8 console=tty1"; ++ bootargs = "root=/dev/fit0 rootwait earlycon=uart8250,mmio32,0x11004000 console=ttyS2,115200n8 console=tty1"; ++ rootdisk-emmc = <&emmc_rootdisk>; ++ rootdisk-sd = <&sd_rootdisk>; + }; + + connector { +@@ -315,6 +317,20 @@ + vmmc-supply = <®_3p3v>; + vqmmc-supply = <®_1p8v>; + non-removable; ++ ++ card@0 { ++ compatible = "mmc-card"; ++ reg = <0>; ++ ++ block { ++ compatible = "block-device"; ++ partitions { ++ emmc_rootdisk: block-partition-fit { ++ partno = <3>; ++ }; ++ }; ++ }; ++ }; + }; + + &mmc1 { +@@ -328,6 +344,20 @@ + cd-gpios = <&pio 261 GPIO_ACTIVE_LOW>; + vmmc-supply = <®_3p3v>; + vqmmc-supply = <®_3p3v>; ++ ++ card@0 { ++ compatible = "mmc-card"; ++ reg = <0>; ++ ++ block { ++ compatible = "block-device"; ++ partitions { ++ sd_rootdisk: block-partition-fit { ++ partno = <3>; ++ }; ++ }; ++ }; ++ }; + }; + + &mt6323_leds { diff --git a/lede/target/linux/mediatek/patches-6.1/180-dts-mt7622-bpi-r64-add-mt7531-irq.patch b/lede/target/linux/mediatek/patches-6.1/180-dts-mt7622-bpi-r64-add-mt7531-irq.patch deleted file mode 100644 index 3452b108fe..0000000000 --- a/lede/target/linux/mediatek/patches-6.1/180-dts-mt7622-bpi-r64-add-mt7531-irq.patch +++ /dev/null @@ -1,13 +0,0 @@ ---- a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts -+++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts -@@ -157,6 +157,10 @@ - switch@0 { - compatible = "mediatek,mt7531"; - reg = <0>; -+ interrupt-controller; -+ #interrupt-cells = <1>; -+ interrupt-parent = <&pio>; -+ interrupts = <53 IRQ_TYPE_LEVEL_HIGH>; - reset-gpios = <&pio 54 0>; - - ports { diff --git a/lede/target/linux/mediatek/patches-6.1/180-v6.5-arm64-dts-mt7622-handle-interrupts-from-MT7531-switc.patch b/lede/target/linux/mediatek/patches-6.1/180-v6.5-arm64-dts-mt7622-handle-interrupts-from-MT7531-switc.patch new file mode 100644 index 0000000000..d396d38f20 --- /dev/null +++ b/lede/target/linux/mediatek/patches-6.1/180-v6.5-arm64-dts-mt7622-handle-interrupts-from-MT7531-switc.patch @@ -0,0 +1,32 @@ +From 983f37ee08acb60435744f1b1e2afea2d2a09c48 Mon Sep 17 00:00:00 2001 +From: Daniel Golle +Date: Wed, 19 Apr 2023 20:16:29 +0100 +Subject: [PATCH] arm64: dts: mt7622: handle interrupts from MT7531 switch on + BPI-R64 + +Since commit ba751e28d442 ("net: dsa: mt7530: add interrupt support") +the mt7530 driver can act as an interrupt controller. Wire up irq line +of the MT7531 switch on the BananaPi BPi-R64 board, so the status of +the PHYs of the five 1000Base-T ports doesn't need to be polled any +more. + +Signed-off-by: Daniel Golle +Link: https://lore.kernel.org/r/ZEA-DV_OsmFg5egL@makrotopia.org +Signed-off-by: Matthias Brugger +--- + arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts | 4 ++++ + 1 file changed, 4 insertions(+) + +--- a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts ++++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts +@@ -155,6 +155,10 @@ + switch@0 { + compatible = "mediatek,mt7531"; + reg = <0>; ++ interrupt-controller; ++ #interrupt-cells = <1>; ++ interrupt-parent = <&pio>; ++ interrupts = <53 IRQ_TYPE_LEVEL_HIGH>; + reset-gpios = <&pio 54 0>; + + ports { diff --git a/lede/target/linux/mediatek/patches-6.1/181-mt7622_fix_dts_mt7531_reg.patch b/lede/target/linux/mediatek/patches-6.1/181-mt7622_fix_dts_mt7531_reg.patch new file mode 100644 index 0000000000..3d2c2c1dec --- /dev/null +++ b/lede/target/linux/mediatek/patches-6.1/181-mt7622_fix_dts_mt7531_reg.patch @@ -0,0 +1,28 @@ +--- a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts ++++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts +@@ -152,9 +152,9 @@ + #address-cells = <1>; + #size-cells = <0>; + +- switch@0 { ++ switch@1f { + compatible = "mediatek,mt7531"; +- reg = <0>; ++ reg = <31>; + interrupt-controller; + #interrupt-cells = <1>; + interrupt-parent = <&pio>; +--- a/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts ++++ b/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts +@@ -117,9 +117,9 @@ + #address-cells = <1>; + #size-cells = <0>; + +- switch@0 { ++ switch@1f { + compatible = "mediatek,mt7531"; +- reg = <0>; ++ reg = <31>; + reset-gpios = <&pio 54 0>; + + ports { diff --git a/lede/target/linux/mediatek/patches-6.1/190-arm64-dts-mediatek-mt7622-fix-GICv2-range.patch b/lede/target/linux/mediatek/patches-6.1/190-arm64-dts-mediatek-mt7622-fix-GICv2-range.patch index 9da8ffe325..1e04d23a0e 100644 --- a/lede/target/linux/mediatek/patches-6.1/190-arm64-dts-mediatek-mt7622-fix-GICv2-range.patch +++ b/lede/target/linux/mediatek/patches-6.1/190-arm64-dts-mediatek-mt7622-fix-GICv2-range.patch @@ -95,7 +95,7 @@ Signed-off-by: Daniel Golle --- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi -@@ -344,7 +344,7 @@ +@@ -346,7 +346,7 @@ #interrupt-cells = <3>; interrupt-parent = <&gic>; reg = <0 0x10310000 0 0x1000>, diff --git a/lede/target/linux/mediatek/patches-6.1/196-dts-mt7986a-bpi-r3-use-all-ubi-nand-layout.patch b/lede/target/linux/mediatek/patches-6.1/196-dts-mt7986a-bpi-r3-use-all-ubi-nand-layout.patch new file mode 100644 index 0000000000..38510c0fc7 --- /dev/null +++ b/lede/target/linux/mediatek/patches-6.1/196-dts-mt7986a-bpi-r3-use-all-ubi-nand-layout.patch @@ -0,0 +1,131 @@ +--- a/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-emmc.dtso ++++ b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-emmc.dtso +@@ -23,7 +23,27 @@ + no-sd; + no-sdio; + status = "okay"; ++ ++ card@0 { ++ compatible = "mmc-card"; ++ reg = <0>; ++ ++ block { ++ compatible = "block-device"; ++ partitions { ++ emmc_rootdisk: block-partition-production { ++ partname = "production"; ++ }; ++ }; ++ }; ++ }; + }; + }; +-}; + ++ fragment@1 { ++ target-path = "/chosen"; ++ __overlay__ { ++ rootdisk-emmc = <&emmc_rootdisk>; ++ }; ++ }; ++}; +--- a/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-nand.dtso ++++ b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-nand.dtso +@@ -29,27 +29,30 @@ + + partition@0 { + label = "bl2"; +- reg = <0x0 0x100000>; ++ reg = <0x0 0x200000>; + read-only; + }; + +- partition@100000 { +- label = "reserved"; +- reg = <0x100000 0x280000>; +- }; +- +- partition@380000 { +- label = "fip"; +- reg = <0x380000 0x200000>; +- read-only; +- }; +- +- partition@580000 { ++ partition@200000 { + label = "ubi"; +- reg = <0x580000 0x7a80000>; ++ reg = <0x200000 0x7e00000>; ++ compatible = "linux,ubi"; ++ ++ volumes { ++ nand_rootdisk: ubi-volume-fit { ++ volname = "fit"; ++ }; ++ }; + }; + }; + }; + }; + }; ++ ++ fragment@1 { ++ target-path = "/chosen"; ++ __overlay__ { ++ rootdisk-spim-nand = <&nand_rootdisk>; ++ }; ++ }; + }; +--- a/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-nor.dtso ++++ b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-nor.dtso +@@ -52,7 +52,7 @@ + reg = <0x180000 0xa80000>; + }; + +- partition@c00000 { ++ nor_rootdisk: partition@c00000 { + label = "fit"; + reg = <0xc00000 0x1400000>; + compatible = "denx,fit"; +@@ -61,4 +61,11 @@ + }; + }; + }; ++ ++ fragment@1 { ++ target-path = "/chosen"; ++ __overlay__ { ++ rootdisk-nor = <&nor_rootdisk>; ++ }; ++ }; + }; +--- a/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-sd.dtso ++++ b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-sd.dtso +@@ -17,6 +17,27 @@ + max-frequency = <52000000>; + cap-sd-highspeed; + status = "okay"; ++ ++ card@0 { ++ compatible = "mmc-card"; ++ reg = <0>; ++ ++ block { ++ compatible = "block-device"; ++ partitions { ++ sd_rootdisk: block-partition-production { ++ partname = "production"; ++ }; ++ }; ++ }; ++ }; ++ }; ++ }; ++ ++ fragment@1 { ++ target-path = "/chosen"; ++ __overlay__ { ++ rootdisk-sd = <&sd_rootdisk>; + }; + }; + }; diff --git a/lede/target/linux/mediatek/patches-6.1/219-pinctrl-mediatek-assign-functions-to-configure-pin-b.patch b/lede/target/linux/mediatek/patches-6.1/219-v6.6-pinctrl-mediatek-assign-functions-to-configure-pin-b.patch similarity index 100% rename from lede/target/linux/mediatek/patches-6.1/219-pinctrl-mediatek-assign-functions-to-configure-pin-b.patch rename to lede/target/linux/mediatek/patches-6.1/219-v6.6-pinctrl-mediatek-assign-functions-to-configure-pin-b.patch diff --git a/lede/target/linux/mediatek/patches-6.1/232-clk-mediatek-mt7981-topckgen-flag-SGM_REG_SEL-as-cri.patch b/lede/target/linux/mediatek/patches-6.1/232-clk-mediatek-mt7981-topckgen-flag-SGM_REG_SEL-as-cri.patch new file mode 100644 index 0000000000..8820d57f01 --- /dev/null +++ b/lede/target/linux/mediatek/patches-6.1/232-clk-mediatek-mt7981-topckgen-flag-SGM_REG_SEL-as-cri.patch @@ -0,0 +1,30 @@ +From fc157139e6b7f8dfb6430ac7191ba754027705e8 Mon Sep 17 00:00:00 2001 +From: Daniel Golle +Date: Sun, 18 Feb 2024 01:59:59 +0000 +Subject: [PATCH] clk: mediatek: mt7981-topckgen: flag SGM_REG_SEL as critical + +Without the SGM_REG_SEL clock enabled the system freezes if trying to +access registers used by MT7981 clock drivers itself. +Mark SGM_REG_SEL as critical to make sure it is always enabled to +prevent freezes on boot depending on probe order. + +Fixes: 813c3b53b55ba ("clk: mediatek: add MT7981 clock support") +Signed-off-by: Daniel Golle +--- + drivers/clk/mediatek/clk-mt7981-topckgen.c | 5 +++-- + 1 file changed, 3 insertions(+), 2 deletions(-) + +--- a/drivers/clk/mediatek/clk-mt7981-topckgen.c ++++ b/drivers/clk/mediatek/clk-mt7981-topckgen.c +@@ -359,8 +359,9 @@ static const struct mtk_mux top_muxes[] + MUX_GATE_CLR_SET_UPD(CLK_TOP_SGM_325M_SEL, "sgm_325m_sel", + sgm_325m_parents, 0x050, 0x054, 0x058, 8, 1, 15, + 0x1C0, 21), +- MUX_GATE_CLR_SET_UPD(CLK_TOP_SGM_REG_SEL, "sgm_reg_sel", sgm_reg_parents, +- 0x050, 0x054, 0x058, 16, 1, 23, 0x1C0, 22), ++ MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SGM_REG_SEL, "sgm_reg_sel", sgm_reg_parents, ++ 0x050, 0x054, 0x058, 16, 1, 23, 0x1C0, 22, ++ CLK_IS_CRITICAL | CLK_SET_RATE_PARENT), + MUX_GATE_CLR_SET_UPD(CLK_TOP_EIP97B_SEL, "eip97b_sel", eip97b_parents, + 0x050, 0x054, 0x058, 24, 3, 31, 0x1C0, 23), + /* CLK_CFG_6 */ diff --git a/lede/target/linux/mediatek/patches-6.1/241-clk-mediatek-Add-pcw-chg-shift-control.patch b/lede/target/linux/mediatek/patches-6.1/241-clk-mediatek-Add-pcw-chg-shift-control.patch deleted file mode 100644 index 75ca114a58..0000000000 --- a/lede/target/linux/mediatek/patches-6.1/241-clk-mediatek-Add-pcw-chg-shift-control.patch +++ /dev/null @@ -1,24 +0,0 @@ ---- a/drivers/clk/mediatek/clk-pll.c -+++ b/drivers/clk/mediatek/clk-pll.c -@@ -141,7 +141,10 @@ static void mtk_pll_set_rate_regs(struct - pll->data->pcw_shift); - val |= pcw << pll->data->pcw_shift; - writel(val, pll->pcw_addr); -- chg = readl(pll->pcw_chg_addr) | PCW_CHG_MASK; -+ if (pll->data->pcw_chg_shift) -+ chg = readl(pll->pcw_chg_addr) | BIT(pll->data->pcw_chg_shift); -+ else -+ chg = readl(pll->pcw_chg_addr) | PCW_CHG_MASK; - writel(chg, pll->pcw_chg_addr); - if (pll->tuner_addr) - writel(val + 1, pll->tuner_addr); ---- a/drivers/clk/mediatek/clk-pll.h -+++ b/drivers/clk/mediatek/clk-pll.h -@@ -42,6 +42,7 @@ struct mtk_pll_data { - u32 pcw_reg; - int pcw_shift; - u32 pcw_chg_reg; -+ int pcw_chg_shift; - const struct mtk_pll_div_table *div_table; - const char *parent_name; - u32 en_reg; diff --git a/lede/target/linux/mediatek/patches-6.1/241-v6.3-dt-bindings-clock-Add-compatibles-for-MT7981.patch b/lede/target/linux/mediatek/patches-6.1/241-v6.3-dt-bindings-clock-Add-compatibles-for-MT7981.patch new file mode 100644 index 0000000000..ad4ecdf83f --- /dev/null +++ b/lede/target/linux/mediatek/patches-6.1/241-v6.3-dt-bindings-clock-Add-compatibles-for-MT7981.patch @@ -0,0 +1,75 @@ +From cc4d9e0c77494fcf6bccbc57e23db0007cf681b7 Mon Sep 17 00:00:00 2001 +From: Daniel Golle +Date: Thu, 26 Jan 2023 03:33:46 +0000 +Subject: [PATCH] dt-bindings: clock: Add compatibles for MT7981 + +Add compatible string for MT7981 to existing bindings at + - mediatek,apmixedsys.yaml + - mediatek,topckgen.yaml + - mediatek,ethsys.txt + - mediatek,infracfg.yaml + - mediatek,sgmiisys.txt + +Signed-off-by: Jianhui Zhao +Signed-off-by: Daniel Golle +Link: https://lore.kernel.org/r/cc85ee470c781ff4013f6c21c92c0a21574b12b2.1674703830.git.daniel@makrotopia.org +Signed-off-by: Stephen Boyd +--- + .../devicetree/bindings/arm/mediatek/mediatek,ethsys.txt | 1 + + .../devicetree/bindings/arm/mediatek/mediatek,infracfg.yaml | 1 + + .../devicetree/bindings/arm/mediatek/mediatek,sgmiisys.txt | 2 ++ + .../devicetree/bindings/clock/mediatek,apmixedsys.yaml | 1 + + Documentation/devicetree/bindings/clock/mediatek,topckgen.yaml | 1 + + 5 files changed, 6 insertions(+) + +--- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,ethsys.txt ++++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,ethsys.txt +@@ -10,6 +10,7 @@ Required Properties: + - "mediatek,mt7622-ethsys", "syscon" + - "mediatek,mt7623-ethsys", "mediatek,mt2701-ethsys", "syscon" + - "mediatek,mt7629-ethsys", "syscon" ++ - "mediatek,mt7981-ethsys", "syscon" + - "mediatek,mt7986-ethsys", "syscon" + - #clock-cells: Must be 1 + - #reset-cells: Must be 1 +--- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.yaml ++++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.yaml +@@ -28,6 +28,7 @@ properties: + - mediatek,mt6797-infracfg + - mediatek,mt7622-infracfg + - mediatek,mt7629-infracfg ++ - mediatek,mt7981-infracfg + - mediatek,mt7986-infracfg + - mediatek,mt8135-infracfg + - mediatek,mt8167-infracfg +--- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,sgmiisys.txt ++++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,sgmiisys.txt +@@ -8,6 +8,8 @@ Required Properties: + - compatible: Should be: + - "mediatek,mt7622-sgmiisys", "syscon" + - "mediatek,mt7629-sgmiisys", "syscon" ++ - "mediatek,mt7981-sgmiisys_0", "syscon" ++ - "mediatek,mt7981-sgmiisys_1", "syscon" + - "mediatek,mt7986-sgmiisys_0", "syscon" + - "mediatek,mt7986-sgmiisys_1", "syscon" + - #clock-cells: Must be 1 +--- a/Documentation/devicetree/bindings/clock/mediatek,apmixedsys.yaml ++++ b/Documentation/devicetree/bindings/clock/mediatek,apmixedsys.yaml +@@ -20,6 +20,7 @@ properties: + - enum: + - mediatek,mt6797-apmixedsys + - mediatek,mt7622-apmixedsys ++ - mediatek,mt7981-apmixedsys + - mediatek,mt7986-apmixedsys + - mediatek,mt8135-apmixedsys + - mediatek,mt8173-apmixedsys +--- a/Documentation/devicetree/bindings/clock/mediatek,topckgen.yaml ++++ b/Documentation/devicetree/bindings/clock/mediatek,topckgen.yaml +@@ -35,6 +35,7 @@ properties: + - mediatek,mt6779-topckgen + - mediatek,mt6795-topckgen + - mediatek,mt7629-topckgen ++ - mediatek,mt7981-topckgen + - mediatek,mt7986-topckgen + - mediatek,mt8167-topckgen + - mediatek,mt8183-topckgen diff --git a/lede/target/linux/mediatek/patches-6.1/242-clk-mediatek-add-mt7988-clock-support.patch b/lede/target/linux/mediatek/patches-6.1/242-clk-mediatek-add-mt7988-clock-support.patch deleted file mode 100644 index 3ced012495..0000000000 --- a/lede/target/linux/mediatek/patches-6.1/242-clk-mediatek-add-mt7988-clock-support.patch +++ /dev/null @@ -1,31 +0,0 @@ ---- a/drivers/clk/mediatek/Kconfig -+++ b/drivers/clk/mediatek/Kconfig -@@ -415,6 +415,15 @@ config COMMON_CLK_MT7986_ETHSYS - This driver adds support for clocks for Ethernet and SGMII - required on MediaTek MT7986 SoC. - -+config COMMON_CLK_MT7988 -+ bool "Clock driver for MediaTek MT7988" -+ depends on ARCH_MEDIATEK || COMPILE_TEST -+ select COMMON_CLK_MEDIATEK -+ default ARCH_MEDIATEK -+ help -+ This driver supports MediaTek MT7988 basic clocks and clocks -+ required for various periperals found on MediaTek. -+ - config COMMON_CLK_MT8135 - bool "Clock driver for MediaTek MT8135" - depends on (ARCH_MEDIATEK && ARM) || COMPILE_TEST ---- a/drivers/clk/mediatek/Makefile -+++ b/drivers/clk/mediatek/Makefile -@@ -60,6 +60,10 @@ obj-$(CONFIG_COMMON_CLK_MT7986) += clk-m - obj-$(CONFIG_COMMON_CLK_MT7986) += clk-mt7986-topckgen.o - obj-$(CONFIG_COMMON_CLK_MT7986) += clk-mt7986-infracfg.o - obj-$(CONFIG_COMMON_CLK_MT7986_ETHSYS) += clk-mt7986-eth.o -+obj-$(CONFIG_COMMON_CLK_MT7988) += clk-mt7988-apmixed.o -+obj-$(CONFIG_COMMON_CLK_MT7988) += clk-mt7988-topckgen.o -+obj-$(CONFIG_COMMON_CLK_MT7988) += clk-mt7988-infracfg.o -+obj-$(CONFIG_COMMON_CLK_MT7988) += clk-mt7988-eth.o - obj-$(CONFIG_COMMON_CLK_MT8135) += clk-mt8135.o - obj-$(CONFIG_COMMON_CLK_MT8167) += clk-mt8167.o - obj-$(CONFIG_COMMON_CLK_MT8167_AUDSYS) += clk-mt8167-aud.o diff --git a/lede/target/linux/mediatek/patches-6.1/242-v6.4-dt-bindings-arm-mediatek-sgmiisys-Convert-to-DT-sche.patch b/lede/target/linux/mediatek/patches-6.1/242-v6.4-dt-bindings-arm-mediatek-sgmiisys-Convert-to-DT-sche.patch new file mode 100644 index 0000000000..48d3d4e90c --- /dev/null +++ b/lede/target/linux/mediatek/patches-6.1/242-v6.4-dt-bindings-arm-mediatek-sgmiisys-Convert-to-DT-sche.patch @@ -0,0 +1,107 @@ +From d4f08a703565abf47baa5a77d05365cf4598d55c Mon Sep 17 00:00:00 2001 +From: Daniel Golle +Date: Sun, 19 Mar 2023 12:56:52 +0000 +Subject: [PATCH 1/2] dt-bindings: arm: mediatek: sgmiisys: Convert to DT + schema + +Convert mediatek,sgmiiisys bindings to DT schema format. +Add maintainer Matthias Brugger, no maintainers were listed in the +original documentation. +As this node is also referenced by the Ethernet controller and used +as SGMII PCS add this fact to the description. +Move the file to Documentation/devicetree/bindings/net/pcs/ which seems +more appropriate given that the great majority of registers are related +to SGMII PCS functionality and only one register represents clock bits. + +Reviewed-by: Rob Herring +Signed-off-by: Daniel Golle +Signed-off-by: Jakub Kicinski +--- + .../arm/mediatek/mediatek,sgmiisys.txt | 27 ---------- + .../bindings/net/pcs/mediatek,sgmiisys.yaml | 49 +++++++++++++++++++ + 2 files changed, 49 insertions(+), 27 deletions(-) + delete mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,sgmiisys.txt + create mode 100644 Documentation/devicetree/bindings/net/pcs/mediatek,sgmiisys.yaml + +--- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,sgmiisys.txt ++++ /dev/null +@@ -1,27 +0,0 @@ +-MediaTek SGMIISYS controller +-============================ +- +-The MediaTek SGMIISYS controller provides various clocks to the system. +- +-Required Properties: +- +-- compatible: Should be: +- - "mediatek,mt7622-sgmiisys", "syscon" +- - "mediatek,mt7629-sgmiisys", "syscon" +- - "mediatek,mt7981-sgmiisys_0", "syscon" +- - "mediatek,mt7981-sgmiisys_1", "syscon" +- - "mediatek,mt7986-sgmiisys_0", "syscon" +- - "mediatek,mt7986-sgmiisys_1", "syscon" +-- #clock-cells: Must be 1 +- +-The SGMIISYS controller uses the common clk binding from +-Documentation/devicetree/bindings/clock/clock-bindings.txt +-The available clocks are defined in dt-bindings/clock/mt*-clk.h. +- +-Example: +- +-sgmiisys: sgmiisys@1b128000 { +- compatible = "mediatek,mt7622-sgmiisys", "syscon"; +- reg = <0 0x1b128000 0 0x1000>; +- #clock-cells = <1>; +-}; +--- /dev/null ++++ b/Documentation/devicetree/bindings/net/pcs/mediatek,sgmiisys.yaml +@@ -0,0 +1,49 @@ ++# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) ++%YAML 1.2 ++--- ++$id: http://devicetree.org/schemas/net/pcs/mediatek,sgmiisys.yaml# ++$schema: http://devicetree.org/meta-schemas/core.yaml# ++ ++title: MediaTek SGMIISYS Controller ++ ++maintainers: ++ - Matthias Brugger ++ ++description: ++ The MediaTek SGMIISYS controller provides a SGMII PCS and some clocks ++ to the ethernet subsystem to which it is attached. ++ ++properties: ++ compatible: ++ items: ++ - enum: ++ - mediatek,mt7622-sgmiisys ++ - mediatek,mt7629-sgmiisys ++ - mediatek,mt7986-sgmiisys_0 ++ - mediatek,mt7986-sgmiisys_1 ++ - const: syscon ++ ++ reg: ++ maxItems: 1 ++ ++ '#clock-cells': ++ const: 1 ++ ++required: ++ - compatible ++ - reg ++ - '#clock-cells' ++ ++additionalProperties: false ++ ++examples: ++ - | ++ soc { ++ #address-cells = <2>; ++ #size-cells = <2>; ++ sgmiisys: syscon@1b128000 { ++ compatible = "mediatek,mt7622-sgmiisys", "syscon"; ++ reg = <0 0x1b128000 0 0x1000>; ++ #clock-cells = <1>; ++ }; ++ }; diff --git a/lede/target/linux/mediatek/patches-6.1/243-v6.4-dt-bindings-net-pcs-mediatek-sgmiisys-add-MT7981-SoC.patch b/lede/target/linux/mediatek/patches-6.1/243-v6.4-dt-bindings-net-pcs-mediatek-sgmiisys-add-MT7981-SoC.patch new file mode 100644 index 0000000000..62a64b9dd0 --- /dev/null +++ b/lede/target/linux/mediatek/patches-6.1/243-v6.4-dt-bindings-net-pcs-mediatek-sgmiisys-add-MT7981-SoC.patch @@ -0,0 +1,37 @@ +From 4f7eb19c4f44078100659f6ba073b0cc7191bc91 Mon Sep 17 00:00:00 2001 +From: Daniel Golle +Date: Sun, 19 Mar 2023 12:57:04 +0000 +Subject: [PATCH 2/2] dt-bindings: net: pcs: mediatek,sgmiisys: add MT7981 SoC + +Add mediatek,pnswap boolean property needed on many boards using the +MediaTek MT7981 SoC. + +Reviewed-by: Rob Herring +Signed-off-by: Daniel Golle +Signed-off-by: Jakub Kicinski +--- + .../devicetree/bindings/net/pcs/mediatek,sgmiisys.yaml | 6 ++++++ + 1 file changed, 6 insertions(+) + +--- a/Documentation/devicetree/bindings/net/pcs/mediatek,sgmiisys.yaml ++++ b/Documentation/devicetree/bindings/net/pcs/mediatek,sgmiisys.yaml +@@ -19,6 +19,8 @@ properties: + - enum: + - mediatek,mt7622-sgmiisys + - mediatek,mt7629-sgmiisys ++ - mediatek,mt7981-sgmiisys_0 ++ - mediatek,mt7981-sgmiisys_1 + - mediatek,mt7986-sgmiisys_0 + - mediatek,mt7986-sgmiisys_1 + - const: syscon +@@ -29,6 +31,10 @@ properties: + '#clock-cells': + const: 1 + ++ mediatek,pnswap: ++ description: Invert polarity of the SGMII data lanes ++ type: boolean ++ + required: + - compatible + - reg diff --git a/lede/target/linux/mediatek/patches-6.1/244-v6.8-dt-bindings-arm-mediatek-move-ethsys-controller-conv.patch b/lede/target/linux/mediatek/patches-6.1/244-v6.8-dt-bindings-arm-mediatek-move-ethsys-controller-conv.patch new file mode 100644 index 0000000000..946db82235 --- /dev/null +++ b/lede/target/linux/mediatek/patches-6.1/244-v6.8-dt-bindings-arm-mediatek-move-ethsys-controller-conv.patch @@ -0,0 +1,113 @@ +From 94b0f301f6ee92f79a2fe2c655dfdbdfe2aec536 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= +Date: Sun, 19 Nov 2023 22:24:16 +0100 +Subject: [PATCH] dt-bindings: arm: mediatek: move ethsys controller & convert + to DT schema +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +DT schema helps validating DTS files. Binding was moved to clock/ as +this hardware is a clock provider. Example required a small fix for +"reg" value (1 address cell + 1 size cell). + +Signed-off-by: Rafał Miłecki +Reviewed-by: Rob Herring +Link: https://lore.kernel.org/r/20231119212416.2682-1-zajec5@gmail.com +Signed-off-by: Stephen Boyd +--- + .../bindings/arm/mediatek/mediatek,ethsys.txt | 29 ---------- + .../bindings/clock/mediatek,ethsys.yaml | 54 +++++++++++++++++++ + 2 files changed, 54 insertions(+), 29 deletions(-) + delete mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,ethsys.txt + create mode 100644 Documentation/devicetree/bindings/clock/mediatek,ethsys.yaml + +--- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,ethsys.txt ++++ /dev/null +@@ -1,29 +0,0 @@ +-Mediatek ethsys controller +-============================ +- +-The Mediatek ethsys controller provides various clocks to the system. +- +-Required Properties: +- +-- compatible: Should be: +- - "mediatek,mt2701-ethsys", "syscon" +- - "mediatek,mt7622-ethsys", "syscon" +- - "mediatek,mt7623-ethsys", "mediatek,mt2701-ethsys", "syscon" +- - "mediatek,mt7629-ethsys", "syscon" +- - "mediatek,mt7981-ethsys", "syscon" +- - "mediatek,mt7986-ethsys", "syscon" +-- #clock-cells: Must be 1 +-- #reset-cells: Must be 1 +- +-The ethsys controller uses the common clk binding from +-Documentation/devicetree/bindings/clock/clock-bindings.txt +-The available clocks are defined in dt-bindings/clock/mt*-clk.h. +- +-Example: +- +-ethsys: clock-controller@1b000000 { +- compatible = "mediatek,mt2701-ethsys", "syscon"; +- reg = <0 0x1b000000 0 0x1000>; +- #clock-cells = <1>; +- #reset-cells = <1>; +-}; +--- /dev/null ++++ b/Documentation/devicetree/bindings/clock/mediatek,ethsys.yaml +@@ -0,0 +1,54 @@ ++# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause ++%YAML 1.2 ++--- ++$id: http://devicetree.org/schemas/clock/mediatek,ethsys.yaml# ++$schema: http://devicetree.org/meta-schemas/core.yaml# ++ ++title: Mediatek ethsys controller ++ ++description: ++ The available clocks are defined in dt-bindings/clock/mt*-clk.h. ++ ++maintainers: ++ - James Liao ++ ++properties: ++ compatible: ++ oneOf: ++ - items: ++ - enum: ++ - mediatek,mt2701-ethsys ++ - mediatek,mt7622-ethsys ++ - mediatek,mt7629-ethsys ++ - mediatek,mt7981-ethsys ++ - mediatek,mt7986-ethsys ++ - const: syscon ++ - items: ++ - const: mediatek,mt7623-ethsys ++ - const: mediatek,mt2701-ethsys ++ - const: syscon ++ ++ reg: ++ maxItems: 1 ++ ++ "#clock-cells": ++ const: 1 ++ ++ "#reset-cells": ++ const: 1 ++ ++required: ++ - reg ++ - "#clock-cells" ++ - "#reset-cells" ++ ++additionalProperties: false ++ ++examples: ++ - | ++ clock-controller@1b000000 { ++ compatible = "mediatek,mt2701-ethsys", "syscon"; ++ reg = <0x1b000000 0x1000>; ++ #clock-cells = <1>; ++ #reset-cells = <1>; ++ }; diff --git a/lede/target/linux/mediatek/patches-6.1/245-v6.8-dt-bindings-reset-mediatek-add-MT7988-ethwarp-reset-.patch b/lede/target/linux/mediatek/patches-6.1/245-v6.8-dt-bindings-reset-mediatek-add-MT7988-ethwarp-reset-.patch new file mode 100644 index 0000000000..47f05e93c6 --- /dev/null +++ b/lede/target/linux/mediatek/patches-6.1/245-v6.8-dt-bindings-reset-mediatek-add-MT7988-ethwarp-reset-.patch @@ -0,0 +1,35 @@ +From 5cfa3beb7761cb84be77225902e018d9d3f9b973 Mon Sep 17 00:00:00 2001 +From: Daniel Golle +Date: Sun, 17 Dec 2023 21:49:45 +0000 +Subject: [PATCH 1/4] dt-bindings: reset: mediatek: add MT7988 ethwarp reset + IDs + +Add reset ID for ethwarp subsystem allowing to reset the built-in +Ethernet switch of the MediaTek MT7988 SoC. + +Signed-off-by: Daniel Golle +Reviewed-by: AngeloGioacchino Del Regno +Acked-by: Krzysztof Kozlowski +Link: https://lore.kernel.org/r/0c14bbacf471683af67ffa7572bfa1d5c45a0b5d.1702849494.git.daniel@makrotopia.org +Signed-off-by: Stephen Boyd +--- + include/dt-bindings/reset/mediatek,mt7988-resets.h | 13 +++++++++++++ + 1 file changed, 13 insertions(+) + create mode 100644 include/dt-bindings/reset/mediatek,mt7988-resets.h + +--- /dev/null ++++ b/include/dt-bindings/reset/mediatek,mt7988-resets.h +@@ -0,0 +1,13 @@ ++/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ ++/* ++ * Copyright (c) 2023 Daniel Golle ++ * Author: Daniel Golle ++ */ ++ ++#ifndef _DT_BINDINGS_RESET_CONTROLLER_MT7988 ++#define _DT_BINDINGS_RESET_CONTROLLER_MT7988 ++ ++/* ETHWARP resets */ ++#define MT7988_ETHWARP_RST_SWITCH 0 ++ ++#endif /* _DT_BINDINGS_RESET_CONTROLLER_MT7988 */ diff --git a/lede/target/linux/mediatek/patches-6.1/246-v6.8-dt-bindings-clock-mediatek-add-MT7988-clock-IDs.patch b/lede/target/linux/mediatek/patches-6.1/246-v6.8-dt-bindings-clock-mediatek-add-MT7988-clock-IDs.patch new file mode 100644 index 0000000000..cf5cae6341 --- /dev/null +++ b/lede/target/linux/mediatek/patches-6.1/246-v6.8-dt-bindings-clock-mediatek-add-MT7988-clock-IDs.patch @@ -0,0 +1,302 @@ +From 8187e001de156e99ef95366ffd10d627ed090826 Mon Sep 17 00:00:00 2001 +From: Sam Shih +Date: Sun, 17 Dec 2023 21:49:33 +0000 +Subject: [PATCH] dt-bindings: clock: mediatek: add MT7988 clock IDs + +Add MT7988 clock dt-bindings for topckgen, apmixedsys, infracfg, +ethernet and xfipll subsystem clocks. + +Signed-off-by: Sam Shih +Signed-off-by: Daniel Golle +Acked-by: Krzysztof Kozlowski +Reviewed-by: AngeloGioacchino Del Regno +Link: https://lore.kernel.org/r/27f99db432e9ccc804cc5b6501d7d17d72cae879.1702849494.git.daniel@makrotopia.org +Signed-off-by: Stephen Boyd +--- + .../dt-bindings/clock/mediatek,mt7988-clk.h | 280 ++++++++++++++++++ + 1 file changed, 280 insertions(+) + create mode 100644 include/dt-bindings/clock/mediatek,mt7988-clk.h + +--- /dev/null ++++ b/include/dt-bindings/clock/mediatek,mt7988-clk.h +@@ -0,0 +1,280 @@ ++/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ ++/* ++ * Copyright (c) 2023 MediaTek Inc. ++ * Author: Sam Shih ++ * Author: Xiufeng Li ++ */ ++ ++#ifndef _DT_BINDINGS_CLK_MT7988_H ++#define _DT_BINDINGS_CLK_MT7988_H ++ ++/* APMIXEDSYS */ ++ ++#define CLK_APMIXED_NETSYSPLL 0 ++#define CLK_APMIXED_MPLL 1 ++#define CLK_APMIXED_MMPLL 2 ++#define CLK_APMIXED_APLL2 3 ++#define CLK_APMIXED_NET1PLL 4 ++#define CLK_APMIXED_NET2PLL 5 ++#define CLK_APMIXED_WEDMCUPLL 6 ++#define CLK_APMIXED_SGMPLL 7 ++#define CLK_APMIXED_ARM_B 8 ++#define CLK_APMIXED_CCIPLL2_B 9 ++#define CLK_APMIXED_USXGMIIPLL 10 ++#define CLK_APMIXED_MSDCPLL 11 ++ ++/* TOPCKGEN */ ++ ++#define CLK_TOP_XTAL 0 ++#define CLK_TOP_XTAL_D2 1 ++#define CLK_TOP_RTC_32K 2 ++#define CLK_TOP_RTC_32P7K 3 ++#define CLK_TOP_MPLL_D2 4 ++#define CLK_TOP_MPLL_D3_D2 5 ++#define CLK_TOP_MPLL_D4 6 ++#define CLK_TOP_MPLL_D8 7 ++#define CLK_TOP_MPLL_D8_D2 8 ++#define CLK_TOP_MMPLL_D2 9 ++#define CLK_TOP_MMPLL_D3_D5 10 ++#define CLK_TOP_MMPLL_D4 11 ++#define CLK_TOP_MMPLL_D6_D2 12 ++#define CLK_TOP_MMPLL_D8 13 ++#define CLK_TOP_APLL2_D4 14 ++#define CLK_TOP_NET1PLL_D4 15 ++#define CLK_TOP_NET1PLL_D5 16 ++#define CLK_TOP_NET1PLL_D5_D2 17 ++#define CLK_TOP_NET1PLL_D5_D4 18 ++#define CLK_TOP_NET1PLL_D8 19 ++#define CLK_TOP_NET1PLL_D8_D2 20 ++#define CLK_TOP_NET1PLL_D8_D4 21 ++#define CLK_TOP_NET1PLL_D8_D8 22 ++#define CLK_TOP_NET1PLL_D8_D16 23 ++#define CLK_TOP_NET2PLL_D2 24 ++#define CLK_TOP_NET2PLL_D4 25 ++#define CLK_TOP_NET2PLL_D4_D4 26 ++#define CLK_TOP_NET2PLL_D4_D8 27 ++#define CLK_TOP_NET2PLL_D6 28 ++#define CLK_TOP_NET2PLL_D8 29 ++#define CLK_TOP_NETSYS_SEL 30 ++#define CLK_TOP_NETSYS_500M_SEL 31 ++#define CLK_TOP_NETSYS_2X_SEL 32 ++#define CLK_TOP_NETSYS_GSW_SEL 33 ++#define CLK_TOP_ETH_GMII_SEL 34 ++#define CLK_TOP_NETSYS_MCU_SEL 35 ++#define CLK_TOP_NETSYS_PAO_2X_SEL 36 ++#define CLK_TOP_EIP197_SEL 37 ++#define CLK_TOP_AXI_INFRA_SEL 38 ++#define CLK_TOP_UART_SEL 39 ++#define CLK_TOP_EMMC_250M_SEL 40 ++#define CLK_TOP_EMMC_400M_SEL 41 ++#define CLK_TOP_SPI_SEL 42 ++#define CLK_TOP_SPIM_MST_SEL 43 ++#define CLK_TOP_NFI1X_SEL 44 ++#define CLK_TOP_SPINFI_SEL 45 ++#define CLK_TOP_PWM_SEL 46 ++#define CLK_TOP_I2C_SEL 47 ++#define CLK_TOP_PCIE_MBIST_250M_SEL 48 ++#define CLK_TOP_PEXTP_TL_SEL 49 ++#define CLK_TOP_PEXTP_TL_P1_SEL 50 ++#define CLK_TOP_PEXTP_TL_P2_SEL 51 ++#define CLK_TOP_PEXTP_TL_P3_SEL 52 ++#define CLK_TOP_USB_SYS_SEL 53 ++#define CLK_TOP_USB_SYS_P1_SEL 54 ++#define CLK_TOP_USB_XHCI_SEL 55 ++#define CLK_TOP_USB_XHCI_P1_SEL 56 ++#define CLK_TOP_USB_FRMCNT_SEL 57 ++#define CLK_TOP_USB_FRMCNT_P1_SEL 58 ++#define CLK_TOP_AUD_SEL 59 ++#define CLK_TOP_A1SYS_SEL 60 ++#define CLK_TOP_AUD_L_SEL 61 ++#define CLK_TOP_A_TUNER_SEL 62 ++#define CLK_TOP_SSPXTP_SEL 63 ++#define CLK_TOP_USB_PHY_SEL 64 ++#define CLK_TOP_USXGMII_SBUS_0_SEL 65 ++#define CLK_TOP_USXGMII_SBUS_1_SEL 66 ++#define CLK_TOP_SGM_0_SEL 67 ++#define CLK_TOP_SGM_SBUS_0_SEL 68 ++#define CLK_TOP_SGM_1_SEL 69 ++#define CLK_TOP_SGM_SBUS_1_SEL 70 ++#define CLK_TOP_XFI_PHY_0_XTAL_SEL 71 ++#define CLK_TOP_XFI_PHY_1_XTAL_SEL 72 ++#define CLK_TOP_SYSAXI_SEL 73 ++#define CLK_TOP_SYSAPB_SEL 74 ++#define CLK_TOP_ETH_REFCK_50M_SEL 75 ++#define CLK_TOP_ETH_SYS_200M_SEL 76 ++#define CLK_TOP_ETH_SYS_SEL 77 ++#define CLK_TOP_ETH_XGMII_SEL 78 ++#define CLK_TOP_BUS_TOPS_SEL 79 ++#define CLK_TOP_NPU_TOPS_SEL 80 ++#define CLK_TOP_DRAMC_SEL 81 ++#define CLK_TOP_DRAMC_MD32_SEL 82 ++#define CLK_TOP_INFRA_F26M_SEL 83 ++#define CLK_TOP_PEXTP_P0_SEL 84 ++#define CLK_TOP_PEXTP_P1_SEL 85 ++#define CLK_TOP_PEXTP_P2_SEL 86 ++#define CLK_TOP_PEXTP_P3_SEL 87 ++#define CLK_TOP_DA_XTP_GLB_P0_SEL 88 ++#define CLK_TOP_DA_XTP_GLB_P1_SEL 89 ++#define CLK_TOP_DA_XTP_GLB_P2_SEL 90 ++#define CLK_TOP_DA_XTP_GLB_P3_SEL 91 ++#define CLK_TOP_CKM_SEL 92 ++#define CLK_TOP_DA_SEL 93 ++#define CLK_TOP_PEXTP_SEL 94 ++#define CLK_TOP_TOPS_P2_26M_SEL 95 ++#define CLK_TOP_MCUSYS_BACKUP_625M_SEL 96 ++#define CLK_TOP_NETSYS_SYNC_250M_SEL 97 ++#define CLK_TOP_MACSEC_SEL 98 ++#define CLK_TOP_NETSYS_TOPS_400M_SEL 99 ++#define CLK_TOP_NETSYS_PPEFB_250M_SEL 100 ++#define CLK_TOP_NETSYS_WARP_SEL 101 ++#define CLK_TOP_ETH_MII_SEL 102 ++#define CLK_TOP_NPU_SEL 103 ++#define CLK_TOP_AUD_I2S_M 104 ++ ++/* MCUSYS */ ++ ++#define CLK_MCU_BUS_DIV_SEL 0 ++#define CLK_MCU_ARM_DIV_SEL 1 ++ ++/* INFRACFG_AO */ ++ ++#define CLK_INFRA_MUX_UART0_SEL 0 ++#define CLK_INFRA_MUX_UART1_SEL 1 ++#define CLK_INFRA_MUX_UART2_SEL 2 ++#define CLK_INFRA_MUX_SPI0_SEL 3 ++#define CLK_INFRA_MUX_SPI1_SEL 4 ++#define CLK_INFRA_MUX_SPI2_SEL 5 ++#define CLK_INFRA_PWM_SEL 6 ++#define CLK_INFRA_PWM_CK1_SEL 7 ++#define CLK_INFRA_PWM_CK2_SEL 8 ++#define CLK_INFRA_PWM_CK3_SEL 9 ++#define CLK_INFRA_PWM_CK4_SEL 10 ++#define CLK_INFRA_PWM_CK5_SEL 11 ++#define CLK_INFRA_PWM_CK6_SEL 12 ++#define CLK_INFRA_PWM_CK7_SEL 13 ++#define CLK_INFRA_PWM_CK8_SEL 14 ++#define CLK_INFRA_PCIE_GFMUX_TL_O_P0_SEL 15 ++#define CLK_INFRA_PCIE_GFMUX_TL_O_P1_SEL 16 ++#define CLK_INFRA_PCIE_GFMUX_TL_O_P2_SEL 17 ++#define CLK_INFRA_PCIE_GFMUX_TL_O_P3_SEL 18 ++ ++/* INFRACFG */ ++ ++#define CLK_INFRA_PCIE_PERI_26M_CK_P0 19 ++#define CLK_INFRA_PCIE_PERI_26M_CK_P1 20 ++#define CLK_INFRA_PCIE_PERI_26M_CK_P2 21 ++#define CLK_INFRA_PCIE_PERI_26M_CK_P3 22 ++#define CLK_INFRA_66M_GPT_BCK 23 ++#define CLK_INFRA_66M_PWM_HCK 24 ++#define CLK_INFRA_66M_PWM_BCK 25 ++#define CLK_INFRA_66M_PWM_CK1 26 ++#define CLK_INFRA_66M_PWM_CK2 27 ++#define CLK_INFRA_66M_PWM_CK3 28 ++#define CLK_INFRA_66M_PWM_CK4 29 ++#define CLK_INFRA_66M_PWM_CK5 30 ++#define CLK_INFRA_66M_PWM_CK6 31 ++#define CLK_INFRA_66M_PWM_CK7 32 ++#define CLK_INFRA_66M_PWM_CK8 33 ++#define CLK_INFRA_133M_CQDMA_BCK 34 ++#define CLK_INFRA_66M_AUD_SLV_BCK 35 ++#define CLK_INFRA_AUD_26M 36 ++#define CLK_INFRA_AUD_L 37 ++#define CLK_INFRA_AUD_AUD 38 ++#define CLK_INFRA_AUD_EG2 39 ++#define CLK_INFRA_DRAMC_F26M 40 ++#define CLK_INFRA_133M_DBG_ACKM 41 ++#define CLK_INFRA_66M_AP_DMA_BCK 42 ++#define CLK_INFRA_66M_SEJ_BCK 43 ++#define CLK_INFRA_PRE_CK_SEJ_F13M 44 ++#define CLK_INFRA_26M_THERM_SYSTEM 45 ++#define CLK_INFRA_I2C_BCK 46 ++#define CLK_INFRA_52M_UART0_CK 47 ++#define CLK_INFRA_52M_UART1_CK 48 ++#define CLK_INFRA_52M_UART2_CK 49 ++#define CLK_INFRA_NFI 50 ++#define CLK_INFRA_SPINFI 51 ++#define CLK_INFRA_66M_NFI_HCK 52 ++#define CLK_INFRA_104M_SPI0 53 ++#define CLK_INFRA_104M_SPI1 54 ++#define CLK_INFRA_104M_SPI2_BCK 55 ++#define CLK_INFRA_66M_SPI0_HCK 56 ++#define CLK_INFRA_66M_SPI1_HCK 57 ++#define CLK_INFRA_66M_SPI2_HCK 58 ++#define CLK_INFRA_66M_FLASHIF_AXI 59 ++#define CLK_INFRA_RTC 60 ++#define CLK_INFRA_26M_ADC_BCK 61 ++#define CLK_INFRA_RC_ADC 62 ++#define CLK_INFRA_MSDC400 63 ++#define CLK_INFRA_MSDC2_HCK 64 ++#define CLK_INFRA_133M_MSDC_0_HCK 65 ++#define CLK_INFRA_66M_MSDC_0_HCK 66 ++#define CLK_INFRA_133M_CPUM_BCK 67 ++#define CLK_INFRA_BIST2FPC 68 ++#define CLK_INFRA_I2C_X16W_MCK_CK_P1 69 ++#define CLK_INFRA_I2C_X16W_PCK_CK_P1 70 ++#define CLK_INFRA_133M_USB_HCK 71 ++#define CLK_INFRA_133M_USB_HCK_CK_P1 72 ++#define CLK_INFRA_66M_USB_HCK 73 ++#define CLK_INFRA_66M_USB_HCK_CK_P1 74 ++#define CLK_INFRA_USB_SYS 75 ++#define CLK_INFRA_USB_SYS_CK_P1 76 ++#define CLK_INFRA_USB_REF 77 ++#define CLK_INFRA_USB_CK_P1 78 ++#define CLK_INFRA_USB_FRMCNT 79 ++#define CLK_INFRA_USB_FRMCNT_CK_P1 80 ++#define CLK_INFRA_USB_PIPE 81 ++#define CLK_INFRA_USB_PIPE_CK_P1 82 ++#define CLK_INFRA_USB_UTMI 83 ++#define CLK_INFRA_USB_UTMI_CK_P1 84 ++#define CLK_INFRA_USB_XHCI 85 ++#define CLK_INFRA_USB_XHCI_CK_P1 86 ++#define CLK_INFRA_PCIE_GFMUX_TL_P0 87 ++#define CLK_INFRA_PCIE_GFMUX_TL_P1 88 ++#define CLK_INFRA_PCIE_GFMUX_TL_P2 89 ++#define CLK_INFRA_PCIE_GFMUX_TL_P3 90 ++#define CLK_INFRA_PCIE_PIPE_P0 91 ++#define CLK_INFRA_PCIE_PIPE_P1 92 ++#define CLK_INFRA_PCIE_PIPE_P2 93 ++#define CLK_INFRA_PCIE_PIPE_P3 94 ++#define CLK_INFRA_133M_PCIE_CK_P0 95 ++#define CLK_INFRA_133M_PCIE_CK_P1 96 ++#define CLK_INFRA_133M_PCIE_CK_P2 97 ++#define CLK_INFRA_133M_PCIE_CK_P3 98 ++ ++/* ETHDMA */ ++ ++#define CLK_ETHDMA_XGP1_EN 0 ++#define CLK_ETHDMA_XGP2_EN 1 ++#define CLK_ETHDMA_XGP3_EN 2 ++#define CLK_ETHDMA_FE_EN 3 ++#define CLK_ETHDMA_GP2_EN 4 ++#define CLK_ETHDMA_GP1_EN 5 ++#define CLK_ETHDMA_GP3_EN 6 ++#define CLK_ETHDMA_ESW_EN 7 ++#define CLK_ETHDMA_CRYPT0_EN 8 ++#define CLK_ETHDMA_NR_CLK 9 ++ ++/* SGMIISYS_0 */ ++ ++#define CLK_SGM0_TX_EN 0 ++#define CLK_SGM0_RX_EN 1 ++#define CLK_SGMII0_NR_CLK 2 ++ ++/* SGMIISYS_1 */ ++ ++#define CLK_SGM1_TX_EN 0 ++#define CLK_SGM1_RX_EN 1 ++#define CLK_SGMII1_NR_CLK 2 ++ ++/* ETHWARP */ ++ ++#define CLK_ETHWARP_WOCPU2_EN 0 ++#define CLK_ETHWARP_WOCPU1_EN 1 ++#define CLK_ETHWARP_WOCPU0_EN 2 ++#define CLK_ETHWARP_NR_CLK 3 ++ ++/* XFIPLL */ ++#define CLK_XFIPLL_PLL 0 ++#define CLK_XFIPLL_PLL_EN 1 ++ ++#endif /* _DT_BINDINGS_CLK_MT7988_H */ diff --git a/lede/target/linux/mediatek/patches-6.1/247-v6.8-dt-bindings-clock-mediatek-add-clock-controllers-of-.patch b/lede/target/linux/mediatek/patches-6.1/247-v6.8-dt-bindings-clock-mediatek-add-clock-controllers-of-.patch new file mode 100644 index 0000000000..79088b461b --- /dev/null +++ b/lede/target/linux/mediatek/patches-6.1/247-v6.8-dt-bindings-clock-mediatek-add-clock-controllers-of-.patch @@ -0,0 +1,260 @@ +From afd36e9d91b0a840983b829a9e95407d8151f7e7 Mon Sep 17 00:00:00 2001 +From: Daniel Golle +Date: Sun, 17 Dec 2023 21:49:55 +0000 +Subject: [PATCH 2/4] dt-bindings: clock: mediatek: add clock controllers of + MT7988 + +Add various clock controllers found in the MT7988 SoC to existing +bindings (if applicable) and add files for the new ethwarp, mcusys +and xfi-pll clock controllers not previously present in any SoC. + +Signed-off-by: Daniel Golle +Reviewed-by: AngeloGioacchino Del Regno +Link: https://lore.kernel.org/r/07e76a544ce4392bcb88e34d5480e99bb7994618.1702849494.git.daniel@makrotopia.org +Reviewed-by: Krzysztof Kozlowski +Signed-off-by: Stephen Boyd +--- + .../arm/mediatek/mediatek,infracfg.yaml | 1 + + .../bindings/clock/mediatek,apmixedsys.yaml | 1 + + .../bindings/clock/mediatek,ethsys.yaml | 1 + + .../clock/mediatek,mt7988-ethwarp.yaml | 52 +++++++++++++++ + .../clock/mediatek,mt7988-xfi-pll.yaml | 48 ++++++++++++++ + .../bindings/clock/mediatek,topckgen.yaml | 2 + + .../bindings/net/pcs/mediatek,sgmiisys.yaml | 65 ++++++++++++++++--- + 7 files changed, 161 insertions(+), 9 deletions(-) + create mode 100644 Documentation/devicetree/bindings/clock/mediatek,mt7988-ethwarp.yaml + create mode 100644 Documentation/devicetree/bindings/clock/mediatek,mt7988-xfi-pll.yaml + +--- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.yaml ++++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.yaml +@@ -30,6 +30,7 @@ properties: + - mediatek,mt7629-infracfg + - mediatek,mt7981-infracfg + - mediatek,mt7986-infracfg ++ - mediatek,mt7988-infracfg + - mediatek,mt8135-infracfg + - mediatek,mt8167-infracfg + - mediatek,mt8173-infracfg +--- a/Documentation/devicetree/bindings/clock/mediatek,apmixedsys.yaml ++++ b/Documentation/devicetree/bindings/clock/mediatek,apmixedsys.yaml +@@ -22,6 +22,7 @@ properties: + - mediatek,mt7622-apmixedsys + - mediatek,mt7981-apmixedsys + - mediatek,mt7986-apmixedsys ++ - mediatek,mt7988-apmixedsys + - mediatek,mt8135-apmixedsys + - mediatek,mt8173-apmixedsys + - mediatek,mt8516-apmixedsys +--- a/Documentation/devicetree/bindings/clock/mediatek,ethsys.yaml ++++ b/Documentation/devicetree/bindings/clock/mediatek,ethsys.yaml +@@ -22,6 +22,7 @@ properties: + - mediatek,mt7629-ethsys + - mediatek,mt7981-ethsys + - mediatek,mt7986-ethsys ++ - mediatek,mt7988-ethsys + - const: syscon + - items: + - const: mediatek,mt7623-ethsys +--- /dev/null ++++ b/Documentation/devicetree/bindings/clock/mediatek,mt7988-ethwarp.yaml +@@ -0,0 +1,52 @@ ++# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) ++%YAML 1.2 ++--- ++$id: http://devicetree.org/schemas/clock/mediatek,mt7988-ethwarp.yaml# ++$schema: http://devicetree.org/meta-schemas/core.yaml# ++ ++title: MediaTek MT7988 ethwarp Controller ++ ++maintainers: ++ - Daniel Golle ++ ++description: ++ The Mediatek MT7988 ethwarp controller provides clocks and resets for the ++ Ethernet related subsystems found the MT7988 SoC. ++ The clock values can be found in . ++ ++properties: ++ compatible: ++ items: ++ - const: mediatek,mt7988-ethwarp ++ ++ reg: ++ maxItems: 1 ++ ++ '#clock-cells': ++ const: 1 ++ ++ '#reset-cells': ++ const: 1 ++ ++required: ++ - compatible ++ - reg ++ - '#clock-cells' ++ - '#reset-cells' ++ ++additionalProperties: false ++ ++examples: ++ - | ++ #include ++ soc { ++ #address-cells = <2>; ++ #size-cells = <2>; ++ ++ clock-controller@15031000 { ++ compatible = "mediatek,mt7988-ethwarp"; ++ reg = <0 0x15031000 0 0x1000>; ++ #clock-cells = <1>; ++ #reset-cells = <1>; ++ }; ++ }; +--- /dev/null ++++ b/Documentation/devicetree/bindings/clock/mediatek,mt7988-xfi-pll.yaml +@@ -0,0 +1,48 @@ ++# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) ++%YAML 1.2 ++--- ++$id: http://devicetree.org/schemas/clock/mediatek,mt7988-xfi-pll.yaml# ++$schema: http://devicetree.org/meta-schemas/core.yaml# ++ ++title: MediaTek MT7988 XFI PLL Clock Controller ++ ++maintainers: ++ - Daniel Golle ++ ++description: ++ The MediaTek XFI PLL controller provides the 156.25MHz clock for the ++ Ethernet SerDes PHY from the 40MHz top_xtal clock. ++ ++properties: ++ compatible: ++ const: mediatek,mt7988-xfi-pll ++ ++ reg: ++ maxItems: 1 ++ ++ resets: ++ maxItems: 1 ++ ++ '#clock-cells': ++ const: 1 ++ ++required: ++ - compatible ++ - reg ++ - resets ++ - '#clock-cells' ++ ++additionalProperties: false ++ ++examples: ++ - | ++ soc { ++ #address-cells = <2>; ++ #size-cells = <2>; ++ clock-controller@11f40000 { ++ compatible = "mediatek,mt7988-xfi-pll"; ++ reg = <0 0x11f40000 0 0x1000>; ++ resets = <&watchdog 16>; ++ #clock-cells = <1>; ++ }; ++ }; +--- a/Documentation/devicetree/bindings/clock/mediatek,topckgen.yaml ++++ b/Documentation/devicetree/bindings/clock/mediatek,topckgen.yaml +@@ -37,6 +37,8 @@ properties: + - mediatek,mt7629-topckgen + - mediatek,mt7981-topckgen + - mediatek,mt7986-topckgen ++ - mediatek,mt7988-mcusys ++ - mediatek,mt7988-topckgen + - mediatek,mt8167-topckgen + - mediatek,mt8183-topckgen + - const: syscon +--- a/Documentation/devicetree/bindings/net/pcs/mediatek,sgmiisys.yaml ++++ b/Documentation/devicetree/bindings/net/pcs/mediatek,sgmiisys.yaml +@@ -15,15 +15,22 @@ description: + + properties: + compatible: +- items: +- - enum: +- - mediatek,mt7622-sgmiisys +- - mediatek,mt7629-sgmiisys +- - mediatek,mt7981-sgmiisys_0 +- - mediatek,mt7981-sgmiisys_1 +- - mediatek,mt7986-sgmiisys_0 +- - mediatek,mt7986-sgmiisys_1 +- - const: syscon ++ oneOf: ++ - items: ++ - enum: ++ - mediatek,mt7622-sgmiisys ++ - mediatek,mt7629-sgmiisys ++ - mediatek,mt7981-sgmiisys_0 ++ - mediatek,mt7981-sgmiisys_1 ++ - mediatek,mt7986-sgmiisys_0 ++ - mediatek,mt7986-sgmiisys_1 ++ - const: syscon ++ - items: ++ - enum: ++ - mediatek,mt7988-sgmiisys0 ++ - mediatek,mt7988-sgmiisys1 ++ - const: simple-mfd ++ - const: syscon + + reg: + maxItems: 1 +@@ -35,11 +42,51 @@ properties: + description: Invert polarity of the SGMII data lanes + type: boolean + ++ pcs: ++ type: object ++ description: MediaTek LynxI HSGMII PCS ++ properties: ++ compatible: ++ const: mediatek,mt7988-sgmii ++ ++ clocks: ++ maxItems: 3 ++ ++ clock-names: ++ items: ++ - const: sgmii_sel ++ - const: sgmii_tx ++ - const: sgmii_rx ++ ++ required: ++ - compatible ++ - clocks ++ - clock-names ++ ++ additionalProperties: false ++ + required: + - compatible + - reg + - '#clock-cells' + ++allOf: ++ - if: ++ properties: ++ compatible: ++ contains: ++ enum: ++ - mediatek,mt7988-sgmiisys0 ++ - mediatek,mt7988-sgmiisys1 ++ ++ then: ++ required: ++ - pcs ++ ++ else: ++ properties: ++ pcs: false ++ + additionalProperties: false + + examples: diff --git a/lede/target/linux/mediatek/patches-6.1/248-v6.8-clk-mediatek-add-pcw_chg_bit-control-for-PLLs-of-MT7.patch b/lede/target/linux/mediatek/patches-6.1/248-v6.8-clk-mediatek-add-pcw_chg_bit-control-for-PLLs-of-MT7.patch new file mode 100644 index 0000000000..ca37fc793a --- /dev/null +++ b/lede/target/linux/mediatek/patches-6.1/248-v6.8-clk-mediatek-add-pcw_chg_bit-control-for-PLLs-of-MT7.patch @@ -0,0 +1,50 @@ +From d9bf944beaaad1890ad3fcb755c61e1c7e4c5630 Mon Sep 17 00:00:00 2001 +From: Sam Shih +Date: Sun, 17 Dec 2023 21:50:07 +0000 +Subject: [PATCH 3/4] clk: mediatek: add pcw_chg_bit control for PLLs of MT7988 + +Introduce pcw_chg_bit member to struct mtk_pll_data and use it instead +of the previously hardcoded PCW_CHG_MASK macro if set. +This will needed for clocks on the MT7988 SoC. + +Signed-off-by: Sam Shih +Signed-off-by: Daniel Golle +Reviewed-by: AngeloGioacchino Del Regno +Link: https://lore.kernel.org/r/3b9c65ddb08c8bedf790aacf29871af026b6f0b7.1702849494.git.daniel@makrotopia.org +Signed-off-by: Stephen Boyd +--- + drivers/clk/mediatek/clk-pll.c | 5 +++-- + drivers/clk/mediatek/clk-pll.h | 1 + + 2 files changed, 4 insertions(+), 2 deletions(-) + +--- a/drivers/clk/mediatek/clk-pll.c ++++ b/drivers/clk/mediatek/clk-pll.c +@@ -23,7 +23,7 @@ + #define CON0_BASE_EN BIT(0) + #define CON0_PWR_ON BIT(0) + #define CON0_ISO_EN BIT(1) +-#define PCW_CHG_MASK BIT(31) ++#define PCW_CHG_BIT 31 + + #define AUDPLL_TUNER_EN BIT(31) + +@@ -141,7 +141,8 @@ static void mtk_pll_set_rate_regs(struct + pll->data->pcw_shift); + val |= pcw << pll->data->pcw_shift; + writel(val, pll->pcw_addr); +- chg = readl(pll->pcw_chg_addr) | PCW_CHG_MASK; ++ chg = readl(pll->pcw_chg_addr) | ++ BIT(pll->data->pcw_chg_bit ? : PCW_CHG_BIT); + writel(chg, pll->pcw_chg_addr); + if (pll->tuner_addr) + writel(val + 1, pll->tuner_addr); +--- a/drivers/clk/mediatek/clk-pll.h ++++ b/drivers/clk/mediatek/clk-pll.h +@@ -46,6 +46,7 @@ struct mtk_pll_data { + const char *parent_name; + u32 en_reg; + u8 pll_en_bit; /* Assume 0, indicates BIT(0) by default */ ++ u8 pcw_chg_bit; + }; + + int mtk_clk_register_plls(struct device_node *node, diff --git a/lede/target/linux/mediatek/patches-6.1/249-v6.8-clk-mediatek-add-drivers-for-MT7988-SoC.patch b/lede/target/linux/mediatek/patches-6.1/249-v6.8-clk-mediatek-add-drivers-for-MT7988-SoC.patch new file mode 100644 index 0000000000..61664b934c --- /dev/null +++ b/lede/target/linux/mediatek/patches-6.1/249-v6.8-clk-mediatek-add-drivers-for-MT7988-SoC.patch @@ -0,0 +1,1026 @@ +From 4b4719437d85f0173d344f2c76fa1a5b7f7d184b Mon Sep 17 00:00:00 2001 +From: Sam Shih +Date: Sun, 17 Dec 2023 21:50:15 +0000 +Subject: [PATCH 4/4] clk: mediatek: add drivers for MT7988 SoC + +Add APMIXED, ETH, INFRACFG and TOPCKGEN clock drivers which are +typical MediaTek designs. + +Also add driver for XFIPLL clock generating the 156.25MHz clock for +the XFI SerDes. It needs an undocumented software workaround and has +an unknown internal design. + +Signed-off-by: Sam Shih +Signed-off-by: Daniel Golle +Reviewed-by: AngeloGioacchino Del Regno +Link: https://lore.kernel.org/r/c7574d808e2da1a530182f0fd790c1337c336e1b.1702849494.git.daniel@makrotopia.org +[sboyd@kernel.org: Add module license to infracfg file] +Signed-off-by: Stephen Boyd +--- + drivers/clk/mediatek/Kconfig | 9 + + drivers/clk/mediatek/Makefile | 5 + + drivers/clk/mediatek/clk-mt7988-apmixed.c | 114 ++++++++ + drivers/clk/mediatek/clk-mt7988-eth.c | 150 ++++++++++ + drivers/clk/mediatek/clk-mt7988-infracfg.c | 275 +++++++++++++++++ + drivers/clk/mediatek/clk-mt7988-topckgen.c | 325 +++++++++++++++++++++ + drivers/clk/mediatek/clk-mt7988-xfipll.c | 82 ++++++ + 7 files changed, 960 insertions(+) + create mode 100644 drivers/clk/mediatek/clk-mt7988-apmixed.c + create mode 100644 drivers/clk/mediatek/clk-mt7988-eth.c + create mode 100644 drivers/clk/mediatek/clk-mt7988-infracfg.c + create mode 100644 drivers/clk/mediatek/clk-mt7988-topckgen.c + create mode 100644 drivers/clk/mediatek/clk-mt7988-xfipll.c + +--- a/drivers/clk/mediatek/Kconfig ++++ b/drivers/clk/mediatek/Kconfig +@@ -415,6 +415,15 @@ config COMMON_CLK_MT7986_ETHSYS + This driver adds support for clocks for Ethernet and SGMII + required on MediaTek MT7986 SoC. + ++config COMMON_CLK_MT7988 ++ tristate "Clock driver for MediaTek MT7988" ++ depends on ARCH_MEDIATEK || COMPILE_TEST ++ select COMMON_CLK_MEDIATEK ++ default ARCH_MEDIATEK ++ help ++ This driver supports MediaTek MT7988 basic clocks and clocks ++ required for various periperals found on this SoC. ++ + config COMMON_CLK_MT8135 + bool "Clock driver for MediaTek MT8135" + depends on (ARCH_MEDIATEK && ARM) || COMPILE_TEST +--- a/drivers/clk/mediatek/Makefile ++++ b/drivers/clk/mediatek/Makefile +@@ -60,6 +60,11 @@ obj-$(CONFIG_COMMON_CLK_MT7986) += clk-m + obj-$(CONFIG_COMMON_CLK_MT7986) += clk-mt7986-topckgen.o + obj-$(CONFIG_COMMON_CLK_MT7986) += clk-mt7986-infracfg.o + obj-$(CONFIG_COMMON_CLK_MT7986_ETHSYS) += clk-mt7986-eth.o ++obj-$(CONFIG_COMMON_CLK_MT7988) += clk-mt7988-apmixed.o ++obj-$(CONFIG_COMMON_CLK_MT7988) += clk-mt7988-topckgen.o ++obj-$(CONFIG_COMMON_CLK_MT7988) += clk-mt7988-infracfg.o ++obj-$(CONFIG_COMMON_CLK_MT7988) += clk-mt7988-eth.o ++obj-$(CONFIG_COMMON_CLK_MT7988) += clk-mt7988-xfipll.o + obj-$(CONFIG_COMMON_CLK_MT8135) += clk-mt8135.o + obj-$(CONFIG_COMMON_CLK_MT8167) += clk-mt8167.o + obj-$(CONFIG_COMMON_CLK_MT8167_AUDSYS) += clk-mt8167-aud.o +--- /dev/null ++++ b/drivers/clk/mediatek/clk-mt7988-apmixed.c +@@ -0,0 +1,114 @@ ++// SPDX-License-Identifier: GPL-2.0 ++/* ++ * Copyright (c) 2023 MediaTek Inc. ++ * Author: Sam Shih ++ * Author: Xiufeng Li ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include "clk-mtk.h" ++#include "clk-gate.h" ++#include "clk-mux.h" ++#include "clk-pll.h" ++#include ++ ++#define MT7988_PLL_FMAX (2500UL * MHZ) ++#define MT7988_PCW_CHG_BIT 2 ++ ++#define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _rst_bar_mask, _pcwbits, _pd_reg, \ ++ _pd_shift, _tuner_reg, _tuner_en_reg, _tuner_en_bit, _pcw_reg, _pcw_shift, \ ++ _pcw_chg_reg) \ ++ { \ ++ .id = _id, \ ++ .name = _name, \ ++ .reg = _reg, \ ++ .pwr_reg = _pwr_reg, \ ++ .en_mask = _en_mask, \ ++ .flags = _flags, \ ++ .rst_bar_mask = BIT(_rst_bar_mask), \ ++ .fmax = MT7988_PLL_FMAX, \ ++ .pcwbits = _pcwbits, \ ++ .pd_reg = _pd_reg, \ ++ .pd_shift = _pd_shift, \ ++ .tuner_reg = _tuner_reg, \ ++ .tuner_en_reg = _tuner_en_reg, \ ++ .tuner_en_bit = _tuner_en_bit, \ ++ .pcw_reg = _pcw_reg, \ ++ .pcw_shift = _pcw_shift, \ ++ .pcw_chg_reg = _pcw_chg_reg, \ ++ .pcw_chg_bit = MT7988_PCW_CHG_BIT, \ ++ .parent_name = "clkxtal", \ ++ } ++ ++static const struct mtk_pll_data plls[] = { ++ PLL(CLK_APMIXED_NETSYSPLL, "netsyspll", 0x0104, 0x0110, 0x00000001, 0, 0, 32, 0x0104, 4, 0, ++ 0, 0, 0x0108, 0, 0x0104), ++ PLL(CLK_APMIXED_MPLL, "mpll", 0x0114, 0x0120, 0xff000001, HAVE_RST_BAR, 23, 32, 0x0114, 4, ++ 0, 0, 0, 0x0118, 0, 0x0114), ++ PLL(CLK_APMIXED_MMPLL, "mmpll", 0x0124, 0x0130, 0xff000001, HAVE_RST_BAR, 23, 32, 0x0124, 4, ++ 0, 0, 0, 0x0128, 0, 0x0124), ++ PLL(CLK_APMIXED_APLL2, "apll2", 0x0134, 0x0140, 0x00000001, 0, 0, 32, 0x0134, 4, 0x0704, ++ 0x0700, 1, 0x0138, 0, 0x0134), ++ PLL(CLK_APMIXED_NET1PLL, "net1pll", 0x0144, 0x0150, 0xff000001, HAVE_RST_BAR, 23, 32, ++ 0x0144, 4, 0, 0, 0, 0x0148, 0, 0x0144), ++ PLL(CLK_APMIXED_NET2PLL, "net2pll", 0x0154, 0x0160, 0xff000001, (HAVE_RST_BAR | PLL_AO), 23, ++ 32, 0x0154, 4, 0, 0, 0, 0x0158, 0, 0x0154), ++ PLL(CLK_APMIXED_WEDMCUPLL, "wedmcupll", 0x0164, 0x0170, 0x00000001, 0, 0, 32, 0x0164, 4, 0, ++ 0, 0, 0x0168, 0, 0x0164), ++ PLL(CLK_APMIXED_SGMPLL, "sgmpll", 0x0174, 0x0180, 0x00000001, 0, 0, 32, 0x0174, 4, 0, 0, 0, ++ 0x0178, 0, 0x0174), ++ PLL(CLK_APMIXED_ARM_B, "arm_b", 0x0204, 0x0210, 0xff000001, (HAVE_RST_BAR | PLL_AO), 23, 32, ++ 0x0204, 4, 0, 0, 0, 0x0208, 0, 0x0204), ++ PLL(CLK_APMIXED_CCIPLL2_B, "ccipll2_b", 0x0214, 0x0220, 0xff000001, HAVE_RST_BAR, 23, 32, ++ 0x0214, 4, 0, 0, 0, 0x0218, 0, 0x0214), ++ PLL(CLK_APMIXED_USXGMIIPLL, "usxgmiipll", 0x0304, 0x0310, 0xff000001, HAVE_RST_BAR, 23, 32, ++ 0x0304, 4, 0, 0, 0, 0x0308, 0, 0x0304), ++ PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x0314, 0x0320, 0x00000001, 0, 0, 32, 0x0314, 4, 0, 0, ++ 0, 0x0318, 0, 0x0314), ++}; ++ ++static const struct of_device_id of_match_clk_mt7988_apmixed[] = { ++ { .compatible = "mediatek,mt7988-apmixedsys" }, ++ { /* sentinel */ } ++}; ++ ++static int clk_mt7988_apmixed_probe(struct platform_device *pdev) ++{ ++ struct clk_hw_onecell_data *clk_data; ++ struct device_node *node = pdev->dev.of_node; ++ int r; ++ ++ clk_data = mtk_alloc_clk_data(ARRAY_SIZE(plls)); ++ if (!clk_data) ++ return -ENOMEM; ++ ++ r = mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data); ++ if (r) ++ goto free_apmixed_data; ++ ++ r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); ++ if (r) ++ goto unregister_plls; ++ ++ return r; ++ ++unregister_plls: ++ mtk_clk_unregister_plls(plls, ARRAY_SIZE(plls), clk_data); ++free_apmixed_data: ++ mtk_free_clk_data(clk_data); ++ return r; ++} ++ ++static struct platform_driver clk_mt7988_apmixed_drv = { ++ .probe = clk_mt7988_apmixed_probe, ++ .driver = { ++ .name = "clk-mt7988-apmixed", ++ .of_match_table = of_match_clk_mt7988_apmixed, ++ }, ++}; ++builtin_platform_driver(clk_mt7988_apmixed_drv); ++MODULE_LICENSE("GPL"); +--- /dev/null ++++ b/drivers/clk/mediatek/clk-mt7988-eth.c +@@ -0,0 +1,150 @@ ++// SPDX-License-Identifier: GPL-2.0 ++/* ++ * Copyright (c) 2023 MediaTek Inc. ++ * Author: Sam Shih ++ * Author: Xiufeng Li ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include "clk-mtk.h" ++#include "clk-gate.h" ++#include "reset.h" ++#include ++#include ++ ++static const struct mtk_gate_regs ethdma_cg_regs = { ++ .set_ofs = 0x30, ++ .clr_ofs = 0x30, ++ .sta_ofs = 0x30, ++}; ++ ++#define GATE_ETHDMA(_id, _name, _parent, _shift) \ ++ { \ ++ .id = _id, \ ++ .name = _name, \ ++ .parent_name = _parent, \ ++ .regs = ðdma_cg_regs, \ ++ .shift = _shift, \ ++ .ops = &mtk_clk_gate_ops_no_setclr_inv, \ ++ } ++ ++static const struct mtk_gate ethdma_clks[] = { ++ GATE_ETHDMA(CLK_ETHDMA_XGP1_EN, "ethdma_xgp1_en", "top_xtal", 0), ++ GATE_ETHDMA(CLK_ETHDMA_XGP2_EN, "ethdma_xgp2_en", "top_xtal", 1), ++ GATE_ETHDMA(CLK_ETHDMA_XGP3_EN, "ethdma_xgp3_en", "top_xtal", 2), ++ GATE_ETHDMA(CLK_ETHDMA_FE_EN, "ethdma_fe_en", "netsys_2x_sel", 6), ++ GATE_ETHDMA(CLK_ETHDMA_GP2_EN, "ethdma_gp2_en", "top_xtal", 7), ++ GATE_ETHDMA(CLK_ETHDMA_GP1_EN, "ethdma_gp1_en", "top_xtal", 8), ++ GATE_ETHDMA(CLK_ETHDMA_GP3_EN, "ethdma_gp3_en", "top_xtal", 10), ++ GATE_ETHDMA(CLK_ETHDMA_ESW_EN, "ethdma_esw_en", "netsys_gsw_sel", 16), ++ GATE_ETHDMA(CLK_ETHDMA_CRYPT0_EN, "ethdma_crypt0_en", "eip197_sel", 29), ++}; ++ ++static const struct mtk_clk_desc ethdma_desc = { ++ .clks = ethdma_clks, ++ .num_clks = ARRAY_SIZE(ethdma_clks), ++}; ++ ++static const struct mtk_gate_regs sgmii_cg_regs = { ++ .set_ofs = 0xe4, ++ .clr_ofs = 0xe4, ++ .sta_ofs = 0xe4, ++}; ++ ++#define GATE_SGMII(_id, _name, _parent, _shift) \ ++ { \ ++ .id = _id, \ ++ .name = _name, \ ++ .parent_name = _parent, \ ++ .regs = &sgmii_cg_regs, \ ++ .shift = _shift, \ ++ .ops = &mtk_clk_gate_ops_no_setclr_inv, \ ++ } ++ ++static const struct mtk_gate sgmii0_clks[] = { ++ GATE_SGMII(CLK_SGM0_TX_EN, "sgm0_tx_en", "top_xtal", 2), ++ GATE_SGMII(CLK_SGM0_RX_EN, "sgm0_rx_en", "top_xtal", 3), ++}; ++ ++static const struct mtk_clk_desc sgmii0_desc = { ++ .clks = sgmii0_clks, ++ .num_clks = ARRAY_SIZE(sgmii0_clks), ++}; ++ ++static const struct mtk_gate sgmii1_clks[] = { ++ GATE_SGMII(CLK_SGM1_TX_EN, "sgm1_tx_en", "top_xtal", 2), ++ GATE_SGMII(CLK_SGM1_RX_EN, "sgm1_rx_en", "top_xtal", 3), ++}; ++ ++static const struct mtk_clk_desc sgmii1_desc = { ++ .clks = sgmii1_clks, ++ .num_clks = ARRAY_SIZE(sgmii1_clks), ++}; ++ ++static const struct mtk_gate_regs ethwarp_cg_regs = { ++ .set_ofs = 0x14, ++ .clr_ofs = 0x14, ++ .sta_ofs = 0x14, ++}; ++ ++#define GATE_ETHWARP(_id, _name, _parent, _shift) \ ++ { \ ++ .id = _id, \ ++ .name = _name, \ ++ .parent_name = _parent, \ ++ .regs = ðwarp_cg_regs, \ ++ .shift = _shift, \ ++ .ops = &mtk_clk_gate_ops_no_setclr_inv, \ ++ } ++ ++static const struct mtk_gate ethwarp_clks[] = { ++ GATE_ETHWARP(CLK_ETHWARP_WOCPU2_EN, "ethwarp_wocpu2_en", "netsys_mcu_sel", 13), ++ GATE_ETHWARP(CLK_ETHWARP_WOCPU1_EN, "ethwarp_wocpu1_en", "netsys_mcu_sel", 14), ++ GATE_ETHWARP(CLK_ETHWARP_WOCPU0_EN, "ethwarp_wocpu0_en", "netsys_mcu_sel", 15), ++}; ++ ++static u16 ethwarp_rst_ofs[] = { 0x8 }; ++ ++static u16 ethwarp_idx_map[] = { ++ [MT7988_ETHWARP_RST_SWITCH] = 9, ++}; ++ ++static const struct mtk_clk_rst_desc ethwarp_rst_desc = { ++ .version = MTK_RST_SIMPLE, ++ .rst_bank_ofs = ethwarp_rst_ofs, ++ .rst_bank_nr = ARRAY_SIZE(ethwarp_rst_ofs), ++ .rst_idx_map = ethwarp_idx_map, ++ .rst_idx_map_nr = ARRAY_SIZE(ethwarp_idx_map), ++}; ++ ++static const struct mtk_clk_desc ethwarp_desc = { ++ .clks = ethwarp_clks, ++ .num_clks = ARRAY_SIZE(ethwarp_clks), ++ .rst_desc = ðwarp_rst_desc, ++}; ++ ++static const struct of_device_id of_match_clk_mt7988_eth[] = { ++ { .compatible = "mediatek,mt7988-ethsys", .data = ðdma_desc }, ++ { .compatible = "mediatek,mt7988-sgmiisys0", .data = &sgmii0_desc }, ++ { .compatible = "mediatek,mt7988-sgmiisys1", .data = &sgmii1_desc }, ++ { .compatible = "mediatek,mt7988-ethwarp", .data = ðwarp_desc }, ++ { /* sentinel */ } ++}; ++MODULE_DEVICE_TABLE(of, of_match_clk_mt7988_eth); ++ ++static struct platform_driver clk_mt7988_eth_drv = { ++ .driver = { ++ .name = "clk-mt7988-eth", ++ .of_match_table = of_match_clk_mt7988_eth, ++ }, ++ .probe = mtk_clk_simple_probe, ++ .remove = mtk_clk_simple_remove, ++}; ++module_platform_driver(clk_mt7988_eth_drv); ++ ++MODULE_DESCRIPTION("MediaTek MT7988 Ethernet clocks driver"); ++MODULE_LICENSE("GPL"); +--- /dev/null ++++ b/drivers/clk/mediatek/clk-mt7988-infracfg.c +@@ -0,0 +1,275 @@ ++// SPDX-License-Identifier: GPL-2.0 ++/* ++ * Copyright (c) 2023 MediaTek Inc. ++ * Author: Sam Shih ++ * Author: Xiufeng Li ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include "clk-mtk.h" ++#include "clk-gate.h" ++#include "clk-mux.h" ++#include ++ ++static DEFINE_SPINLOCK(mt7988_clk_lock); ++ ++static const char *const infra_mux_uart0_parents[] __initconst = { "csw_infra_f26m_sel", ++ "uart_sel" }; ++ ++static const char *const infra_mux_uart1_parents[] __initconst = { "csw_infra_f26m_sel", ++ "uart_sel" }; ++ ++static const char *const infra_mux_uart2_parents[] __initconst = { "csw_infra_f26m_sel", ++ "uart_sel" }; ++ ++static const char *const infra_mux_spi0_parents[] __initconst = { "i2c_sel", "spi_sel" }; ++ ++static const char *const infra_mux_spi1_parents[] __initconst = { "i2c_sel", "spim_mst_sel" }; ++ ++static const char *const infra_pwm_bck_parents[] __initconst = { "top_rtc_32p7k", ++ "csw_infra_f26m_sel", "sysaxi_sel", ++ "pwm_sel" }; ++ ++static const char *const infra_pcie_gfmux_tl_ck_o_p0_parents[] __initconst = { ++ "top_rtc_32p7k", "csw_infra_f26m_sel", "csw_infra_f26m_sel", "pextp_tl_sel" ++}; ++ ++static const char *const infra_pcie_gfmux_tl_ck_o_p1_parents[] __initconst = { ++ "top_rtc_32p7k", "csw_infra_f26m_sel", "csw_infra_f26m_sel", "pextp_tl_p1_sel" ++}; ++ ++static const char *const infra_pcie_gfmux_tl_ck_o_p2_parents[] __initconst = { ++ "top_rtc_32p7k", "csw_infra_f26m_sel", "csw_infra_f26m_sel", "pextp_tl_p2_sel" ++}; ++ ++static const char *const infra_pcie_gfmux_tl_ck_o_p3_parents[] __initconst = { ++ "top_rtc_32p7k", "csw_infra_f26m_sel", "csw_infra_f26m_sel", "pextp_tl_p3_sel" ++}; ++ ++static const struct mtk_mux infra_muxes[] = { ++ /* MODULE_CLK_SEL_0 */ ++ MUX_GATE_CLR_SET_UPD(CLK_INFRA_MUX_UART0_SEL, "infra_mux_uart0_sel", ++ infra_mux_uart0_parents, 0x0018, 0x0010, 0x0014, 0, 1, -1, -1, -1), ++ MUX_GATE_CLR_SET_UPD(CLK_INFRA_MUX_UART1_SEL, "infra_mux_uart1_sel", ++ infra_mux_uart1_parents, 0x0018, 0x0010, 0x0014, 1, 1, -1, -1, -1), ++ MUX_GATE_CLR_SET_UPD(CLK_INFRA_MUX_UART2_SEL, "infra_mux_uart2_sel", ++ infra_mux_uart2_parents, 0x0018, 0x0010, 0x0014, 2, 1, -1, -1, -1), ++ MUX_GATE_CLR_SET_UPD(CLK_INFRA_MUX_SPI0_SEL, "infra_mux_spi0_sel", infra_mux_spi0_parents, ++ 0x0018, 0x0010, 0x0014, 4, 1, -1, -1, -1), ++ MUX_GATE_CLR_SET_UPD(CLK_INFRA_MUX_SPI1_SEL, "infra_mux_spi1_sel", infra_mux_spi1_parents, ++ 0x0018, 0x0010, 0x0014, 5, 1, -1, -1, -1), ++ MUX_GATE_CLR_SET_UPD(CLK_INFRA_MUX_SPI2_SEL, "infra_mux_spi2_sel", infra_mux_spi0_parents, ++ 0x0018, 0x0010, 0x0014, 6, 1, -1, -1, -1), ++ MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM_SEL, "infra_pwm_sel", infra_pwm_bck_parents, 0x0018, ++ 0x0010, 0x0014, 14, 2, -1, -1, -1), ++ MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM_CK1_SEL, "infra_pwm_ck1_sel", infra_pwm_bck_parents, ++ 0x0018, 0x0010, 0x0014, 16, 2, -1, -1, -1), ++ MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM_CK2_SEL, "infra_pwm_ck2_sel", infra_pwm_bck_parents, ++ 0x0018, 0x0010, 0x0014, 18, 2, -1, -1, -1), ++ MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM_CK3_SEL, "infra_pwm_ck3_sel", infra_pwm_bck_parents, ++ 0x0018, 0x0010, 0x0014, 20, 2, -1, -1, -1), ++ MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM_CK4_SEL, "infra_pwm_ck4_sel", infra_pwm_bck_parents, ++ 0x0018, 0x0010, 0x0014, 22, 2, -1, -1, -1), ++ MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM_CK5_SEL, "infra_pwm_ck5_sel", infra_pwm_bck_parents, ++ 0x0018, 0x0010, 0x0014, 24, 2, -1, -1, -1), ++ MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM_CK6_SEL, "infra_pwm_ck6_sel", infra_pwm_bck_parents, ++ 0x0018, 0x0010, 0x0014, 26, 2, -1, -1, -1), ++ MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM_CK7_SEL, "infra_pwm_ck7_sel", infra_pwm_bck_parents, ++ 0x0018, 0x0010, 0x0014, 28, 2, -1, -1, -1), ++ MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM_CK8_SEL, "infra_pwm_ck8_sel", infra_pwm_bck_parents, ++ 0x0018, 0x0010, 0x0014, 30, 2, -1, -1, -1), ++ /* MODULE_CLK_SEL_1 */ ++ MUX_GATE_CLR_SET_UPD(CLK_INFRA_PCIE_GFMUX_TL_O_P0_SEL, "infra_pcie_gfmux_tl_o_p0_sel", ++ infra_pcie_gfmux_tl_ck_o_p0_parents, 0x0028, 0x0020, 0x0024, 0, 2, -1, ++ -1, -1), ++ MUX_GATE_CLR_SET_UPD(CLK_INFRA_PCIE_GFMUX_TL_O_P1_SEL, "infra_pcie_gfmux_tl_o_p1_sel", ++ infra_pcie_gfmux_tl_ck_o_p1_parents, 0x0028, 0x0020, 0x0024, 2, 2, -1, ++ -1, -1), ++ MUX_GATE_CLR_SET_UPD(CLK_INFRA_PCIE_GFMUX_TL_O_P2_SEL, "infra_pcie_gfmux_tl_o_p2_sel", ++ infra_pcie_gfmux_tl_ck_o_p2_parents, 0x0028, 0x0020, 0x0024, 4, 2, -1, ++ -1, -1), ++ MUX_GATE_CLR_SET_UPD(CLK_INFRA_PCIE_GFMUX_TL_O_P3_SEL, "infra_pcie_gfmux_tl_o_p3_sel", ++ infra_pcie_gfmux_tl_ck_o_p3_parents, 0x0028, 0x0020, 0x0024, 6, 2, -1, ++ -1, -1), ++}; ++ ++static const struct mtk_gate_regs infra0_cg_regs = { ++ .set_ofs = 0x10, ++ .clr_ofs = 0x14, ++ .sta_ofs = 0x18, ++}; ++ ++static const struct mtk_gate_regs infra1_cg_regs = { ++ .set_ofs = 0x40, ++ .clr_ofs = 0x44, ++ .sta_ofs = 0x48, ++}; ++ ++static const struct mtk_gate_regs infra2_cg_regs = { ++ .set_ofs = 0x50, ++ .clr_ofs = 0x54, ++ .sta_ofs = 0x58, ++}; ++ ++static const struct mtk_gate_regs infra3_cg_regs = { ++ .set_ofs = 0x60, ++ .clr_ofs = 0x64, ++ .sta_ofs = 0x68, ++}; ++ ++#define GATE_INFRA0_FLAGS(_id, _name, _parent, _shift, _flags) \ ++ GATE_MTK_FLAGS(_id, _name, _parent, &infra0_cg_regs, _shift, &mtk_clk_gate_ops_setclr, \ ++ _flags) ++ ++#define GATE_INFRA1_FLAGS(_id, _name, _parent, _shift, _flags) \ ++ GATE_MTK_FLAGS(_id, _name, _parent, &infra1_cg_regs, _shift, &mtk_clk_gate_ops_setclr, \ ++ _flags) ++ ++#define GATE_INFRA2_FLAGS(_id, _name, _parent, _shift, _flags) \ ++ GATE_MTK_FLAGS(_id, _name, _parent, &infra2_cg_regs, _shift, &mtk_clk_gate_ops_setclr, \ ++ _flags) ++ ++#define GATE_INFRA3_FLAGS(_id, _name, _parent, _shift, _flags) \ ++ GATE_MTK_FLAGS(_id, _name, _parent, &infra3_cg_regs, _shift, &mtk_clk_gate_ops_setclr, \ ++ _flags) ++ ++#define GATE_INFRA0(_id, _name, _parent, _shift) GATE_INFRA0_FLAGS(_id, _name, _parent, _shift, 0) ++ ++#define GATE_INFRA1(_id, _name, _parent, _shift) GATE_INFRA1_FLAGS(_id, _name, _parent, _shift, 0) ++ ++#define GATE_INFRA2(_id, _name, _parent, _shift) GATE_INFRA2_FLAGS(_id, _name, _parent, _shift, 0) ++ ++#define GATE_INFRA3(_id, _name, _parent, _shift) GATE_INFRA3_FLAGS(_id, _name, _parent, _shift, 0) ++ ++static const struct mtk_gate infra_clks[] = { ++ /* INFRA0 */ ++ GATE_INFRA0(CLK_INFRA_PCIE_PERI_26M_CK_P0, "infra_pcie_peri_ck_26m_ck_p0", ++ "csw_infra_f26m_sel", 7), ++ GATE_INFRA0(CLK_INFRA_PCIE_PERI_26M_CK_P1, "infra_pcie_peri_ck_26m_ck_p1", ++ "csw_infra_f26m_sel", 8), ++ GATE_INFRA0(CLK_INFRA_PCIE_PERI_26M_CK_P2, "infra_pcie_peri_ck_26m_ck_p2", ++ "csw_infra_f26m_sel", 9), ++ GATE_INFRA0(CLK_INFRA_PCIE_PERI_26M_CK_P3, "infra_pcie_peri_ck_26m_ck_p3", ++ "csw_infra_f26m_sel", 10), ++ /* INFRA1 */ ++ GATE_INFRA1(CLK_INFRA_66M_GPT_BCK, "infra_hf_66m_gpt_bck", "sysaxi_sel", 0), ++ GATE_INFRA1(CLK_INFRA_66M_PWM_HCK, "infra_hf_66m_pwm_hck", "sysaxi_sel", 1), ++ GATE_INFRA1(CLK_INFRA_66M_PWM_BCK, "infra_hf_66m_pwm_bck", "infra_pwm_sel", 2), ++ GATE_INFRA1(CLK_INFRA_66M_PWM_CK1, "infra_hf_66m_pwm_ck1", "infra_pwm_ck1_sel", 3), ++ GATE_INFRA1(CLK_INFRA_66M_PWM_CK2, "infra_hf_66m_pwm_ck2", "infra_pwm_ck2_sel", 4), ++ GATE_INFRA1(CLK_INFRA_66M_PWM_CK3, "infra_hf_66m_pwm_ck3", "infra_pwm_ck3_sel", 5), ++ GATE_INFRA1(CLK_INFRA_66M_PWM_CK4, "infra_hf_66m_pwm_ck4", "infra_pwm_ck4_sel", 6), ++ GATE_INFRA1(CLK_INFRA_66M_PWM_CK5, "infra_hf_66m_pwm_ck5", "infra_pwm_ck5_sel", 7), ++ GATE_INFRA1(CLK_INFRA_66M_PWM_CK6, "infra_hf_66m_pwm_ck6", "infra_pwm_ck6_sel", 8), ++ GATE_INFRA1(CLK_INFRA_66M_PWM_CK7, "infra_hf_66m_pwm_ck7", "infra_pwm_ck7_sel", 9), ++ GATE_INFRA1(CLK_INFRA_66M_PWM_CK8, "infra_hf_66m_pwm_ck8", "infra_pwm_ck8_sel", 10), ++ GATE_INFRA1(CLK_INFRA_133M_CQDMA_BCK, "infra_hf_133m_cqdma_bck", "sysaxi_sel", 12), ++ GATE_INFRA1(CLK_INFRA_66M_AUD_SLV_BCK, "infra_66m_aud_slv_bck", "sysaxi_sel", 13), ++ GATE_INFRA1(CLK_INFRA_AUD_26M, "infra_f_faud_26m", "csw_infra_f26m_sel", 14), ++ GATE_INFRA1(CLK_INFRA_AUD_L, "infra_f_faud_l", "aud_l_sel", 15), ++ GATE_INFRA1(CLK_INFRA_AUD_AUD, "infra_f_aud_aud", "a1sys_sel", 16), ++ GATE_INFRA1(CLK_INFRA_AUD_EG2, "infra_f_faud_eg2", "a_tuner_sel", 18), ++ GATE_INFRA1_FLAGS(CLK_INFRA_DRAMC_F26M, "infra_dramc_f26m", "csw_infra_f26m_sel", 19, ++ CLK_IS_CRITICAL), ++ /* JTAG */ ++ GATE_INFRA1_FLAGS(CLK_INFRA_133M_DBG_ACKM, "infra_hf_133m_dbg_ackm", "sysaxi_sel", 20, ++ CLK_IS_CRITICAL), ++ GATE_INFRA1(CLK_INFRA_66M_AP_DMA_BCK, "infra_66m_ap_dma_bck", "sysaxi_sel", 21), ++ GATE_INFRA1(CLK_INFRA_66M_SEJ_BCK, "infra_hf_66m_sej_bck", "sysaxi_sel", 29), ++ GATE_INFRA1(CLK_INFRA_PRE_CK_SEJ_F13M, "infra_pre_ck_sej_f13m", "csw_infra_f26m_sel", 30), ++ /* INFRA2 */ ++ GATE_INFRA2(CLK_INFRA_26M_THERM_SYSTEM, "infra_hf_26m_therm_system", "csw_infra_f26m_sel", ++ 0), ++ GATE_INFRA2(CLK_INFRA_I2C_BCK, "infra_i2c_bck", "i2c_sel", 1), ++ GATE_INFRA2(CLK_INFRA_52M_UART0_CK, "infra_f_52m_uart0", "infra_mux_uart0_sel", 3), ++ GATE_INFRA2(CLK_INFRA_52M_UART1_CK, "infra_f_52m_uart1", "infra_mux_uart1_sel", 4), ++ GATE_INFRA2(CLK_INFRA_52M_UART2_CK, "infra_f_52m_uart2", "infra_mux_uart2_sel", 5), ++ GATE_INFRA2(CLK_INFRA_NFI, "infra_f_fnfi", "nfi1x_sel", 9), ++ GATE_INFRA2(CLK_INFRA_SPINFI, "infra_f_fspinfi", "spinfi_sel", 10), ++ GATE_INFRA2_FLAGS(CLK_INFRA_66M_NFI_HCK, "infra_hf_66m_nfi_hck", "sysaxi_sel", 11, ++ CLK_IS_CRITICAL), ++ GATE_INFRA2_FLAGS(CLK_INFRA_104M_SPI0, "infra_hf_104m_spi0", "infra_mux_spi0_sel", 12, ++ CLK_IS_CRITICAL), ++ GATE_INFRA2(CLK_INFRA_104M_SPI1, "infra_hf_104m_spi1", "infra_mux_spi1_sel", 13), ++ GATE_INFRA2(CLK_INFRA_104M_SPI2_BCK, "infra_hf_104m_spi2_bck", "infra_mux_spi2_sel", 14), ++ GATE_INFRA2_FLAGS(CLK_INFRA_66M_SPI0_HCK, "infra_hf_66m_spi0_hck", "sysaxi_sel", 15, ++ CLK_IS_CRITICAL), ++ GATE_INFRA2(CLK_INFRA_66M_SPI1_HCK, "infra_hf_66m_spi1_hck", "sysaxi_sel", 16), ++ GATE_INFRA2(CLK_INFRA_66M_SPI2_HCK, "infra_hf_66m_spi2_hck", "sysaxi_sel", 17), ++ GATE_INFRA2(CLK_INFRA_66M_FLASHIF_AXI, "infra_hf_66m_flashif_axi", "sysaxi_sel", 18), ++ GATE_INFRA2_FLAGS(CLK_INFRA_RTC, "infra_f_frtc", "top_rtc_32k", 19, CLK_IS_CRITICAL), ++ GATE_INFRA2(CLK_INFRA_26M_ADC_BCK, "infra_f_26m_adc_bck", "csw_infra_f26m_sel", 20), ++ GATE_INFRA2(CLK_INFRA_RC_ADC, "infra_f_frc_adc", "infra_f_26m_adc_bck", 21), ++ GATE_INFRA2(CLK_INFRA_MSDC400, "infra_f_fmsdc400", "emmc_400m_sel", 22), ++ GATE_INFRA2(CLK_INFRA_MSDC2_HCK, "infra_f_fmsdc2_hck", "emmc_250m_sel", 23), ++ GATE_INFRA2(CLK_INFRA_133M_MSDC_0_HCK, "infra_hf_133m_msdc_0_hck", "sysaxi_sel", 24), ++ GATE_INFRA2(CLK_INFRA_66M_MSDC_0_HCK, "infra_66m_msdc_0_hck", "sysaxi_sel", 25), ++ GATE_INFRA2(CLK_INFRA_133M_CPUM_BCK, "infra_hf_133m_cpum_bck", "sysaxi_sel", 26), ++ GATE_INFRA2(CLK_INFRA_BIST2FPC, "infra_hf_fbist2fpc", "nfi1x_sel", 27), ++ GATE_INFRA2(CLK_INFRA_I2C_X16W_MCK_CK_P1, "infra_hf_i2c_x16w_mck_ck_p1", "sysaxi_sel", 29), ++ GATE_INFRA2(CLK_INFRA_I2C_X16W_PCK_CK_P1, "infra_hf_i2c_x16w_pck_ck_p1", "sysaxi_sel", 31), ++ /* INFRA3 */ ++ GATE_INFRA3(CLK_INFRA_133M_USB_HCK, "infra_133m_usb_hck", "sysaxi_sel", 0), ++ GATE_INFRA3(CLK_INFRA_133M_USB_HCK_CK_P1, "infra_133m_usb_hck_ck_p1", "sysaxi_sel", 1), ++ GATE_INFRA3(CLK_INFRA_66M_USB_HCK, "infra_66m_usb_hck", "sysaxi_sel", 2), ++ GATE_INFRA3(CLK_INFRA_66M_USB_HCK_CK_P1, "infra_66m_usb_hck_ck_p1", "sysaxi_sel", 3), ++ GATE_INFRA3(CLK_INFRA_USB_SYS, "infra_usb_sys", "usb_sys_sel", 4), ++ GATE_INFRA3(CLK_INFRA_USB_SYS_CK_P1, "infra_usb_sys_ck_p1", "usb_sys_p1_sel", 5), ++ GATE_INFRA3(CLK_INFRA_USB_REF, "infra_usb_ref", "top_xtal", 6), ++ GATE_INFRA3(CLK_INFRA_USB_CK_P1, "infra_usb_ck_p1", "top_xtal", 7), ++ GATE_INFRA3_FLAGS(CLK_INFRA_USB_FRMCNT, "infra_usb_frmcnt", "usb_frmcnt_sel", 8, ++ CLK_IS_CRITICAL), ++ GATE_INFRA3_FLAGS(CLK_INFRA_USB_FRMCNT_CK_P1, "infra_usb_frmcnt_ck_p1", "usb_frmcnt_p1_sel", ++ 9, CLK_IS_CRITICAL), ++ GATE_INFRA3(CLK_INFRA_USB_PIPE, "infra_usb_pipe", "sspxtp_sel", 10), ++ GATE_INFRA3(CLK_INFRA_USB_PIPE_CK_P1, "infra_usb_pipe_ck_p1", "usb_phy_sel", 11), ++ GATE_INFRA3(CLK_INFRA_USB_UTMI, "infra_usb_utmi", "top_xtal", 12), ++ GATE_INFRA3(CLK_INFRA_USB_UTMI_CK_P1, "infra_usb_utmi_ck_p1", "top_xtal", 13), ++ GATE_INFRA3(CLK_INFRA_USB_XHCI, "infra_usb_xhci", "usb_xhci_sel", 14), ++ GATE_INFRA3(CLK_INFRA_USB_XHCI_CK_P1, "infra_usb_xhci_ck_p1", "usb_xhci_p1_sel", 15), ++ GATE_INFRA3(CLK_INFRA_PCIE_GFMUX_TL_P0, "infra_pcie_gfmux_tl_ck_p0", ++ "infra_pcie_gfmux_tl_o_p0_sel", 20), ++ GATE_INFRA3(CLK_INFRA_PCIE_GFMUX_TL_P1, "infra_pcie_gfmux_tl_ck_p1", ++ "infra_pcie_gfmux_tl_o_p1_sel", 21), ++ GATE_INFRA3(CLK_INFRA_PCIE_GFMUX_TL_P2, "infra_pcie_gfmux_tl_ck_p2", ++ "infra_pcie_gfmux_tl_o_p2_sel", 22), ++ GATE_INFRA3(CLK_INFRA_PCIE_GFMUX_TL_P3, "infra_pcie_gfmux_tl_ck_p3", ++ "infra_pcie_gfmux_tl_o_p3_sel", 23), ++ GATE_INFRA3(CLK_INFRA_PCIE_PIPE_P0, "infra_pcie_pipe_ck_p0", "top_xtal", 24), ++ GATE_INFRA3(CLK_INFRA_PCIE_PIPE_P1, "infra_pcie_pipe_ck_p1", "top_xtal", 25), ++ GATE_INFRA3(CLK_INFRA_PCIE_PIPE_P2, "infra_pcie_pipe_ck_p2", "top_xtal", 26), ++ GATE_INFRA3(CLK_INFRA_PCIE_PIPE_P3, "infra_pcie_pipe_ck_p3", "top_xtal", 27), ++ GATE_INFRA3(CLK_INFRA_133M_PCIE_CK_P0, "infra_133m_pcie_ck_p0", "sysaxi_sel", 28), ++ GATE_INFRA3(CLK_INFRA_133M_PCIE_CK_P1, "infra_133m_pcie_ck_p1", "sysaxi_sel", 29), ++ GATE_INFRA3(CLK_INFRA_133M_PCIE_CK_P2, "infra_133m_pcie_ck_p2", "sysaxi_sel", 30), ++ GATE_INFRA3(CLK_INFRA_133M_PCIE_CK_P3, "infra_133m_pcie_ck_p3", "sysaxi_sel", 31), ++}; ++ ++static const struct mtk_clk_desc infra_desc = { ++ .clks = infra_clks, ++ .num_clks = ARRAY_SIZE(infra_clks), ++ .mux_clks = infra_muxes, ++ .num_mux_clks = ARRAY_SIZE(infra_muxes), ++ .clk_lock = &mt7988_clk_lock, ++}; ++ ++static const struct of_device_id of_match_clk_mt7988_infracfg[] = { ++ { .compatible = "mediatek,mt7988-infracfg", .data = &infra_desc }, ++ { /* sentinel */ } ++}; ++MODULE_DEVICE_TABLE(of, of_match_clk_mt7988_infracfg); ++ ++static struct platform_driver clk_mt7988_infracfg_drv = { ++ .driver = { ++ .name = "clk-mt7988-infracfg", ++ .of_match_table = of_match_clk_mt7988_infracfg, ++ }, ++ .probe = mtk_clk_simple_probe, ++ .remove = mtk_clk_simple_remove, ++}; ++module_platform_driver(clk_mt7988_infracfg_drv); ++MODULE_LICENSE("GPL"); +--- /dev/null ++++ b/drivers/clk/mediatek/clk-mt7988-topckgen.c +@@ -0,0 +1,325 @@ ++// SPDX-License-Identifier: GPL-2.0 ++/* ++ * Copyright (c) 2023 MediaTek Inc. ++ * Author: Sam Shih ++ * Author: Xiufeng Li ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include "clk-mtk.h" ++#include "clk-gate.h" ++#include "clk-mux.h" ++#include ++ ++static DEFINE_SPINLOCK(mt7988_clk_lock); ++ ++static const struct mtk_fixed_clk top_fixed_clks[] = { ++ FIXED_CLK(CLK_TOP_XTAL, "top_xtal", "clkxtal", 40000000), ++}; ++ ++static const struct mtk_fixed_factor top_divs[] = { ++ FACTOR(CLK_TOP_XTAL_D2, "top_xtal_d2", "top_xtal", 1, 2), ++ FACTOR(CLK_TOP_RTC_32K, "top_rtc_32k", "top_xtal", 1, 1250), ++ FACTOR(CLK_TOP_RTC_32P7K, "top_rtc_32p7k", "top_xtal", 1, 1220), ++ FACTOR(CLK_TOP_MPLL_D2, "mpll_d2", "mpll", 1, 2), ++ FACTOR(CLK_TOP_MPLL_D3_D2, "mpll_d3_d2", "mpll", 1, 2), ++ FACTOR(CLK_TOP_MPLL_D4, "mpll_d4", "mpll", 1, 4), ++ FACTOR(CLK_TOP_MPLL_D8, "mpll_d8", "mpll", 1, 8), ++ FACTOR(CLK_TOP_MPLL_D8_D2, "mpll_d8_d2", "mpll", 1, 16), ++ FACTOR(CLK_TOP_MMPLL_D2, "mmpll_d2", "mmpll", 1, 2), ++ FACTOR(CLK_TOP_MMPLL_D3_D5, "mmpll_d3_d5", "mmpll", 1, 15), ++ FACTOR(CLK_TOP_MMPLL_D4, "mmpll_d4", "mmpll", 1, 4), ++ FACTOR(CLK_TOP_MMPLL_D6_D2, "mmpll_d6_d2", "mmpll", 1, 12), ++ FACTOR(CLK_TOP_MMPLL_D8, "mmpll_d8", "mmpll", 1, 8), ++ FACTOR(CLK_TOP_APLL2_D4, "apll2_d4", "apll2", 1, 4), ++ FACTOR(CLK_TOP_NET1PLL_D4, "net1pll_d4", "net1pll", 1, 4), ++ FACTOR(CLK_TOP_NET1PLL_D5, "net1pll_d5", "net1pll", 1, 5), ++ FACTOR(CLK_TOP_NET1PLL_D5_D2, "net1pll_d5_d2", "net1pll", 1, 10), ++ FACTOR(CLK_TOP_NET1PLL_D5_D4, "net1pll_d5_d4", "net1pll", 1, 20), ++ FACTOR(CLK_TOP_NET1PLL_D8, "net1pll_d8", "net1pll", 1, 8), ++ FACTOR(CLK_TOP_NET1PLL_D8_D2, "net1pll_d8_d2", "net1pll", 1, 16), ++ FACTOR(CLK_TOP_NET1PLL_D8_D4, "net1pll_d8_d4", "net1pll", 1, 32), ++ FACTOR(CLK_TOP_NET1PLL_D8_D8, "net1pll_d8_d8", "net1pll", 1, 64), ++ FACTOR(CLK_TOP_NET1PLL_D8_D16, "net1pll_d8_d16", "net1pll", 1, 128), ++ FACTOR(CLK_TOP_NET2PLL_D2, "net2pll_d2", "net2pll", 1, 2), ++ FACTOR(CLK_TOP_NET2PLL_D4, "net2pll_d4", "net2pll", 1, 4), ++ FACTOR(CLK_TOP_NET2PLL_D4_D4, "net2pll_d4_d4", "net2pll", 1, 16), ++ FACTOR(CLK_TOP_NET2PLL_D4_D8, "net2pll_d4_d8", "net2pll", 1, 32), ++ FACTOR(CLK_TOP_NET2PLL_D6, "net2pll_d6", "net2pll", 1, 6), ++ FACTOR(CLK_TOP_NET2PLL_D8, "net2pll_d8", "net2pll", 1, 8), ++}; ++ ++static const char *const netsys_parents[] = { "top_xtal", "net2pll_d2", "mmpll_d2" }; ++static const char *const netsys_500m_parents[] = { "top_xtal", "net1pll_d5", "net1pll_d5_d2" }; ++static const char *const netsys_2x_parents[] = { "top_xtal", "net2pll", "mmpll" }; ++static const char *const netsys_gsw_parents[] = { "top_xtal", "net1pll_d4", "net1pll_d5" }; ++static const char *const eth_gmii_parents[] = { "top_xtal", "net1pll_d5_d4" }; ++static const char *const netsys_mcu_parents[] = { "top_xtal", "net2pll", "mmpll", ++ "net1pll_d4", "net1pll_d5", "mpll" }; ++static const char *const eip197_parents[] = { "top_xtal", "netsyspll", "net2pll", ++ "mmpll", "net1pll_d4", "net1pll_d5" }; ++static const char *const axi_infra_parents[] = { "top_xtal", "net1pll_d8_d2" }; ++static const char *const uart_parents[] = { "top_xtal", "mpll_d8", "mpll_d8_d2" }; ++static const char *const emmc_250m_parents[] = { "top_xtal", "net1pll_d5_d2", "mmpll_d4" }; ++static const char *const emmc_400m_parents[] = { "top_xtal", "msdcpll", "mmpll_d2", ++ "mpll_d2", "mmpll_d4", "net1pll_d8_d2" }; ++static const char *const spi_parents[] = { "top_xtal", "mpll_d2", "mmpll_d4", ++ "net1pll_d8_d2", "net2pll_d6", "net1pll_d5_d4", ++ "mpll_d4", "net1pll_d8_d4" }; ++static const char *const nfi1x_parents[] = { "top_xtal", "mmpll_d4", "net1pll_d8_d2", "net2pll_d6", ++ "mpll_d4", "mmpll_d8", "net1pll_d8_d4", "mpll_d8" }; ++static const char *const spinfi_parents[] = { "top_xtal_d2", "top_xtal", "net1pll_d5_d4", ++ "mpll_d4", "mmpll_d8", "net1pll_d8_d4", ++ "mmpll_d6_d2", "mpll_d8" }; ++static const char *const pwm_parents[] = { "top_xtal", "net1pll_d8_d2", "net1pll_d5_d4", ++ "mpll_d4", "mpll_d8_d2", "top_rtc_32k" }; ++static const char *const i2c_parents[] = { "top_xtal", "net1pll_d5_d4", "mpll_d4", ++ "net1pll_d8_d4" }; ++static const char *const pcie_mbist_250m_parents[] = { "top_xtal", "net1pll_d5_d2" }; ++static const char *const pextp_tl_ck_parents[] = { "top_xtal", "net2pll_d6", "mmpll_d8", ++ "mpll_d8_d2", "top_rtc_32k" }; ++static const char *const usb_frmcnt_parents[] = { "top_xtal", "mmpll_d3_d5" }; ++static const char *const aud_parents[] = { "top_xtal", "apll2" }; ++static const char *const a1sys_parents[] = { "top_xtal", "apll2_d4" }; ++static const char *const aud_l_parents[] = { "top_xtal", "apll2", "mpll_d8_d2" }; ++static const char *const sspxtp_parents[] = { "top_xtal_d2", "mpll_d8_d2" }; ++static const char *const usxgmii_sbus_0_parents[] = { "top_xtal", "net1pll_d8_d4" }; ++static const char *const sgm_0_parents[] = { "top_xtal", "sgmpll" }; ++static const char *const sysapb_parents[] = { "top_xtal", "mpll_d3_d2" }; ++static const char *const eth_refck_50m_parents[] = { "top_xtal", "net2pll_d4_d4" }; ++static const char *const eth_sys_200m_parents[] = { "top_xtal", "net2pll_d4" }; ++static const char *const eth_xgmii_parents[] = { "top_xtal_d2", "net1pll_d8_d8", "net1pll_d8_d16" }; ++static const char *const bus_tops_parents[] = { "top_xtal", "net1pll_d5", "net2pll_d2" }; ++static const char *const npu_tops_parents[] = { "top_xtal", "net2pll" }; ++static const char *const dramc_md32_parents[] = { "top_xtal", "mpll_d2", "wedmcupll" }; ++static const char *const da_xtp_glb_p0_parents[] = { "top_xtal", "net2pll_d8" }; ++static const char *const mcusys_backup_625m_parents[] = { "top_xtal", "net1pll_d4" }; ++static const char *const macsec_parents[] = { "top_xtal", "sgmpll", "net1pll_d8" }; ++static const char *const netsys_tops_400m_parents[] = { "top_xtal", "net2pll_d2" }; ++static const char *const eth_mii_parents[] = { "top_xtal_d2", "net2pll_d4_d8" }; ++ ++static const struct mtk_mux top_muxes[] = { ++ /* CLK_CFG_0 */ ++ MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_SEL, "netsys_sel", netsys_parents, 0x000, 0x004, 0x008, ++ 0, 2, 7, 0x1c0, 0), ++ MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_500M_SEL, "netsys_500m_sel", netsys_500m_parents, 0x000, ++ 0x004, 0x008, 8, 2, 15, 0x1C0, 1), ++ MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_2X_SEL, "netsys_2x_sel", netsys_2x_parents, 0x000, ++ 0x004, 0x008, 16, 2, 23, 0x1C0, 2), ++ MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_GSW_SEL, "netsys_gsw_sel", netsys_gsw_parents, 0x000, ++ 0x004, 0x008, 24, 2, 31, 0x1C0, 3), ++ /* CLK_CFG_1 */ ++ MUX_GATE_CLR_SET_UPD(CLK_TOP_ETH_GMII_SEL, "eth_gmii_sel", eth_gmii_parents, 0x010, 0x014, ++ 0x018, 0, 1, 7, 0x1C0, 4), ++ MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_MCU_SEL, "netsys_mcu_sel", netsys_mcu_parents, 0x010, ++ 0x014, 0x018, 8, 3, 15, 0x1C0, 5), ++ MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_PAO_2X_SEL, "netsys_pao_2x_sel", netsys_mcu_parents, ++ 0x010, 0x014, 0x018, 16, 3, 23, 0x1C0, 6), ++ MUX_GATE_CLR_SET_UPD(CLK_TOP_EIP197_SEL, "eip197_sel", eip197_parents, 0x010, 0x014, 0x018, ++ 24, 3, 31, 0x1c0, 7), ++ /* CLK_CFG_2 */ ++ MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_AXI_INFRA_SEL, "axi_infra_sel", axi_infra_parents, 0x020, ++ 0x024, 0x028, 0, 1, 7, 0x1C0, 8, CLK_IS_CRITICAL), ++ MUX_GATE_CLR_SET_UPD(CLK_TOP_UART_SEL, "uart_sel", uart_parents, 0x020, 0x024, 0x028, 8, 2, ++ 15, 0x1c0, 9), ++ MUX_GATE_CLR_SET_UPD(CLK_TOP_EMMC_250M_SEL, "emmc_250m_sel", emmc_250m_parents, 0x020, ++ 0x024, 0x028, 16, 2, 23, 0x1C0, 10), ++ MUX_GATE_CLR_SET_UPD(CLK_TOP_EMMC_400M_SEL, "emmc_400m_sel", emmc_400m_parents, 0x020, ++ 0x024, 0x028, 24, 3, 31, 0x1C0, 11), ++ /* CLK_CFG_3 */ ++ MUX_GATE_CLR_SET_UPD(CLK_TOP_SPI_SEL, "spi_sel", spi_parents, 0x030, 0x034, 0x038, 0, 3, 7, ++ 0x1c0, 12), ++ MUX_GATE_CLR_SET_UPD(CLK_TOP_SPIM_MST_SEL, "spim_mst_sel", spi_parents, 0x030, 0x034, 0x038, ++ 8, 3, 15, 0x1c0, 13), ++ MUX_GATE_CLR_SET_UPD(CLK_TOP_NFI1X_SEL, "nfi1x_sel", nfi1x_parents, 0x030, 0x034, 0x038, 16, ++ 3, 23, 0x1c0, 14), ++ MUX_GATE_CLR_SET_UPD(CLK_TOP_SPINFI_SEL, "spinfi_sel", spinfi_parents, 0x030, 0x034, 0x038, ++ 24, 3, 31, 0x1c0, 15), ++ /* CLK_CFG_4 */ ++ MUX_GATE_CLR_SET_UPD(CLK_TOP_PWM_SEL, "pwm_sel", pwm_parents, 0x040, 0x044, 0x048, 0, 3, 7, ++ 0x1c0, 16), ++ MUX_GATE_CLR_SET_UPD(CLK_TOP_I2C_SEL, "i2c_sel", i2c_parents, 0x040, 0x044, 0x048, 8, 2, 15, ++ 0x1c0, 17), ++ MUX_GATE_CLR_SET_UPD(CLK_TOP_PCIE_MBIST_250M_SEL, "pcie_mbist_250m_sel", ++ pcie_mbist_250m_parents, 0x040, 0x044, 0x048, 16, 1, 23, 0x1C0, 18), ++ MUX_GATE_CLR_SET_UPD(CLK_TOP_PEXTP_TL_SEL, "pextp_tl_sel", pextp_tl_ck_parents, 0x040, ++ 0x044, 0x048, 24, 3, 31, 0x1C0, 19), ++ /* CLK_CFG_5 */ ++ MUX_GATE_CLR_SET_UPD(CLK_TOP_PEXTP_TL_P1_SEL, "pextp_tl_p1_sel", pextp_tl_ck_parents, 0x050, ++ 0x054, 0x058, 0, 3, 7, 0x1C0, 20), ++ MUX_GATE_CLR_SET_UPD(CLK_TOP_PEXTP_TL_P2_SEL, "pextp_tl_p2_sel", pextp_tl_ck_parents, 0x050, ++ 0x054, 0x058, 8, 3, 15, 0x1C0, 21), ++ MUX_GATE_CLR_SET_UPD(CLK_TOP_PEXTP_TL_P3_SEL, "pextp_tl_p3_sel", pextp_tl_ck_parents, 0x050, ++ 0x054, 0x058, 16, 3, 23, 0x1C0, 22), ++ MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_SYS_SEL, "usb_sys_sel", eth_gmii_parents, 0x050, 0x054, ++ 0x058, 24, 1, 31, 0x1C0, 23), ++ /* CLK_CFG_6 */ ++ MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_SYS_P1_SEL, "usb_sys_p1_sel", eth_gmii_parents, 0x060, ++ 0x064, 0x068, 0, 1, 7, 0x1C0, 24), ++ MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_XHCI_SEL, "usb_xhci_sel", eth_gmii_parents, 0x060, 0x064, ++ 0x068, 8, 1, 15, 0x1C0, 25), ++ MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_XHCI_P1_SEL, "usb_xhci_p1_sel", eth_gmii_parents, 0x060, ++ 0x064, 0x068, 16, 1, 23, 0x1C0, 26), ++ MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_FRMCNT_SEL, "usb_frmcnt_sel", usb_frmcnt_parents, 0x060, ++ 0x064, 0x068, 24, 1, 31, 0x1C0, 27), ++ /* CLK_CFG_7 */ ++ MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_FRMCNT_P1_SEL, "usb_frmcnt_p1_sel", usb_frmcnt_parents, ++ 0x070, 0x074, 0x078, 0, 1, 7, 0x1C0, 28), ++ MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_SEL, "aud_sel", aud_parents, 0x070, 0x074, 0x078, 8, 1, 15, ++ 0x1c0, 29), ++ MUX_GATE_CLR_SET_UPD(CLK_TOP_A1SYS_SEL, "a1sys_sel", a1sys_parents, 0x070, 0x074, 0x078, 16, ++ 1, 23, 0x1c0, 30), ++ MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_L_SEL, "aud_l_sel", aud_l_parents, 0x070, 0x074, 0x078, 24, ++ 2, 31, 0x1c4, 0), ++ /* CLK_CFG_8 */ ++ MUX_GATE_CLR_SET_UPD(CLK_TOP_A_TUNER_SEL, "a_tuner_sel", a1sys_parents, 0x080, 0x084, 0x088, ++ 0, 1, 7, 0x1c4, 1), ++ MUX_GATE_CLR_SET_UPD(CLK_TOP_SSPXTP_SEL, "sspxtp_sel", sspxtp_parents, 0x080, 0x084, 0x088, ++ 8, 1, 15, 0x1c4, 2), ++ MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_PHY_SEL, "usb_phy_sel", sspxtp_parents, 0x080, 0x084, ++ 0x088, 16, 1, 23, 0x1c4, 3), ++ MUX_GATE_CLR_SET_UPD(CLK_TOP_USXGMII_SBUS_0_SEL, "usxgmii_sbus_0_sel", ++ usxgmii_sbus_0_parents, 0x080, 0x084, 0x088, 24, 1, 31, 0x1C4, 4), ++ /* CLK_CFG_9 */ ++ MUX_GATE_CLR_SET_UPD(CLK_TOP_USXGMII_SBUS_1_SEL, "usxgmii_sbus_1_sel", ++ usxgmii_sbus_0_parents, 0x090, 0x094, 0x098, 0, 1, 7, 0x1C4, 5), ++ MUX_GATE_CLR_SET_UPD(CLK_TOP_SGM_0_SEL, "sgm_0_sel", sgm_0_parents, 0x090, 0x094, 0x098, 8, ++ 1, 15, 0x1c4, 6), ++ MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SGM_SBUS_0_SEL, "sgm_sbus_0_sel", usxgmii_sbus_0_parents, ++ 0x090, 0x094, 0x098, 16, 1, 23, 0x1C4, 7, CLK_IS_CRITICAL), ++ MUX_GATE_CLR_SET_UPD(CLK_TOP_SGM_1_SEL, "sgm_1_sel", sgm_0_parents, 0x090, 0x094, 0x098, 24, ++ 1, 31, 0x1c4, 8), ++ /* CLK_CFG_10 */ ++ MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SGM_SBUS_1_SEL, "sgm_sbus_1_sel", usxgmii_sbus_0_parents, ++ 0x0a0, 0x0a4, 0x0a8, 0, 1, 7, 0x1C4, 9, CLK_IS_CRITICAL), ++ MUX_GATE_CLR_SET_UPD(CLK_TOP_XFI_PHY_0_XTAL_SEL, "xfi_phy_0_xtal_sel", sspxtp_parents, ++ 0x0a0, 0x0a4, 0x0a8, 8, 1, 15, 0x1C4, 10), ++ MUX_GATE_CLR_SET_UPD(CLK_TOP_XFI_PHY_1_XTAL_SEL, "xfi_phy_1_xtal_sel", sspxtp_parents, ++ 0x0a0, 0x0a4, 0x0a8, 16, 1, 23, 0x1C4, 11), ++ /* CLK_CFG_11 */ ++ MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SYSAXI_SEL, "sysaxi_sel", axi_infra_parents, 0x0a0, ++ 0x0a4, 0x0a8, 24, 1, 31, 0x1C4, 12, CLK_IS_CRITICAL), ++ MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SYSAPB_SEL, "sysapb_sel", sysapb_parents, 0x0b0, 0x0b4, ++ 0x0b8, 0, 1, 7, 0x1c4, 13, CLK_IS_CRITICAL), ++ MUX_GATE_CLR_SET_UPD(CLK_TOP_ETH_REFCK_50M_SEL, "eth_refck_50m_sel", eth_refck_50m_parents, ++ 0x0b0, 0x0b4, 0x0b8, 8, 1, 15, 0x1C4, 14), ++ MUX_GATE_CLR_SET_UPD(CLK_TOP_ETH_SYS_200M_SEL, "eth_sys_200m_sel", eth_sys_200m_parents, ++ 0x0b0, 0x0b4, 0x0b8, 16, 1, 23, 0x1C4, 15), ++ MUX_GATE_CLR_SET_UPD(CLK_TOP_ETH_SYS_SEL, "eth_sys_sel", pcie_mbist_250m_parents, 0x0b0, ++ 0x0b4, 0x0b8, 24, 1, 31, 0x1C4, 16), ++ /* CLK_CFG_12 */ ++ MUX_GATE_CLR_SET_UPD(CLK_TOP_ETH_XGMII_SEL, "eth_xgmii_sel", eth_xgmii_parents, 0x0c0, ++ 0x0c4, 0x0c8, 0, 2, 7, 0x1C4, 17), ++ MUX_GATE_CLR_SET_UPD(CLK_TOP_BUS_TOPS_SEL, "bus_tops_sel", bus_tops_parents, 0x0c0, 0x0c4, ++ 0x0c8, 8, 2, 15, 0x1C4, 18), ++ MUX_GATE_CLR_SET_UPD(CLK_TOP_NPU_TOPS_SEL, "npu_tops_sel", npu_tops_parents, 0x0c0, 0x0c4, ++ 0x0c8, 16, 1, 23, 0x1C4, 19), ++ MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_DRAMC_SEL, "dramc_sel", sspxtp_parents, 0x0c0, 0x0c4, ++ 0x0c8, 24, 1, 31, 0x1C4, 20, CLK_IS_CRITICAL), ++ /* CLK_CFG_13 */ ++ MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_DRAMC_MD32_SEL, "dramc_md32_sel", dramc_md32_parents, ++ 0x0d0, 0x0d4, 0x0d8, 0, 2, 7, 0x1C4, 21, CLK_IS_CRITICAL), ++ MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_INFRA_F26M_SEL, "csw_infra_f26m_sel", sspxtp_parents, ++ 0x0d0, 0x0d4, 0x0d8, 8, 1, 15, 0x1C4, 22, CLK_IS_CRITICAL), ++ MUX_GATE_CLR_SET_UPD(CLK_TOP_PEXTP_P0_SEL, "pextp_p0_sel", sspxtp_parents, 0x0d0, 0x0d4, ++ 0x0d8, 16, 1, 23, 0x1C4, 23), ++ MUX_GATE_CLR_SET_UPD(CLK_TOP_PEXTP_P1_SEL, "pextp_p1_sel", sspxtp_parents, 0x0d0, 0x0d4, ++ 0x0d8, 24, 1, 31, 0x1C4, 24), ++ /* CLK_CFG_14 */ ++ MUX_GATE_CLR_SET_UPD(CLK_TOP_PEXTP_P2_SEL, "pextp_p2_sel", sspxtp_parents, 0x0e0, 0x0e4, ++ 0x0e8, 0, 1, 7, 0x1C4, 25), ++ MUX_GATE_CLR_SET_UPD(CLK_TOP_PEXTP_P3_SEL, "pextp_p3_sel", sspxtp_parents, 0x0e0, 0x0e4, ++ 0x0e8, 8, 1, 15, 0x1C4, 26), ++ MUX_GATE_CLR_SET_UPD(CLK_TOP_DA_XTP_GLB_P0_SEL, "da_xtp_glb_p0_sel", da_xtp_glb_p0_parents, ++ 0x0e0, 0x0e4, 0x0e8, 16, 1, 23, 0x1C4, 27), ++ MUX_GATE_CLR_SET_UPD(CLK_TOP_DA_XTP_GLB_P1_SEL, "da_xtp_glb_p1_sel", da_xtp_glb_p0_parents, ++ 0x0e0, 0x0e4, 0x0e8, 24, 1, 31, 0x1C4, 28), ++ /* CLK_CFG_15 */ ++ MUX_GATE_CLR_SET_UPD(CLK_TOP_DA_XTP_GLB_P2_SEL, "da_xtp_glb_p2_sel", da_xtp_glb_p0_parents, ++ 0x0f0, 0x0f4, 0x0f8, 0, 1, 7, 0x1C4, 29), ++ MUX_GATE_CLR_SET_UPD(CLK_TOP_DA_XTP_GLB_P3_SEL, "da_xtp_glb_p3_sel", da_xtp_glb_p0_parents, ++ 0x0f0, 0x0f4, 0x0f8, 8, 1, 15, 0x1C4, 30), ++ MUX_GATE_CLR_SET_UPD(CLK_TOP_CKM_SEL, "ckm_sel", sspxtp_parents, 0x0F0, 0x0f4, 0x0f8, 16, 1, ++ 23, 0x1c8, 0), ++ MUX_GATE_CLR_SET_UPD(CLK_TOP_DA_SEL, "da_sel", sspxtp_parents, 0x0f0, 0x0f4, 0x0f8, 24, 1, ++ 31, 0x1C8, 1), ++ /* CLK_CFG_16 */ ++ MUX_GATE_CLR_SET_UPD(CLK_TOP_PEXTP_SEL, "pextp_sel", sspxtp_parents, 0x0100, 0x104, 0x108, ++ 0, 1, 7, 0x1c8, 2), ++ MUX_GATE_CLR_SET_UPD(CLK_TOP_TOPS_P2_26M_SEL, "tops_p2_26m_sel", sspxtp_parents, 0x0100, ++ 0x104, 0x108, 8, 1, 15, 0x1C8, 3), ++ MUX_GATE_CLR_SET_UPD(CLK_TOP_MCUSYS_BACKUP_625M_SEL, "mcusys_backup_625m_sel", ++ mcusys_backup_625m_parents, 0x0100, 0x104, 0x108, 16, 1, 23, 0x1C8, 4), ++ MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_SYNC_250M_SEL, "netsys_sync_250m_sel", ++ pcie_mbist_250m_parents, 0x0100, 0x104, 0x108, 24, 1, 31, 0x1c8, 5), ++ /* CLK_CFG_17 */ ++ MUX_GATE_CLR_SET_UPD(CLK_TOP_MACSEC_SEL, "macsec_sel", macsec_parents, 0x0110, 0x114, 0x118, ++ 0, 2, 7, 0x1c8, 6), ++ MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_TOPS_400M_SEL, "netsys_tops_400m_sel", ++ netsys_tops_400m_parents, 0x0110, 0x114, 0x118, 8, 1, 15, 0x1c8, 7), ++ MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_PPEFB_250M_SEL, "netsys_ppefb_250m_sel", ++ pcie_mbist_250m_parents, 0x0110, 0x114, 0x118, 16, 1, 23, 0x1c8, 8), ++ MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_WARP_SEL, "netsys_warp_sel", netsys_parents, 0x0110, ++ 0x114, 0x118, 24, 2, 31, 0x1C8, 9), ++ /* CLK_CFG_18 */ ++ MUX_GATE_CLR_SET_UPD(CLK_TOP_ETH_MII_SEL, "eth_mii_sel", eth_mii_parents, 0x0120, 0x124, ++ 0x128, 0, 1, 7, 0x1c8, 10), ++ MUX_GATE_CLR_SET_UPD(CLK_TOP_NPU_SEL, "ck_npu_sel", netsys_2x_parents, 0x0120, 0x124, 0x128, ++ 8, 2, 15, 0x1c8, 11), ++}; ++ ++static const struct mtk_composite top_aud_divs[] = { ++ DIV_GATE(CLK_TOP_AUD_I2S_M, "aud_i2s_m", "aud_sel", 0x0420, 0, 0x0420, 8, 8), ++}; ++ ++static const struct mtk_clk_desc topck_desc = { ++ .fixed_clks = top_fixed_clks, ++ .num_fixed_clks = ARRAY_SIZE(top_fixed_clks), ++ .factor_clks = top_divs, ++ .num_factor_clks = ARRAY_SIZE(top_divs), ++ .mux_clks = top_muxes, ++ .num_mux_clks = ARRAY_SIZE(top_muxes), ++ .composite_clks = top_aud_divs, ++ .num_composite_clks = ARRAY_SIZE(top_aud_divs), ++ .clk_lock = &mt7988_clk_lock, ++}; ++ ++static const char *const mcu_bus_div_parents[] = { "top_xtal", "ccipll2_b", "net1pll_d4" }; ++ ++static const char *const mcu_arm_div_parents[] = { "top_xtal", "arm_b", "net1pll_d4" }; ++ ++static struct mtk_composite mcu_muxes[] = { ++ /* bus_pll_divider_cfg */ ++ MUX_GATE_FLAGS(CLK_MCU_BUS_DIV_SEL, "mcu_bus_div_sel", mcu_bus_div_parents, 0x7C0, 9, 2, -1, ++ CLK_IS_CRITICAL), ++ /* mp2_pll_divider_cfg */ ++ MUX_GATE_FLAGS(CLK_MCU_ARM_DIV_SEL, "mcu_arm_div_sel", mcu_arm_div_parents, 0x7A8, 9, 2, -1, ++ CLK_IS_CRITICAL), ++}; ++ ++static const struct mtk_clk_desc mcusys_desc = { ++ .composite_clks = mcu_muxes, ++ .num_composite_clks = ARRAY_SIZE(mcu_muxes), ++}; ++ ++static const struct of_device_id of_match_clk_mt7988_topckgen[] = { ++ { .compatible = "mediatek,mt7988-topckgen", .data = &topck_desc }, ++ { .compatible = "mediatek,mt7988-mcusys", .data = &mcusys_desc }, ++ { /* sentinel */ } ++}; ++MODULE_DEVICE_TABLE(of, of_match_clk_mt7988_topckgen); ++ ++static struct platform_driver clk_mt7988_topckgen_drv = { ++ .probe = mtk_clk_simple_probe, ++ .remove = mtk_clk_simple_remove, ++ .driver = { ++ .name = "clk-mt7988-topckgen", ++ .of_match_table = of_match_clk_mt7988_topckgen, ++ }, ++}; ++module_platform_driver(clk_mt7988_topckgen_drv); ++MODULE_LICENSE("GPL"); +--- /dev/null ++++ b/drivers/clk/mediatek/clk-mt7988-xfipll.c +@@ -0,0 +1,82 @@ ++// SPDX-License-Identifier: GPL-2.0 ++/* ++ * Copyright (c) 2023 Daniel Golle ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include "clk-mtk.h" ++#include "clk-gate.h" ++#include ++ ++/* Register to control USXGMII XFI PLL analog */ ++#define XFI_PLL_ANA_GLB8 0x108 ++#define RG_XFI_PLL_ANA_SWWA 0x02283248 ++ ++static const struct mtk_gate_regs xfipll_cg_regs = { ++ .set_ofs = 0x8, ++ .clr_ofs = 0x8, ++ .sta_ofs = 0x8, ++}; ++ ++#define GATE_XFIPLL(_id, _name, _parent, _shift) \ ++ { \ ++ .id = _id, \ ++ .name = _name, \ ++ .parent_name = _parent, \ ++ .regs = &xfipll_cg_regs, \ ++ .shift = _shift, \ ++ .ops = &mtk_clk_gate_ops_no_setclr_inv, \ ++ } ++ ++static const struct mtk_fixed_factor xfipll_divs[] = { ++ FACTOR(CLK_XFIPLL_PLL, "xfipll_pll", "top_xtal", 125, 32), ++}; ++ ++static const struct mtk_gate xfipll_clks[] = { ++ GATE_XFIPLL(CLK_XFIPLL_PLL_EN, "xfipll_pll_en", "xfipll_pll", 31), ++}; ++ ++static const struct mtk_clk_desc xfipll_desc = { ++ .clks = xfipll_clks, ++ .num_clks = ARRAY_SIZE(xfipll_clks), ++ .factor_clks = xfipll_divs, ++ .num_factor_clks = ARRAY_SIZE(xfipll_divs), ++}; ++ ++static int clk_mt7988_xfipll_probe(struct platform_device *pdev) ++{ ++ struct device_node *node = pdev->dev.of_node; ++ void __iomem *base = of_iomap(node, 0); ++ ++ if (!base) ++ return -ENOMEM; ++ ++ /* Apply software workaround for USXGMII PLL TCL issue */ ++ writel(RG_XFI_PLL_ANA_SWWA, base + XFI_PLL_ANA_GLB8); ++ iounmap(base); ++ ++ return mtk_clk_simple_probe(pdev); ++}; ++ ++static const struct of_device_id of_match_clk_mt7988_xfipll[] = { ++ { .compatible = "mediatek,mt7988-xfi-pll", .data = &xfipll_desc }, ++ { /* sentinel */ } ++}; ++MODULE_DEVICE_TABLE(of, of_match_clk_mt7988_xfipll); ++ ++static struct platform_driver clk_mt7988_xfipll_drv = { ++ .driver = { ++ .name = "clk-mt7988-xfipll", ++ .of_match_table = of_match_clk_mt7988_xfipll, ++ }, ++ .probe = clk_mt7988_xfipll_probe, ++ .remove = mtk_clk_simple_remove, ++}; ++module_platform_driver(clk_mt7988_xfipll_drv); ++ ++MODULE_DESCRIPTION("MediaTek MT7988 XFI PLL clock driver"); ++MODULE_LICENSE("GPL"); diff --git a/lede/target/linux/mediatek/patches-6.1/250-clk-mediatek-add-infracfg-reset-controller-for-mt798.patch b/lede/target/linux/mediatek/patches-6.1/250-clk-mediatek-add-infracfg-reset-controller-for-mt798.patch new file mode 100644 index 0000000000..cecf095e92 --- /dev/null +++ b/lede/target/linux/mediatek/patches-6.1/250-clk-mediatek-add-infracfg-reset-controller-for-mt798.patch @@ -0,0 +1,57 @@ +From 26ced94177b150710d94cf365002a09cc48950e9 Mon Sep 17 00:00:00 2001 +From: Frank Wunderlich +Date: Wed, 17 Jan 2024 19:41:11 +0100 +Subject: [PATCH] clk: mediatek: add infracfg reset controller for mt7988 + +Infracfg can also operate as reset controller, add support for it. + +Signed-off-by: Frank Wunderlich +--- + drivers/clk/mediatek/clk-mt7988-infracfg.c | 23 ++++++++++++++++++++++ + 1 file changed, 23 insertions(+) + +--- a/drivers/clk/mediatek/clk-mt7988-infracfg.c ++++ b/drivers/clk/mediatek/clk-mt7988-infracfg.c +@@ -14,6 +14,10 @@ + #include "clk-gate.h" + #include "clk-mux.h" + #include ++#include ++ ++#define MT7988_INFRA_RST0_SET_OFFSET 0x70 ++#define MT7988_INFRA_RST1_SET_OFFSET 0x80 + + static DEFINE_SPINLOCK(mt7988_clk_lock); + +@@ -249,12 +253,31 @@ static const struct mtk_gate infra_clks[ + GATE_INFRA3(CLK_INFRA_133M_PCIE_CK_P3, "infra_133m_pcie_ck_p3", "sysaxi_sel", 31), + }; + ++static u16 infra_rst_ofs[] = { ++ MT7988_INFRA_RST0_SET_OFFSET, ++ MT7988_INFRA_RST1_SET_OFFSET, ++}; ++ ++static u16 infra_idx_map[] = { ++ [MT7988_INFRA_RST0_PEXTP_MAC_SWRST] = 0 * RST_NR_PER_BANK + 6, ++ [MT7988_INFRA_RST1_THERM_CTRL_SWRST] = 1 * RST_NR_PER_BANK + 9, ++}; ++ ++static struct mtk_clk_rst_desc infra_rst_desc = { ++ .version = MTK_RST_SET_CLR, ++ .rst_bank_ofs = infra_rst_ofs, ++ .rst_bank_nr = ARRAY_SIZE(infra_rst_ofs), ++ .rst_idx_map = infra_idx_map, ++ .rst_idx_map_nr = ARRAY_SIZE(infra_idx_map), ++}; ++ + static const struct mtk_clk_desc infra_desc = { + .clks = infra_clks, + .num_clks = ARRAY_SIZE(infra_clks), + .mux_clks = infra_muxes, + .num_mux_clks = ARRAY_SIZE(infra_muxes), + .clk_lock = &mt7988_clk_lock, ++ .rst_desc = &infra_rst_desc, + }; + + static const struct of_device_id of_match_clk_mt7988_infracfg[] = { diff --git a/lede/target/linux/mediatek/patches-6.1/250-dt-bindings-reset-mediatek-add-MT7988-reset-IDs.patch b/lede/target/linux/mediatek/patches-6.1/250-dt-bindings-reset-mediatek-add-MT7988-reset-IDs.patch new file mode 100644 index 0000000000..d353074e84 --- /dev/null +++ b/lede/target/linux/mediatek/patches-6.1/250-dt-bindings-reset-mediatek-add-MT7988-reset-IDs.patch @@ -0,0 +1,25 @@ +From 3c810da3206f2e52c92f9f15a87f05db4bbba734 Mon Sep 17 00:00:00 2001 +From: Frank Wunderlich +Date: Wed, 17 Jan 2024 19:41:10 +0100 +Subject: [PATCH] dt-bindings: reset: mediatek: add MT7988 reset IDs + +Add reset constants for using as index in driver and dts. + +Signed-off-by: Frank Wunderlich +--- + include/dt-bindings/reset/mediatek,mt7988-resets.h | 6 ++++++ + 1 file changed, 6 insertions(+) + +--- a/include/dt-bindings/reset/mediatek,mt7988-resets.h ++++ b/include/dt-bindings/reset/mediatek,mt7988-resets.h +@@ -10,4 +10,10 @@ + /* ETHWARP resets */ + #define MT7988_ETHWARP_RST_SWITCH 0 + ++/* INFRA resets */ ++#define MT7988_INFRA_RST0_PEXTP_MAC_SWRST 0 ++#define MT7988_INFRA_RST1_THERM_CTRL_SWRST 1 ++ ++ + #endif /* _DT_BINDINGS_RESET_CONTROLLER_MT7988 */ ++ diff --git a/lede/target/linux/mediatek/patches-6.1/251-v6.8-watchdog-mediatek-mt7988-add-wdt-support.patch b/lede/target/linux/mediatek/patches-6.1/251-v6.8-watchdog-mediatek-mt7988-add-wdt-support.patch new file mode 100644 index 0000000000..cb49ce1d25 --- /dev/null +++ b/lede/target/linux/mediatek/patches-6.1/251-v6.8-watchdog-mediatek-mt7988-add-wdt-support.patch @@ -0,0 +1,125 @@ +From 137c9e08e5e542d58aa606b0bb4f0990117309a0 Mon Sep 17 00:00:00 2001 +From: Daniel Golle +Date: Mon, 20 Nov 2023 18:22:31 +0000 +Subject: [PATCH] watchdog: mediatek: mt7988: add wdt support + +Add support for watchdog and reset generator unit of the MediaTek +MT7988 SoC. + +Signed-off-by: Daniel Golle +Reviewed-by: AngeloGioacchino Del Regno +Reviewed-by: Guenter Roeck +Link: https://lore.kernel.org/r/c0cf5f701801cce60470853fa15f1d9dced78c4f.1700504385.git.daniel@makrotopia.org +Signed-off-by: Guenter Roeck +Signed-off-by: Wim Van Sebroeck +--- + drivers/watchdog/mtk_wdt.c | 42 ++++++++++++++++++++++++++++++++++++++ + 1 file changed, 42 insertions(+) + +--- a/drivers/watchdog/mtk_wdt.c ++++ b/drivers/watchdog/mtk_wdt.c +@@ -56,9 +56,13 @@ + #define WDT_SWSYSRST 0x18U + #define WDT_SWSYS_RST_KEY 0x88000000 + ++#define WDT_SWSYSRST_EN 0xfc ++ + #define DRV_NAME "mtk-wdt" + #define DRV_VERSION "1.0" + ++#define MT7988_TOPRGU_SW_RST_NUM 24 ++ + static bool nowayout = WATCHDOG_NOWAYOUT; + static unsigned int timeout; + +@@ -68,10 +72,12 @@ struct mtk_wdt_dev { + spinlock_t lock; /* protects WDT_SWSYSRST reg */ + struct reset_controller_dev rcdev; + bool disable_wdt_extrst; ++ bool has_swsysrst_en; + }; + + struct mtk_wdt_data { + int toprgu_sw_rst_num; ++ bool has_swsysrst_en; + }; + + static const struct mtk_wdt_data mt2712_data = { +@@ -82,6 +88,11 @@ static const struct mtk_wdt_data mt7986_ + .toprgu_sw_rst_num = MT7986_TOPRGU_SW_RST_NUM, + }; + ++static const struct mtk_wdt_data mt7988_data = { ++ .toprgu_sw_rst_num = MT7988_TOPRGU_SW_RST_NUM, ++ .has_swsysrst_en = true, ++}; ++ + static const struct mtk_wdt_data mt8183_data = { + .toprgu_sw_rst_num = MT8183_TOPRGU_SW_RST_NUM, + }; +@@ -98,6 +109,28 @@ static const struct mtk_wdt_data mt8195_ + .toprgu_sw_rst_num = MT8195_TOPRGU_SW_RST_NUM, + }; + ++/** ++ * toprgu_reset_sw_en_unlocked() - enable/disable software control for reset bit ++ * @data: Pointer to instance of driver data. ++ * @id: Bit number identifying the reset to be enabled or disabled. ++ * @enable: If true, enable software control for that bit, disable otherwise. ++ * ++ * Context: The caller must hold lock of struct mtk_wdt_dev. ++ */ ++static void toprgu_reset_sw_en_unlocked(struct mtk_wdt_dev *data, ++ unsigned long id, bool enable) ++{ ++ u32 tmp; ++ ++ tmp = readl(data->wdt_base + WDT_SWSYSRST_EN); ++ if (enable) ++ tmp |= BIT(id); ++ else ++ tmp &= ~BIT(id); ++ ++ writel(tmp, data->wdt_base + WDT_SWSYSRST_EN); ++} ++ + static int toprgu_reset_update(struct reset_controller_dev *rcdev, + unsigned long id, bool assert) + { +@@ -108,6 +141,9 @@ static int toprgu_reset_update(struct re + + spin_lock_irqsave(&data->lock, flags); + ++ if (assert && data->has_swsysrst_en) ++ toprgu_reset_sw_en_unlocked(data, id, true); ++ + tmp = readl(data->wdt_base + WDT_SWSYSRST); + if (assert) + tmp |= BIT(id); +@@ -116,6 +152,9 @@ static int toprgu_reset_update(struct re + tmp |= WDT_SWSYS_RST_KEY; + writel(tmp, data->wdt_base + WDT_SWSYSRST); + ++ if (!assert && data->has_swsysrst_en) ++ toprgu_reset_sw_en_unlocked(data, id, false); ++ + spin_unlock_irqrestore(&data->lock, flags); + + return 0; +@@ -393,6 +432,8 @@ static int mtk_wdt_probe(struct platform + wdt_data->toprgu_sw_rst_num); + if (err) + return err; ++ ++ mtk_wdt->has_swsysrst_en = wdt_data->has_swsysrst_en; + } + + mtk_wdt->disable_wdt_extrst = +@@ -427,6 +468,7 @@ static const struct of_device_id mtk_wdt + { .compatible = "mediatek,mt2712-wdt", .data = &mt2712_data }, + { .compatible = "mediatek,mt6589-wdt" }, + { .compatible = "mediatek,mt7986-wdt", .data = &mt7986_data }, ++ { .compatible = "mediatek,mt7988-wdt", .data = &mt7988_data }, + { .compatible = "mediatek,mt8183-wdt", .data = &mt8183_data }, + { .compatible = "mediatek,mt8186-wdt", .data = &mt8186_data }, + { .compatible = "mediatek,mt8192-wdt", .data = &mt8192_data }, diff --git a/lede/target/linux/mediatek/patches-6.1/252-clk-mediatek-mt7988-infracfg-fix-clocks-for-2nd-PCIe.patch b/lede/target/linux/mediatek/patches-6.1/252-clk-mediatek-mt7988-infracfg-fix-clocks-for-2nd-PCIe.patch new file mode 100644 index 0000000000..c4760b9eff --- /dev/null +++ b/lede/target/linux/mediatek/patches-6.1/252-clk-mediatek-mt7988-infracfg-fix-clocks-for-2nd-PCIe.patch @@ -0,0 +1,31 @@ +From c202f510bbaa34ab5d65a69a61e0e72761374b17 Mon Sep 17 00:00:00 2001 +From: Daniel Golle +Date: Mon, 11 Mar 2024 17:14:19 +0000 +Subject: [PATCH] clk: mediatek: mt7988-infracfg: fix clocks for 2nd PCIe port + +Due to what seems to be an undocumented oddity in MediaTek's MT7988 +SoC design the CLK_INFRA_PCIE_PERI_26M_CK_P2 clock requires +CLK_INFRA_PCIE_PERI_26M_CK_P3 to be enabled. + +This currently leads to PCIe port 2 not working in Linux. + +Reflect the apparent relationship in the clk driver to make sure PCIe +port 2 of the MT7988 SoC works. + +Suggested-by: Sam Shih +Signed-off-by: Daniel Golle +--- + drivers/clk/mediatek/clk-mt7988-infracfg.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/drivers/clk/mediatek/clk-mt7988-infracfg.c ++++ b/drivers/clk/mediatek/clk-mt7988-infracfg.c +@@ -156,7 +156,7 @@ static const struct mtk_gate infra_clks[ + GATE_INFRA0(CLK_INFRA_PCIE_PERI_26M_CK_P1, "infra_pcie_peri_ck_26m_ck_p1", + "csw_infra_f26m_sel", 8), + GATE_INFRA0(CLK_INFRA_PCIE_PERI_26M_CK_P2, "infra_pcie_peri_ck_26m_ck_p2", +- "csw_infra_f26m_sel", 9), ++ "infra_pcie_peri_ck_26m_ck_p3", 9), + GATE_INFRA0(CLK_INFRA_PCIE_PERI_26M_CK_P3, "infra_pcie_peri_ck_26m_ck_p3", + "csw_infra_f26m_sel", 10), + /* INFRA1 */ diff --git a/lede/target/linux/mediatek/patches-6.1/253-pinctrl-mediatek-mt7981-add-additional-uart-group.patch b/lede/target/linux/mediatek/patches-6.1/253-pinctrl-mediatek-mt7981-add-additional-uart-group.patch new file mode 100644 index 0000000000..1e53777d65 --- /dev/null +++ b/lede/target/linux/mediatek/patches-6.1/253-pinctrl-mediatek-mt7981-add-additional-uart-group.patch @@ -0,0 +1,63 @@ +From patchwork Wed Jan 17 12:42:33 2024 +Content-Type: text/plain; charset="utf-8" +MIME-Version: 1.0 +Content-Transfer-Encoding: 7bit +X-Patchwork-Submitter: Jean Thomas +X-Patchwork-Id: 13521682 +Return-Path: + +From: Jean Thomas +To: sean.wang@kernel.org, + linus.walleij@linaro.org, + matthias.bgg@gmail.com, + angelogioacchino.delregno@collabora.com, + linux-mediatek@lists.infradead.org, + linux-gpio@vger.kernel.org, + linux-kernel@vger.kernel.org, + linux-arm-kernel@lists.infradead.org +Cc: Jean Thomas +Subject: [PATCH 1/2] pinctrl: mediatek: mt7981: add additional uart group +Date: Wed, 17 Jan 2024 13:42:33 +0100 +Message-Id: <20240117124234.3137050-1-jean.thomas@wifirst.fr> +MIME-Version: 1.0 +List-Id: + +Add uart1_3 (pins 26, 27) group to the pinctrl driver for the +MediaTek MT7981 SoC. + +Signed-off-by: Jean Thomas +Reviewed-by: Daniel Golle +--- + drivers/pinctrl/mediatek/pinctrl-mt7981.c | 7 ++++++- + 1 file changed, 6 insertions(+), 1 deletion(-) + +--- a/drivers/pinctrl/mediatek/pinctrl-mt7981.c ++++ b/drivers/pinctrl/mediatek/pinctrl-mt7981.c +@@ -737,6 +737,9 @@ static int mt7981_uart1_1_funcs[] = { 2, + static int mt7981_uart1_2_pins[] = { 9, 10, }; + static int mt7981_uart1_2_funcs[] = { 2, 2, }; + ++static int mt7981_uart1_3_pins[] = { 26, 27, }; ++static int mt7981_uart1_3_funcs[] = { 2, 2, }; ++ + /* UART2 */ + static int mt7981_uart2_1_pins[] = { 22, 23, 24, 25, }; + static int mt7981_uart2_1_funcs[] = { 3, 3, 3, 3, }; +@@ -871,6 +874,8 @@ static const struct group_desc mt7981_gr + PINCTRL_PIN_GROUP("uart1_1", mt7981_uart1_1), + /* @GPIO(9,10): UART1(2) */ + PINCTRL_PIN_GROUP("uart1_2", mt7981_uart1_2), ++ /* @GPIO(26,27): UART1(2) */ ++ PINCTRL_PIN_GROUP("uart1_3", mt7981_uart1_3), + /* @GPIO(22,25): UART1(3) */ + PINCTRL_PIN_GROUP("uart2_1", mt7981_uart2_1), + /* @GPIO(22,24) PTA_EXT(4) */ +@@ -933,7 +938,7 @@ static const struct group_desc mt7981_gr + static const char *mt7981_wa_aice_groups[] = { "wa_aice1", "wa_aice2", "wm_aice1_1", + "wa_aice3", "wm_aice1_2", }; + static const char *mt7981_uart_groups[] = { "net_wo0_uart_txd_0", "net_wo0_uart_txd_1", +- "net_wo0_uart_txd_2", "uart0", "uart1_0", "uart1_1", "uart1_2", "uart2_0", ++ "net_wo0_uart_txd_2", "uart0", "uart1_0", "uart1_1", "uart1_2", "uart1_3", "uart2_0", + "uart2_0_tx_rx", "uart2_1", "wm_uart_0", "wm_aurt_1", "wm_aurt_2", }; + static const char *mt7981_dfd_groups[] = { "dfd", "dfd_ntrst", }; + static const char *mt7981_wdt_groups[] = { "watchdog", "watchdog1", }; diff --git a/lede/target/linux/mediatek/patches-6.1/254-pinctrl-mediatek-mt7981-add-additional-emmc-group.patch b/lede/target/linux/mediatek/patches-6.1/254-pinctrl-mediatek-mt7981-add-additional-emmc-group.patch new file mode 100644 index 0000000000..df4d82c9d9 --- /dev/null +++ b/lede/target/linux/mediatek/patches-6.1/254-pinctrl-mediatek-mt7981-add-additional-emmc-group.patch @@ -0,0 +1,82 @@ +From patchwork Wed Jan 17 14:55:47 2024 +Content-Type: text/plain; charset="utf-8" +MIME-Version: 1.0 +Content-Transfer-Encoding: 7bit +X-Patchwork-Submitter: Jean Thomas +X-Patchwork-Id: 13521855 +Return-Path: + +From: Jean Thomas +To: sean.wang@kernel.org, + linus.walleij@linaro.org, + matthias.bgg@gmail.com, + angelogioacchino.delregno@collabora.com, + linux-mediatek@lists.infradead.org, + linux-gpio@vger.kernel.org, + linux-kernel@vger.kernel.org, + linux-arm-kernel@lists.infradead.org +Cc: Jean Thomas , + Daniel Golle +Subject: [PATCH v2 2/2] pinctrl: mediatek: mt7981: add additional emmc groups +Date: Wed, 17 Jan 2024 15:55:47 +0100 +Message-Id: <20240117145547.3354242-1-jean.thomas@wifirst.fr> +List-Id: + +Add new emmc groups in the pinctrl driver for the +MediaTek MT7981 SoC: +* emmc reset, with pin 15. +* emmc 4-bit bus-width, with pins 16 to 19, and 24 to 25. +* emmc 8-bit bus-width, with pins 16 to 25. + +The existing emmc_45 group is kept for legacy reasons, even +if this is the union of emmc_reset and emmc_8 groups. + +Signed-off-by: Jean Thomas +Reviewed-by: Daniel Golle +--- + drivers/pinctrl/mediatek/pinctrl-mt7981.c | 17 ++++++++++++++++- + 1 file changed, 16 insertions(+), 1 deletion(-) + +-- +2.39.2 + +--- a/drivers/pinctrl/mediatek/pinctrl-mt7981.c ++++ b/drivers/pinctrl/mediatek/pinctrl-mt7981.c +@@ -700,6 +700,15 @@ static int mt7981_drv_vbus_pins[] = { 14 + static int mt7981_drv_vbus_funcs[] = { 1, }; + + /* EMMC */ ++static int mt7981_emmc_reset_pins[] = { 15, }; ++static int mt7981_emmc_reset_funcs[] = { 2, }; ++ ++static int mt7981_emmc_4_pins[] = { 16, 17, 18, 19, 24, 25, }; ++static int mt7981_emmc_4_funcs[] = { 2, 2, 2, 2, 2, 2, }; ++ ++static int mt7981_emmc_8_pins[] = { 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, }; ++static int mt7981_emmc_8_funcs[] = { 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, }; ++ + static int mt7981_emmc_45_pins[] = { 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, }; + static int mt7981_emmc_45_funcs[] = { 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, }; + +@@ -854,6 +863,12 @@ static const struct group_desc mt7981_gr + PINCTRL_PIN_GROUP("udi", mt7981_udi), + /* @GPIO(14) DRV_VBUS(1) */ + PINCTRL_PIN_GROUP("drv_vbus", mt7981_drv_vbus), ++ /* @GPIO(15): EMMC_RSTB(2) */ ++ PINCTRL_PIN_GROUP("emmc_reset", mt7981_emmc_reset), ++ /* @GPIO(16,17,18,19,24,25): EMMC_DATx, EMMC_CLK, EMMC_CMD */ ++ PINCTRL_PIN_GROUP("emmc_4", mt7981_emmc_4), ++ /* @GPIO(16,17,18,19,20,21,22,23,24,25): EMMC_DATx, EMMC_CLK, EMMC_CMD */ ++ PINCTRL_PIN_GROUP("emmc_8", mt7981_emmc_8), + /* @GPIO(15,25): EMMC(2) */ + PINCTRL_PIN_GROUP("emmc_45", mt7981_emmc_45), + /* @GPIO(16,21): SNFI(3) */ +@@ -957,7 +972,7 @@ static const char *mt7981_i2c_groups[] = + static const char *mt7981_pcm_groups[] = { "pcm", }; + static const char *mt7981_udi_groups[] = { "udi", }; + static const char *mt7981_usb_groups[] = { "drv_vbus", }; +-static const char *mt7981_flash_groups[] = { "emmc_45", "snfi", }; ++static const char *mt7981_flash_groups[] = { "emmc_reset", "emmc_4", "emmc_8", "emmc_45", "snfi", }; + static const char *mt7981_ethernet_groups[] = { "smi_mdc_mdio", "gbe_ext_mdc_mdio", + "wf0_mode1", "wf0_mode3", "mt7531_int", }; + static const char *mt7981_ant_groups[] = { "ant_sel", }; diff --git a/lede/target/linux/mediatek/patches-6.1/331-mt7622-rfb1-enable-bmt.patch b/lede/target/linux/mediatek/patches-6.1/331-mt7622-rfb1-enable-bmt.patch index 9c1a8f284a..a6f98fdf83 100644 --- a/lede/target/linux/mediatek/patches-6.1/331-mt7622-rfb1-enable-bmt.patch +++ b/lede/target/linux/mediatek/patches-6.1/331-mt7622-rfb1-enable-bmt.patch @@ -1,6 +1,6 @@ --- a/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts +++ b/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts -@@ -553,6 +553,7 @@ +@@ -549,6 +549,7 @@ spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; nand-ecc-engine = <&snfi>; diff --git a/lede/target/linux/mediatek/patches-6.1/340-mtd-spinand-Add-support-for-the-Fidelix-FM35X1GA.patch b/lede/target/linux/mediatek/patches-6.1/340-mtd-spinand-Add-support-for-the-Fidelix-FM35X1GA.patch index b00c6fc3fb..ec66363dc9 100644 --- a/lede/target/linux/mediatek/patches-6.1/340-mtd-spinand-Add-support-for-the-Fidelix-FM35X1GA.patch +++ b/lede/target/linux/mediatek/patches-6.1/340-mtd-spinand-Add-support-for-the-Fidelix-FM35X1GA.patch @@ -56,8 +56,8 @@ Signed-off-by: Davide Fioravanti + SPINAND_PROG_LOAD(true, 0, NULL, 0)); + +static SPINAND_OP_VARIANTS(update_cache_variants, -+ SPINAND_PROG_LOAD_X4(true, 0, NULL, 0), -+ SPINAND_PROG_LOAD(true, 0, NULL, 0)); ++ SPINAND_PROG_LOAD_X4(false, 0, NULL, 0), ++ SPINAND_PROG_LOAD(false, 0, NULL, 0)); + +static int fm35x1ga_ooblayout_ecc(struct mtd_info *mtd, int section, + struct mtd_oob_region *region) diff --git a/lede/target/linux/mediatek/patches-6.1/350-21-cpufreq-mediatek-Add-support-for-MT7988.patch b/lede/target/linux/mediatek/patches-6.1/350-21-cpufreq-mediatek-Add-support-for-MT7988.patch index 49cd62d0ae..96bc7cebd0 100644 --- a/lede/target/linux/mediatek/patches-6.1/350-21-cpufreq-mediatek-Add-support-for-MT7988.patch +++ b/lede/target/linux/mediatek/patches-6.1/350-21-cpufreq-mediatek-Add-support-for-MT7988.patch @@ -1,11 +1,31 @@ -From 4983a1517e7ddbc6f53fc07607e4ebeb51412843 Mon Sep 17 00:00:00 2001 +From patchwork Fri Apr 19 16:59:07 2024 +Content-Type: text/plain; charset="utf-8" +MIME-Version: 1.0 +Content-Transfer-Encoding: 7bit +X-Patchwork-Submitter: Daniel Golle +X-Patchwork-Id: 13636668 +Return-Path: + +Date: Fri, 19 Apr 2024 17:59:07 +0100 +From: Daniel Golle +To: "Rafael J. Wysocki" , + Viresh Kumar , + Matthias Brugger , + AngeloGioacchino Del Regno , + linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, + linux-arm-kernel@lists.infradead.org, + linux-mediatek@lists.infradead.org +Subject: [PATCH] cpufreq: mediatek: Add support for MT7988A +Message-ID: + +Content-Disposition: inline +List-Id: + From: Sam Shih -Date: Tue, 28 Feb 2023 19:59:22 +0800 -Subject: [PATCH 21/21] cpufreq: mediatek: Add support for MT7988 -This add cpufreq support for mediatek MT7988 SoC. +This add cpufreq support for mediatek MT7988A SoC. -The platform data of MT7988 is different from previous MediaTek SoCs, +The platform data of MT7988A is different from previous MediaTek SoCs, so we add a new compatible and platform data for it. Signed-off-by: Sam Shih @@ -35,7 +55,7 @@ Signed-off-by: Sam Shih { .compatible = "mediatek,mt2712", .data = &mt2701_platform_data }, { .compatible = "mediatek,mt7622", .data = &mt7622_platform_data }, { .compatible = "mediatek,mt7623", .data = &mt7623_platform_data }, -+ { .compatible = "mediatek,mt7988", .data = &mt7988_platform_data }, ++ { .compatible = "mediatek,mt7988a", .data = &mt7988_platform_data }, { .compatible = "mediatek,mt8167", .data = &mt8516_platform_data }, { .compatible = "mediatek,mt817x", .data = &mt2701_platform_data }, { .compatible = "mediatek,mt8173", .data = &mt2701_platform_data }, diff --git a/lede/target/linux/mediatek/patches-6.1/351-pinctrl-add-mt7988-pd-pulltype-support.patch b/lede/target/linux/mediatek/patches-6.1/351-pinctrl-add-mt7988-pd-pulltype-support.patch new file mode 100644 index 0000000000..1fcb1e64c7 --- /dev/null +++ b/lede/target/linux/mediatek/patches-6.1/351-pinctrl-add-mt7988-pd-pulltype-support.patch @@ -0,0 +1,99 @@ +--- a/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c ++++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c +@@ -601,6 +601,30 @@ out: + return err; + } + ++static int mtk_pinconf_bias_set_pd(struct mtk_pinctrl *hw, ++ const struct mtk_pin_desc *desc, ++ u32 pullup, u32 arg) ++{ ++ int err, pd; ++ ++ if (arg == MTK_DISABLE) ++ pd = 0; ++ else if ((arg == MTK_ENABLE) && pullup) ++ pd = 0; ++ else if ((arg == MTK_ENABLE) && !pullup) ++ pd = 1; ++ else { ++ err = -EINVAL; ++ goto out; ++ } ++ ++ err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_PD, pd); ++ ++out: ++ return err; ++ ++} ++ + static int mtk_pinconf_bias_set_pullsel_pullen(struct mtk_pinctrl *hw, + const struct mtk_pin_desc *desc, + u32 pullup, u32 arg) +@@ -755,6 +779,12 @@ int mtk_pinconf_bias_set_combo(struct mt + return err; + } + ++ if (try_all_type & MTK_PULL_PD_TYPE) { ++ err = mtk_pinconf_bias_set_pd(hw, desc, pullup, arg); ++ if (!err) ++ return err; ++ } ++ + if (try_all_type & MTK_PULL_PU_PD_TYPE) { + err = mtk_pinconf_bias_set_pu_pd(hw, desc, pullup, arg); + if (!err) +@@ -875,6 +905,29 @@ out: + return err; + } + ++static int mtk_pinconf_bias_get_pd(struct mtk_pinctrl *hw, ++ const struct mtk_pin_desc *desc, ++ u32 *pullup, u32 *enable) ++{ ++ int err, pd; ++ ++ err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_PD, &pd); ++ if (err) ++ goto out; ++ ++ if (pd == 0) { ++ *pullup = 0; ++ *enable = MTK_DISABLE; ++ } else if (pd == 1) { ++ *pullup = 0; ++ *enable = MTK_ENABLE; ++ } else ++ err = -EINVAL; ++ ++out: ++ return err; ++} ++ + static int mtk_pinconf_bias_get_pullsel_pullen(struct mtk_pinctrl *hw, + const struct mtk_pin_desc *desc, + u32 *pullup, u32 *enable) +@@ -943,6 +996,12 @@ int mtk_pinconf_bias_get_combo(struct mt + if (!err) + return err; + } ++ ++ if (try_all_type & MTK_PULL_PD_TYPE) { ++ err = mtk_pinconf_bias_get_pd(hw, desc, pullup, enable); ++ if (!err) ++ return err; ++ } + + if (try_all_type & MTK_PULL_PU_PD_TYPE) { + err = mtk_pinconf_bias_get_pu_pd(hw, desc, pullup, enable); +--- a/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.h ++++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.h +@@ -24,6 +24,7 @@ + * turned on/off itself. But it can't be selected pull up/down + */ + #define MTK_PULL_RSEL_TYPE BIT(3) ++#define MTK_PULL_PD_TYPE BIT(4) + /* MTK_PULL_PU_PD_RSEL_TYPE is a type which is controlled by + * MTK_PULL_PU_PD_TYPE and MTK_PULL_RSEL_TYPE. + */ diff --git a/lede/target/linux/mediatek/patches-6.1/432-drivers-spi-Add-support-for-dynamic-calibration.patch b/lede/target/linux/mediatek/patches-6.1/432-drivers-spi-Add-support-for-dynamic-calibration.patch index 10e528dba8..b2c9df4386 100644 --- a/lede/target/linux/mediatek/patches-6.1/432-drivers-spi-Add-support-for-dynamic-calibration.patch +++ b/lede/target/linux/mediatek/patches-6.1/432-drivers-spi-Add-support-for-dynamic-calibration.patch @@ -11,7 +11,7 @@ Signed-off-by: SkyLake.Huang --- a/drivers/spi/spi.c +++ b/drivers/spi/spi.c -@@ -1389,6 +1389,70 @@ static int spi_transfer_wait(struct spi_ +@@ -1385,6 +1385,70 @@ static int spi_transfer_wait(struct spi_ return 0; } @@ -82,7 +82,7 @@ Signed-off-by: SkyLake.Huang static void _spi_transfer_delay_ns(u32 ns) { if (!ns) -@@ -2227,6 +2291,75 @@ void spi_flush_queue(struct spi_controll +@@ -2223,6 +2287,75 @@ void spi_flush_queue(struct spi_controll /*-------------------------------------------------------------------------*/ #if defined(CONFIG_OF) @@ -158,7 +158,7 @@ Signed-off-by: SkyLake.Huang static int of_spi_parse_dt(struct spi_controller *ctlr, struct spi_device *spi, struct device_node *nc) { -@@ -2345,6 +2478,10 @@ of_register_spi_device(struct spi_contro +@@ -2341,6 +2474,10 @@ of_register_spi_device(struct spi_contro if (rc) goto err_out; @@ -212,7 +212,7 @@ Signed-off-by: SkyLake.Huang static inline struct spi_driver *to_spi_driver(struct device_driver *drv) { return drv ? container_of(drv, struct spi_driver, driver) : NULL; -@@ -712,6 +746,11 @@ struct spi_controller { +@@ -703,6 +737,11 @@ struct spi_controller { void *dummy_rx; void *dummy_tx; @@ -224,7 +224,7 @@ Signed-off-by: SkyLake.Huang int (*fw_translate_cs)(struct spi_controller *ctlr, unsigned cs); /* -@@ -1555,6 +1594,9 @@ spi_register_board_info(struct spi_board +@@ -1510,6 +1549,9 @@ spi_register_board_info(struct spi_board { return 0; } #endif diff --git a/lede/target/linux/mediatek/patches-6.1/602-arm64-dts-mediatek-add-mt7622-pcie-slot-node.patch b/lede/target/linux/mediatek/patches-6.1/602-arm64-dts-mediatek-add-mt7622-pcie-slot-node.patch index d58082aa6f..bf479ab53b 100644 --- a/lede/target/linux/mediatek/patches-6.1/602-arm64-dts-mediatek-add-mt7622-pcie-slot-node.patch +++ b/lede/target/linux/mediatek/patches-6.1/602-arm64-dts-mediatek-add-mt7622-pcie-slot-node.patch @@ -1,6 +1,6 @@ --- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi -@@ -844,6 +844,12 @@ +@@ -849,6 +849,12 @@ #address-cells = <0>; #interrupt-cells = <1>; }; @@ -13,7 +13,7 @@ }; pcie1: pcie@1a145000 { -@@ -882,6 +888,12 @@ +@@ -887,6 +893,12 @@ #address-cells = <0>; #interrupt-cells = <1>; }; diff --git a/lede/target/linux/mediatek/patches-6.1/611-pcie-mediatek-gen3-PERST-for-100ms.patch b/lede/target/linux/mediatek/patches-6.1/611-pcie-mediatek-gen3-PERST-for-100ms.patch new file mode 100644 index 0000000000..32b4237d82 --- /dev/null +++ b/lede/target/linux/mediatek/patches-6.1/611-pcie-mediatek-gen3-PERST-for-100ms.patch @@ -0,0 +1,17 @@ +--- a/drivers/pci/controller/pcie-mediatek-gen3.c ++++ b/drivers/pci/controller/pcie-mediatek-gen3.c +@@ -375,7 +375,13 @@ static int mtk_pcie_startup_port(struct + msleep(100); + + /* De-assert reset signals */ +- val &= ~(PCIE_MAC_RSTB | PCIE_PHY_RSTB | PCIE_BRG_RSTB | PCIE_PE_RSTB); ++ val &= ~(PCIE_MAC_RSTB | PCIE_PHY_RSTB | PCIE_BRG_RSTB); ++ writel_relaxed(val, pcie->base + PCIE_RST_CTRL_REG); ++ ++ msleep(100); ++ ++ /* De-assert PERST# signals */ ++ val &= ~(PCIE_PE_RSTB); + writel_relaxed(val, pcie->base + PCIE_RST_CTRL_REG); + + /* Check if the link is up or not */ diff --git a/lede/target/linux/mediatek/patches-6.1/615-phy-phy-mtk-xsphy-support-type-switch-by-pericfg.patch b/lede/target/linux/mediatek/patches-6.1/615-phy-phy-mtk-xsphy-support-type-switch-by-pericfg.patch new file mode 100644 index 0000000000..a597f70caa --- /dev/null +++ b/lede/target/linux/mediatek/patches-6.1/615-phy-phy-mtk-xsphy-support-type-switch-by-pericfg.patch @@ -0,0 +1,167 @@ +From 50cefacc6c001eea1d9b1c78ba27304566f304f1 Mon Sep 17 00:00:00 2001 +From: Daniel Golle +Date: Fri, 2 Jun 2023 13:06:26 +0800 +Subject: [PATCH] phy: mediatek: xsphy: support type switch by pericfg + +Patch from Sam Shih found in MediaTek SDK +released under GPL. + +Get syscon and use it to set the PHY type. +Extend support to PCIe and SGMII mode in addition to USB2 and USB3. + +Signed-off-by: Daniel Golle +--- + drivers/phy/mediatek/phy-mtk-xsphy.c | 81 +++++++++++++++++++++++++++- + 1 file changed, 80 insertions(+), 1 deletion(-) + +--- a/drivers/phy/mediatek/phy-mtk-xsphy.c ++++ b/drivers/phy/mediatek/phy-mtk-xsphy.c +@@ -11,10 +11,12 @@ + #include + #include + #include ++#include + #include + #include + #include + #include ++#include + + #include "phy-mtk-io.h" + +@@ -81,12 +83,22 @@ + #define XSP_SR_COEF_DIVISOR 1000 + #define XSP_FM_DET_CYCLE_CNT 1024 + ++/* PHY switch between pcie/usb3/sgmii */ ++#define USB_PHY_SWITCH_CTRL 0x0 ++#define RG_PHY_SW_TYPE GENMASK(3, 0) ++#define RG_PHY_SW_PCIE 0x0 ++#define RG_PHY_SW_USB3 0x1 ++#define RG_PHY_SW_SGMII 0x2 ++ + struct xsphy_instance { + struct phy *phy; + void __iomem *port_base; + struct clk *ref_clk; /* reference clock of anolog phy */ + u32 index; + u32 type; ++ struct regmap *type_sw; ++ u32 type_sw_reg; ++ u32 type_sw_index; + /* only for HQA test */ + int efuse_intr; + int efuse_tx_imp; +@@ -259,6 +271,10 @@ static void phy_parse_property(struct mt + inst->efuse_intr, inst->efuse_tx_imp, + inst->efuse_rx_imp); + break; ++ case PHY_TYPE_PCIE: ++ case PHY_TYPE_SGMII: ++ /* nothing to do */ ++ break; + default: + dev_err(xsphy->dev, "incompatible phy type\n"); + return; +@@ -305,6 +321,62 @@ static void u3_phy_props_set(struct mtk_ + RG_XTP_LN0_RX_IMPSEL, inst->efuse_rx_imp); + } + ++/* type switch for usb3/pcie/sgmii */ ++static int phy_type_syscon_get(struct xsphy_instance *instance, ++ struct device_node *dn) ++{ ++ struct of_phandle_args args; ++ int ret; ++ ++ /* type switch function is optional */ ++ if (!of_property_read_bool(dn, "mediatek,syscon-type")) ++ return 0; ++ ++ ret = of_parse_phandle_with_fixed_args(dn, "mediatek,syscon-type", ++ 2, 0, &args); ++ if (ret) ++ return ret; ++ ++ instance->type_sw_reg = args.args[0]; ++ instance->type_sw_index = args.args[1] & 0x3; /* <=3 */ ++ instance->type_sw = syscon_node_to_regmap(args.np); ++ of_node_put(args.np); ++ dev_info(&instance->phy->dev, "type_sw - reg %#x, index %d\n", ++ instance->type_sw_reg, instance->type_sw_index); ++ ++ return PTR_ERR_OR_ZERO(instance->type_sw); ++} ++ ++static int phy_type_set(struct xsphy_instance *instance) ++{ ++ int type; ++ u32 offset; ++ ++ if (!instance->type_sw) ++ return 0; ++ ++ switch (instance->type) { ++ case PHY_TYPE_USB3: ++ type = RG_PHY_SW_USB3; ++ break; ++ case PHY_TYPE_PCIE: ++ type = RG_PHY_SW_PCIE; ++ break; ++ case PHY_TYPE_SGMII: ++ type = RG_PHY_SW_SGMII; ++ break; ++ case PHY_TYPE_USB2: ++ default: ++ return 0; ++ } ++ ++ offset = instance->type_sw_index * BITS_PER_BYTE; ++ regmap_update_bits(instance->type_sw, instance->type_sw_reg, ++ RG_PHY_SW_TYPE << offset, type << offset); ++ ++ return 0; ++} ++ + static int mtk_phy_init(struct phy *phy) + { + struct xsphy_instance *inst = phy_get_drvdata(phy); +@@ -325,6 +397,10 @@ static int mtk_phy_init(struct phy *phy) + case PHY_TYPE_USB3: + u3_phy_props_set(xsphy, inst); + break; ++ case PHY_TYPE_PCIE: ++ case PHY_TYPE_SGMII: ++ /* nothing to do, only used to set type */ ++ break; + default: + dev_err(xsphy->dev, "incompatible phy type\n"); + clk_disable_unprepare(inst->ref_clk); +@@ -403,12 +479,15 @@ static struct phy *mtk_phy_xlate(struct + + inst->type = args->args[0]; + if (!(inst->type == PHY_TYPE_USB2 || +- inst->type == PHY_TYPE_USB3)) { ++ inst->type == PHY_TYPE_USB3 || ++ inst->type == PHY_TYPE_PCIE || ++ inst->type == PHY_TYPE_SGMII)) { + dev_err(dev, "unsupported phy type: %d\n", inst->type); + return ERR_PTR(-EINVAL); + } + + phy_parse_property(xsphy, inst); ++ phy_type_set(inst); + + return inst->phy; + } +@@ -515,6 +594,10 @@ static int mtk_xsphy_probe(struct platfo + retval = PTR_ERR(inst->ref_clk); + goto put_child; + } ++ ++ retval = phy_type_syscon_get(inst, child_np); ++ if (retval) ++ goto put_child; + } + + provider = devm_of_phy_provider_register(dev, mtk_phy_xlate); diff --git a/lede/target/linux/mediatek/patches-6.1/710-pci-pcie-mediatek-add-support-for-coherent-DMA.patch b/lede/target/linux/mediatek/patches-6.1/710-pci-pcie-mediatek-add-support-for-coherent-DMA.patch index 917a458d30..76ee2fc89a 100644 --- a/lede/target/linux/mediatek/patches-6.1/710-pci-pcie-mediatek-add-support-for-coherent-DMA.patch +++ b/lede/target/linux/mediatek/patches-6.1/710-pci-pcie-mediatek-add-support-for-coherent-DMA.patch @@ -10,7 +10,7 @@ Signed-off-by: Felix Fietkau --- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi -@@ -832,6 +832,9 @@ +@@ -837,6 +837,9 @@ bus-range = <0x00 0xff>; ranges = <0x82000000 0 0x20000000 0x0 0x20000000 0 0x8000000>; status = "disabled"; @@ -20,7 +20,7 @@ Signed-off-by: Felix Fietkau #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 7>; -@@ -876,6 +879,9 @@ +@@ -881,6 +884,9 @@ bus-range = <0x00 0xff>; ranges = <0x82000000 0 0x28000000 0x0 0x28000000 0 0x8000000>; status = "disabled"; @@ -30,15 +30,6 @@ Signed-off-by: Felix Fietkau #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 7>; -@@ -937,7 +943,7 @@ - }; - - hifsys: clock-controller@1af00000 { -- compatible = "mediatek,mt7622-hifsys"; -+ compatible = "mediatek,mt7622-hifsys", "syscon"; - reg = <0 0x1af00000 0 0x70>; - #clock-cells = <1>; - }; --- a/drivers/pci/controller/pcie-mediatek.c +++ b/drivers/pci/controller/pcie-mediatek.c @@ -20,6 +20,7 @@ diff --git a/lede/target/linux/mediatek/patches-6.1/732-net-phy-mxl-gpy-don-t-use-SGMII-AN-if-using-phylink.patch b/lede/target/linux/mediatek/patches-6.1/732-net-phy-mxl-gpy-don-t-use-SGMII-AN-if-using-phylink.patch index ecc77bd92a..76d8b0ef00 100644 --- a/lede/target/linux/mediatek/patches-6.1/732-net-phy-mxl-gpy-don-t-use-SGMII-AN-if-using-phylink.patch +++ b/lede/target/linux/mediatek/patches-6.1/732-net-phy-mxl-gpy-don-t-use-SGMII-AN-if-using-phylink.patch @@ -14,7 +14,7 @@ Signed-off-by: Daniel Golle --- a/drivers/net/phy/mxl-gpy.c +++ b/drivers/net/phy/mxl-gpy.c -@@ -377,8 +377,11 @@ static bool gpy_2500basex_chk(struct phy +@@ -371,8 +371,11 @@ static bool gpy_2500basex_chk(struct phy phydev->speed = SPEED_2500; phydev->interface = PHY_INTERFACE_MODE_2500BASEX; @@ -28,7 +28,7 @@ Signed-off-by: Daniel Golle return true; } -@@ -402,6 +405,14 @@ static int gpy_config_aneg(struct phy_de +@@ -396,6 +399,14 @@ static int gpy_config_aneg(struct phy_de u32 adv; int ret; @@ -43,7 +43,7 @@ Signed-off-by: Daniel Golle if (phydev->autoneg == AUTONEG_DISABLE) { /* Configure half duplex with genphy_setup_forced, * because genphy_c45_pma_setup_forced does not support. -@@ -492,6 +503,8 @@ static void gpy_update_interface(struct +@@ -486,6 +497,8 @@ static void gpy_update_interface(struct switch (phydev->speed) { case SPEED_2500: phydev->interface = PHY_INTERFACE_MODE_2500BASEX; @@ -52,7 +52,7 @@ Signed-off-by: Daniel Golle ret = phy_modify_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_SGMII_CTRL, VSPEC1_SGMII_CTRL_ANEN, 0); if (ret < 0) -@@ -503,7 +516,7 @@ static void gpy_update_interface(struct +@@ -497,7 +510,7 @@ static void gpy_update_interface(struct case SPEED_100: case SPEED_10: phydev->interface = PHY_INTERFACE_MODE_SGMII; diff --git a/lede/target/linux/mediatek/patches-6.1/734-v6.8-net-phy-mediatek-ge-soc-sync-driver-with-MediaTek-SD.patch b/lede/target/linux/mediatek/patches-6.1/734-v6.8-net-phy-mediatek-ge-soc-sync-driver-with-MediaTek-SD.patch new file mode 100644 index 0000000000..5daa62b6b7 --- /dev/null +++ b/lede/target/linux/mediatek/patches-6.1/734-v6.8-net-phy-mediatek-ge-soc-sync-driver-with-MediaTek-SD.patch @@ -0,0 +1,270 @@ +From f2195279c234c0f618946424b8236026126bc595 Mon Sep 17 00:00:00 2001 +Message-ID: +From: Daniel Golle +Date: Wed, 24 Jan 2024 02:27:04 +0000 +Subject: [PATCH net] net: phy: mediatek-ge-soc: sync driver with MediaTek SDK +To: Daniel Golle , + Qingfang Deng , + SkyLake Huang , + Andrew Lunn , + Heiner Kallweit , + Russell King , + David S. Miller , + Eric Dumazet , + Jakub Kicinski , + Paolo Abeni , + Matthias Brugger , + AngeloGioacchino Del Regno , + netdev@vger.kernel.org, + linux-kernel@vger.kernel.org, + linux-arm-kernel@lists.infradead.org, + linux-mediatek@lists.infradead.org + +Sync initialization and calibration routines with MediaTek's reference +driver. Improves compliance and resolves link stability issues with +CH340 IoT devices connected to MT798x built-in PHYs. + +Fixes: 98c485eaf509 ("net: phy: add driver for MediaTek SoC built-in GE PHYs") +Signed-off-by: Daniel Golle +--- + drivers/net/phy/mediatek-ge-soc.c | 147 ++++++++++++++++-------------- + 1 file changed, 81 insertions(+), 66 deletions(-) + +--- a/drivers/net/phy/mediatek-ge-soc.c ++++ b/drivers/net/phy/mediatek-ge-soc.c +@@ -491,7 +491,7 @@ static int tx_r50_fill_result(struct phy + u16 reg, val; + + if (phydev->drv->phy_id == MTK_GPHY_ID_MT7988) +- bias = -2; ++ bias = -1; + + val = clamp_val(bias + tx_r50_cal_val, 0, 63); + +@@ -707,6 +707,11 @@ restore: + static void mt798x_phy_common_finetune(struct phy_device *phydev) + { + phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_52B5); ++ /* SlvDSPreadyTime = 24, MasDSPreadyTime = 24 */ ++ __phy_write(phydev, 0x11, 0xc71); ++ __phy_write(phydev, 0x12, 0xc); ++ __phy_write(phydev, 0x10, 0x8fae); ++ + /* EnabRandUpdTrig = 1 */ + __phy_write(phydev, 0x11, 0x2f00); + __phy_write(phydev, 0x12, 0xe); +@@ -717,15 +722,56 @@ static void mt798x_phy_common_finetune(s + __phy_write(phydev, 0x12, 0x0); + __phy_write(phydev, 0x10, 0x83aa); + +- /* TrFreeze = 0 */ ++ /* FfeUpdGainForce = 1(Enable), FfeUpdGainForceVal = 4 */ ++ __phy_write(phydev, 0x11, 0x240); ++ __phy_write(phydev, 0x12, 0x0); ++ __phy_write(phydev, 0x10, 0x9680); ++ ++ /* TrFreeze = 0 (mt7988 default) */ + __phy_write(phydev, 0x11, 0x0); + __phy_write(phydev, 0x12, 0x0); + __phy_write(phydev, 0x10, 0x9686); + ++ /* SSTrKp100 = 5 */ ++ /* SSTrKf100 = 6 */ ++ /* SSTrKp1000Mas = 5 */ ++ /* SSTrKf1000Mas = 6 */ + /* SSTrKp1000Slv = 5 */ ++ /* SSTrKf1000Slv = 6 */ + __phy_write(phydev, 0x11, 0xbaef); + __phy_write(phydev, 0x12, 0x2e); + __phy_write(phydev, 0x10, 0x968c); ++ phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0); ++} ++ ++static void mt7981_phy_finetune(struct phy_device *phydev) ++{ ++ u16 val[8] = { 0x01ce, 0x01c1, ++ 0x020f, 0x0202, ++ 0x03d0, 0x03c0, ++ 0x0013, 0x0005 }; ++ int i, k; ++ ++ /* 100M eye finetune: ++ * Keep middle level of TX MLT3 shapper as default. ++ * Only change TX MLT3 overshoot level here. ++ */ ++ for (k = 0, i = 1; i < 12; i++) { ++ if (i % 3 == 0) ++ continue; ++ phy_write_mmd(phydev, MDIO_MMD_VEND1, i, val[k++]); ++ } ++ ++ phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_52B5); ++ /* ResetSyncOffset = 6 */ ++ __phy_write(phydev, 0x11, 0x600); ++ __phy_write(phydev, 0x12, 0x0); ++ __phy_write(phydev, 0x10, 0x8fc0); ++ ++ /* VgaDecRate = 1 */ ++ __phy_write(phydev, 0x11, 0x4c2a); ++ __phy_write(phydev, 0x12, 0x3e); ++ __phy_write(phydev, 0x10, 0x8fa4); + + /* MrvlTrFix100Kp = 3, MrvlTrFix100Kf = 2, + * MrvlTrFix1000Kp = 3, MrvlTrFix1000Kf = 2 +@@ -740,7 +786,7 @@ static void mt798x_phy_common_finetune(s + __phy_write(phydev, 0x10, 0x8ec0); + phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0); + +- /* TR_OPEN_LOOP_EN = 1, lpf_x_average = 9*/ ++ /* TR_OPEN_LOOP_EN = 1, lpf_x_average = 9 */ + phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG234, + MTK_PHY_TR_OPEN_LOOP_EN_MASK | MTK_PHY_LPF_X_AVERAGE_MASK, + BIT(0) | FIELD_PREP(MTK_PHY_LPF_X_AVERAGE_MASK, 0x9)); +@@ -773,48 +819,6 @@ static void mt798x_phy_common_finetune(s + phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_LDO_OUTPUT_V, 0x2222); + } + +-static void mt7981_phy_finetune(struct phy_device *phydev) +-{ +- u16 val[8] = { 0x01ce, 0x01c1, +- 0x020f, 0x0202, +- 0x03d0, 0x03c0, +- 0x0013, 0x0005 }; +- int i, k; +- +- /* 100M eye finetune: +- * Keep middle level of TX MLT3 shapper as default. +- * Only change TX MLT3 overshoot level here. +- */ +- for (k = 0, i = 1; i < 12; i++) { +- if (i % 3 == 0) +- continue; +- phy_write_mmd(phydev, MDIO_MMD_VEND1, i, val[k++]); +- } +- +- phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_52B5); +- /* SlvDSPreadyTime = 24, MasDSPreadyTime = 24 */ +- __phy_write(phydev, 0x11, 0xc71); +- __phy_write(phydev, 0x12, 0xc); +- __phy_write(phydev, 0x10, 0x8fae); +- +- /* ResetSyncOffset = 6 */ +- __phy_write(phydev, 0x11, 0x600); +- __phy_write(phydev, 0x12, 0x0); +- __phy_write(phydev, 0x10, 0x8fc0); +- +- /* VgaDecRate = 1 */ +- __phy_write(phydev, 0x11, 0x4c2a); +- __phy_write(phydev, 0x12, 0x3e); +- __phy_write(phydev, 0x10, 0x8fa4); +- +- /* FfeUpdGainForce = 4 */ +- __phy_write(phydev, 0x11, 0x240); +- __phy_write(phydev, 0x12, 0x0); +- __phy_write(phydev, 0x10, 0x9680); +- +- phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0); +-} +- + static void mt7988_phy_finetune(struct phy_device *phydev) + { + u16 val[12] = { 0x0187, 0x01cd, 0x01c8, 0x0182, +@@ -829,17 +833,7 @@ static void mt7988_phy_finetune(struct p + /* TCT finetune */ + phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_TX_FILTER, 0x5); + +- /* Disable TX power saving */ +- phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RXADC_CTRL_RG7, +- MTK_PHY_DA_AD_BUF_BIAS_LP_MASK, 0x3 << 8); +- + phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_52B5); +- +- /* SlvDSPreadyTime = 24, MasDSPreadyTime = 12 */ +- __phy_write(phydev, 0x11, 0x671); +- __phy_write(phydev, 0x12, 0xc); +- __phy_write(phydev, 0x10, 0x8fae); +- + /* ResetSyncOffset = 5 */ + __phy_write(phydev, 0x11, 0x500); + __phy_write(phydev, 0x12, 0x0); +@@ -847,13 +841,27 @@ static void mt7988_phy_finetune(struct p + + /* VgaDecRate is 1 at default on mt7988 */ + +- phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0); ++ /* MrvlTrFix100Kp = 6, MrvlTrFix100Kf = 7, ++ * MrvlTrFix1000Kp = 6, MrvlTrFix1000Kf = 7 ++ */ ++ __phy_write(phydev, 0x11, 0xb90a); ++ __phy_write(phydev, 0x12, 0x6f); ++ __phy_write(phydev, 0x10, 0x8f82); ++ ++ /* RemAckCntLimitCtrl = 1 */ ++ __phy_write(phydev, 0x11, 0xfbba); ++ __phy_write(phydev, 0x12, 0xc3); ++ __phy_write(phydev, 0x10, 0x87f8); + +- phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_2A30); +- /* TxClkOffset = 2 */ +- __phy_modify(phydev, MTK_PHY_ANARG_RG, MTK_PHY_TCLKOFFSET_MASK, +- FIELD_PREP(MTK_PHY_TCLKOFFSET_MASK, 0x2)); + phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0); ++ ++ /* TR_OPEN_LOOP_EN = 1, lpf_x_average = 10 */ ++ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG234, ++ MTK_PHY_TR_OPEN_LOOP_EN_MASK | MTK_PHY_LPF_X_AVERAGE_MASK, ++ BIT(0) | FIELD_PREP(MTK_PHY_LPF_X_AVERAGE_MASK, 0xa)); ++ ++ /* rg_tr_lpf_cnt_val = 1023 */ ++ phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LPF_CNT_VAL, 0x3ff); + } + + static void mt798x_phy_eee(struct phy_device *phydev) +@@ -886,11 +894,11 @@ static void mt798x_phy_eee(struct phy_de + MTK_PHY_LPI_SLV_SEND_TX_EN, + FIELD_PREP(MTK_PHY_LPI_SLV_SEND_TX_TIMER_MASK, 0x120)); + +- phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG239, +- MTK_PHY_LPI_SEND_LOC_TIMER_MASK | +- MTK_PHY_LPI_TXPCS_LOC_RCV, +- FIELD_PREP(MTK_PHY_LPI_SEND_LOC_TIMER_MASK, 0x117)); ++ /* Keep MTK_PHY_LPI_SEND_LOC_TIMER as 375 */ ++ phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG239, ++ MTK_PHY_LPI_TXPCS_LOC_RCV); + ++ /* This also fixes some IoT issues, such as CH340 */ + phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG2C7, + MTK_PHY_MAX_GAIN_MASK | MTK_PHY_MIN_GAIN_MASK, + FIELD_PREP(MTK_PHY_MAX_GAIN_MASK, 0x8) | +@@ -924,7 +932,7 @@ static void mt798x_phy_eee(struct phy_de + __phy_write(phydev, 0x12, 0x0); + __phy_write(phydev, 0x10, 0x9690); + +- /* REG_EEE_st2TrKf1000 = 3 */ ++ /* REG_EEE_st2TrKf1000 = 2 */ + __phy_write(phydev, 0x11, 0x114f); + __phy_write(phydev, 0x12, 0x2); + __phy_write(phydev, 0x10, 0x969a); +@@ -949,7 +957,7 @@ static void mt798x_phy_eee(struct phy_de + __phy_write(phydev, 0x12, 0x0); + __phy_write(phydev, 0x10, 0x96b8); + +- /* REGEEE_wake_slv_tr_wait_dfesigdet_en = 1 */ ++ /* REGEEE_wake_slv_tr_wait_dfesigdet_en = 0 */ + __phy_write(phydev, 0x11, 0x1463); + __phy_write(phydev, 0x12, 0x0); + __phy_write(phydev, 0x10, 0x96ca); +@@ -1461,6 +1469,13 @@ static int mt7988_phy_probe(struct phy_d + if (err) + return err; + ++ /* Disable TX power saving at probing to: ++ * 1. Meet common mode compliance test criteria ++ * 2. Make sure that TX-VCM calibration works fine ++ */ ++ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RXADC_CTRL_RG7, ++ MTK_PHY_DA_AD_BUF_BIAS_LP_MASK, 0x3 << 8); ++ + return mt798x_phy_calibration(phydev); + } + diff --git a/lede/target/linux/mediatek/patches-6.1/735-net-phy-add-Airoha-EN8801SC-PHY.patch b/lede/target/linux/mediatek/patches-6.1/735-net-phy-add-Airoha-EN8801SC-PHY.patch new file mode 100644 index 0000000000..51f2a197e9 --- /dev/null +++ b/lede/target/linux/mediatek/patches-6.1/735-net-phy-add-Airoha-EN8801SC-PHY.patch @@ -0,0 +1,38 @@ +From 5314e73cb941b47e6866b49b3b78c25e32d62df8 Mon Sep 17 00:00:00 2001 +From: Robert Marko +Date: Sat, 23 Mar 2024 20:21:14 +0100 +Subject: [PATCH] net: phy: add Airoha EN8801SC PHY + +Airoha EN8801SC Gigabit PHY is used on Edgecore EAP111, so include a +modified version of MTK SDK driver. + +Signed-off-by: Robert Marko +--- + drivers/net/phy/Kconfig | 5 +++++ + drivers/net/phy/Makefile | 1 + + 2 files changed, 6 insertions(+) + +--- a/drivers/net/phy/Kconfig ++++ b/drivers/net/phy/Kconfig +@@ -143,6 +143,11 @@ endif # RTL8366_SMI + + comment "MII PHY device drivers" + ++config AIROHA_EN8801SC_PHY ++ tristate "Airoha EN8801SC Gigabit PHY" ++ help ++ Currently supports the Airoha EN8801SC PHY. ++ + config AIR_EN8811H_PHY + tristate "Airoha EN8811H 2.5 Gigabit PHY" + help +--- a/drivers/net/phy/Makefile ++++ b/drivers/net/phy/Makefile +@@ -47,6 +47,7 @@ obj-y += $(sfp-obj-y) $(sfp-obj-m) + + obj-$(CONFIG_ADIN_PHY) += adin.o + obj-$(CONFIG_ADIN1100_PHY) += adin1100.o ++obj-$(CONFIG_AIROHA_EN8801SC_PHY) += en8801sc.o + obj-$(CONFIG_AIR_EN8811H_PHY) += air_en8811h.o + obj-$(CONFIG_AMD_PHY) += amd.o + obj-$(CONFIG_AQUANTIA_PHY) += aquantia/ diff --git a/lede/target/linux/mediatek/patches-6.1/804-pwm-add-mt7986-support.patch b/lede/target/linux/mediatek/patches-6.1/804-v6.2-pwm-add-mt7986-support.patch similarity index 100% rename from lede/target/linux/mediatek/patches-6.1/804-pwm-add-mt7986-support.patch rename to lede/target/linux/mediatek/patches-6.1/804-v6.2-pwm-add-mt7986-support.patch diff --git a/lede/target/linux/mediatek/patches-6.1/805-v6.5-pwm-mediatek-Add-support-for-MT7981.patch b/lede/target/linux/mediatek/patches-6.1/805-v6.5-pwm-mediatek-Add-support-for-MT7981.patch new file mode 100644 index 0000000000..72feecadb1 --- /dev/null +++ b/lede/target/linux/mediatek/patches-6.1/805-v6.5-pwm-mediatek-Add-support-for-MT7981.patch @@ -0,0 +1,147 @@ +From 967da67a745fb73fd0fc7aa61fd197b76fceb273 Mon Sep 17 00:00:00 2001 +From: Daniel Golle +Date: Fri, 21 Apr 2023 00:23:21 +0100 +Subject: [PATCH] pwm: mediatek: Add support for MT7981 + +The PWM unit on MT7981 uses different register offsets than previous +MediaTek PWM units. Add support for these new offsets and add support +for PWM on MT7981 which has 3 PWM channels, one of them is typically +used for a temperature controlled fan. +While at it, also reorder pwm_mediatek_of_data entries to restore +alphabetic order. + +Signed-off-by: Daniel Golle +Reviewed-by: AngeloGioacchino Del Regno +Reviewed-by: Matthias Brugger +Signed-off-by: Thierry Reding +--- + drivers/pwm/pwm-mediatek.c | 39 ++++++++++++++++++++++++++++++-------- + 1 file changed, 31 insertions(+), 8 deletions(-) + +--- a/drivers/pwm/pwm-mediatek.c ++++ b/drivers/pwm/pwm-mediatek.c +@@ -38,6 +38,7 @@ struct pwm_mediatek_of_data { + unsigned int num_pwms; + bool pwm45_fixup; + bool has_ck_26m_sel; ++ const unsigned int *reg_offset; + }; + + /** +@@ -59,10 +60,14 @@ struct pwm_mediatek_chip { + const struct pwm_mediatek_of_data *soc; + }; + +-static const unsigned int pwm_mediatek_reg_offset[] = { ++static const unsigned int mtk_pwm_reg_offset_v1[] = { + 0x0010, 0x0050, 0x0090, 0x00d0, 0x0110, 0x0150, 0x0190, 0x0220 + }; + ++static const unsigned int mtk_pwm_reg_offset_v2[] = { ++ 0x0080, 0x00c0, 0x0100, 0x0140, 0x0180, 0x01c0, 0x0200, 0x0240 ++}; ++ + static inline struct pwm_mediatek_chip * + to_pwm_mediatek_chip(struct pwm_chip *chip) + { +@@ -111,7 +116,7 @@ static inline void pwm_mediatek_writel(s + unsigned int num, unsigned int offset, + u32 value) + { +- writel(value, chip->regs + pwm_mediatek_reg_offset[num] + offset); ++ writel(value, chip->regs + chip->soc->reg_offset[num] + offset); + } + + static int pwm_mediatek_config(struct pwm_chip *chip, struct pwm_device *pwm, +@@ -285,60 +290,77 @@ static const struct pwm_mediatek_of_data + .num_pwms = 8, + .pwm45_fixup = false, + .has_ck_26m_sel = false, ++ .reg_offset = mtk_pwm_reg_offset_v1, + }; + + static const struct pwm_mediatek_of_data mt6795_pwm_data = { + .num_pwms = 7, + .pwm45_fixup = false, + .has_ck_26m_sel = false, ++ .reg_offset = mtk_pwm_reg_offset_v1, + }; + + static const struct pwm_mediatek_of_data mt7622_pwm_data = { + .num_pwms = 6, + .pwm45_fixup = false, + .has_ck_26m_sel = true, ++ .reg_offset = mtk_pwm_reg_offset_v1, + }; + + static const struct pwm_mediatek_of_data mt7623_pwm_data = { + .num_pwms = 5, + .pwm45_fixup = true, + .has_ck_26m_sel = false, ++ .reg_offset = mtk_pwm_reg_offset_v1, + }; + + static const struct pwm_mediatek_of_data mt7628_pwm_data = { + .num_pwms = 4, + .pwm45_fixup = true, + .has_ck_26m_sel = false, ++ .reg_offset = mtk_pwm_reg_offset_v1, + }; + + static const struct pwm_mediatek_of_data mt7629_pwm_data = { + .num_pwms = 1, + .pwm45_fixup = false, + .has_ck_26m_sel = false, ++ .reg_offset = mtk_pwm_reg_offset_v1, + }; + +-static const struct pwm_mediatek_of_data mt8183_pwm_data = { +- .num_pwms = 4, ++static const struct pwm_mediatek_of_data mt7981_pwm_data = { ++ .num_pwms = 3, + .pwm45_fixup = false, + .has_ck_26m_sel = true, ++ .reg_offset = mtk_pwm_reg_offset_v2, + }; + +-static const struct pwm_mediatek_of_data mt8365_pwm_data = { +- .num_pwms = 3, ++static const struct pwm_mediatek_of_data mt7986_pwm_data = { ++ .num_pwms = 2, + .pwm45_fixup = false, + .has_ck_26m_sel = true, ++ .reg_offset = mtk_pwm_reg_offset_v1, + }; + +-static const struct pwm_mediatek_of_data mt7986_pwm_data = { +- .num_pwms = 2, ++static const struct pwm_mediatek_of_data mt8183_pwm_data = { ++ .num_pwms = 4, ++ .pwm45_fixup = false, ++ .has_ck_26m_sel = true, ++ .reg_offset = mtk_pwm_reg_offset_v1, ++}; ++ ++static const struct pwm_mediatek_of_data mt8365_pwm_data = { ++ .num_pwms = 3, + .pwm45_fixup = false, + .has_ck_26m_sel = true, ++ .reg_offset = mtk_pwm_reg_offset_v1, + }; + + static const struct pwm_mediatek_of_data mt8516_pwm_data = { + .num_pwms = 5, + .pwm45_fixup = false, + .has_ck_26m_sel = true, ++ .reg_offset = mtk_pwm_reg_offset_v1, + }; + + static const struct of_device_id pwm_mediatek_of_match[] = { +@@ -348,6 +370,7 @@ static const struct of_device_id pwm_med + { .compatible = "mediatek,mt7623-pwm", .data = &mt7623_pwm_data }, + { .compatible = "mediatek,mt7628-pwm", .data = &mt7628_pwm_data }, + { .compatible = "mediatek,mt7629-pwm", .data = &mt7629_pwm_data }, ++ { .compatible = "mediatek,mt7981-pwm", .data = &mt7981_pwm_data }, + { .compatible = "mediatek,mt7986-pwm", .data = &mt7986_pwm_data }, + { .compatible = "mediatek,mt8183-pwm", .data = &mt8183_pwm_data }, + { .compatible = "mediatek,mt8365-pwm", .data = &mt8365_pwm_data }, diff --git a/lede/target/linux/mediatek/patches-6.1/806-v6.9-pwm-mediatek-add-support-for-MT7988.patch b/lede/target/linux/mediatek/patches-6.1/806-v6.9-pwm-mediatek-add-support-for-MT7988.patch new file mode 100644 index 0000000000..00543a1bb1 --- /dev/null +++ b/lede/target/linux/mediatek/patches-6.1/806-v6.9-pwm-mediatek-add-support-for-MT7988.patch @@ -0,0 +1,44 @@ +From eb58bf4afd708eb3c64c7b9b2c5fbfacdcdee3e5 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= +Date: Wed, 14 Feb 2024 15:04:54 +0100 +Subject: [PATCH] pwm: mediatek: add support for MT7988 +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +MT7988 uses new registers layout just like MT7981 but it supports 8 PWM +interfaces. + +Signed-off-by: Rafał Miłecki +Reviewed-by: Daniel Golle +Reviewed-by: AngeloGioacchino Del Regno +Link: https://lore.kernel.org/r/20240214140454.6438-2-zajec5@gmail.com +Signed-off-by: Uwe Kleine-König +--- + drivers/pwm/pwm-mediatek.c | 8 ++++++++ + 1 file changed, 8 insertions(+) + +--- a/drivers/pwm/pwm-mediatek.c ++++ b/drivers/pwm/pwm-mediatek.c +@@ -342,6 +342,13 @@ static const struct pwm_mediatek_of_data + .reg_offset = mtk_pwm_reg_offset_v1, + }; + ++static const struct pwm_mediatek_of_data mt7988_pwm_data = { ++ .num_pwms = 8, ++ .pwm45_fixup = false, ++ .has_ck_26m_sel = false, ++ .reg_offset = mtk_pwm_reg_offset_v2, ++}; ++ + static const struct pwm_mediatek_of_data mt8183_pwm_data = { + .num_pwms = 4, + .pwm45_fixup = false, +@@ -372,6 +379,7 @@ static const struct of_device_id pwm_med + { .compatible = "mediatek,mt7629-pwm", .data = &mt7629_pwm_data }, + { .compatible = "mediatek,mt7981-pwm", .data = &mt7981_pwm_data }, + { .compatible = "mediatek,mt7986-pwm", .data = &mt7986_pwm_data }, ++ { .compatible = "mediatek,mt7988-pwm", .data = &mt7988_pwm_data }, + { .compatible = "mediatek,mt8183-pwm", .data = &mt8183_pwm_data }, + { .compatible = "mediatek,mt8365-pwm", .data = &mt8365_pwm_data }, + { .compatible = "mediatek,mt8516-pwm", .data = &mt8516_pwm_data }, diff --git a/lede/target/linux/mediatek/patches-6.1/830-v6.3-01-thermal-drivers-mtk_thermal-Fix-kernel-doc-function-.patch b/lede/target/linux/mediatek/patches-6.1/830-v6.3-01-thermal-drivers-mtk_thermal-Fix-kernel-doc-function-.patch new file mode 100644 index 0000000000..694b73a2b1 --- /dev/null +++ b/lede/target/linux/mediatek/patches-6.1/830-v6.3-01-thermal-drivers-mtk_thermal-Fix-kernel-doc-function-.patch @@ -0,0 +1,37 @@ +From f167da186acf90847e1a6d3716e253825a6218ec Mon Sep 17 00:00:00 2001 +From: Randy Dunlap +Date: Thu, 12 Jan 2023 22:44:49 -0800 +Subject: [PATCH 01/42] thermal/drivers/mtk_thermal: Fix kernel-doc function + name + +Use the correct function name in a kernel-doc comment to prevent +a warning: + +drivers/thermal/mtk_thermal.c:562: warning: expecting prototype for raw_to_mcelsius(). Prototype was for raw_to_mcelsius_v1() instead + +Signed-off-by: Randy Dunlap +Cc: "Rafael J. Wysocki" +Cc: Daniel Lezcano +Cc: Amit Kucheria +Cc: Zhang Rui +Cc: Matthias Brugger +Cc: linux-pm@vger.kernel.org +Cc: linux-arm-kernel@lists.infradead.org +Cc: linux-mediatek@lists.infradead.org +Link: https://lore.kernel.org/r/20230113064449.15061-1-rdunlap@infradead.org +Signed-off-by: Daniel Lezcano +--- + drivers/thermal/mtk_thermal.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/drivers/thermal/mtk_thermal.c ++++ b/drivers/thermal/mtk_thermal.c +@@ -550,7 +550,7 @@ static const struct mtk_thermal_data mt8 + }; + + /** +- * raw_to_mcelsius - convert a raw ADC value to mcelsius ++ * raw_to_mcelsius_v1 - convert a raw ADC value to mcelsius + * @mt: The thermal controller + * @sensno: sensor number + * @raw: raw ADC value diff --git a/lede/target/linux/mediatek/patches-6.1/830-v6.3-02-thermal-drivers-mtk_thermal-Use-devm_platform_get_an.patch b/lede/target/linux/mediatek/patches-6.1/830-v6.3-02-thermal-drivers-mtk_thermal-Use-devm_platform_get_an.patch new file mode 100644 index 0000000000..aaed9d7e90 --- /dev/null +++ b/lede/target/linux/mediatek/patches-6.1/830-v6.3-02-thermal-drivers-mtk_thermal-Use-devm_platform_get_an.patch @@ -0,0 +1,37 @@ +From 255509232417ee71fd606cb957d44cf6544f0c43 Mon Sep 17 00:00:00 2001 +From: ye xingchen +Date: Wed, 18 Jan 2023 16:37:47 +0800 +Subject: [PATCH 02/42] thermal/drivers/mtk_thermal: Use + devm_platform_get_and_ioremap_resource() + +Convert platform_get_resource(), devm_ioremap_resource() to a single +call to devm_platform_get_and_ioremap_resource(), as this is exactly +what this function does. + +Signed-off-by: ye xingchen +Link: https://lore.kernel.org/r/202301181637472073620@zte.com.cn +Signed-off-by: Daniel Lezcano +--- + drivers/thermal/mtk_thermal.c | 4 +--- + 1 file changed, 1 insertion(+), 3 deletions(-) + +--- a/drivers/thermal/mtk_thermal.c ++++ b/drivers/thermal/mtk_thermal.c +@@ -990,7 +990,6 @@ static int mtk_thermal_probe(struct plat + int ret, i, ctrl_id; + struct device_node *auxadc, *apmixedsys, *np = pdev->dev.of_node; + struct mtk_thermal *mt; +- struct resource *res; + u64 auxadc_phys_base, apmixed_phys_base; + struct thermal_zone_device *tzdev; + void __iomem *apmixed_base, *auxadc_base; +@@ -1009,8 +1008,7 @@ static int mtk_thermal_probe(struct plat + if (IS_ERR(mt->clk_auxadc)) + return PTR_ERR(mt->clk_auxadc); + +- res = platform_get_resource(pdev, IORESOURCE_MEM, 0); +- mt->thermal_base = devm_ioremap_resource(&pdev->dev, res); ++ mt->thermal_base = devm_platform_get_and_ioremap_resource(pdev, 0, NULL); + if (IS_ERR(mt->thermal_base)) + return PTR_ERR(mt->thermal_base); + diff --git a/lede/target/linux/mediatek/patches-6.1/805-v6.2-thermal-drivers-mtk-use-function-pointer-for-raw_to_.patch b/lede/target/linux/mediatek/patches-6.1/830-v6.3-03-thermal-drivers-mtk-Use-function-pointer-for-raw_to_.patch similarity index 75% rename from lede/target/linux/mediatek/patches-6.1/805-v6.2-thermal-drivers-mtk-use-function-pointer-for-raw_to_.patch rename to lede/target/linux/mediatek/patches-6.1/830-v6.3-03-thermal-drivers-mtk-Use-function-pointer-for-raw_to_.patch index c58ae96403..215b0fd7de 100644 --- a/lede/target/linux/mediatek/patches-6.1/805-v6.2-thermal-drivers-mtk-use-function-pointer-for-raw_to_.patch +++ b/lede/target/linux/mediatek/patches-6.1/830-v6.3-03-thermal-drivers-mtk-Use-function-pointer-for-raw_to_.patch @@ -1,7 +1,7 @@ -From 69c17529e8418da3eec703dde31e1b01e5b0f7e8 Mon Sep 17 00:00:00 2001 +From ca86dbd309ba03bef38ae91f037e2030bb671ab7 Mon Sep 17 00:00:00 2001 From: Daniel Golle -Date: Wed, 18 Jan 2023 02:48:41 +0000 -Subject: [PATCH 1/2] thermal/drivers/mtk: use function pointer for +Date: Wed, 18 Jan 2023 15:40:39 +0000 +Subject: [PATCH 03/42] thermal/drivers/mtk: Use function pointer for raw_to_mcelsius Instead of having if-else logic selecting either raw_to_mcelsius_v1 or @@ -9,7 +9,11 @@ raw_to_mcelsius_v2 in mtk_thermal_bank_temperature introduce a function pointer raw_to_mcelsius to struct mtk_thermal which is initialized in the probe function. +Reviewed-by: AngeloGioacchino Del Regno Signed-off-by: Daniel Golle +Reviewed-by: Matthias Brugger +Link: https://lore.kernel.org/r/69c17529e8418da3eec703dde31e1b01e5b0f7e8.1674055882.git.daniel@makrotopia.org +Signed-off-by: Daniel Lezcano --- drivers/thermal/mtk_thermal.c | 17 ++++++++++------- 1 file changed, 10 insertions(+), 7 deletions(-) @@ -42,7 +46,7 @@ Signed-off-by: Daniel Golle /* * The first read of a sensor often contains very high bogus -@@ -1075,6 +1073,11 @@ static int mtk_thermal_probe(struct plat +@@ -1073,6 +1071,11 @@ static int mtk_thermal_probe(struct plat mtk_thermal_release_periodic_ts(mt, auxadc_base); } diff --git a/lede/target/linux/mediatek/patches-6.1/806-v6.2-thermal-mediatek-add-support-for-MT7986-and-MT7981.patch b/lede/target/linux/mediatek/patches-6.1/830-v6.3-04-thermal-drivers-mtk-Add-support-for-MT7986-and-MT798.patch similarity index 89% rename from lede/target/linux/mediatek/patches-6.1/806-v6.2-thermal-mediatek-add-support-for-MT7986-and-MT7981.patch rename to lede/target/linux/mediatek/patches-6.1/830-v6.3-04-thermal-drivers-mtk-Add-support-for-MT7986-and-MT798.patch index 65311d5718..ef2006775a 100644 --- a/lede/target/linux/mediatek/patches-6.1/806-v6.2-thermal-mediatek-add-support-for-MT7986-and-MT7981.patch +++ b/lede/target/linux/mediatek/patches-6.1/830-v6.3-04-thermal-drivers-mtk-Add-support-for-MT7986-and-MT798.patch @@ -1,7 +1,7 @@ -From aa957c759b1182aee00cc35178667f849f941b42 Mon Sep 17 00:00:00 2001 +From aec1d89dccc7cba04fdb3e52dfda328f3302ba17 Mon Sep 17 00:00:00 2001 From: Daniel Golle -Date: Wed, 30 Nov 2022 13:19:39 +0000 -Subject: [PATCH 2/2] thermal: mediatek: add support for MT7986 and MT7981 +Date: Wed, 18 Jan 2023 15:40:58 +0000 +Subject: [PATCH 04/42] thermal/drivers/mtk: Add support for MT7986 and MT7981 Add support for V3 generation thermal found in MT7986 and MT7981 SoCs. Brings code to assign values from efuse as well as new function to @@ -9,10 +9,14 @@ convert raw temperature to millidegree celsius, as found in MediaTek's SDK sources (but cleaned up and de-duplicated) [1]: https://git01.mediatek.com/plugins/gitiles/openwrt/feeds/mtk-openwrt-feeds/+/baf36c7eef477aae1f8f2653b6c29e2caf48475b + Signed-off-by: Daniel Golle +Reviewed-by: AngeloGioacchino Del Regno +Link: https://lore.kernel.org/r/2d341fc45266217249586eb4bd3be3ac4ca83a12.1674055882.git.daniel@makrotopia.org +Signed-off-by: Daniel Lezcano --- - drivers/thermal/mtk_thermal.c | 137 ++++++++++++++++++++++++++++++++-- - 1 file changed, 132 insertions(+), 5 deletions(-) + drivers/thermal/mtk_thermal.c | 128 ++++++++++++++++++++++++++++++++-- + 1 file changed, 124 insertions(+), 4 deletions(-) --- a/drivers/thermal/mtk_thermal.c +++ b/drivers/thermal/mtk_thermal.c @@ -117,7 +121,7 @@ Signed-off-by: Daniel Golle +}; + /** - * raw_to_mcelsius - convert a raw ADC value to mcelsius + * raw_to_mcelsius_v1 - convert a raw ADC value to mcelsius * @mt: The thermal controller @@ -605,6 +673,22 @@ static int raw_to_mcelsius_v2(struct mtk return (format_2 - tmp) * 100; @@ -210,7 +214,7 @@ Signed-off-by: Daniel Golle .compatible = "mediatek,mt8183-thermal", .data = (void *)&mt8183_thermal_data, }, { -@@ -1068,15 +1186,24 @@ static int mtk_thermal_probe(struct plat +@@ -1066,15 +1184,17 @@ static int mtk_thermal_probe(struct plat goto err_disable_clk_auxadc; } @@ -220,21 +224,13 @@ Signed-off-by: Daniel Golle mtk_thermal_release_periodic_ts(mt, auxadc_base); } -- if (mt->conf->version == MTK_THERMAL_V1) -+ switch (mt->conf->version) { -+ case MTK_THERMAL_V1: + if (mt->conf->version == MTK_THERMAL_V1) mt->raw_to_mcelsius = raw_to_mcelsius_v1; - else -+ break; -+ case MTK_THERMAL_V2: ++ else if (mt->conf->version == MTK_THERMAL_V2) mt->raw_to_mcelsius = raw_to_mcelsius_v2; -+ break; -+ case MTK_THERMAL_V3: ++ else + mt->raw_to_mcelsius = raw_to_mcelsius_v3; -+ break; -+ default: -+ break; -+ } for (ctrl_id = 0; ctrl_id < mt->conf->num_controller ; ctrl_id++) for (i = 0; i < mt->conf->num_banks; i++) diff --git a/lede/target/linux/mediatek/patches-6.1/830-v6.3-05-thermal-drivers-mediatek-Relocate-driver-to-mediatek.patch b/lede/target/linux/mediatek/patches-6.1/830-v6.3-05-thermal-drivers-mediatek-Relocate-driver-to-mediatek.patch new file mode 100644 index 0000000000..e102a338cd --- /dev/null +++ b/lede/target/linux/mediatek/patches-6.1/830-v6.3-05-thermal-drivers-mediatek-Relocate-driver-to-mediatek.patch @@ -0,0 +1,2602 @@ +From 5e3aac197a74914ccec2732a89c29d960730d28f Mon Sep 17 00:00:00 2001 +From: Balsam CHIHI +Date: Thu, 9 Feb 2023 11:56:23 +0100 +Subject: [PATCH 05/42] thermal/drivers/mediatek: Relocate driver to mediatek + folder + +Add MediaTek proprietary folder to upstream more thermal zone and cooler +drivers, relocate the original thermal controller driver to it, and rename it +as "auxadc_thermal.c" to show its purpose more clearly. + +Signed-off-by: Balsam CHIHI +Reviewed-by: AngeloGioacchino Del Regno +Link: https://lore.kernel.org/r/20230209105628.50294-2-bchihi@baylibre.com +Signed-off-by: Daniel Lezcano +Signed-off-by: Rafael J. Wysocki +--- + drivers/thermal/Kconfig | 14 ++++--------- + drivers/thermal/Makefile | 2 +- + drivers/thermal/mediatek/Kconfig | 21 +++++++++++++++++++ + drivers/thermal/mediatek/Makefile | 1 + + .../auxadc_thermal.c} | 2 +- + 5 files changed, 28 insertions(+), 12 deletions(-) + create mode 100644 drivers/thermal/mediatek/Kconfig + create mode 100644 drivers/thermal/mediatek/Makefile + rename drivers/thermal/{mtk_thermal.c => mediatek/auxadc_thermal.c} (99%) + +--- a/drivers/thermal/Kconfig ++++ b/drivers/thermal/Kconfig +@@ -412,16 +412,10 @@ config DA9062_THERMAL + zone. + Compatible with the DA9062 and DA9061 PMICs. + +-config MTK_THERMAL +- tristate "Temperature sensor driver for mediatek SoCs" +- depends on ARCH_MEDIATEK || COMPILE_TEST +- depends on HAS_IOMEM +- depends on NVMEM || NVMEM=n +- depends on RESET_CONTROLLER +- default y +- help +- Enable this option if you want to have support for thermal management +- controller present in Mediatek SoCs ++menu "Mediatek thermal drivers" ++depends on ARCH_MEDIATEK || COMPILE_TEST ++source "drivers/thermal/mediatek/Kconfig" ++endmenu + + config AMLOGIC_THERMAL + tristate "Amlogic Thermal Support" +--- a/drivers/thermal/Makefile ++++ b/drivers/thermal/Makefile +@@ -55,7 +55,7 @@ obj-y += st/ + obj-y += qcom/ + obj-y += tegra/ + obj-$(CONFIG_HISI_THERMAL) += hisi_thermal.o +-obj-$(CONFIG_MTK_THERMAL) += mtk_thermal.o ++obj-y += mediatek/ + obj-$(CONFIG_GENERIC_ADC_THERMAL) += thermal-generic-adc.o + obj-$(CONFIG_UNIPHIER_THERMAL) += uniphier_thermal.o + obj-$(CONFIG_AMLOGIC_THERMAL) += amlogic_thermal.o +--- /dev/null ++++ b/drivers/thermal/mediatek/Kconfig +@@ -0,0 +1,21 @@ ++config MTK_THERMAL ++ tristate "MediaTek thermal drivers" ++ depends on THERMAL_OF ++ help ++ This is the option for MediaTek thermal software solutions. ++ Please enable corresponding options to get temperature ++ information from thermal sensors or turn on throttle ++ mechaisms for thermal mitigation. ++ ++if MTK_THERMAL ++ ++config MTK_SOC_THERMAL ++ tristate "AUXADC temperature sensor driver for MediaTek SoCs" ++ depends on HAS_IOMEM ++ help ++ Enable this option if you want to get SoC temperature ++ information for MediaTek platforms. ++ This driver configures thermal controllers to collect ++ temperature via AUXADC interface. ++ ++endif +--- /dev/null ++++ b/drivers/thermal/mediatek/Makefile +@@ -0,0 +1 @@ ++obj-$(CONFIG_MTK_SOC_THERMAL) += auxadc_thermal.o +--- a/drivers/thermal/mtk_thermal.c ++++ /dev/null +@@ -1,1254 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * Copyright (c) 2015 MediaTek Inc. +- * Author: Hanyi Wu +- * Sascha Hauer +- * Dawei Chien +- * Louis Yu +- */ +- +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +- +-#include "thermal_hwmon.h" +- +-/* AUXADC Registers */ +-#define AUXADC_CON1_SET_V 0x008 +-#define AUXADC_CON1_CLR_V 0x00c +-#define AUXADC_CON2_V 0x010 +-#define AUXADC_DATA(channel) (0x14 + (channel) * 4) +- +-#define APMIXED_SYS_TS_CON1 0x604 +- +-/* Thermal Controller Registers */ +-#define TEMP_MONCTL0 0x000 +-#define TEMP_MONCTL1 0x004 +-#define TEMP_MONCTL2 0x008 +-#define TEMP_MONIDET0 0x014 +-#define TEMP_MONIDET1 0x018 +-#define TEMP_MSRCTL0 0x038 +-#define TEMP_MSRCTL1 0x03c +-#define TEMP_AHBPOLL 0x040 +-#define TEMP_AHBTO 0x044 +-#define TEMP_ADCPNP0 0x048 +-#define TEMP_ADCPNP1 0x04c +-#define TEMP_ADCPNP2 0x050 +-#define TEMP_ADCPNP3 0x0b4 +- +-#define TEMP_ADCMUX 0x054 +-#define TEMP_ADCEN 0x060 +-#define TEMP_PNPMUXADDR 0x064 +-#define TEMP_ADCMUXADDR 0x068 +-#define TEMP_ADCENADDR 0x074 +-#define TEMP_ADCVALIDADDR 0x078 +-#define TEMP_ADCVOLTADDR 0x07c +-#define TEMP_RDCTRL 0x080 +-#define TEMP_ADCVALIDMASK 0x084 +-#define TEMP_ADCVOLTAGESHIFT 0x088 +-#define TEMP_ADCWRITECTRL 0x08c +-#define TEMP_MSR0 0x090 +-#define TEMP_MSR1 0x094 +-#define TEMP_MSR2 0x098 +-#define TEMP_MSR3 0x0B8 +- +-#define TEMP_SPARE0 0x0f0 +- +-#define TEMP_ADCPNP0_1 0x148 +-#define TEMP_ADCPNP1_1 0x14c +-#define TEMP_ADCPNP2_1 0x150 +-#define TEMP_MSR0_1 0x190 +-#define TEMP_MSR1_1 0x194 +-#define TEMP_MSR2_1 0x198 +-#define TEMP_ADCPNP3_1 0x1b4 +-#define TEMP_MSR3_1 0x1B8 +- +-#define PTPCORESEL 0x400 +- +-#define TEMP_MONCTL1_PERIOD_UNIT(x) ((x) & 0x3ff) +- +-#define TEMP_MONCTL2_FILTER_INTERVAL(x) (((x) & 0x3ff) << 16) +-#define TEMP_MONCTL2_SENSOR_INTERVAL(x) ((x) & 0x3ff) +- +-#define TEMP_AHBPOLL_ADC_POLL_INTERVAL(x) (x) +- +-#define TEMP_ADCWRITECTRL_ADC_PNP_WRITE BIT(0) +-#define TEMP_ADCWRITECTRL_ADC_MUX_WRITE BIT(1) +- +-#define TEMP_ADCVALIDMASK_VALID_HIGH BIT(5) +-#define TEMP_ADCVALIDMASK_VALID_POS(bit) (bit) +- +-/* MT8173 thermal sensors */ +-#define MT8173_TS1 0 +-#define MT8173_TS2 1 +-#define MT8173_TS3 2 +-#define MT8173_TS4 3 +-#define MT8173_TSABB 4 +- +-/* AUXADC channel 11 is used for the temperature sensors */ +-#define MT8173_TEMP_AUXADC_CHANNEL 11 +- +-/* The total number of temperature sensors in the MT8173 */ +-#define MT8173_NUM_SENSORS 5 +- +-/* The number of banks in the MT8173 */ +-#define MT8173_NUM_ZONES 4 +- +-/* The number of sensing points per bank */ +-#define MT8173_NUM_SENSORS_PER_ZONE 4 +- +-/* The number of controller in the MT8173 */ +-#define MT8173_NUM_CONTROLLER 1 +- +-/* The calibration coefficient of sensor */ +-#define MT8173_CALIBRATION 165 +- +-/* +- * Layout of the fuses providing the calibration data +- * These macros could be used for MT8183, MT8173, MT2701, and MT2712. +- * MT8183 has 6 sensors and needs 6 VTS calibration data. +- * MT8173 has 5 sensors and needs 5 VTS calibration data. +- * MT2701 has 3 sensors and needs 3 VTS calibration data. +- * MT2712 has 4 sensors and needs 4 VTS calibration data. +- */ +-#define CALIB_BUF0_VALID_V1 BIT(0) +-#define CALIB_BUF1_ADC_GE_V1(x) (((x) >> 22) & 0x3ff) +-#define CALIB_BUF0_VTS_TS1_V1(x) (((x) >> 17) & 0x1ff) +-#define CALIB_BUF0_VTS_TS2_V1(x) (((x) >> 8) & 0x1ff) +-#define CALIB_BUF1_VTS_TS3_V1(x) (((x) >> 0) & 0x1ff) +-#define CALIB_BUF2_VTS_TS4_V1(x) (((x) >> 23) & 0x1ff) +-#define CALIB_BUF2_VTS_TS5_V1(x) (((x) >> 5) & 0x1ff) +-#define CALIB_BUF2_VTS_TSABB_V1(x) (((x) >> 14) & 0x1ff) +-#define CALIB_BUF0_DEGC_CALI_V1(x) (((x) >> 1) & 0x3f) +-#define CALIB_BUF0_O_SLOPE_V1(x) (((x) >> 26) & 0x3f) +-#define CALIB_BUF0_O_SLOPE_SIGN_V1(x) (((x) >> 7) & 0x1) +-#define CALIB_BUF1_ID_V1(x) (((x) >> 9) & 0x1) +- +-/* +- * Layout of the fuses providing the calibration data +- * These macros could be used for MT7622. +- */ +-#define CALIB_BUF0_ADC_OE_V2(x) (((x) >> 22) & 0x3ff) +-#define CALIB_BUF0_ADC_GE_V2(x) (((x) >> 12) & 0x3ff) +-#define CALIB_BUF0_DEGC_CALI_V2(x) (((x) >> 6) & 0x3f) +-#define CALIB_BUF0_O_SLOPE_V2(x) (((x) >> 0) & 0x3f) +-#define CALIB_BUF1_VTS_TS1_V2(x) (((x) >> 23) & 0x1ff) +-#define CALIB_BUF1_VTS_TS2_V2(x) (((x) >> 14) & 0x1ff) +-#define CALIB_BUF1_VTS_TSABB_V2(x) (((x) >> 5) & 0x1ff) +-#define CALIB_BUF1_VALID_V2(x) (((x) >> 4) & 0x1) +-#define CALIB_BUF1_O_SLOPE_SIGN_V2(x) (((x) >> 3) & 0x1) +- +-/* +- * Layout of the fuses providing the calibration data +- * These macros can be used for MT7981 and MT7986. +- */ +-#define CALIB_BUF0_ADC_GE_V3(x) (((x) >> 0) & 0x3ff) +-#define CALIB_BUF0_DEGC_CALI_V3(x) (((x) >> 20) & 0x3f) +-#define CALIB_BUF0_O_SLOPE_V3(x) (((x) >> 26) & 0x3f) +-#define CALIB_BUF1_VTS_TS1_V3(x) (((x) >> 0) & 0x1ff) +-#define CALIB_BUF1_VTS_TS2_V3(x) (((x) >> 21) & 0x1ff) +-#define CALIB_BUF1_VTS_TSABB_V3(x) (((x) >> 9) & 0x1ff) +-#define CALIB_BUF1_VALID_V3(x) (((x) >> 18) & 0x1) +-#define CALIB_BUF1_O_SLOPE_SIGN_V3(x) (((x) >> 19) & 0x1) +-#define CALIB_BUF1_ID_V3(x) (((x) >> 20) & 0x1) +- +-enum { +- VTS1, +- VTS2, +- VTS3, +- VTS4, +- VTS5, +- VTSABB, +- MAX_NUM_VTS, +-}; +- +-enum mtk_thermal_version { +- MTK_THERMAL_V1 = 1, +- MTK_THERMAL_V2, +- MTK_THERMAL_V3, +-}; +- +-/* MT2701 thermal sensors */ +-#define MT2701_TS1 0 +-#define MT2701_TS2 1 +-#define MT2701_TSABB 2 +- +-/* AUXADC channel 11 is used for the temperature sensors */ +-#define MT2701_TEMP_AUXADC_CHANNEL 11 +- +-/* The total number of temperature sensors in the MT2701 */ +-#define MT2701_NUM_SENSORS 3 +- +-/* The number of sensing points per bank */ +-#define MT2701_NUM_SENSORS_PER_ZONE 3 +- +-/* The number of controller in the MT2701 */ +-#define MT2701_NUM_CONTROLLER 1 +- +-/* The calibration coefficient of sensor */ +-#define MT2701_CALIBRATION 165 +- +-/* MT2712 thermal sensors */ +-#define MT2712_TS1 0 +-#define MT2712_TS2 1 +-#define MT2712_TS3 2 +-#define MT2712_TS4 3 +- +-/* AUXADC channel 11 is used for the temperature sensors */ +-#define MT2712_TEMP_AUXADC_CHANNEL 11 +- +-/* The total number of temperature sensors in the MT2712 */ +-#define MT2712_NUM_SENSORS 4 +- +-/* The number of sensing points per bank */ +-#define MT2712_NUM_SENSORS_PER_ZONE 4 +- +-/* The number of controller in the MT2712 */ +-#define MT2712_NUM_CONTROLLER 1 +- +-/* The calibration coefficient of sensor */ +-#define MT2712_CALIBRATION 165 +- +-#define MT7622_TEMP_AUXADC_CHANNEL 11 +-#define MT7622_NUM_SENSORS 1 +-#define MT7622_NUM_ZONES 1 +-#define MT7622_NUM_SENSORS_PER_ZONE 1 +-#define MT7622_TS1 0 +-#define MT7622_NUM_CONTROLLER 1 +- +-/* The maximum number of banks */ +-#define MAX_NUM_ZONES 8 +- +-/* The calibration coefficient of sensor */ +-#define MT7622_CALIBRATION 165 +- +-/* MT8183 thermal sensors */ +-#define MT8183_TS1 0 +-#define MT8183_TS2 1 +-#define MT8183_TS3 2 +-#define MT8183_TS4 3 +-#define MT8183_TS5 4 +-#define MT8183_TSABB 5 +- +-/* AUXADC channel is used for the temperature sensors */ +-#define MT8183_TEMP_AUXADC_CHANNEL 11 +- +-/* The total number of temperature sensors in the MT8183 */ +-#define MT8183_NUM_SENSORS 6 +- +-/* The number of banks in the MT8183 */ +-#define MT8183_NUM_ZONES 1 +- +-/* The number of sensing points per bank */ +-#define MT8183_NUM_SENSORS_PER_ZONE 6 +- +-/* The number of controller in the MT8183 */ +-#define MT8183_NUM_CONTROLLER 2 +- +-/* The calibration coefficient of sensor */ +-#define MT8183_CALIBRATION 153 +- +-/* AUXADC channel 11 is used for the temperature sensors */ +-#define MT7986_TEMP_AUXADC_CHANNEL 11 +- +-/* The total number of temperature sensors in the MT7986 */ +-#define MT7986_NUM_SENSORS 1 +- +-/* The number of banks in the MT7986 */ +-#define MT7986_NUM_ZONES 1 +- +-/* The number of sensing points per bank */ +-#define MT7986_NUM_SENSORS_PER_ZONE 1 +- +-/* MT7986 thermal sensors */ +-#define MT7986_TS1 0 +- +-/* The number of controller in the MT7986 */ +-#define MT7986_NUM_CONTROLLER 1 +- +-/* The calibration coefficient of sensor */ +-#define MT7986_CALIBRATION 165 +- +-struct mtk_thermal; +- +-struct thermal_bank_cfg { +- unsigned int num_sensors; +- const int *sensors; +-}; +- +-struct mtk_thermal_bank { +- struct mtk_thermal *mt; +- int id; +-}; +- +-struct mtk_thermal_data { +- s32 num_banks; +- s32 num_sensors; +- s32 auxadc_channel; +- const int *vts_index; +- const int *sensor_mux_values; +- const int *msr; +- const int *adcpnp; +- const int cali_val; +- const int num_controller; +- const int *controller_offset; +- bool need_switch_bank; +- struct thermal_bank_cfg bank_data[MAX_NUM_ZONES]; +- enum mtk_thermal_version version; +-}; +- +-struct mtk_thermal { +- struct device *dev; +- void __iomem *thermal_base; +- +- struct clk *clk_peri_therm; +- struct clk *clk_auxadc; +- /* lock: for getting and putting banks */ +- struct mutex lock; +- +- /* Calibration values */ +- s32 adc_ge; +- s32 adc_oe; +- s32 degc_cali; +- s32 o_slope; +- s32 o_slope_sign; +- s32 vts[MAX_NUM_VTS]; +- +- const struct mtk_thermal_data *conf; +- struct mtk_thermal_bank banks[MAX_NUM_ZONES]; +- +- int (*raw_to_mcelsius)(struct mtk_thermal *mt, int sensno, s32 raw); +-}; +- +-/* MT8183 thermal sensor data */ +-static const int mt8183_bank_data[MT8183_NUM_SENSORS] = { +- MT8183_TS1, MT8183_TS2, MT8183_TS3, MT8183_TS4, MT8183_TS5, MT8183_TSABB +-}; +- +-static const int mt8183_msr[MT8183_NUM_SENSORS_PER_ZONE] = { +- TEMP_MSR0_1, TEMP_MSR1_1, TEMP_MSR2_1, TEMP_MSR1, TEMP_MSR0, TEMP_MSR3_1 +-}; +- +-static const int mt8183_adcpnp[MT8183_NUM_SENSORS_PER_ZONE] = { +- TEMP_ADCPNP0_1, TEMP_ADCPNP1_1, TEMP_ADCPNP2_1, +- TEMP_ADCPNP1, TEMP_ADCPNP0, TEMP_ADCPNP3_1 +-}; +- +-static const int mt8183_mux_values[MT8183_NUM_SENSORS] = { 0, 1, 2, 3, 4, 0 }; +-static const int mt8183_tc_offset[MT8183_NUM_CONTROLLER] = {0x0, 0x100}; +- +-static const int mt8183_vts_index[MT8183_NUM_SENSORS] = { +- VTS1, VTS2, VTS3, VTS4, VTS5, VTSABB +-}; +- +-/* MT8173 thermal sensor data */ +-static const int mt8173_bank_data[MT8173_NUM_ZONES][3] = { +- { MT8173_TS2, MT8173_TS3 }, +- { MT8173_TS2, MT8173_TS4 }, +- { MT8173_TS1, MT8173_TS2, MT8173_TSABB }, +- { MT8173_TS2 }, +-}; +- +-static const int mt8173_msr[MT8173_NUM_SENSORS_PER_ZONE] = { +- TEMP_MSR0, TEMP_MSR1, TEMP_MSR2, TEMP_MSR3 +-}; +- +-static const int mt8173_adcpnp[MT8173_NUM_SENSORS_PER_ZONE] = { +- TEMP_ADCPNP0, TEMP_ADCPNP1, TEMP_ADCPNP2, TEMP_ADCPNP3 +-}; +- +-static const int mt8173_mux_values[MT8173_NUM_SENSORS] = { 0, 1, 2, 3, 16 }; +-static const int mt8173_tc_offset[MT8173_NUM_CONTROLLER] = { 0x0, }; +- +-static const int mt8173_vts_index[MT8173_NUM_SENSORS] = { +- VTS1, VTS2, VTS3, VTS4, VTSABB +-}; +- +-/* MT2701 thermal sensor data */ +-static const int mt2701_bank_data[MT2701_NUM_SENSORS] = { +- MT2701_TS1, MT2701_TS2, MT2701_TSABB +-}; +- +-static const int mt2701_msr[MT2701_NUM_SENSORS_PER_ZONE] = { +- TEMP_MSR0, TEMP_MSR1, TEMP_MSR2 +-}; +- +-static const int mt2701_adcpnp[MT2701_NUM_SENSORS_PER_ZONE] = { +- TEMP_ADCPNP0, TEMP_ADCPNP1, TEMP_ADCPNP2 +-}; +- +-static const int mt2701_mux_values[MT2701_NUM_SENSORS] = { 0, 1, 16 }; +-static const int mt2701_tc_offset[MT2701_NUM_CONTROLLER] = { 0x0, }; +- +-static const int mt2701_vts_index[MT2701_NUM_SENSORS] = { +- VTS1, VTS2, VTS3 +-}; +- +-/* MT2712 thermal sensor data */ +-static const int mt2712_bank_data[MT2712_NUM_SENSORS] = { +- MT2712_TS1, MT2712_TS2, MT2712_TS3, MT2712_TS4 +-}; +- +-static const int mt2712_msr[MT2712_NUM_SENSORS_PER_ZONE] = { +- TEMP_MSR0, TEMP_MSR1, TEMP_MSR2, TEMP_MSR3 +-}; +- +-static const int mt2712_adcpnp[MT2712_NUM_SENSORS_PER_ZONE] = { +- TEMP_ADCPNP0, TEMP_ADCPNP1, TEMP_ADCPNP2, TEMP_ADCPNP3 +-}; +- +-static const int mt2712_mux_values[MT2712_NUM_SENSORS] = { 0, 1, 2, 3 }; +-static const int mt2712_tc_offset[MT2712_NUM_CONTROLLER] = { 0x0, }; +- +-static const int mt2712_vts_index[MT2712_NUM_SENSORS] = { +- VTS1, VTS2, VTS3, VTS4 +-}; +- +-/* MT7622 thermal sensor data */ +-static const int mt7622_bank_data[MT7622_NUM_SENSORS] = { MT7622_TS1, }; +-static const int mt7622_msr[MT7622_NUM_SENSORS_PER_ZONE] = { TEMP_MSR0, }; +-static const int mt7622_adcpnp[MT7622_NUM_SENSORS_PER_ZONE] = { TEMP_ADCPNP0, }; +-static const int mt7622_mux_values[MT7622_NUM_SENSORS] = { 0, }; +-static const int mt7622_vts_index[MT7622_NUM_SENSORS] = { VTS1 }; +-static const int mt7622_tc_offset[MT7622_NUM_CONTROLLER] = { 0x0, }; +- +-/* MT7986 thermal sensor data */ +-static const int mt7986_bank_data[MT7986_NUM_SENSORS] = { MT7986_TS1, }; +-static const int mt7986_msr[MT7986_NUM_SENSORS_PER_ZONE] = { TEMP_MSR0, }; +-static const int mt7986_adcpnp[MT7986_NUM_SENSORS_PER_ZONE] = { TEMP_ADCPNP0, }; +-static const int mt7986_mux_values[MT7986_NUM_SENSORS] = { 0, }; +-static const int mt7986_vts_index[MT7986_NUM_SENSORS] = { VTS1 }; +-static const int mt7986_tc_offset[MT7986_NUM_CONTROLLER] = { 0x0, }; +- +-/* +- * The MT8173 thermal controller has four banks. Each bank can read up to +- * four temperature sensors simultaneously. The MT8173 has a total of 5 +- * temperature sensors. We use each bank to measure a certain area of the +- * SoC. Since TS2 is located centrally in the SoC it is influenced by multiple +- * areas, hence is used in different banks. +- * +- * The thermal core only gets the maximum temperature of all banks, so +- * the bank concept wouldn't be necessary here. However, the SVS (Smart +- * Voltage Scaling) unit makes its decisions based on the same bank +- * data, and this indeed needs the temperatures of the individual banks +- * for making better decisions. +- */ +-static const struct mtk_thermal_data mt8173_thermal_data = { +- .auxadc_channel = MT8173_TEMP_AUXADC_CHANNEL, +- .num_banks = MT8173_NUM_ZONES, +- .num_sensors = MT8173_NUM_SENSORS, +- .vts_index = mt8173_vts_index, +- .cali_val = MT8173_CALIBRATION, +- .num_controller = MT8173_NUM_CONTROLLER, +- .controller_offset = mt8173_tc_offset, +- .need_switch_bank = true, +- .bank_data = { +- { +- .num_sensors = 2, +- .sensors = mt8173_bank_data[0], +- }, { +- .num_sensors = 2, +- .sensors = mt8173_bank_data[1], +- }, { +- .num_sensors = 3, +- .sensors = mt8173_bank_data[2], +- }, { +- .num_sensors = 1, +- .sensors = mt8173_bank_data[3], +- }, +- }, +- .msr = mt8173_msr, +- .adcpnp = mt8173_adcpnp, +- .sensor_mux_values = mt8173_mux_values, +- .version = MTK_THERMAL_V1, +-}; +- +-/* +- * The MT2701 thermal controller has one bank, which can read up to +- * three temperature sensors simultaneously. The MT2701 has a total of 3 +- * temperature sensors. +- * +- * The thermal core only gets the maximum temperature of this one bank, +- * so the bank concept wouldn't be necessary here. However, the SVS (Smart +- * Voltage Scaling) unit makes its decisions based on the same bank +- * data. +- */ +-static const struct mtk_thermal_data mt2701_thermal_data = { +- .auxadc_channel = MT2701_TEMP_AUXADC_CHANNEL, +- .num_banks = 1, +- .num_sensors = MT2701_NUM_SENSORS, +- .vts_index = mt2701_vts_index, +- .cali_val = MT2701_CALIBRATION, +- .num_controller = MT2701_NUM_CONTROLLER, +- .controller_offset = mt2701_tc_offset, +- .need_switch_bank = true, +- .bank_data = { +- { +- .num_sensors = 3, +- .sensors = mt2701_bank_data, +- }, +- }, +- .msr = mt2701_msr, +- .adcpnp = mt2701_adcpnp, +- .sensor_mux_values = mt2701_mux_values, +- .version = MTK_THERMAL_V1, +-}; +- +-/* +- * The MT2712 thermal controller has one bank, which can read up to +- * four temperature sensors simultaneously. The MT2712 has a total of 4 +- * temperature sensors. +- * +- * The thermal core only gets the maximum temperature of this one bank, +- * so the bank concept wouldn't be necessary here. However, the SVS (Smart +- * Voltage Scaling) unit makes its decisions based on the same bank +- * data. +- */ +-static const struct mtk_thermal_data mt2712_thermal_data = { +- .auxadc_channel = MT2712_TEMP_AUXADC_CHANNEL, +- .num_banks = 1, +- .num_sensors = MT2712_NUM_SENSORS, +- .vts_index = mt2712_vts_index, +- .cali_val = MT2712_CALIBRATION, +- .num_controller = MT2712_NUM_CONTROLLER, +- .controller_offset = mt2712_tc_offset, +- .need_switch_bank = true, +- .bank_data = { +- { +- .num_sensors = 4, +- .sensors = mt2712_bank_data, +- }, +- }, +- .msr = mt2712_msr, +- .adcpnp = mt2712_adcpnp, +- .sensor_mux_values = mt2712_mux_values, +- .version = MTK_THERMAL_V1, +-}; +- +-/* +- * MT7622 have only one sensing point which uses AUXADC Channel 11 for raw data +- * access. +- */ +-static const struct mtk_thermal_data mt7622_thermal_data = { +- .auxadc_channel = MT7622_TEMP_AUXADC_CHANNEL, +- .num_banks = MT7622_NUM_ZONES, +- .num_sensors = MT7622_NUM_SENSORS, +- .vts_index = mt7622_vts_index, +- .cali_val = MT7622_CALIBRATION, +- .num_controller = MT7622_NUM_CONTROLLER, +- .controller_offset = mt7622_tc_offset, +- .need_switch_bank = true, +- .bank_data = { +- { +- .num_sensors = 1, +- .sensors = mt7622_bank_data, +- }, +- }, +- .msr = mt7622_msr, +- .adcpnp = mt7622_adcpnp, +- .sensor_mux_values = mt7622_mux_values, +- .version = MTK_THERMAL_V2, +-}; +- +-/* +- * The MT8183 thermal controller has one bank for the current SW framework. +- * The MT8183 has a total of 6 temperature sensors. +- * There are two thermal controller to control the six sensor. +- * The first one bind 2 sensor, and the other bind 4 sensors. +- * The thermal core only gets the maximum temperature of all sensor, so +- * the bank concept wouldn't be necessary here. However, the SVS (Smart +- * Voltage Scaling) unit makes its decisions based on the same bank +- * data, and this indeed needs the temperatures of the individual banks +- * for making better decisions. +- */ +-static const struct mtk_thermal_data mt8183_thermal_data = { +- .auxadc_channel = MT8183_TEMP_AUXADC_CHANNEL, +- .num_banks = MT8183_NUM_ZONES, +- .num_sensors = MT8183_NUM_SENSORS, +- .vts_index = mt8183_vts_index, +- .cali_val = MT8183_CALIBRATION, +- .num_controller = MT8183_NUM_CONTROLLER, +- .controller_offset = mt8183_tc_offset, +- .need_switch_bank = false, +- .bank_data = { +- { +- .num_sensors = 6, +- .sensors = mt8183_bank_data, +- }, +- }, +- +- .msr = mt8183_msr, +- .adcpnp = mt8183_adcpnp, +- .sensor_mux_values = mt8183_mux_values, +- .version = MTK_THERMAL_V1, +-}; +- +-/* +- * MT7986 uses AUXADC Channel 11 for raw data access. +- */ +-static const struct mtk_thermal_data mt7986_thermal_data = { +- .auxadc_channel = MT7986_TEMP_AUXADC_CHANNEL, +- .num_banks = MT7986_NUM_ZONES, +- .num_sensors = MT7986_NUM_SENSORS, +- .vts_index = mt7986_vts_index, +- .cali_val = MT7986_CALIBRATION, +- .num_controller = MT7986_NUM_CONTROLLER, +- .controller_offset = mt7986_tc_offset, +- .need_switch_bank = true, +- .bank_data = { +- { +- .num_sensors = 1, +- .sensors = mt7986_bank_data, +- }, +- }, +- .msr = mt7986_msr, +- .adcpnp = mt7986_adcpnp, +- .sensor_mux_values = mt7986_mux_values, +- .version = MTK_THERMAL_V3, +-}; +- +-/** +- * raw_to_mcelsius_v1 - convert a raw ADC value to mcelsius +- * @mt: The thermal controller +- * @sensno: sensor number +- * @raw: raw ADC value +- * +- * This converts the raw ADC value to mcelsius using the SoC specific +- * calibration constants +- */ +-static int raw_to_mcelsius_v1(struct mtk_thermal *mt, int sensno, s32 raw) +-{ +- s32 tmp; +- +- raw &= 0xfff; +- +- tmp = 203450520 << 3; +- tmp /= mt->conf->cali_val + mt->o_slope; +- tmp /= 10000 + mt->adc_ge; +- tmp *= raw - mt->vts[sensno] - 3350; +- tmp >>= 3; +- +- return mt->degc_cali * 500 - tmp; +-} +- +-static int raw_to_mcelsius_v2(struct mtk_thermal *mt, int sensno, s32 raw) +-{ +- s32 format_1; +- s32 format_2; +- s32 g_oe; +- s32 g_gain; +- s32 g_x_roomt; +- s32 tmp; +- +- if (raw == 0) +- return 0; +- +- raw &= 0xfff; +- g_gain = 10000 + (((mt->adc_ge - 512) * 10000) >> 12); +- g_oe = mt->adc_oe - 512; +- format_1 = mt->vts[VTS2] + 3105 - g_oe; +- format_2 = (mt->degc_cali * 10) >> 1; +- g_x_roomt = (((format_1 * 10000) >> 12) * 10000) / g_gain; +- +- tmp = (((((raw - g_oe) * 10000) >> 12) * 10000) / g_gain) - g_x_roomt; +- tmp = tmp * 10 * 100 / 11; +- +- if (mt->o_slope_sign == 0) +- tmp = tmp / (165 - mt->o_slope); +- else +- tmp = tmp / (165 + mt->o_slope); +- +- return (format_2 - tmp) * 100; +-} +- +-static int raw_to_mcelsius_v3(struct mtk_thermal *mt, int sensno, s32 raw) +-{ +- s32 tmp; +- +- if (raw == 0) +- return 0; +- +- raw &= 0xfff; +- tmp = 100000 * 15 / 16 * 10000; +- tmp /= 4096 - 512 + mt->adc_ge; +- tmp /= 1490; +- tmp *= raw - mt->vts[sensno] - 2900; +- +- return mt->degc_cali * 500 - tmp; +-} +- +-/** +- * mtk_thermal_get_bank - get bank +- * @bank: The bank +- * +- * The bank registers are banked, we have to select a bank in the +- * PTPCORESEL register to access it. +- */ +-static void mtk_thermal_get_bank(struct mtk_thermal_bank *bank) +-{ +- struct mtk_thermal *mt = bank->mt; +- u32 val; +- +- if (mt->conf->need_switch_bank) { +- mutex_lock(&mt->lock); +- +- val = readl(mt->thermal_base + PTPCORESEL); +- val &= ~0xf; +- val |= bank->id; +- writel(val, mt->thermal_base + PTPCORESEL); +- } +-} +- +-/** +- * mtk_thermal_put_bank - release bank +- * @bank: The bank +- * +- * release a bank previously taken with mtk_thermal_get_bank, +- */ +-static void mtk_thermal_put_bank(struct mtk_thermal_bank *bank) +-{ +- struct mtk_thermal *mt = bank->mt; +- +- if (mt->conf->need_switch_bank) +- mutex_unlock(&mt->lock); +-} +- +-/** +- * mtk_thermal_bank_temperature - get the temperature of a bank +- * @bank: The bank +- * +- * The temperature of a bank is considered the maximum temperature of +- * the sensors associated to the bank. +- */ +-static int mtk_thermal_bank_temperature(struct mtk_thermal_bank *bank) +-{ +- struct mtk_thermal *mt = bank->mt; +- const struct mtk_thermal_data *conf = mt->conf; +- int i, temp = INT_MIN, max = INT_MIN; +- u32 raw; +- +- for (i = 0; i < conf->bank_data[bank->id].num_sensors; i++) { +- raw = readl(mt->thermal_base + conf->msr[i]); +- +- temp = mt->raw_to_mcelsius( +- mt, conf->bank_data[bank->id].sensors[i], raw); +- +- +- /* +- * The first read of a sensor often contains very high bogus +- * temperature value. Filter these out so that the system does +- * not immediately shut down. +- */ +- if (temp > 200000) +- temp = 0; +- +- if (temp > max) +- max = temp; +- } +- +- return max; +-} +- +-static int mtk_read_temp(struct thermal_zone_device *tz, int *temperature) +-{ +- struct mtk_thermal *mt = tz->devdata; +- int i; +- int tempmax = INT_MIN; +- +- for (i = 0; i < mt->conf->num_banks; i++) { +- struct mtk_thermal_bank *bank = &mt->banks[i]; +- +- mtk_thermal_get_bank(bank); +- +- tempmax = max(tempmax, mtk_thermal_bank_temperature(bank)); +- +- mtk_thermal_put_bank(bank); +- } +- +- *temperature = tempmax; +- +- return 0; +-} +- +-static const struct thermal_zone_device_ops mtk_thermal_ops = { +- .get_temp = mtk_read_temp, +-}; +- +-static void mtk_thermal_init_bank(struct mtk_thermal *mt, int num, +- u32 apmixed_phys_base, u32 auxadc_phys_base, +- int ctrl_id) +-{ +- struct mtk_thermal_bank *bank = &mt->banks[num]; +- const struct mtk_thermal_data *conf = mt->conf; +- int i; +- +- int offset = mt->conf->controller_offset[ctrl_id]; +- void __iomem *controller_base = mt->thermal_base + offset; +- +- bank->id = num; +- bank->mt = mt; +- +- mtk_thermal_get_bank(bank); +- +- /* bus clock 66M counting unit is 12 * 15.15ns * 256 = 46.540us */ +- writel(TEMP_MONCTL1_PERIOD_UNIT(12), controller_base + TEMP_MONCTL1); +- +- /* +- * filt interval is 1 * 46.540us = 46.54us, +- * sen interval is 429 * 46.540us = 19.96ms +- */ +- writel(TEMP_MONCTL2_FILTER_INTERVAL(1) | +- TEMP_MONCTL2_SENSOR_INTERVAL(429), +- controller_base + TEMP_MONCTL2); +- +- /* poll is set to 10u */ +- writel(TEMP_AHBPOLL_ADC_POLL_INTERVAL(768), +- controller_base + TEMP_AHBPOLL); +- +- /* temperature sampling control, 1 sample */ +- writel(0x0, controller_base + TEMP_MSRCTL0); +- +- /* exceed this polling time, IRQ would be inserted */ +- writel(0xffffffff, controller_base + TEMP_AHBTO); +- +- /* number of interrupts per event, 1 is enough */ +- writel(0x0, controller_base + TEMP_MONIDET0); +- writel(0x0, controller_base + TEMP_MONIDET1); +- +- /* +- * The MT8173 thermal controller does not have its own ADC. Instead it +- * uses AHB bus accesses to control the AUXADC. To do this the thermal +- * controller has to be programmed with the physical addresses of the +- * AUXADC registers and with the various bit positions in the AUXADC. +- * Also the thermal controller controls a mux in the APMIXEDSYS register +- * space. +- */ +- +- /* +- * this value will be stored to TEMP_PNPMUXADDR (TEMP_SPARE0) +- * automatically by hw +- */ +- writel(BIT(conf->auxadc_channel), controller_base + TEMP_ADCMUX); +- +- /* AHB address for auxadc mux selection */ +- writel(auxadc_phys_base + AUXADC_CON1_CLR_V, +- controller_base + TEMP_ADCMUXADDR); +- +- if (mt->conf->version == MTK_THERMAL_V1) { +- /* AHB address for pnp sensor mux selection */ +- writel(apmixed_phys_base + APMIXED_SYS_TS_CON1, +- controller_base + TEMP_PNPMUXADDR); +- } +- +- /* AHB value for auxadc enable */ +- writel(BIT(conf->auxadc_channel), controller_base + TEMP_ADCEN); +- +- /* AHB address for auxadc enable (channel 0 immediate mode selected) */ +- writel(auxadc_phys_base + AUXADC_CON1_SET_V, +- controller_base + TEMP_ADCENADDR); +- +- /* AHB address for auxadc valid bit */ +- writel(auxadc_phys_base + AUXADC_DATA(conf->auxadc_channel), +- controller_base + TEMP_ADCVALIDADDR); +- +- /* AHB address for auxadc voltage output */ +- writel(auxadc_phys_base + AUXADC_DATA(conf->auxadc_channel), +- controller_base + TEMP_ADCVOLTADDR); +- +- /* read valid & voltage are at the same register */ +- writel(0x0, controller_base + TEMP_RDCTRL); +- +- /* indicate where the valid bit is */ +- writel(TEMP_ADCVALIDMASK_VALID_HIGH | TEMP_ADCVALIDMASK_VALID_POS(12), +- controller_base + TEMP_ADCVALIDMASK); +- +- /* no shift */ +- writel(0x0, controller_base + TEMP_ADCVOLTAGESHIFT); +- +- /* enable auxadc mux write transaction */ +- writel(TEMP_ADCWRITECTRL_ADC_MUX_WRITE, +- controller_base + TEMP_ADCWRITECTRL); +- +- for (i = 0; i < conf->bank_data[num].num_sensors; i++) +- writel(conf->sensor_mux_values[conf->bank_data[num].sensors[i]], +- mt->thermal_base + conf->adcpnp[i]); +- +- writel((1 << conf->bank_data[num].num_sensors) - 1, +- controller_base + TEMP_MONCTL0); +- +- writel(TEMP_ADCWRITECTRL_ADC_PNP_WRITE | +- TEMP_ADCWRITECTRL_ADC_MUX_WRITE, +- controller_base + TEMP_ADCWRITECTRL); +- +- mtk_thermal_put_bank(bank); +-} +- +-static u64 of_get_phys_base(struct device_node *np) +-{ +- u64 size64; +- const __be32 *regaddr_p; +- +- regaddr_p = of_get_address(np, 0, &size64, NULL); +- if (!regaddr_p) +- return OF_BAD_ADDR; +- +- return of_translate_address(np, regaddr_p); +-} +- +-static int mtk_thermal_extract_efuse_v1(struct mtk_thermal *mt, u32 *buf) +-{ +- int i; +- +- if (!(buf[0] & CALIB_BUF0_VALID_V1)) +- return -EINVAL; +- +- mt->adc_ge = CALIB_BUF1_ADC_GE_V1(buf[1]); +- +- for (i = 0; i < mt->conf->num_sensors; i++) { +- switch (mt->conf->vts_index[i]) { +- case VTS1: +- mt->vts[VTS1] = CALIB_BUF0_VTS_TS1_V1(buf[0]); +- break; +- case VTS2: +- mt->vts[VTS2] = CALIB_BUF0_VTS_TS2_V1(buf[0]); +- break; +- case VTS3: +- mt->vts[VTS3] = CALIB_BUF1_VTS_TS3_V1(buf[1]); +- break; +- case VTS4: +- mt->vts[VTS4] = CALIB_BUF2_VTS_TS4_V1(buf[2]); +- break; +- case VTS5: +- mt->vts[VTS5] = CALIB_BUF2_VTS_TS5_V1(buf[2]); +- break; +- case VTSABB: +- mt->vts[VTSABB] = +- CALIB_BUF2_VTS_TSABB_V1(buf[2]); +- break; +- default: +- break; +- } +- } +- +- mt->degc_cali = CALIB_BUF0_DEGC_CALI_V1(buf[0]); +- if (CALIB_BUF1_ID_V1(buf[1]) & +- CALIB_BUF0_O_SLOPE_SIGN_V1(buf[0])) +- mt->o_slope = -CALIB_BUF0_O_SLOPE_V1(buf[0]); +- else +- mt->o_slope = CALIB_BUF0_O_SLOPE_V1(buf[0]); +- +- return 0; +-} +- +-static int mtk_thermal_extract_efuse_v2(struct mtk_thermal *mt, u32 *buf) +-{ +- if (!CALIB_BUF1_VALID_V2(buf[1])) +- return -EINVAL; +- +- mt->adc_oe = CALIB_BUF0_ADC_OE_V2(buf[0]); +- mt->adc_ge = CALIB_BUF0_ADC_GE_V2(buf[0]); +- mt->degc_cali = CALIB_BUF0_DEGC_CALI_V2(buf[0]); +- mt->o_slope = CALIB_BUF0_O_SLOPE_V2(buf[0]); +- mt->vts[VTS1] = CALIB_BUF1_VTS_TS1_V2(buf[1]); +- mt->vts[VTS2] = CALIB_BUF1_VTS_TS2_V2(buf[1]); +- mt->vts[VTSABB] = CALIB_BUF1_VTS_TSABB_V2(buf[1]); +- mt->o_slope_sign = CALIB_BUF1_O_SLOPE_SIGN_V2(buf[1]); +- +- return 0; +-} +- +-static int mtk_thermal_extract_efuse_v3(struct mtk_thermal *mt, u32 *buf) +-{ +- if (!CALIB_BUF1_VALID_V3(buf[1])) +- return -EINVAL; +- +- mt->adc_ge = CALIB_BUF0_ADC_GE_V3(buf[0]); +- mt->degc_cali = CALIB_BUF0_DEGC_CALI_V3(buf[0]); +- mt->o_slope = CALIB_BUF0_O_SLOPE_V3(buf[0]); +- mt->vts[VTS1] = CALIB_BUF1_VTS_TS1_V3(buf[1]); +- mt->vts[VTS2] = CALIB_BUF1_VTS_TS2_V3(buf[1]); +- mt->vts[VTSABB] = CALIB_BUF1_VTS_TSABB_V3(buf[1]); +- mt->o_slope_sign = CALIB_BUF1_O_SLOPE_SIGN_V3(buf[1]); +- +- if (CALIB_BUF1_ID_V3(buf[1]) == 0) +- mt->o_slope = 0; +- +- return 0; +-} +- +-static int mtk_thermal_get_calibration_data(struct device *dev, +- struct mtk_thermal *mt) +-{ +- struct nvmem_cell *cell; +- u32 *buf; +- size_t len; +- int i, ret = 0; +- +- /* Start with default values */ +- mt->adc_ge = 512; +- mt->adc_oe = 512; +- for (i = 0; i < mt->conf->num_sensors; i++) +- mt->vts[i] = 260; +- mt->degc_cali = 40; +- mt->o_slope = 0; +- +- cell = nvmem_cell_get(dev, "calibration-data"); +- if (IS_ERR(cell)) { +- if (PTR_ERR(cell) == -EPROBE_DEFER) +- return PTR_ERR(cell); +- return 0; +- } +- +- buf = (u32 *)nvmem_cell_read(cell, &len); +- +- nvmem_cell_put(cell); +- +- if (IS_ERR(buf)) +- return PTR_ERR(buf); +- +- if (len < 3 * sizeof(u32)) { +- dev_warn(dev, "invalid calibration data\n"); +- ret = -EINVAL; +- goto out; +- } +- +- switch (mt->conf->version) { +- case MTK_THERMAL_V1: +- ret = mtk_thermal_extract_efuse_v1(mt, buf); +- break; +- case MTK_THERMAL_V2: +- ret = mtk_thermal_extract_efuse_v2(mt, buf); +- break; +- case MTK_THERMAL_V3: +- ret = mtk_thermal_extract_efuse_v3(mt, buf); +- break; +- default: +- ret = -EINVAL; +- break; +- } +- +- if (ret) { +- dev_info(dev, "Device not calibrated, using default calibration values\n"); +- ret = 0; +- } +- +-out: +- kfree(buf); +- +- return ret; +-} +- +-static const struct of_device_id mtk_thermal_of_match[] = { +- { +- .compatible = "mediatek,mt8173-thermal", +- .data = (void *)&mt8173_thermal_data, +- }, +- { +- .compatible = "mediatek,mt2701-thermal", +- .data = (void *)&mt2701_thermal_data, +- }, +- { +- .compatible = "mediatek,mt2712-thermal", +- .data = (void *)&mt2712_thermal_data, +- }, +- { +- .compatible = "mediatek,mt7622-thermal", +- .data = (void *)&mt7622_thermal_data, +- }, +- { +- .compatible = "mediatek,mt7986-thermal", +- .data = (void *)&mt7986_thermal_data, +- }, +- { +- .compatible = "mediatek,mt8183-thermal", +- .data = (void *)&mt8183_thermal_data, +- }, { +- }, +-}; +-MODULE_DEVICE_TABLE(of, mtk_thermal_of_match); +- +-static void mtk_thermal_turn_on_buffer(void __iomem *apmixed_base) +-{ +- int tmp; +- +- tmp = readl(apmixed_base + APMIXED_SYS_TS_CON1); +- tmp &= ~(0x37); +- tmp |= 0x1; +- writel(tmp, apmixed_base + APMIXED_SYS_TS_CON1); +- udelay(200); +-} +- +-static void mtk_thermal_release_periodic_ts(struct mtk_thermal *mt, +- void __iomem *auxadc_base) +-{ +- int tmp; +- +- writel(0x800, auxadc_base + AUXADC_CON1_SET_V); +- writel(0x1, mt->thermal_base + TEMP_MONCTL0); +- tmp = readl(mt->thermal_base + TEMP_MSRCTL1); +- writel((tmp & (~0x10e)), mt->thermal_base + TEMP_MSRCTL1); +-} +- +-static int mtk_thermal_probe(struct platform_device *pdev) +-{ +- int ret, i, ctrl_id; +- struct device_node *auxadc, *apmixedsys, *np = pdev->dev.of_node; +- struct mtk_thermal *mt; +- u64 auxadc_phys_base, apmixed_phys_base; +- struct thermal_zone_device *tzdev; +- void __iomem *apmixed_base, *auxadc_base; +- +- mt = devm_kzalloc(&pdev->dev, sizeof(*mt), GFP_KERNEL); +- if (!mt) +- return -ENOMEM; +- +- mt->conf = of_device_get_match_data(&pdev->dev); +- +- mt->clk_peri_therm = devm_clk_get(&pdev->dev, "therm"); +- if (IS_ERR(mt->clk_peri_therm)) +- return PTR_ERR(mt->clk_peri_therm); +- +- mt->clk_auxadc = devm_clk_get(&pdev->dev, "auxadc"); +- if (IS_ERR(mt->clk_auxadc)) +- return PTR_ERR(mt->clk_auxadc); +- +- mt->thermal_base = devm_platform_get_and_ioremap_resource(pdev, 0, NULL); +- if (IS_ERR(mt->thermal_base)) +- return PTR_ERR(mt->thermal_base); +- +- ret = mtk_thermal_get_calibration_data(&pdev->dev, mt); +- if (ret) +- return ret; +- +- mutex_init(&mt->lock); +- +- mt->dev = &pdev->dev; +- +- auxadc = of_parse_phandle(np, "mediatek,auxadc", 0); +- if (!auxadc) { +- dev_err(&pdev->dev, "missing auxadc node\n"); +- return -ENODEV; +- } +- +- auxadc_base = of_iomap(auxadc, 0); +- auxadc_phys_base = of_get_phys_base(auxadc); +- +- of_node_put(auxadc); +- +- if (auxadc_phys_base == OF_BAD_ADDR) { +- dev_err(&pdev->dev, "Can't get auxadc phys address\n"); +- return -EINVAL; +- } +- +- apmixedsys = of_parse_phandle(np, "mediatek,apmixedsys", 0); +- if (!apmixedsys) { +- dev_err(&pdev->dev, "missing apmixedsys node\n"); +- return -ENODEV; +- } +- +- apmixed_base = of_iomap(apmixedsys, 0); +- apmixed_phys_base = of_get_phys_base(apmixedsys); +- +- of_node_put(apmixedsys); +- +- if (apmixed_phys_base == OF_BAD_ADDR) { +- dev_err(&pdev->dev, "Can't get auxadc phys address\n"); +- return -EINVAL; +- } +- +- ret = device_reset_optional(&pdev->dev); +- if (ret) +- return ret; +- +- ret = clk_prepare_enable(mt->clk_auxadc); +- if (ret) { +- dev_err(&pdev->dev, "Can't enable auxadc clk: %d\n", ret); +- return ret; +- } +- +- ret = clk_prepare_enable(mt->clk_peri_therm); +- if (ret) { +- dev_err(&pdev->dev, "Can't enable peri clk: %d\n", ret); +- goto err_disable_clk_auxadc; +- } +- +- if (mt->conf->version != MTK_THERMAL_V1) { +- mtk_thermal_turn_on_buffer(apmixed_base); +- mtk_thermal_release_periodic_ts(mt, auxadc_base); +- } +- +- if (mt->conf->version == MTK_THERMAL_V1) +- mt->raw_to_mcelsius = raw_to_mcelsius_v1; +- else if (mt->conf->version == MTK_THERMAL_V2) +- mt->raw_to_mcelsius = raw_to_mcelsius_v2; +- else +- mt->raw_to_mcelsius = raw_to_mcelsius_v3; +- +- for (ctrl_id = 0; ctrl_id < mt->conf->num_controller ; ctrl_id++) +- for (i = 0; i < mt->conf->num_banks; i++) +- mtk_thermal_init_bank(mt, i, apmixed_phys_base, +- auxadc_phys_base, ctrl_id); +- +- platform_set_drvdata(pdev, mt); +- +- tzdev = devm_thermal_of_zone_register(&pdev->dev, 0, mt, +- &mtk_thermal_ops); +- if (IS_ERR(tzdev)) { +- ret = PTR_ERR(tzdev); +- goto err_disable_clk_peri_therm; +- } +- +- ret = devm_thermal_add_hwmon_sysfs(tzdev); +- if (ret) +- dev_warn(&pdev->dev, "error in thermal_add_hwmon_sysfs"); +- +- return 0; +- +-err_disable_clk_peri_therm: +- clk_disable_unprepare(mt->clk_peri_therm); +-err_disable_clk_auxadc: +- clk_disable_unprepare(mt->clk_auxadc); +- +- return ret; +-} +- +-static int mtk_thermal_remove(struct platform_device *pdev) +-{ +- struct mtk_thermal *mt = platform_get_drvdata(pdev); +- +- clk_disable_unprepare(mt->clk_peri_therm); +- clk_disable_unprepare(mt->clk_auxadc); +- +- return 0; +-} +- +-static struct platform_driver mtk_thermal_driver = { +- .probe = mtk_thermal_probe, +- .remove = mtk_thermal_remove, +- .driver = { +- .name = "mtk-thermal", +- .of_match_table = mtk_thermal_of_match, +- }, +-}; +- +-module_platform_driver(mtk_thermal_driver); +- +-MODULE_AUTHOR("Michael Kao "); +-MODULE_AUTHOR("Louis Yu "); +-MODULE_AUTHOR("Dawei Chien "); +-MODULE_AUTHOR("Sascha Hauer "); +-MODULE_AUTHOR("Hanyi Wu "); +-MODULE_DESCRIPTION("Mediatek thermal driver"); +-MODULE_LICENSE("GPL v2"); +--- /dev/null ++++ b/drivers/thermal/mediatek/auxadc_thermal.c +@@ -0,0 +1,1254 @@ ++// SPDX-License-Identifier: GPL-2.0-only ++/* ++ * Copyright (c) 2015 MediaTek Inc. ++ * Author: Hanyi Wu ++ * Sascha Hauer ++ * Dawei Chien ++ * Louis Yu ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "../thermal_hwmon.h" ++ ++/* AUXADC Registers */ ++#define AUXADC_CON1_SET_V 0x008 ++#define AUXADC_CON1_CLR_V 0x00c ++#define AUXADC_CON2_V 0x010 ++#define AUXADC_DATA(channel) (0x14 + (channel) * 4) ++ ++#define APMIXED_SYS_TS_CON1 0x604 ++ ++/* Thermal Controller Registers */ ++#define TEMP_MONCTL0 0x000 ++#define TEMP_MONCTL1 0x004 ++#define TEMP_MONCTL2 0x008 ++#define TEMP_MONIDET0 0x014 ++#define TEMP_MONIDET1 0x018 ++#define TEMP_MSRCTL0 0x038 ++#define TEMP_MSRCTL1 0x03c ++#define TEMP_AHBPOLL 0x040 ++#define TEMP_AHBTO 0x044 ++#define TEMP_ADCPNP0 0x048 ++#define TEMP_ADCPNP1 0x04c ++#define TEMP_ADCPNP2 0x050 ++#define TEMP_ADCPNP3 0x0b4 ++ ++#define TEMP_ADCMUX 0x054 ++#define TEMP_ADCEN 0x060 ++#define TEMP_PNPMUXADDR 0x064 ++#define TEMP_ADCMUXADDR 0x068 ++#define TEMP_ADCENADDR 0x074 ++#define TEMP_ADCVALIDADDR 0x078 ++#define TEMP_ADCVOLTADDR 0x07c ++#define TEMP_RDCTRL 0x080 ++#define TEMP_ADCVALIDMASK 0x084 ++#define TEMP_ADCVOLTAGESHIFT 0x088 ++#define TEMP_ADCWRITECTRL 0x08c ++#define TEMP_MSR0 0x090 ++#define TEMP_MSR1 0x094 ++#define TEMP_MSR2 0x098 ++#define TEMP_MSR3 0x0B8 ++ ++#define TEMP_SPARE0 0x0f0 ++ ++#define TEMP_ADCPNP0_1 0x148 ++#define TEMP_ADCPNP1_1 0x14c ++#define TEMP_ADCPNP2_1 0x150 ++#define TEMP_MSR0_1 0x190 ++#define TEMP_MSR1_1 0x194 ++#define TEMP_MSR2_1 0x198 ++#define TEMP_ADCPNP3_1 0x1b4 ++#define TEMP_MSR3_1 0x1B8 ++ ++#define PTPCORESEL 0x400 ++ ++#define TEMP_MONCTL1_PERIOD_UNIT(x) ((x) & 0x3ff) ++ ++#define TEMP_MONCTL2_FILTER_INTERVAL(x) (((x) & 0x3ff) << 16) ++#define TEMP_MONCTL2_SENSOR_INTERVAL(x) ((x) & 0x3ff) ++ ++#define TEMP_AHBPOLL_ADC_POLL_INTERVAL(x) (x) ++ ++#define TEMP_ADCWRITECTRL_ADC_PNP_WRITE BIT(0) ++#define TEMP_ADCWRITECTRL_ADC_MUX_WRITE BIT(1) ++ ++#define TEMP_ADCVALIDMASK_VALID_HIGH BIT(5) ++#define TEMP_ADCVALIDMASK_VALID_POS(bit) (bit) ++ ++/* MT8173 thermal sensors */ ++#define MT8173_TS1 0 ++#define MT8173_TS2 1 ++#define MT8173_TS3 2 ++#define MT8173_TS4 3 ++#define MT8173_TSABB 4 ++ ++/* AUXADC channel 11 is used for the temperature sensors */ ++#define MT8173_TEMP_AUXADC_CHANNEL 11 ++ ++/* The total number of temperature sensors in the MT8173 */ ++#define MT8173_NUM_SENSORS 5 ++ ++/* The number of banks in the MT8173 */ ++#define MT8173_NUM_ZONES 4 ++ ++/* The number of sensing points per bank */ ++#define MT8173_NUM_SENSORS_PER_ZONE 4 ++ ++/* The number of controller in the MT8173 */ ++#define MT8173_NUM_CONTROLLER 1 ++ ++/* The calibration coefficient of sensor */ ++#define MT8173_CALIBRATION 165 ++ ++/* ++ * Layout of the fuses providing the calibration data ++ * These macros could be used for MT8183, MT8173, MT2701, and MT2712. ++ * MT8183 has 6 sensors and needs 6 VTS calibration data. ++ * MT8173 has 5 sensors and needs 5 VTS calibration data. ++ * MT2701 has 3 sensors and needs 3 VTS calibration data. ++ * MT2712 has 4 sensors and needs 4 VTS calibration data. ++ */ ++#define CALIB_BUF0_VALID_V1 BIT(0) ++#define CALIB_BUF1_ADC_GE_V1(x) (((x) >> 22) & 0x3ff) ++#define CALIB_BUF0_VTS_TS1_V1(x) (((x) >> 17) & 0x1ff) ++#define CALIB_BUF0_VTS_TS2_V1(x) (((x) >> 8) & 0x1ff) ++#define CALIB_BUF1_VTS_TS3_V1(x) (((x) >> 0) & 0x1ff) ++#define CALIB_BUF2_VTS_TS4_V1(x) (((x) >> 23) & 0x1ff) ++#define CALIB_BUF2_VTS_TS5_V1(x) (((x) >> 5) & 0x1ff) ++#define CALIB_BUF2_VTS_TSABB_V1(x) (((x) >> 14) & 0x1ff) ++#define CALIB_BUF0_DEGC_CALI_V1(x) (((x) >> 1) & 0x3f) ++#define CALIB_BUF0_O_SLOPE_V1(x) (((x) >> 26) & 0x3f) ++#define CALIB_BUF0_O_SLOPE_SIGN_V1(x) (((x) >> 7) & 0x1) ++#define CALIB_BUF1_ID_V1(x) (((x) >> 9) & 0x1) ++ ++/* ++ * Layout of the fuses providing the calibration data ++ * These macros could be used for MT7622. ++ */ ++#define CALIB_BUF0_ADC_OE_V2(x) (((x) >> 22) & 0x3ff) ++#define CALIB_BUF0_ADC_GE_V2(x) (((x) >> 12) & 0x3ff) ++#define CALIB_BUF0_DEGC_CALI_V2(x) (((x) >> 6) & 0x3f) ++#define CALIB_BUF0_O_SLOPE_V2(x) (((x) >> 0) & 0x3f) ++#define CALIB_BUF1_VTS_TS1_V2(x) (((x) >> 23) & 0x1ff) ++#define CALIB_BUF1_VTS_TS2_V2(x) (((x) >> 14) & 0x1ff) ++#define CALIB_BUF1_VTS_TSABB_V2(x) (((x) >> 5) & 0x1ff) ++#define CALIB_BUF1_VALID_V2(x) (((x) >> 4) & 0x1) ++#define CALIB_BUF1_O_SLOPE_SIGN_V2(x) (((x) >> 3) & 0x1) ++ ++/* ++ * Layout of the fuses providing the calibration data ++ * These macros can be used for MT7981 and MT7986. ++ */ ++#define CALIB_BUF0_ADC_GE_V3(x) (((x) >> 0) & 0x3ff) ++#define CALIB_BUF0_DEGC_CALI_V3(x) (((x) >> 20) & 0x3f) ++#define CALIB_BUF0_O_SLOPE_V3(x) (((x) >> 26) & 0x3f) ++#define CALIB_BUF1_VTS_TS1_V3(x) (((x) >> 0) & 0x1ff) ++#define CALIB_BUF1_VTS_TS2_V3(x) (((x) >> 21) & 0x1ff) ++#define CALIB_BUF1_VTS_TSABB_V3(x) (((x) >> 9) & 0x1ff) ++#define CALIB_BUF1_VALID_V3(x) (((x) >> 18) & 0x1) ++#define CALIB_BUF1_O_SLOPE_SIGN_V3(x) (((x) >> 19) & 0x1) ++#define CALIB_BUF1_ID_V3(x) (((x) >> 20) & 0x1) ++ ++enum { ++ VTS1, ++ VTS2, ++ VTS3, ++ VTS4, ++ VTS5, ++ VTSABB, ++ MAX_NUM_VTS, ++}; ++ ++enum mtk_thermal_version { ++ MTK_THERMAL_V1 = 1, ++ MTK_THERMAL_V2, ++ MTK_THERMAL_V3, ++}; ++ ++/* MT2701 thermal sensors */ ++#define MT2701_TS1 0 ++#define MT2701_TS2 1 ++#define MT2701_TSABB 2 ++ ++/* AUXADC channel 11 is used for the temperature sensors */ ++#define MT2701_TEMP_AUXADC_CHANNEL 11 ++ ++/* The total number of temperature sensors in the MT2701 */ ++#define MT2701_NUM_SENSORS 3 ++ ++/* The number of sensing points per bank */ ++#define MT2701_NUM_SENSORS_PER_ZONE 3 ++ ++/* The number of controller in the MT2701 */ ++#define MT2701_NUM_CONTROLLER 1 ++ ++/* The calibration coefficient of sensor */ ++#define MT2701_CALIBRATION 165 ++ ++/* MT2712 thermal sensors */ ++#define MT2712_TS1 0 ++#define MT2712_TS2 1 ++#define MT2712_TS3 2 ++#define MT2712_TS4 3 ++ ++/* AUXADC channel 11 is used for the temperature sensors */ ++#define MT2712_TEMP_AUXADC_CHANNEL 11 ++ ++/* The total number of temperature sensors in the MT2712 */ ++#define MT2712_NUM_SENSORS 4 ++ ++/* The number of sensing points per bank */ ++#define MT2712_NUM_SENSORS_PER_ZONE 4 ++ ++/* The number of controller in the MT2712 */ ++#define MT2712_NUM_CONTROLLER 1 ++ ++/* The calibration coefficient of sensor */ ++#define MT2712_CALIBRATION 165 ++ ++#define MT7622_TEMP_AUXADC_CHANNEL 11 ++#define MT7622_NUM_SENSORS 1 ++#define MT7622_NUM_ZONES 1 ++#define MT7622_NUM_SENSORS_PER_ZONE 1 ++#define MT7622_TS1 0 ++#define MT7622_NUM_CONTROLLER 1 ++ ++/* The maximum number of banks */ ++#define MAX_NUM_ZONES 8 ++ ++/* The calibration coefficient of sensor */ ++#define MT7622_CALIBRATION 165 ++ ++/* MT8183 thermal sensors */ ++#define MT8183_TS1 0 ++#define MT8183_TS2 1 ++#define MT8183_TS3 2 ++#define MT8183_TS4 3 ++#define MT8183_TS5 4 ++#define MT8183_TSABB 5 ++ ++/* AUXADC channel is used for the temperature sensors */ ++#define MT8183_TEMP_AUXADC_CHANNEL 11 ++ ++/* The total number of temperature sensors in the MT8183 */ ++#define MT8183_NUM_SENSORS 6 ++ ++/* The number of banks in the MT8183 */ ++#define MT8183_NUM_ZONES 1 ++ ++/* The number of sensing points per bank */ ++#define MT8183_NUM_SENSORS_PER_ZONE 6 ++ ++/* The number of controller in the MT8183 */ ++#define MT8183_NUM_CONTROLLER 2 ++ ++/* The calibration coefficient of sensor */ ++#define MT8183_CALIBRATION 153 ++ ++/* AUXADC channel 11 is used for the temperature sensors */ ++#define MT7986_TEMP_AUXADC_CHANNEL 11 ++ ++/* The total number of temperature sensors in the MT7986 */ ++#define MT7986_NUM_SENSORS 1 ++ ++/* The number of banks in the MT7986 */ ++#define MT7986_NUM_ZONES 1 ++ ++/* The number of sensing points per bank */ ++#define MT7986_NUM_SENSORS_PER_ZONE 1 ++ ++/* MT7986 thermal sensors */ ++#define MT7986_TS1 0 ++ ++/* The number of controller in the MT7986 */ ++#define MT7986_NUM_CONTROLLER 1 ++ ++/* The calibration coefficient of sensor */ ++#define MT7986_CALIBRATION 165 ++ ++struct mtk_thermal; ++ ++struct thermal_bank_cfg { ++ unsigned int num_sensors; ++ const int *sensors; ++}; ++ ++struct mtk_thermal_bank { ++ struct mtk_thermal *mt; ++ int id; ++}; ++ ++struct mtk_thermal_data { ++ s32 num_banks; ++ s32 num_sensors; ++ s32 auxadc_channel; ++ const int *vts_index; ++ const int *sensor_mux_values; ++ const int *msr; ++ const int *adcpnp; ++ const int cali_val; ++ const int num_controller; ++ const int *controller_offset; ++ bool need_switch_bank; ++ struct thermal_bank_cfg bank_data[MAX_NUM_ZONES]; ++ enum mtk_thermal_version version; ++}; ++ ++struct mtk_thermal { ++ struct device *dev; ++ void __iomem *thermal_base; ++ ++ struct clk *clk_peri_therm; ++ struct clk *clk_auxadc; ++ /* lock: for getting and putting banks */ ++ struct mutex lock; ++ ++ /* Calibration values */ ++ s32 adc_ge; ++ s32 adc_oe; ++ s32 degc_cali; ++ s32 o_slope; ++ s32 o_slope_sign; ++ s32 vts[MAX_NUM_VTS]; ++ ++ const struct mtk_thermal_data *conf; ++ struct mtk_thermal_bank banks[MAX_NUM_ZONES]; ++ ++ int (*raw_to_mcelsius)(struct mtk_thermal *mt, int sensno, s32 raw); ++}; ++ ++/* MT8183 thermal sensor data */ ++static const int mt8183_bank_data[MT8183_NUM_SENSORS] = { ++ MT8183_TS1, MT8183_TS2, MT8183_TS3, MT8183_TS4, MT8183_TS5, MT8183_TSABB ++}; ++ ++static const int mt8183_msr[MT8183_NUM_SENSORS_PER_ZONE] = { ++ TEMP_MSR0_1, TEMP_MSR1_1, TEMP_MSR2_1, TEMP_MSR1, TEMP_MSR0, TEMP_MSR3_1 ++}; ++ ++static const int mt8183_adcpnp[MT8183_NUM_SENSORS_PER_ZONE] = { ++ TEMP_ADCPNP0_1, TEMP_ADCPNP1_1, TEMP_ADCPNP2_1, ++ TEMP_ADCPNP1, TEMP_ADCPNP0, TEMP_ADCPNP3_1 ++}; ++ ++static const int mt8183_mux_values[MT8183_NUM_SENSORS] = { 0, 1, 2, 3, 4, 0 }; ++static const int mt8183_tc_offset[MT8183_NUM_CONTROLLER] = {0x0, 0x100}; ++ ++static const int mt8183_vts_index[MT8183_NUM_SENSORS] = { ++ VTS1, VTS2, VTS3, VTS4, VTS5, VTSABB ++}; ++ ++/* MT8173 thermal sensor data */ ++static const int mt8173_bank_data[MT8173_NUM_ZONES][3] = { ++ { MT8173_TS2, MT8173_TS3 }, ++ { MT8173_TS2, MT8173_TS4 }, ++ { MT8173_TS1, MT8173_TS2, MT8173_TSABB }, ++ { MT8173_TS2 }, ++}; ++ ++static const int mt8173_msr[MT8173_NUM_SENSORS_PER_ZONE] = { ++ TEMP_MSR0, TEMP_MSR1, TEMP_MSR2, TEMP_MSR3 ++}; ++ ++static const int mt8173_adcpnp[MT8173_NUM_SENSORS_PER_ZONE] = { ++ TEMP_ADCPNP0, TEMP_ADCPNP1, TEMP_ADCPNP2, TEMP_ADCPNP3 ++}; ++ ++static const int mt8173_mux_values[MT8173_NUM_SENSORS] = { 0, 1, 2, 3, 16 }; ++static const int mt8173_tc_offset[MT8173_NUM_CONTROLLER] = { 0x0, }; ++ ++static const int mt8173_vts_index[MT8173_NUM_SENSORS] = { ++ VTS1, VTS2, VTS3, VTS4, VTSABB ++}; ++ ++/* MT2701 thermal sensor data */ ++static const int mt2701_bank_data[MT2701_NUM_SENSORS] = { ++ MT2701_TS1, MT2701_TS2, MT2701_TSABB ++}; ++ ++static const int mt2701_msr[MT2701_NUM_SENSORS_PER_ZONE] = { ++ TEMP_MSR0, TEMP_MSR1, TEMP_MSR2 ++}; ++ ++static const int mt2701_adcpnp[MT2701_NUM_SENSORS_PER_ZONE] = { ++ TEMP_ADCPNP0, TEMP_ADCPNP1, TEMP_ADCPNP2 ++}; ++ ++static const int mt2701_mux_values[MT2701_NUM_SENSORS] = { 0, 1, 16 }; ++static const int mt2701_tc_offset[MT2701_NUM_CONTROLLER] = { 0x0, }; ++ ++static const int mt2701_vts_index[MT2701_NUM_SENSORS] = { ++ VTS1, VTS2, VTS3 ++}; ++ ++/* MT2712 thermal sensor data */ ++static const int mt2712_bank_data[MT2712_NUM_SENSORS] = { ++ MT2712_TS1, MT2712_TS2, MT2712_TS3, MT2712_TS4 ++}; ++ ++static const int mt2712_msr[MT2712_NUM_SENSORS_PER_ZONE] = { ++ TEMP_MSR0, TEMP_MSR1, TEMP_MSR2, TEMP_MSR3 ++}; ++ ++static const int mt2712_adcpnp[MT2712_NUM_SENSORS_PER_ZONE] = { ++ TEMP_ADCPNP0, TEMP_ADCPNP1, TEMP_ADCPNP2, TEMP_ADCPNP3 ++}; ++ ++static const int mt2712_mux_values[MT2712_NUM_SENSORS] = { 0, 1, 2, 3 }; ++static const int mt2712_tc_offset[MT2712_NUM_CONTROLLER] = { 0x0, }; ++ ++static const int mt2712_vts_index[MT2712_NUM_SENSORS] = { ++ VTS1, VTS2, VTS3, VTS4 ++}; ++ ++/* MT7622 thermal sensor data */ ++static const int mt7622_bank_data[MT7622_NUM_SENSORS] = { MT7622_TS1, }; ++static const int mt7622_msr[MT7622_NUM_SENSORS_PER_ZONE] = { TEMP_MSR0, }; ++static const int mt7622_adcpnp[MT7622_NUM_SENSORS_PER_ZONE] = { TEMP_ADCPNP0, }; ++static const int mt7622_mux_values[MT7622_NUM_SENSORS] = { 0, }; ++static const int mt7622_vts_index[MT7622_NUM_SENSORS] = { VTS1 }; ++static const int mt7622_tc_offset[MT7622_NUM_CONTROLLER] = { 0x0, }; ++ ++/* MT7986 thermal sensor data */ ++static const int mt7986_bank_data[MT7986_NUM_SENSORS] = { MT7986_TS1, }; ++static const int mt7986_msr[MT7986_NUM_SENSORS_PER_ZONE] = { TEMP_MSR0, }; ++static const int mt7986_adcpnp[MT7986_NUM_SENSORS_PER_ZONE] = { TEMP_ADCPNP0, }; ++static const int mt7986_mux_values[MT7986_NUM_SENSORS] = { 0, }; ++static const int mt7986_vts_index[MT7986_NUM_SENSORS] = { VTS1 }; ++static const int mt7986_tc_offset[MT7986_NUM_CONTROLLER] = { 0x0, }; ++ ++/* ++ * The MT8173 thermal controller has four banks. Each bank can read up to ++ * four temperature sensors simultaneously. The MT8173 has a total of 5 ++ * temperature sensors. We use each bank to measure a certain area of the ++ * SoC. Since TS2 is located centrally in the SoC it is influenced by multiple ++ * areas, hence is used in different banks. ++ * ++ * The thermal core only gets the maximum temperature of all banks, so ++ * the bank concept wouldn't be necessary here. However, the SVS (Smart ++ * Voltage Scaling) unit makes its decisions based on the same bank ++ * data, and this indeed needs the temperatures of the individual banks ++ * for making better decisions. ++ */ ++static const struct mtk_thermal_data mt8173_thermal_data = { ++ .auxadc_channel = MT8173_TEMP_AUXADC_CHANNEL, ++ .num_banks = MT8173_NUM_ZONES, ++ .num_sensors = MT8173_NUM_SENSORS, ++ .vts_index = mt8173_vts_index, ++ .cali_val = MT8173_CALIBRATION, ++ .num_controller = MT8173_NUM_CONTROLLER, ++ .controller_offset = mt8173_tc_offset, ++ .need_switch_bank = true, ++ .bank_data = { ++ { ++ .num_sensors = 2, ++ .sensors = mt8173_bank_data[0], ++ }, { ++ .num_sensors = 2, ++ .sensors = mt8173_bank_data[1], ++ }, { ++ .num_sensors = 3, ++ .sensors = mt8173_bank_data[2], ++ }, { ++ .num_sensors = 1, ++ .sensors = mt8173_bank_data[3], ++ }, ++ }, ++ .msr = mt8173_msr, ++ .adcpnp = mt8173_adcpnp, ++ .sensor_mux_values = mt8173_mux_values, ++ .version = MTK_THERMAL_V1, ++}; ++ ++/* ++ * The MT2701 thermal controller has one bank, which can read up to ++ * three temperature sensors simultaneously. The MT2701 has a total of 3 ++ * temperature sensors. ++ * ++ * The thermal core only gets the maximum temperature of this one bank, ++ * so the bank concept wouldn't be necessary here. However, the SVS (Smart ++ * Voltage Scaling) unit makes its decisions based on the same bank ++ * data. ++ */ ++static const struct mtk_thermal_data mt2701_thermal_data = { ++ .auxadc_channel = MT2701_TEMP_AUXADC_CHANNEL, ++ .num_banks = 1, ++ .num_sensors = MT2701_NUM_SENSORS, ++ .vts_index = mt2701_vts_index, ++ .cali_val = MT2701_CALIBRATION, ++ .num_controller = MT2701_NUM_CONTROLLER, ++ .controller_offset = mt2701_tc_offset, ++ .need_switch_bank = true, ++ .bank_data = { ++ { ++ .num_sensors = 3, ++ .sensors = mt2701_bank_data, ++ }, ++ }, ++ .msr = mt2701_msr, ++ .adcpnp = mt2701_adcpnp, ++ .sensor_mux_values = mt2701_mux_values, ++ .version = MTK_THERMAL_V1, ++}; ++ ++/* ++ * The MT2712 thermal controller has one bank, which can read up to ++ * four temperature sensors simultaneously. The MT2712 has a total of 4 ++ * temperature sensors. ++ * ++ * The thermal core only gets the maximum temperature of this one bank, ++ * so the bank concept wouldn't be necessary here. However, the SVS (Smart ++ * Voltage Scaling) unit makes its decisions based on the same bank ++ * data. ++ */ ++static const struct mtk_thermal_data mt2712_thermal_data = { ++ .auxadc_channel = MT2712_TEMP_AUXADC_CHANNEL, ++ .num_banks = 1, ++ .num_sensors = MT2712_NUM_SENSORS, ++ .vts_index = mt2712_vts_index, ++ .cali_val = MT2712_CALIBRATION, ++ .num_controller = MT2712_NUM_CONTROLLER, ++ .controller_offset = mt2712_tc_offset, ++ .need_switch_bank = true, ++ .bank_data = { ++ { ++ .num_sensors = 4, ++ .sensors = mt2712_bank_data, ++ }, ++ }, ++ .msr = mt2712_msr, ++ .adcpnp = mt2712_adcpnp, ++ .sensor_mux_values = mt2712_mux_values, ++ .version = MTK_THERMAL_V1, ++}; ++ ++/* ++ * MT7622 have only one sensing point which uses AUXADC Channel 11 for raw data ++ * access. ++ */ ++static const struct mtk_thermal_data mt7622_thermal_data = { ++ .auxadc_channel = MT7622_TEMP_AUXADC_CHANNEL, ++ .num_banks = MT7622_NUM_ZONES, ++ .num_sensors = MT7622_NUM_SENSORS, ++ .vts_index = mt7622_vts_index, ++ .cali_val = MT7622_CALIBRATION, ++ .num_controller = MT7622_NUM_CONTROLLER, ++ .controller_offset = mt7622_tc_offset, ++ .need_switch_bank = true, ++ .bank_data = { ++ { ++ .num_sensors = 1, ++ .sensors = mt7622_bank_data, ++ }, ++ }, ++ .msr = mt7622_msr, ++ .adcpnp = mt7622_adcpnp, ++ .sensor_mux_values = mt7622_mux_values, ++ .version = MTK_THERMAL_V2, ++}; ++ ++/* ++ * The MT8183 thermal controller has one bank for the current SW framework. ++ * The MT8183 has a total of 6 temperature sensors. ++ * There are two thermal controller to control the six sensor. ++ * The first one bind 2 sensor, and the other bind 4 sensors. ++ * The thermal core only gets the maximum temperature of all sensor, so ++ * the bank concept wouldn't be necessary here. However, the SVS (Smart ++ * Voltage Scaling) unit makes its decisions based on the same bank ++ * data, and this indeed needs the temperatures of the individual banks ++ * for making better decisions. ++ */ ++static const struct mtk_thermal_data mt8183_thermal_data = { ++ .auxadc_channel = MT8183_TEMP_AUXADC_CHANNEL, ++ .num_banks = MT8183_NUM_ZONES, ++ .num_sensors = MT8183_NUM_SENSORS, ++ .vts_index = mt8183_vts_index, ++ .cali_val = MT8183_CALIBRATION, ++ .num_controller = MT8183_NUM_CONTROLLER, ++ .controller_offset = mt8183_tc_offset, ++ .need_switch_bank = false, ++ .bank_data = { ++ { ++ .num_sensors = 6, ++ .sensors = mt8183_bank_data, ++ }, ++ }, ++ ++ .msr = mt8183_msr, ++ .adcpnp = mt8183_adcpnp, ++ .sensor_mux_values = mt8183_mux_values, ++ .version = MTK_THERMAL_V1, ++}; ++ ++/* ++ * MT7986 uses AUXADC Channel 11 for raw data access. ++ */ ++static const struct mtk_thermal_data mt7986_thermal_data = { ++ .auxadc_channel = MT7986_TEMP_AUXADC_CHANNEL, ++ .num_banks = MT7986_NUM_ZONES, ++ .num_sensors = MT7986_NUM_SENSORS, ++ .vts_index = mt7986_vts_index, ++ .cali_val = MT7986_CALIBRATION, ++ .num_controller = MT7986_NUM_CONTROLLER, ++ .controller_offset = mt7986_tc_offset, ++ .need_switch_bank = true, ++ .bank_data = { ++ { ++ .num_sensors = 1, ++ .sensors = mt7986_bank_data, ++ }, ++ }, ++ .msr = mt7986_msr, ++ .adcpnp = mt7986_adcpnp, ++ .sensor_mux_values = mt7986_mux_values, ++ .version = MTK_THERMAL_V3, ++}; ++ ++/** ++ * raw_to_mcelsius_v1 - convert a raw ADC value to mcelsius ++ * @mt: The thermal controller ++ * @sensno: sensor number ++ * @raw: raw ADC value ++ * ++ * This converts the raw ADC value to mcelsius using the SoC specific ++ * calibration constants ++ */ ++static int raw_to_mcelsius_v1(struct mtk_thermal *mt, int sensno, s32 raw) ++{ ++ s32 tmp; ++ ++ raw &= 0xfff; ++ ++ tmp = 203450520 << 3; ++ tmp /= mt->conf->cali_val + mt->o_slope; ++ tmp /= 10000 + mt->adc_ge; ++ tmp *= raw - mt->vts[sensno] - 3350; ++ tmp >>= 3; ++ ++ return mt->degc_cali * 500 - tmp; ++} ++ ++static int raw_to_mcelsius_v2(struct mtk_thermal *mt, int sensno, s32 raw) ++{ ++ s32 format_1; ++ s32 format_2; ++ s32 g_oe; ++ s32 g_gain; ++ s32 g_x_roomt; ++ s32 tmp; ++ ++ if (raw == 0) ++ return 0; ++ ++ raw &= 0xfff; ++ g_gain = 10000 + (((mt->adc_ge - 512) * 10000) >> 12); ++ g_oe = mt->adc_oe - 512; ++ format_1 = mt->vts[VTS2] + 3105 - g_oe; ++ format_2 = (mt->degc_cali * 10) >> 1; ++ g_x_roomt = (((format_1 * 10000) >> 12) * 10000) / g_gain; ++ ++ tmp = (((((raw - g_oe) * 10000) >> 12) * 10000) / g_gain) - g_x_roomt; ++ tmp = tmp * 10 * 100 / 11; ++ ++ if (mt->o_slope_sign == 0) ++ tmp = tmp / (165 - mt->o_slope); ++ else ++ tmp = tmp / (165 + mt->o_slope); ++ ++ return (format_2 - tmp) * 100; ++} ++ ++static int raw_to_mcelsius_v3(struct mtk_thermal *mt, int sensno, s32 raw) ++{ ++ s32 tmp; ++ ++ if (raw == 0) ++ return 0; ++ ++ raw &= 0xfff; ++ tmp = 100000 * 15 / 16 * 10000; ++ tmp /= 4096 - 512 + mt->adc_ge; ++ tmp /= 1490; ++ tmp *= raw - mt->vts[sensno] - 2900; ++ ++ return mt->degc_cali * 500 - tmp; ++} ++ ++/** ++ * mtk_thermal_get_bank - get bank ++ * @bank: The bank ++ * ++ * The bank registers are banked, we have to select a bank in the ++ * PTPCORESEL register to access it. ++ */ ++static void mtk_thermal_get_bank(struct mtk_thermal_bank *bank) ++{ ++ struct mtk_thermal *mt = bank->mt; ++ u32 val; ++ ++ if (mt->conf->need_switch_bank) { ++ mutex_lock(&mt->lock); ++ ++ val = readl(mt->thermal_base + PTPCORESEL); ++ val &= ~0xf; ++ val |= bank->id; ++ writel(val, mt->thermal_base + PTPCORESEL); ++ } ++} ++ ++/** ++ * mtk_thermal_put_bank - release bank ++ * @bank: The bank ++ * ++ * release a bank previously taken with mtk_thermal_get_bank, ++ */ ++static void mtk_thermal_put_bank(struct mtk_thermal_bank *bank) ++{ ++ struct mtk_thermal *mt = bank->mt; ++ ++ if (mt->conf->need_switch_bank) ++ mutex_unlock(&mt->lock); ++} ++ ++/** ++ * mtk_thermal_bank_temperature - get the temperature of a bank ++ * @bank: The bank ++ * ++ * The temperature of a bank is considered the maximum temperature of ++ * the sensors associated to the bank. ++ */ ++static int mtk_thermal_bank_temperature(struct mtk_thermal_bank *bank) ++{ ++ struct mtk_thermal *mt = bank->mt; ++ const struct mtk_thermal_data *conf = mt->conf; ++ int i, temp = INT_MIN, max = INT_MIN; ++ u32 raw; ++ ++ for (i = 0; i < conf->bank_data[bank->id].num_sensors; i++) { ++ raw = readl(mt->thermal_base + conf->msr[i]); ++ ++ temp = mt->raw_to_mcelsius( ++ mt, conf->bank_data[bank->id].sensors[i], raw); ++ ++ ++ /* ++ * The first read of a sensor often contains very high bogus ++ * temperature value. Filter these out so that the system does ++ * not immediately shut down. ++ */ ++ if (temp > 200000) ++ temp = 0; ++ ++ if (temp > max) ++ max = temp; ++ } ++ ++ return max; ++} ++ ++static int mtk_read_temp(struct thermal_zone_device *tz, int *temperature) ++{ ++ struct mtk_thermal *mt = tz->devdata; ++ int i; ++ int tempmax = INT_MIN; ++ ++ for (i = 0; i < mt->conf->num_banks; i++) { ++ struct mtk_thermal_bank *bank = &mt->banks[i]; ++ ++ mtk_thermal_get_bank(bank); ++ ++ tempmax = max(tempmax, mtk_thermal_bank_temperature(bank)); ++ ++ mtk_thermal_put_bank(bank); ++ } ++ ++ *temperature = tempmax; ++ ++ return 0; ++} ++ ++static const struct thermal_zone_device_ops mtk_thermal_ops = { ++ .get_temp = mtk_read_temp, ++}; ++ ++static void mtk_thermal_init_bank(struct mtk_thermal *mt, int num, ++ u32 apmixed_phys_base, u32 auxadc_phys_base, ++ int ctrl_id) ++{ ++ struct mtk_thermal_bank *bank = &mt->banks[num]; ++ const struct mtk_thermal_data *conf = mt->conf; ++ int i; ++ ++ int offset = mt->conf->controller_offset[ctrl_id]; ++ void __iomem *controller_base = mt->thermal_base + offset; ++ ++ bank->id = num; ++ bank->mt = mt; ++ ++ mtk_thermal_get_bank(bank); ++ ++ /* bus clock 66M counting unit is 12 * 15.15ns * 256 = 46.540us */ ++ writel(TEMP_MONCTL1_PERIOD_UNIT(12), controller_base + TEMP_MONCTL1); ++ ++ /* ++ * filt interval is 1 * 46.540us = 46.54us, ++ * sen interval is 429 * 46.540us = 19.96ms ++ */ ++ writel(TEMP_MONCTL2_FILTER_INTERVAL(1) | ++ TEMP_MONCTL2_SENSOR_INTERVAL(429), ++ controller_base + TEMP_MONCTL2); ++ ++ /* poll is set to 10u */ ++ writel(TEMP_AHBPOLL_ADC_POLL_INTERVAL(768), ++ controller_base + TEMP_AHBPOLL); ++ ++ /* temperature sampling control, 1 sample */ ++ writel(0x0, controller_base + TEMP_MSRCTL0); ++ ++ /* exceed this polling time, IRQ would be inserted */ ++ writel(0xffffffff, controller_base + TEMP_AHBTO); ++ ++ /* number of interrupts per event, 1 is enough */ ++ writel(0x0, controller_base + TEMP_MONIDET0); ++ writel(0x0, controller_base + TEMP_MONIDET1); ++ ++ /* ++ * The MT8173 thermal controller does not have its own ADC. Instead it ++ * uses AHB bus accesses to control the AUXADC. To do this the thermal ++ * controller has to be programmed with the physical addresses of the ++ * AUXADC registers and with the various bit positions in the AUXADC. ++ * Also the thermal controller controls a mux in the APMIXEDSYS register ++ * space. ++ */ ++ ++ /* ++ * this value will be stored to TEMP_PNPMUXADDR (TEMP_SPARE0) ++ * automatically by hw ++ */ ++ writel(BIT(conf->auxadc_channel), controller_base + TEMP_ADCMUX); ++ ++ /* AHB address for auxadc mux selection */ ++ writel(auxadc_phys_base + AUXADC_CON1_CLR_V, ++ controller_base + TEMP_ADCMUXADDR); ++ ++ if (mt->conf->version == MTK_THERMAL_V1) { ++ /* AHB address for pnp sensor mux selection */ ++ writel(apmixed_phys_base + APMIXED_SYS_TS_CON1, ++ controller_base + TEMP_PNPMUXADDR); ++ } ++ ++ /* AHB value for auxadc enable */ ++ writel(BIT(conf->auxadc_channel), controller_base + TEMP_ADCEN); ++ ++ /* AHB address for auxadc enable (channel 0 immediate mode selected) */ ++ writel(auxadc_phys_base + AUXADC_CON1_SET_V, ++ controller_base + TEMP_ADCENADDR); ++ ++ /* AHB address for auxadc valid bit */ ++ writel(auxadc_phys_base + AUXADC_DATA(conf->auxadc_channel), ++ controller_base + TEMP_ADCVALIDADDR); ++ ++ /* AHB address for auxadc voltage output */ ++ writel(auxadc_phys_base + AUXADC_DATA(conf->auxadc_channel), ++ controller_base + TEMP_ADCVOLTADDR); ++ ++ /* read valid & voltage are at the same register */ ++ writel(0x0, controller_base + TEMP_RDCTRL); ++ ++ /* indicate where the valid bit is */ ++ writel(TEMP_ADCVALIDMASK_VALID_HIGH | TEMP_ADCVALIDMASK_VALID_POS(12), ++ controller_base + TEMP_ADCVALIDMASK); ++ ++ /* no shift */ ++ writel(0x0, controller_base + TEMP_ADCVOLTAGESHIFT); ++ ++ /* enable auxadc mux write transaction */ ++ writel(TEMP_ADCWRITECTRL_ADC_MUX_WRITE, ++ controller_base + TEMP_ADCWRITECTRL); ++ ++ for (i = 0; i < conf->bank_data[num].num_sensors; i++) ++ writel(conf->sensor_mux_values[conf->bank_data[num].sensors[i]], ++ mt->thermal_base + conf->adcpnp[i]); ++ ++ writel((1 << conf->bank_data[num].num_sensors) - 1, ++ controller_base + TEMP_MONCTL0); ++ ++ writel(TEMP_ADCWRITECTRL_ADC_PNP_WRITE | ++ TEMP_ADCWRITECTRL_ADC_MUX_WRITE, ++ controller_base + TEMP_ADCWRITECTRL); ++ ++ mtk_thermal_put_bank(bank); ++} ++ ++static u64 of_get_phys_base(struct device_node *np) ++{ ++ u64 size64; ++ const __be32 *regaddr_p; ++ ++ regaddr_p = of_get_address(np, 0, &size64, NULL); ++ if (!regaddr_p) ++ return OF_BAD_ADDR; ++ ++ return of_translate_address(np, regaddr_p); ++} ++ ++static int mtk_thermal_extract_efuse_v1(struct mtk_thermal *mt, u32 *buf) ++{ ++ int i; ++ ++ if (!(buf[0] & CALIB_BUF0_VALID_V1)) ++ return -EINVAL; ++ ++ mt->adc_ge = CALIB_BUF1_ADC_GE_V1(buf[1]); ++ ++ for (i = 0; i < mt->conf->num_sensors; i++) { ++ switch (mt->conf->vts_index[i]) { ++ case VTS1: ++ mt->vts[VTS1] = CALIB_BUF0_VTS_TS1_V1(buf[0]); ++ break; ++ case VTS2: ++ mt->vts[VTS2] = CALIB_BUF0_VTS_TS2_V1(buf[0]); ++ break; ++ case VTS3: ++ mt->vts[VTS3] = CALIB_BUF1_VTS_TS3_V1(buf[1]); ++ break; ++ case VTS4: ++ mt->vts[VTS4] = CALIB_BUF2_VTS_TS4_V1(buf[2]); ++ break; ++ case VTS5: ++ mt->vts[VTS5] = CALIB_BUF2_VTS_TS5_V1(buf[2]); ++ break; ++ case VTSABB: ++ mt->vts[VTSABB] = ++ CALIB_BUF2_VTS_TSABB_V1(buf[2]); ++ break; ++ default: ++ break; ++ } ++ } ++ ++ mt->degc_cali = CALIB_BUF0_DEGC_CALI_V1(buf[0]); ++ if (CALIB_BUF1_ID_V1(buf[1]) & ++ CALIB_BUF0_O_SLOPE_SIGN_V1(buf[0])) ++ mt->o_slope = -CALIB_BUF0_O_SLOPE_V1(buf[0]); ++ else ++ mt->o_slope = CALIB_BUF0_O_SLOPE_V1(buf[0]); ++ ++ return 0; ++} ++ ++static int mtk_thermal_extract_efuse_v2(struct mtk_thermal *mt, u32 *buf) ++{ ++ if (!CALIB_BUF1_VALID_V2(buf[1])) ++ return -EINVAL; ++ ++ mt->adc_oe = CALIB_BUF0_ADC_OE_V2(buf[0]); ++ mt->adc_ge = CALIB_BUF0_ADC_GE_V2(buf[0]); ++ mt->degc_cali = CALIB_BUF0_DEGC_CALI_V2(buf[0]); ++ mt->o_slope = CALIB_BUF0_O_SLOPE_V2(buf[0]); ++ mt->vts[VTS1] = CALIB_BUF1_VTS_TS1_V2(buf[1]); ++ mt->vts[VTS2] = CALIB_BUF1_VTS_TS2_V2(buf[1]); ++ mt->vts[VTSABB] = CALIB_BUF1_VTS_TSABB_V2(buf[1]); ++ mt->o_slope_sign = CALIB_BUF1_O_SLOPE_SIGN_V2(buf[1]); ++ ++ return 0; ++} ++ ++static int mtk_thermal_extract_efuse_v3(struct mtk_thermal *mt, u32 *buf) ++{ ++ if (!CALIB_BUF1_VALID_V3(buf[1])) ++ return -EINVAL; ++ ++ mt->adc_ge = CALIB_BUF0_ADC_GE_V3(buf[0]); ++ mt->degc_cali = CALIB_BUF0_DEGC_CALI_V3(buf[0]); ++ mt->o_slope = CALIB_BUF0_O_SLOPE_V3(buf[0]); ++ mt->vts[VTS1] = CALIB_BUF1_VTS_TS1_V3(buf[1]); ++ mt->vts[VTS2] = CALIB_BUF1_VTS_TS2_V3(buf[1]); ++ mt->vts[VTSABB] = CALIB_BUF1_VTS_TSABB_V3(buf[1]); ++ mt->o_slope_sign = CALIB_BUF1_O_SLOPE_SIGN_V3(buf[1]); ++ ++ if (CALIB_BUF1_ID_V3(buf[1]) == 0) ++ mt->o_slope = 0; ++ ++ return 0; ++} ++ ++static int mtk_thermal_get_calibration_data(struct device *dev, ++ struct mtk_thermal *mt) ++{ ++ struct nvmem_cell *cell; ++ u32 *buf; ++ size_t len; ++ int i, ret = 0; ++ ++ /* Start with default values */ ++ mt->adc_ge = 512; ++ mt->adc_oe = 512; ++ for (i = 0; i < mt->conf->num_sensors; i++) ++ mt->vts[i] = 260; ++ mt->degc_cali = 40; ++ mt->o_slope = 0; ++ ++ cell = nvmem_cell_get(dev, "calibration-data"); ++ if (IS_ERR(cell)) { ++ if (PTR_ERR(cell) == -EPROBE_DEFER) ++ return PTR_ERR(cell); ++ return 0; ++ } ++ ++ buf = (u32 *)nvmem_cell_read(cell, &len); ++ ++ nvmem_cell_put(cell); ++ ++ if (IS_ERR(buf)) ++ return PTR_ERR(buf); ++ ++ if (len < 3 * sizeof(u32)) { ++ dev_warn(dev, "invalid calibration data\n"); ++ ret = -EINVAL; ++ goto out; ++ } ++ ++ switch (mt->conf->version) { ++ case MTK_THERMAL_V1: ++ ret = mtk_thermal_extract_efuse_v1(mt, buf); ++ break; ++ case MTK_THERMAL_V2: ++ ret = mtk_thermal_extract_efuse_v2(mt, buf); ++ break; ++ case MTK_THERMAL_V3: ++ ret = mtk_thermal_extract_efuse_v3(mt, buf); ++ break; ++ default: ++ ret = -EINVAL; ++ break; ++ } ++ ++ if (ret) { ++ dev_info(dev, "Device not calibrated, using default calibration values\n"); ++ ret = 0; ++ } ++ ++out: ++ kfree(buf); ++ ++ return ret; ++} ++ ++static const struct of_device_id mtk_thermal_of_match[] = { ++ { ++ .compatible = "mediatek,mt8173-thermal", ++ .data = (void *)&mt8173_thermal_data, ++ }, ++ { ++ .compatible = "mediatek,mt2701-thermal", ++ .data = (void *)&mt2701_thermal_data, ++ }, ++ { ++ .compatible = "mediatek,mt2712-thermal", ++ .data = (void *)&mt2712_thermal_data, ++ }, ++ { ++ .compatible = "mediatek,mt7622-thermal", ++ .data = (void *)&mt7622_thermal_data, ++ }, ++ { ++ .compatible = "mediatek,mt7986-thermal", ++ .data = (void *)&mt7986_thermal_data, ++ }, ++ { ++ .compatible = "mediatek,mt8183-thermal", ++ .data = (void *)&mt8183_thermal_data, ++ }, { ++ }, ++}; ++MODULE_DEVICE_TABLE(of, mtk_thermal_of_match); ++ ++static void mtk_thermal_turn_on_buffer(void __iomem *apmixed_base) ++{ ++ int tmp; ++ ++ tmp = readl(apmixed_base + APMIXED_SYS_TS_CON1); ++ tmp &= ~(0x37); ++ tmp |= 0x1; ++ writel(tmp, apmixed_base + APMIXED_SYS_TS_CON1); ++ udelay(200); ++} ++ ++static void mtk_thermal_release_periodic_ts(struct mtk_thermal *mt, ++ void __iomem *auxadc_base) ++{ ++ int tmp; ++ ++ writel(0x800, auxadc_base + AUXADC_CON1_SET_V); ++ writel(0x1, mt->thermal_base + TEMP_MONCTL0); ++ tmp = readl(mt->thermal_base + TEMP_MSRCTL1); ++ writel((tmp & (~0x10e)), mt->thermal_base + TEMP_MSRCTL1); ++} ++ ++static int mtk_thermal_probe(struct platform_device *pdev) ++{ ++ int ret, i, ctrl_id; ++ struct device_node *auxadc, *apmixedsys, *np = pdev->dev.of_node; ++ struct mtk_thermal *mt; ++ u64 auxadc_phys_base, apmixed_phys_base; ++ struct thermal_zone_device *tzdev; ++ void __iomem *apmixed_base, *auxadc_base; ++ ++ mt = devm_kzalloc(&pdev->dev, sizeof(*mt), GFP_KERNEL); ++ if (!mt) ++ return -ENOMEM; ++ ++ mt->conf = of_device_get_match_data(&pdev->dev); ++ ++ mt->clk_peri_therm = devm_clk_get(&pdev->dev, "therm"); ++ if (IS_ERR(mt->clk_peri_therm)) ++ return PTR_ERR(mt->clk_peri_therm); ++ ++ mt->clk_auxadc = devm_clk_get(&pdev->dev, "auxadc"); ++ if (IS_ERR(mt->clk_auxadc)) ++ return PTR_ERR(mt->clk_auxadc); ++ ++ mt->thermal_base = devm_platform_get_and_ioremap_resource(pdev, 0, NULL); ++ if (IS_ERR(mt->thermal_base)) ++ return PTR_ERR(mt->thermal_base); ++ ++ ret = mtk_thermal_get_calibration_data(&pdev->dev, mt); ++ if (ret) ++ return ret; ++ ++ mutex_init(&mt->lock); ++ ++ mt->dev = &pdev->dev; ++ ++ auxadc = of_parse_phandle(np, "mediatek,auxadc", 0); ++ if (!auxadc) { ++ dev_err(&pdev->dev, "missing auxadc node\n"); ++ return -ENODEV; ++ } ++ ++ auxadc_base = of_iomap(auxadc, 0); ++ auxadc_phys_base = of_get_phys_base(auxadc); ++ ++ of_node_put(auxadc); ++ ++ if (auxadc_phys_base == OF_BAD_ADDR) { ++ dev_err(&pdev->dev, "Can't get auxadc phys address\n"); ++ return -EINVAL; ++ } ++ ++ apmixedsys = of_parse_phandle(np, "mediatek,apmixedsys", 0); ++ if (!apmixedsys) { ++ dev_err(&pdev->dev, "missing apmixedsys node\n"); ++ return -ENODEV; ++ } ++ ++ apmixed_base = of_iomap(apmixedsys, 0); ++ apmixed_phys_base = of_get_phys_base(apmixedsys); ++ ++ of_node_put(apmixedsys); ++ ++ if (apmixed_phys_base == OF_BAD_ADDR) { ++ dev_err(&pdev->dev, "Can't get auxadc phys address\n"); ++ return -EINVAL; ++ } ++ ++ ret = device_reset_optional(&pdev->dev); ++ if (ret) ++ return ret; ++ ++ ret = clk_prepare_enable(mt->clk_auxadc); ++ if (ret) { ++ dev_err(&pdev->dev, "Can't enable auxadc clk: %d\n", ret); ++ return ret; ++ } ++ ++ ret = clk_prepare_enable(mt->clk_peri_therm); ++ if (ret) { ++ dev_err(&pdev->dev, "Can't enable peri clk: %d\n", ret); ++ goto err_disable_clk_auxadc; ++ } ++ ++ if (mt->conf->version != MTK_THERMAL_V1) { ++ mtk_thermal_turn_on_buffer(apmixed_base); ++ mtk_thermal_release_periodic_ts(mt, auxadc_base); ++ } ++ ++ if (mt->conf->version == MTK_THERMAL_V1) ++ mt->raw_to_mcelsius = raw_to_mcelsius_v1; ++ else if (mt->conf->version == MTK_THERMAL_V2) ++ mt->raw_to_mcelsius = raw_to_mcelsius_v2; ++ else ++ mt->raw_to_mcelsius = raw_to_mcelsius_v3; ++ ++ for (ctrl_id = 0; ctrl_id < mt->conf->num_controller ; ctrl_id++) ++ for (i = 0; i < mt->conf->num_banks; i++) ++ mtk_thermal_init_bank(mt, i, apmixed_phys_base, ++ auxadc_phys_base, ctrl_id); ++ ++ platform_set_drvdata(pdev, mt); ++ ++ tzdev = devm_thermal_of_zone_register(&pdev->dev, 0, mt, ++ &mtk_thermal_ops); ++ if (IS_ERR(tzdev)) { ++ ret = PTR_ERR(tzdev); ++ goto err_disable_clk_peri_therm; ++ } ++ ++ ret = devm_thermal_add_hwmon_sysfs(tzdev); ++ if (ret) ++ dev_warn(&pdev->dev, "error in thermal_add_hwmon_sysfs"); ++ ++ return 0; ++ ++err_disable_clk_peri_therm: ++ clk_disable_unprepare(mt->clk_peri_therm); ++err_disable_clk_auxadc: ++ clk_disable_unprepare(mt->clk_auxadc); ++ ++ return ret; ++} ++ ++static int mtk_thermal_remove(struct platform_device *pdev) ++{ ++ struct mtk_thermal *mt = platform_get_drvdata(pdev); ++ ++ clk_disable_unprepare(mt->clk_peri_therm); ++ clk_disable_unprepare(mt->clk_auxadc); ++ ++ return 0; ++} ++ ++static struct platform_driver mtk_thermal_driver = { ++ .probe = mtk_thermal_probe, ++ .remove = mtk_thermal_remove, ++ .driver = { ++ .name = "mtk-thermal", ++ .of_match_table = mtk_thermal_of_match, ++ }, ++}; ++ ++module_platform_driver(mtk_thermal_driver); ++ ++MODULE_AUTHOR("Michael Kao "); ++MODULE_AUTHOR("Louis Yu "); ++MODULE_AUTHOR("Dawei Chien "); ++MODULE_AUTHOR("Sascha Hauer "); ++MODULE_AUTHOR("Hanyi Wu "); ++MODULE_DESCRIPTION("Mediatek thermal driver"); ++MODULE_LICENSE("GPL v2"); diff --git a/lede/target/linux/mediatek/patches-6.1/830-v6.3-06-thermal-drivers-mediatek-Add-the-Low-Voltage-Thermal.patch b/lede/target/linux/mediatek/patches-6.1/830-v6.3-06-thermal-drivers-mediatek-Add-the-Low-Voltage-Thermal.patch new file mode 100644 index 0000000000..2ae3734e40 --- /dev/null +++ b/lede/target/linux/mediatek/patches-6.1/830-v6.3-06-thermal-drivers-mediatek-Add-the-Low-Voltage-Thermal.patch @@ -0,0 +1,1298 @@ +From 325fadf27b21f7d79843c3cc282b7f3e6620ad3d Mon Sep 17 00:00:00 2001 +From: Balsam CHIHI +Date: Thu, 9 Feb 2023 11:56:26 +0100 +Subject: [PATCH 06/42] thermal/drivers/mediatek: Add the Low Voltage Thermal + Sensor driver + +The Low Voltage Thermal Sensor (LVTS) is a multiple sensors, multi +controllers contained in a thermal domain. + +A thermal domains can be the MCU or the AP. + +Each thermal domains contain up to seven controllers, each thermal +controller handle up to four thermal sensors. + +The LVTS has two Finite State Machines (FSM), one to handle the +functionin temperatures range like hot or cold temperature and another +one to handle monitoring trip point. The FSM notifies via interrupts +when a trip point is crossed. + +The interrupt is managed at the thermal controller level, so when an +interrupt occurs, the driver has to find out which sensor triggered +such an interrupt. + +The sampling of the thermal can be filtered or immediate. For the +former, the LVTS measures several points and applies a low pass +filter. + +Signed-off-by: Balsam CHIHI +Reviewed-by: AngeloGioacchino Del Regno + +On MT8195 Tomato Chromebook: + +Tested-by: AngeloGioacchino Del Regno +Link: https://lore.kernel.org/r/20230209105628.50294-5-bchihi@baylibre.com +Signed-off-by: Daniel Lezcano +Signed-off-by: Rafael J. Wysocki +--- + drivers/thermal/mediatek/Kconfig | 16 + + drivers/thermal/mediatek/Makefile | 1 + + drivers/thermal/mediatek/lvts_thermal.c | 1224 +++++++++++++++++++++++ + 3 files changed, 1241 insertions(+) + create mode 100644 drivers/thermal/mediatek/lvts_thermal.c + +--- a/drivers/thermal/mediatek/Kconfig ++++ b/drivers/thermal/mediatek/Kconfig +@@ -18,4 +18,20 @@ config MTK_SOC_THERMAL + This driver configures thermal controllers to collect + temperature via AUXADC interface. + ++config MTK_LVTS_THERMAL ++ tristate "LVTS Thermal Driver for MediaTek SoCs" ++ depends on HAS_IOMEM ++ help ++ Enable this option if you want to get SoC temperature ++ information for supported MediaTek platforms. ++ This driver configures LVTS (Low Voltage Thermal Sensor) ++ thermal controllers to collect temperatures via ASIF ++ (Analog Serial Interface). ++ ++config MTK_LVTS_THERMAL_DEBUGFS ++ bool "LVTS thermal debugfs" ++ depends on MTK_LVTS_THERMAL && DEBUG_FS ++ help ++ Enable this option to debug the internals of the device driver. ++ + endif +--- a/drivers/thermal/mediatek/Makefile ++++ b/drivers/thermal/mediatek/Makefile +@@ -1 +1,2 @@ + obj-$(CONFIG_MTK_SOC_THERMAL) += auxadc_thermal.o ++obj-$(CONFIG_MTK_LVTS_THERMAL) += lvts_thermal.o +--- /dev/null ++++ b/drivers/thermal/mediatek/lvts_thermal.c +@@ -0,0 +1,1224 @@ ++// SPDX-License-Identifier: GPL-2.0-only ++/* ++ * Copyright (c) 2023 MediaTek Inc. ++ * Author: Balsam CHIHI ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#define LVTS_MONCTL0(__base) (__base + 0x0000) ++#define LVTS_MONCTL1(__base) (__base + 0x0004) ++#define LVTS_MONCTL2(__base) (__base + 0x0008) ++#define LVTS_MONINT(__base) (__base + 0x000C) ++#define LVTS_MONINTSTS(__base) (__base + 0x0010) ++#define LVTS_MONIDET0(__base) (__base + 0x0014) ++#define LVTS_MONIDET1(__base) (__base + 0x0018) ++#define LVTS_MONIDET2(__base) (__base + 0x001C) ++#define LVTS_MONIDET3(__base) (__base + 0x0020) ++#define LVTS_H2NTHRE(__base) (__base + 0x0024) ++#define LVTS_HTHRE(__base) (__base + 0x0028) ++#define LVTS_OFFSETH(__base) (__base + 0x0030) ++#define LVTS_OFFSETL(__base) (__base + 0x0034) ++#define LVTS_MSRCTL0(__base) (__base + 0x0038) ++#define LVTS_MSRCTL1(__base) (__base + 0x003C) ++#define LVTS_TSSEL(__base) (__base + 0x0040) ++#define LVTS_CALSCALE(__base) (__base + 0x0048) ++#define LVTS_ID(__base) (__base + 0x004C) ++#define LVTS_CONFIG(__base) (__base + 0x0050) ++#define LVTS_EDATA00(__base) (__base + 0x0054) ++#define LVTS_EDATA01(__base) (__base + 0x0058) ++#define LVTS_EDATA02(__base) (__base + 0x005C) ++#define LVTS_EDATA03(__base) (__base + 0x0060) ++#define LVTS_MSR0(__base) (__base + 0x0090) ++#define LVTS_MSR1(__base) (__base + 0x0094) ++#define LVTS_MSR2(__base) (__base + 0x0098) ++#define LVTS_MSR3(__base) (__base + 0x009C) ++#define LVTS_IMMD0(__base) (__base + 0x00A0) ++#define LVTS_IMMD1(__base) (__base + 0x00A4) ++#define LVTS_IMMD2(__base) (__base + 0x00A8) ++#define LVTS_IMMD3(__base) (__base + 0x00AC) ++#define LVTS_PROTCTL(__base) (__base + 0x00C0) ++#define LVTS_PROTTA(__base) (__base + 0x00C4) ++#define LVTS_PROTTB(__base) (__base + 0x00C8) ++#define LVTS_PROTTC(__base) (__base + 0x00CC) ++#define LVTS_CLKEN(__base) (__base + 0x00E4) ++ ++#define LVTS_PERIOD_UNIT ((118 * 1000) / (256 * 38)) ++#define LVTS_GROUP_INTERVAL 1 ++#define LVTS_FILTER_INTERVAL 1 ++#define LVTS_SENSOR_INTERVAL 1 ++#define LVTS_HW_FILTER 0x2 ++#define LVTS_TSSEL_CONF 0x13121110 ++#define LVTS_CALSCALE_CONF 0x300 ++#define LVTS_MONINT_CONF 0x9FBF7BDE ++ ++#define LVTS_INT_SENSOR0 0x0009001F ++#define LVTS_INT_SENSOR1 0X000881F0 ++#define LVTS_INT_SENSOR2 0x00247C00 ++#define LVTS_INT_SENSOR3 0x1FC00000 ++ ++#define LVTS_SENSOR_MAX 4 ++#define LVTS_GOLDEN_TEMP_MAX 62 ++#define LVTS_GOLDEN_TEMP_DEFAULT 50 ++#define LVTS_COEFF_A -250460 ++#define LVTS_COEFF_B 250460 ++ ++#define LVTS_MSR_IMMEDIATE_MODE 0 ++#define LVTS_MSR_FILTERED_MODE 1 ++ ++#define LVTS_HW_SHUTDOWN_MT8195 105000 ++ ++static int golden_temp = LVTS_GOLDEN_TEMP_DEFAULT; ++static int coeff_b = LVTS_COEFF_B; ++ ++struct lvts_sensor_data { ++ int dt_id; ++}; ++ ++struct lvts_ctrl_data { ++ struct lvts_sensor_data lvts_sensor[LVTS_SENSOR_MAX]; ++ int cal_offset[LVTS_SENSOR_MAX]; ++ int hw_tshut_temp; ++ int num_lvts_sensor; ++ int offset; ++ int mode; ++}; ++ ++struct lvts_data { ++ const struct lvts_ctrl_data *lvts_ctrl; ++ int num_lvts_ctrl; ++}; ++ ++struct lvts_sensor { ++ struct thermal_zone_device *tz; ++ void __iomem *msr; ++ void __iomem *base; ++ int id; ++ int dt_id; ++}; ++ ++struct lvts_ctrl { ++ struct lvts_sensor sensors[LVTS_SENSOR_MAX]; ++ u32 calibration[LVTS_SENSOR_MAX]; ++ u32 hw_tshut_raw_temp; ++ int num_lvts_sensor; ++ int mode; ++ void __iomem *base; ++}; ++ ++struct lvts_domain { ++ struct lvts_ctrl *lvts_ctrl; ++ struct reset_control *reset; ++ struct clk *clk; ++ int num_lvts_ctrl; ++ void __iomem *base; ++ size_t calib_len; ++ u8 *calib; ++#ifdef CONFIG_DEBUG_FS ++ struct dentry *dom_dentry; ++#endif ++}; ++ ++#ifdef CONFIG_MTK_LVTS_THERMAL_DEBUGFS ++ ++#define LVTS_DEBUG_FS_REGS(__reg) \ ++{ \ ++ .name = __stringify(__reg), \ ++ .offset = __reg(0), \ ++} ++ ++static const struct debugfs_reg32 lvts_regs[] = { ++ LVTS_DEBUG_FS_REGS(LVTS_MONCTL0), ++ LVTS_DEBUG_FS_REGS(LVTS_MONCTL1), ++ LVTS_DEBUG_FS_REGS(LVTS_MONCTL2), ++ LVTS_DEBUG_FS_REGS(LVTS_MONINT), ++ LVTS_DEBUG_FS_REGS(LVTS_MONINTSTS), ++ LVTS_DEBUG_FS_REGS(LVTS_MONIDET0), ++ LVTS_DEBUG_FS_REGS(LVTS_MONIDET1), ++ LVTS_DEBUG_FS_REGS(LVTS_MONIDET2), ++ LVTS_DEBUG_FS_REGS(LVTS_MONIDET3), ++ LVTS_DEBUG_FS_REGS(LVTS_H2NTHRE), ++ LVTS_DEBUG_FS_REGS(LVTS_HTHRE), ++ LVTS_DEBUG_FS_REGS(LVTS_OFFSETH), ++ LVTS_DEBUG_FS_REGS(LVTS_OFFSETL), ++ LVTS_DEBUG_FS_REGS(LVTS_MSRCTL0), ++ LVTS_DEBUG_FS_REGS(LVTS_MSRCTL1), ++ LVTS_DEBUG_FS_REGS(LVTS_TSSEL), ++ LVTS_DEBUG_FS_REGS(LVTS_CALSCALE), ++ LVTS_DEBUG_FS_REGS(LVTS_ID), ++ LVTS_DEBUG_FS_REGS(LVTS_CONFIG), ++ LVTS_DEBUG_FS_REGS(LVTS_EDATA00), ++ LVTS_DEBUG_FS_REGS(LVTS_EDATA01), ++ LVTS_DEBUG_FS_REGS(LVTS_EDATA02), ++ LVTS_DEBUG_FS_REGS(LVTS_EDATA03), ++ LVTS_DEBUG_FS_REGS(LVTS_MSR0), ++ LVTS_DEBUG_FS_REGS(LVTS_MSR1), ++ LVTS_DEBUG_FS_REGS(LVTS_MSR2), ++ LVTS_DEBUG_FS_REGS(LVTS_MSR3), ++ LVTS_DEBUG_FS_REGS(LVTS_IMMD0), ++ LVTS_DEBUG_FS_REGS(LVTS_IMMD1), ++ LVTS_DEBUG_FS_REGS(LVTS_IMMD2), ++ LVTS_DEBUG_FS_REGS(LVTS_IMMD3), ++ LVTS_DEBUG_FS_REGS(LVTS_PROTCTL), ++ LVTS_DEBUG_FS_REGS(LVTS_PROTTA), ++ LVTS_DEBUG_FS_REGS(LVTS_PROTTB), ++ LVTS_DEBUG_FS_REGS(LVTS_PROTTC), ++ LVTS_DEBUG_FS_REGS(LVTS_CLKEN), ++}; ++ ++static int lvts_debugfs_init(struct device *dev, struct lvts_domain *lvts_td) ++{ ++ struct debugfs_regset32 *regset; ++ struct lvts_ctrl *lvts_ctrl; ++ struct dentry *dentry; ++ char name[64]; ++ int i; ++ ++ lvts_td->dom_dentry = debugfs_create_dir(dev_name(dev), NULL); ++ if (!lvts_td->dom_dentry) ++ return 0; ++ ++ for (i = 0; i < lvts_td->num_lvts_ctrl; i++) { ++ ++ lvts_ctrl = &lvts_td->lvts_ctrl[i]; ++ ++ sprintf(name, "controller%d", i); ++ dentry = debugfs_create_dir(name, lvts_td->dom_dentry); ++ if (!dentry) ++ continue; ++ ++ regset = devm_kzalloc(dev, sizeof(*regset), GFP_KERNEL); ++ if (!regset) ++ continue; ++ ++ regset->base = lvts_ctrl->base; ++ regset->regs = lvts_regs; ++ regset->nregs = ARRAY_SIZE(lvts_regs); ++ ++ debugfs_create_regset32("registers", 0400, dentry, regset); ++ } ++ ++ return 0; ++} ++ ++static void lvts_debugfs_exit(struct lvts_domain *lvts_td) ++{ ++ debugfs_remove_recursive(lvts_td->dom_dentry); ++} ++ ++#else ++ ++static inline int lvts_debugfs_init(struct device *dev, ++ struct lvts_domain *lvts_td) ++{ ++ return 0; ++} ++ ++static void lvts_debugfs_exit(struct lvts_domain *lvts_td) { } ++ ++#endif ++ ++static int lvts_raw_to_temp(u32 raw_temp) ++{ ++ int temperature; ++ ++ temperature = ((s64)(raw_temp & 0xFFFF) * LVTS_COEFF_A) >> 14; ++ temperature += coeff_b; ++ ++ return temperature; ++} ++ ++static u32 lvts_temp_to_raw(int temperature) ++{ ++ u32 raw_temp = ((s64)(coeff_b - temperature)) << 14; ++ ++ raw_temp = div_s64(raw_temp, -LVTS_COEFF_A); ++ ++ return raw_temp; ++} ++ ++static int lvts_get_temp(struct thermal_zone_device *tz, int *temp) ++{ ++ struct lvts_sensor *lvts_sensor = tz->devdata; ++ void __iomem *msr = lvts_sensor->msr; ++ u32 value; ++ ++ /* ++ * Measurement registers: ++ * ++ * LVTS_MSR[0-3] / LVTS_IMMD[0-3] ++ * ++ * Bits: ++ * ++ * 32-17: Unused ++ * 16 : Valid temperature ++ * 15-0 : Raw temperature ++ */ ++ value = readl(msr); ++ ++ /* ++ * As the thermal zone temperature will read before the ++ * hardware sensor is fully initialized, we have to check the ++ * validity of the temperature returned when reading the ++ * measurement register. The thermal controller will set the ++ * valid bit temperature only when it is totally initialized. ++ * ++ * Otherwise, we may end up with garbage values out of the ++ * functionning temperature and directly jump to a system ++ * shutdown. ++ */ ++ if (!(value & BIT(16))) ++ return -EAGAIN; ++ ++ *temp = lvts_raw_to_temp(value & 0xFFFF); ++ ++ return 0; ++} ++ ++static int lvts_set_trips(struct thermal_zone_device *tz, int low, int high) ++{ ++ struct lvts_sensor *lvts_sensor = tz->devdata; ++ void __iomem *base = lvts_sensor->base; ++ u32 raw_low = lvts_temp_to_raw(low); ++ u32 raw_high = lvts_temp_to_raw(high); ++ ++ /* ++ * Hot to normal temperature threshold ++ * ++ * LVTS_H2NTHRE ++ * ++ * Bits: ++ * ++ * 14-0 : Raw temperature for threshold ++ */ ++ if (low != -INT_MAX) { ++ dev_dbg(&tz->device, "Setting low limit temperature interrupt: %d\n", low); ++ writel(raw_low, LVTS_H2NTHRE(base)); ++ } ++ ++ /* ++ * Hot temperature threshold ++ * ++ * LVTS_HTHRE ++ * ++ * Bits: ++ * ++ * 14-0 : Raw temperature for threshold ++ */ ++ dev_dbg(&tz->device, "Setting high limit temperature interrupt: %d\n", high); ++ writel(raw_high, LVTS_HTHRE(base)); ++ ++ return 0; ++} ++ ++static irqreturn_t lvts_ctrl_irq_handler(struct lvts_ctrl *lvts_ctrl) ++{ ++ irqreturn_t iret = IRQ_NONE; ++ u32 value; ++ u32 masks[] = { ++ LVTS_INT_SENSOR0, ++ LVTS_INT_SENSOR1, ++ LVTS_INT_SENSOR2, ++ LVTS_INT_SENSOR3 ++ }; ++ int i; ++ ++ /* ++ * Interrupt monitoring status ++ * ++ * LVTS_MONINTST ++ * ++ * Bits: ++ * ++ * 31 : Interrupt for stage 3 ++ * 30 : Interrupt for stage 2 ++ * 29 : Interrupt for state 1 ++ * 28 : Interrupt using filter on sensor 3 ++ * ++ * 27 : Interrupt using immediate on sensor 3 ++ * 26 : Interrupt normal to hot on sensor 3 ++ * 25 : Interrupt high offset on sensor 3 ++ * 24 : Interrupt low offset on sensor 3 ++ * ++ * 23 : Interrupt hot threshold on sensor 3 ++ * 22 : Interrupt cold threshold on sensor 3 ++ * 21 : Interrupt using filter on sensor 2 ++ * 20 : Interrupt using filter on sensor 1 ++ * ++ * 19 : Interrupt using filter on sensor 0 ++ * 18 : Interrupt using immediate on sensor 2 ++ * 17 : Interrupt using immediate on sensor 1 ++ * 16 : Interrupt using immediate on sensor 0 ++ * ++ * 15 : Interrupt device access timeout interrupt ++ * 14 : Interrupt normal to hot on sensor 2 ++ * 13 : Interrupt high offset interrupt on sensor 2 ++ * 12 : Interrupt low offset interrupt on sensor 2 ++ * ++ * 11 : Interrupt hot threshold on sensor 2 ++ * 10 : Interrupt cold threshold on sensor 2 ++ * 9 : Interrupt normal to hot on sensor 1 ++ * 8 : Interrupt high offset interrupt on sensor 1 ++ * ++ * 7 : Interrupt low offset interrupt on sensor 1 ++ * 6 : Interrupt hot threshold on sensor 1 ++ * 5 : Interrupt cold threshold on sensor 1 ++ * 4 : Interrupt normal to hot on sensor 0 ++ * ++ * 3 : Interrupt high offset interrupt on sensor 0 ++ * 2 : Interrupt low offset interrupt on sensor 0 ++ * 1 : Interrupt hot threshold on sensor 0 ++ * 0 : Interrupt cold threshold on sensor 0 ++ * ++ * We are interested in the sensor(s) responsible of the ++ * interrupt event. We update the thermal framework with the ++ * thermal zone associated with the sensor. The framework will ++ * take care of the rest whatever the kind of interrupt, we ++ * are only interested in which sensor raised the interrupt. ++ * ++ * sensor 3 interrupt: 0001 1111 1100 0000 0000 0000 0000 0000 ++ * => 0x1FC00000 ++ * sensor 2 interrupt: 0000 0000 0010 0100 0111 1100 0000 0000 ++ * => 0x00247C00 ++ * sensor 1 interrupt: 0000 0000 0001 0001 0000 0011 1110 0000 ++ * => 0X000881F0 ++ * sensor 0 interrupt: 0000 0000 0000 1001 0000 0000 0001 1111 ++ * => 0x0009001F ++ */ ++ value = readl(LVTS_MONINTSTS(lvts_ctrl->base)); ++ ++ /* ++ * Let's figure out which sensors raised the interrupt ++ * ++ * NOTE: the masks array must be ordered with the index ++ * corresponding to the sensor id eg. index=0, mask for ++ * sensor0. ++ */ ++ for (i = 0; i < ARRAY_SIZE(masks); i++) { ++ ++ if (!(value & masks[i])) ++ continue; ++ ++ thermal_zone_device_update(lvts_ctrl->sensors[i].tz, ++ THERMAL_TRIP_VIOLATED); ++ iret = IRQ_HANDLED; ++ } ++ ++ /* ++ * Write back to clear the interrupt status (W1C) ++ */ ++ writel(value, LVTS_MONINTSTS(lvts_ctrl->base)); ++ ++ return iret; ++} ++ ++/* ++ * Temperature interrupt handler. Even if the driver supports more ++ * interrupt modes, we use the interrupt when the temperature crosses ++ * the hot threshold the way up and the way down (modulo the ++ * hysteresis). ++ * ++ * Each thermal domain has a couple of interrupts, one for hardware ++ * reset and another one for all the thermal events happening on the ++ * different sensors. ++ * ++ * The interrupt is configured for thermal events when crossing the ++ * hot temperature limit. At each interrupt, we check in every ++ * controller if there is an interrupt pending. ++ */ ++static irqreturn_t lvts_irq_handler(int irq, void *data) ++{ ++ struct lvts_domain *lvts_td = data; ++ irqreturn_t aux, iret = IRQ_NONE; ++ int i; ++ ++ for (i = 0; i < lvts_td->num_lvts_ctrl; i++) { ++ ++ aux = lvts_ctrl_irq_handler(lvts_td->lvts_ctrl); ++ if (aux != IRQ_HANDLED) ++ continue; ++ ++ iret = IRQ_HANDLED; ++ } ++ ++ return iret; ++} ++ ++static struct thermal_zone_device_ops lvts_ops = { ++ .get_temp = lvts_get_temp, ++ .set_trips = lvts_set_trips, ++}; ++ ++static int lvts_sensor_init(struct device *dev, struct lvts_ctrl *lvts_ctrl, ++ const struct lvts_ctrl_data *lvts_ctrl_data) ++{ ++ struct lvts_sensor *lvts_sensor = lvts_ctrl->sensors; ++ void __iomem *msr_regs[] = { ++ LVTS_MSR0(lvts_ctrl->base), ++ LVTS_MSR1(lvts_ctrl->base), ++ LVTS_MSR2(lvts_ctrl->base), ++ LVTS_MSR3(lvts_ctrl->base) ++ }; ++ ++ void __iomem *imm_regs[] = { ++ LVTS_IMMD0(lvts_ctrl->base), ++ LVTS_IMMD1(lvts_ctrl->base), ++ LVTS_IMMD2(lvts_ctrl->base), ++ LVTS_IMMD3(lvts_ctrl->base) ++ }; ++ ++ int i; ++ ++ for (i = 0; i < lvts_ctrl_data->num_lvts_sensor; i++) { ++ ++ int dt_id = lvts_ctrl_data->lvts_sensor[i].dt_id; ++ ++ /* ++ * At this point, we don't know which id matches which ++ * sensor. Let's set arbitrally the id from the index. ++ */ ++ lvts_sensor[i].id = i; ++ ++ /* ++ * The thermal zone registration will set the trip ++ * point interrupt in the thermal controller ++ * register. But this one will be reset in the ++ * initialization after. So we need to post pone the ++ * thermal zone creation after the controller is ++ * setup. For this reason, we store the device tree ++ * node id from the data in the sensor structure ++ */ ++ lvts_sensor[i].dt_id = dt_id; ++ ++ /* ++ * We assign the base address of the thermal ++ * controller as a back pointer. So it will be ++ * accessible from the different thermal framework ops ++ * as we pass the lvts_sensor pointer as thermal zone ++ * private data. ++ */ ++ lvts_sensor[i].base = lvts_ctrl->base; ++ ++ /* ++ * Each sensor has its own register address to read from. ++ */ ++ lvts_sensor[i].msr = lvts_ctrl_data->mode == LVTS_MSR_IMMEDIATE_MODE ? ++ imm_regs[i] : msr_regs[i]; ++ }; ++ ++ lvts_ctrl->num_lvts_sensor = lvts_ctrl_data->num_lvts_sensor; ++ ++ return 0; ++} ++ ++/* ++ * The efuse blob values follows the sensor enumeration per thermal ++ * controller. The decoding of the stream is as follow: ++ * ++ * <--?-> <----big0 ???---> <-sensor0-> <-0-> ++ * ------------------------------------------ ++ * index in the stream: : | 0x0 | 0x1 | 0x2 | 0x3 | 0x4 | 0x5 | 0x6 | ++ * ------------------------------------------ ++ * ++ * <--sensor1--><-0-> <----big1 ???---> <-sen ++ * ------------------------------------------ ++ * | 0x7 | 0x8 | 0x9 | 0xA | 0xB | OxC | OxD | ++ * ------------------------------------------ ++ * ++ * sor0-> <-0-> <-sensor1-> <-0-> .......... ++ * ------------------------------------------ ++ * | 0x7 | 0x8 | 0x9 | 0xA | 0xB | OxC | OxD | ++ * ------------------------------------------ ++ * ++ * And so on ... ++ * ++ * The data description gives the offset of the calibration data in ++ * this bytes stream for each sensor. ++ * ++ * Each thermal controller can handle up to 4 sensors max, we don't ++ * care if there are less as the array of calibration is sized to 4 ++ * anyway. The unused sensor slot will be zeroed. ++ */ ++static int lvts_calibration_init(struct device *dev, struct lvts_ctrl *lvts_ctrl, ++ const struct lvts_ctrl_data *lvts_ctrl_data, ++ u8 *efuse_calibration) ++{ ++ int i; ++ ++ for (i = 0; i < lvts_ctrl_data->num_lvts_sensor; i++) ++ memcpy(&lvts_ctrl->calibration[i], ++ efuse_calibration + lvts_ctrl_data->cal_offset[i], 2); ++ ++ return 0; ++} ++ ++/* ++ * The efuse bytes stream can be split into different chunk of ++ * nvmems. This function reads and concatenate those into a single ++ * buffer so it can be read sequentially when initializing the ++ * calibration data. ++ */ ++static int lvts_calibration_read(struct device *dev, struct lvts_domain *lvts_td, ++ const struct lvts_data *lvts_data) ++{ ++ struct device_node *np = dev_of_node(dev); ++ struct nvmem_cell *cell; ++ struct property *prop; ++ const char *cell_name; ++ ++ of_property_for_each_string(np, "nvmem-cell-names", prop, cell_name) { ++ size_t len; ++ u8 *efuse; ++ ++ cell = of_nvmem_cell_get(np, cell_name); ++ if (IS_ERR(cell)) { ++ dev_err(dev, "Failed to get cell '%s'\n", cell_name); ++ return PTR_ERR(cell); ++ } ++ ++ efuse = nvmem_cell_read(cell, &len); ++ ++ nvmem_cell_put(cell); ++ ++ if (IS_ERR(efuse)) { ++ dev_err(dev, "Failed to read cell '%s'\n", cell_name); ++ return PTR_ERR(efuse); ++ } ++ ++ lvts_td->calib = devm_krealloc(dev, lvts_td->calib, ++ lvts_td->calib_len + len, GFP_KERNEL); ++ if (!lvts_td->calib) ++ return -ENOMEM; ++ ++ memcpy(lvts_td->calib + lvts_td->calib_len, efuse, len); ++ ++ lvts_td->calib_len += len; ++ ++ kfree(efuse); ++ } ++ ++ return 0; ++} ++ ++static int lvts_golden_temp_init(struct device *dev, u32 *value) ++{ ++ u32 gt; ++ ++ gt = (*value) >> 24; ++ ++ if (gt && gt < LVTS_GOLDEN_TEMP_MAX) ++ golden_temp = gt; ++ ++ coeff_b = golden_temp * 500 + LVTS_COEFF_B; ++ ++ return 0; ++} ++ ++static int lvts_ctrl_init(struct device *dev, struct lvts_domain *lvts_td, ++ const struct lvts_data *lvts_data) ++{ ++ size_t size = sizeof(*lvts_td->lvts_ctrl) * lvts_data->num_lvts_ctrl; ++ struct lvts_ctrl *lvts_ctrl; ++ int i, ret; ++ ++ /* ++ * Create the calibration bytes stream from efuse data ++ */ ++ ret = lvts_calibration_read(dev, lvts_td, lvts_data); ++ if (ret) ++ return ret; ++ ++ /* ++ * The golden temp information is contained in the first chunk ++ * of efuse data. ++ */ ++ ret = lvts_golden_temp_init(dev, (u32 *)lvts_td->calib); ++ if (ret) ++ return ret; ++ ++ lvts_ctrl = devm_kzalloc(dev, size, GFP_KERNEL); ++ if (!lvts_ctrl) ++ return -ENOMEM; ++ ++ for (i = 0; i < lvts_data->num_lvts_ctrl; i++) { ++ ++ lvts_ctrl[i].base = lvts_td->base + lvts_data->lvts_ctrl[i].offset; ++ ++ ret = lvts_sensor_init(dev, &lvts_ctrl[i], ++ &lvts_data->lvts_ctrl[i]); ++ if (ret) ++ return ret; ++ ++ ret = lvts_calibration_init(dev, &lvts_ctrl[i], ++ &lvts_data->lvts_ctrl[i], ++ lvts_td->calib); ++ if (ret) ++ return ret; ++ ++ /* ++ * The mode the ctrl will use to read the temperature ++ * (filtered or immediate) ++ */ ++ lvts_ctrl[i].mode = lvts_data->lvts_ctrl[i].mode; ++ ++ /* ++ * The temperature to raw temperature must be done ++ * after initializing the calibration. ++ */ ++ lvts_ctrl[i].hw_tshut_raw_temp = ++ lvts_temp_to_raw(lvts_data->lvts_ctrl[i].hw_tshut_temp); ++ } ++ ++ /* ++ * We no longer need the efuse bytes stream, let's free it ++ */ ++ devm_kfree(dev, lvts_td->calib); ++ ++ lvts_td->lvts_ctrl = lvts_ctrl; ++ lvts_td->num_lvts_ctrl = lvts_data->num_lvts_ctrl; ++ ++ return 0; ++} ++ ++/* ++ * At this point the configuration register is the only place in the ++ * driver where we write multiple values. Per hardware constraint, ++ * each write in the configuration register must be separated by a ++ * delay of 2 us. ++ */ ++static void lvts_write_config(struct lvts_ctrl *lvts_ctrl, u32 *cmds, int nr_cmds) ++{ ++ int i; ++ ++ /* ++ * Configuration register ++ */ ++ for (i = 0; i < nr_cmds; i++) { ++ writel(cmds[i], LVTS_CONFIG(lvts_ctrl->base)); ++ usleep_range(2, 4); ++ } ++} ++ ++static int lvts_irq_init(struct lvts_ctrl *lvts_ctrl) ++{ ++ /* ++ * LVTS_PROTCTL : Thermal Protection Sensor Selection ++ * ++ * Bits: ++ * ++ * 19-18 : Sensor to base the protection on ++ * 17-16 : Strategy: ++ * 00 : Average of 4 sensors ++ * 01 : Max of 4 sensors ++ * 10 : Selected sensor with bits 19-18 ++ * 11 : Reserved ++ */ ++ writel(BIT(16), LVTS_PROTCTL(lvts_ctrl->base)); ++ ++ /* ++ * LVTS_PROTTA : Stage 1 temperature threshold ++ * LVTS_PROTTB : Stage 2 temperature threshold ++ * LVTS_PROTTC : Stage 3 temperature threshold ++ * ++ * Bits: ++ * ++ * 14-0: Raw temperature threshold ++ * ++ * writel(0x0, LVTS_PROTTA(lvts_ctrl->base)); ++ * writel(0x0, LVTS_PROTTB(lvts_ctrl->base)); ++ */ ++ writel(lvts_ctrl->hw_tshut_raw_temp, LVTS_PROTTC(lvts_ctrl->base)); ++ ++ /* ++ * LVTS_MONINT : Interrupt configuration register ++ * ++ * The LVTS_MONINT register layout is the same as the LVTS_MONINTSTS ++ * register, except we set the bits to enable the interrupt. ++ */ ++ writel(LVTS_MONINT_CONF, LVTS_MONINT(lvts_ctrl->base)); ++ ++ return 0; ++} ++ ++static int lvts_domain_reset(struct device *dev, struct reset_control *reset) ++{ ++ int ret; ++ ++ ret = reset_control_assert(reset); ++ if (ret) ++ return ret; ++ ++ return reset_control_deassert(reset); ++} ++ ++/* ++ * Enable or disable the clocks of a specified thermal controller ++ */ ++static int lvts_ctrl_set_enable(struct lvts_ctrl *lvts_ctrl, int enable) ++{ ++ /* ++ * LVTS_CLKEN : Internal LVTS clock ++ * ++ * Bits: ++ * ++ * 0 : enable / disable clock ++ */ ++ writel(enable, LVTS_CLKEN(lvts_ctrl->base)); ++ ++ return 0; ++} ++ ++static int lvts_ctrl_connect(struct device *dev, struct lvts_ctrl *lvts_ctrl) ++{ ++ u32 id, cmds[] = { 0xC103FFFF, 0xC502FF55 }; ++ ++ lvts_write_config(lvts_ctrl, cmds, ARRAY_SIZE(cmds)); ++ ++ /* ++ * LVTS_ID : Get ID and status of the thermal controller ++ * ++ * Bits: ++ * ++ * 0-5 : thermal controller id ++ * 7 : thermal controller connection is valid ++ */ ++ id = readl(LVTS_ID(lvts_ctrl->base)); ++ if (!(id & BIT(7))) ++ return -EIO; ++ ++ return 0; ++} ++ ++static int lvts_ctrl_initialize(struct device *dev, struct lvts_ctrl *lvts_ctrl) ++{ ++ /* ++ * Write device mask: 0xC1030000 ++ */ ++ u32 cmds[] = { ++ 0xC1030E01, 0xC1030CFC, 0xC1030A8C, 0xC103098D, 0xC10308F1, ++ 0xC10307A6, 0xC10306B8, 0xC1030500, 0xC1030420, 0xC1030300, ++ 0xC1030030, 0xC10300F6, 0xC1030050, 0xC1030060, 0xC10300AC, ++ 0xC10300FC, 0xC103009D, 0xC10300F1, 0xC10300E1 ++ }; ++ ++ lvts_write_config(lvts_ctrl, cmds, ARRAY_SIZE(cmds)); ++ ++ return 0; ++} ++ ++static int lvts_ctrl_calibrate(struct device *dev, struct lvts_ctrl *lvts_ctrl) ++{ ++ int i; ++ void __iomem *lvts_edata[] = { ++ LVTS_EDATA00(lvts_ctrl->base), ++ LVTS_EDATA01(lvts_ctrl->base), ++ LVTS_EDATA02(lvts_ctrl->base), ++ LVTS_EDATA03(lvts_ctrl->base) ++ }; ++ ++ /* ++ * LVTS_EDATA0X : Efuse calibration reference value for sensor X ++ * ++ * Bits: ++ * ++ * 20-0 : Efuse value for normalization data ++ */ ++ for (i = 0; i < LVTS_SENSOR_MAX; i++) ++ writel(lvts_ctrl->calibration[i], lvts_edata[i]); ++ ++ return 0; ++} ++ ++static int lvts_ctrl_configure(struct device *dev, struct lvts_ctrl *lvts_ctrl) ++{ ++ u32 value; ++ ++ /* ++ * LVTS_TSSEL : Sensing point index numbering ++ * ++ * Bits: ++ * ++ * 31-24: ADC Sense 3 ++ * 23-16: ADC Sense 2 ++ * 15-8 : ADC Sense 1 ++ * 7-0 : ADC Sense 0 ++ */ ++ value = LVTS_TSSEL_CONF; ++ writel(value, LVTS_TSSEL(lvts_ctrl->base)); ++ ++ /* ++ * LVTS_CALSCALE : ADC voltage round ++ */ ++ value = 0x300; ++ value = LVTS_CALSCALE_CONF; ++ ++ /* ++ * LVTS_MSRCTL0 : Sensor filtering strategy ++ * ++ * Filters: ++ * ++ * 000 : One sample ++ * 001 : Avg 2 samples ++ * 010 : 4 samples, drop min and max, avg 2 samples ++ * 011 : 6 samples, drop min and max, avg 4 samples ++ * 100 : 10 samples, drop min and max, avg 8 samples ++ * 101 : 18 samples, drop min and max, avg 16 samples ++ * ++ * Bits: ++ * ++ * 0-2 : Sensor0 filter ++ * 3-5 : Sensor1 filter ++ * 6-8 : Sensor2 filter ++ * 9-11 : Sensor3 filter ++ */ ++ value = LVTS_HW_FILTER << 9 | LVTS_HW_FILTER << 6 | ++ LVTS_HW_FILTER << 3 | LVTS_HW_FILTER; ++ writel(value, LVTS_MSRCTL0(lvts_ctrl->base)); ++ ++ /* ++ * LVTS_MSRCTL1 : Measurement control ++ * ++ * Bits: ++ * ++ * 9: Ignore MSRCTL0 config and do immediate measurement on sensor3 ++ * 6: Ignore MSRCTL0 config and do immediate measurement on sensor2 ++ * 5: Ignore MSRCTL0 config and do immediate measurement on sensor1 ++ * 4: Ignore MSRCTL0 config and do immediate measurement on sensor0 ++ * ++ * That configuration will ignore the filtering and the delays ++ * introduced below in MONCTL1 and MONCTL2 ++ */ ++ if (lvts_ctrl->mode == LVTS_MSR_IMMEDIATE_MODE) { ++ value = BIT(9) | BIT(6) | BIT(5) | BIT(4); ++ writel(value, LVTS_MSRCTL1(lvts_ctrl->base)); ++ } ++ ++ /* ++ * LVTS_MONCTL1 : Period unit and group interval configuration ++ * ++ * The clock source of LVTS thermal controller is 26MHz. ++ * ++ * The period unit is a time base for all the interval delays ++ * specified in the registers. By default we use 12. The time ++ * conversion is done by multiplying by 256 and 1/26.10^6 ++ * ++ * An interval delay multiplied by the period unit gives the ++ * duration in seconds. ++ * ++ * - Filter interval delay is a delay between two samples of ++ * the same sensor. ++ * ++ * - Sensor interval delay is a delay between two samples of ++ * different sensors. ++ * ++ * - Group interval delay is a delay between different rounds. ++ * ++ * For example: ++ * If Period unit = C, filter delay = 1, sensor delay = 2, group delay = 1, ++ * and two sensors, TS1 and TS2, are in a LVTS thermal controller ++ * and then ++ * Period unit time = C * 1/26M * 256 = 12 * 38.46ns * 256 = 118.149us ++ * Filter interval delay = 1 * Period unit = 118.149us ++ * Sensor interval delay = 2 * Period unit = 236.298us ++ * Group interval delay = 1 * Period unit = 118.149us ++ * ++ * TS1 TS1 ... TS1 TS2 TS2 ... TS2 TS1... ++ * <--> Filter interval delay ++ * <--> Sensor interval delay ++ * <--> Group interval delay ++ * Bits: ++ * 29 - 20 : Group interval ++ * 16 - 13 : Send a single interrupt when crossing the hot threshold (1) ++ * or an interrupt everytime the hot threshold is crossed (0) ++ * 9 - 0 : Period unit ++ * ++ */ ++ value = LVTS_GROUP_INTERVAL << 20 | LVTS_PERIOD_UNIT; ++ writel(value, LVTS_MONCTL1(lvts_ctrl->base)); ++ ++ /* ++ * LVTS_MONCTL2 : Filtering and sensor interval ++ * ++ * Bits: ++ * ++ * 25-16 : Interval unit in PERIOD_UNIT between sample on ++ * the same sensor, filter interval ++ * 9-0 : Interval unit in PERIOD_UNIT between each sensor ++ * ++ */ ++ value = LVTS_FILTER_INTERVAL << 16 | LVTS_SENSOR_INTERVAL; ++ writel(value, LVTS_MONCTL2(lvts_ctrl->base)); ++ ++ return lvts_irq_init(lvts_ctrl); ++} ++ ++static int lvts_ctrl_start(struct device *dev, struct lvts_ctrl *lvts_ctrl) ++{ ++ struct lvts_sensor *lvts_sensors = lvts_ctrl->sensors; ++ struct thermal_zone_device *tz; ++ u32 sensor_map = 0; ++ int i; ++ ++ for (i = 0; i < lvts_ctrl->num_lvts_sensor; i++) { ++ ++ int dt_id = lvts_sensors[i].dt_id; ++ ++ tz = devm_thermal_of_zone_register(dev, dt_id, &lvts_sensors[i], ++ &lvts_ops); ++ if (IS_ERR(tz)) { ++ /* ++ * This thermal zone is not described in the ++ * device tree. It is not an error from the ++ * thermal OF code POV, we just continue. ++ */ ++ if (PTR_ERR(tz) == -ENODEV) ++ continue; ++ ++ return PTR_ERR(tz); ++ } ++ ++ /* ++ * The thermal zone pointer will be needed in the ++ * interrupt handler, we store it in the sensor ++ * structure. The thermal domain structure will be ++ * passed to the interrupt handler private data as the ++ * interrupt is shared for all the controller ++ * belonging to the thermal domain. ++ */ ++ lvts_sensors[i].tz = tz; ++ ++ /* ++ * This sensor was correctly associated with a thermal ++ * zone, let's set the corresponding bit in the sensor ++ * map, so we can enable the temperature monitoring in ++ * the hardware thermal controller. ++ */ ++ sensor_map |= BIT(i); ++ } ++ ++ /* ++ * Bits: ++ * 9: Single point access flow ++ * 0-3: Enable sensing point 0-3 ++ * ++ * The initialization of the thermal zones give us ++ * which sensor point to enable. If any thermal zone ++ * was not described in the device tree, it won't be ++ * enabled here in the sensor map. ++ */ ++ writel(sensor_map | BIT(9), LVTS_MONCTL0(lvts_ctrl->base)); ++ ++ return 0; ++} ++ ++static int lvts_domain_init(struct device *dev, struct lvts_domain *lvts_td, ++ const struct lvts_data *lvts_data) ++{ ++ struct lvts_ctrl *lvts_ctrl; ++ int i, ret; ++ ++ ret = lvts_ctrl_init(dev, lvts_td, lvts_data); ++ if (ret) ++ return ret; ++ ++ ret = lvts_domain_reset(dev, lvts_td->reset); ++ if (ret) { ++ dev_dbg(dev, "Failed to reset domain"); ++ return ret; ++ } ++ ++ for (i = 0; i < lvts_td->num_lvts_ctrl; i++) { ++ ++ lvts_ctrl = &lvts_td->lvts_ctrl[i]; ++ ++ /* ++ * Initialization steps: ++ * ++ * - Enable the clock ++ * - Connect to the LVTS ++ * - Initialize the LVTS ++ * - Prepare the calibration data ++ * - Select monitored sensors ++ * [ Configure sampling ] ++ * [ Configure the interrupt ] ++ * - Start measurement ++ */ ++ ret = lvts_ctrl_set_enable(lvts_ctrl, true); ++ if (ret) { ++ dev_dbg(dev, "Failed to enable LVTS clock"); ++ return ret; ++ } ++ ++ ret = lvts_ctrl_connect(dev, lvts_ctrl); ++ if (ret) { ++ dev_dbg(dev, "Failed to connect to LVTS controller"); ++ return ret; ++ } ++ ++ ret = lvts_ctrl_initialize(dev, lvts_ctrl); ++ if (ret) { ++ dev_dbg(dev, "Failed to initialize controller"); ++ return ret; ++ } ++ ++ ret = lvts_ctrl_calibrate(dev, lvts_ctrl); ++ if (ret) { ++ dev_dbg(dev, "Failed to calibrate controller"); ++ return ret; ++ } ++ ++ ret = lvts_ctrl_configure(dev, lvts_ctrl); ++ if (ret) { ++ dev_dbg(dev, "Failed to configure controller"); ++ return ret; ++ } ++ ++ ret = lvts_ctrl_start(dev, lvts_ctrl); ++ if (ret) { ++ dev_dbg(dev, "Failed to start controller"); ++ return ret; ++ } ++ } ++ ++ return lvts_debugfs_init(dev, lvts_td); ++} ++ ++static int lvts_probe(struct platform_device *pdev) ++{ ++ const struct lvts_data *lvts_data; ++ struct lvts_domain *lvts_td; ++ struct device *dev = &pdev->dev; ++ struct resource *res; ++ int irq, ret; ++ ++ lvts_td = devm_kzalloc(dev, sizeof(*lvts_td), GFP_KERNEL); ++ if (!lvts_td) ++ return -ENOMEM; ++ ++ lvts_data = of_device_get_match_data(dev); ++ ++ lvts_td->clk = devm_clk_get_enabled(dev, NULL); ++ if (IS_ERR(lvts_td->clk)) ++ return dev_err_probe(dev, PTR_ERR(lvts_td->clk), "Failed to retrieve clock\n"); ++ ++ res = platform_get_mem_or_io(pdev, 0); ++ if (!res) ++ return dev_err_probe(dev, (-ENXIO), "No IO resource\n"); ++ ++ lvts_td->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res); ++ if (IS_ERR(lvts_td->base)) ++ return dev_err_probe(dev, PTR_ERR(lvts_td->base), "Failed to map io resource\n"); ++ ++ lvts_td->reset = devm_reset_control_get_by_index(dev, 0); ++ if (IS_ERR(lvts_td->reset)) ++ return dev_err_probe(dev, PTR_ERR(lvts_td->reset), "Failed to get reset control\n"); ++ ++ irq = platform_get_irq(pdev, 0); ++ if (irq < 0) ++ return dev_err_probe(dev, irq, "No irq resource\n"); ++ ++ ret = lvts_domain_init(dev, lvts_td, lvts_data); ++ if (ret) ++ return dev_err_probe(dev, ret, "Failed to initialize the lvts domain\n"); ++ ++ /* ++ * At this point the LVTS is initialized and enabled. We can ++ * safely enable the interrupt. ++ */ ++ ret = devm_request_threaded_irq(dev, irq, NULL, lvts_irq_handler, ++ IRQF_ONESHOT, dev_name(dev), lvts_td); ++ if (ret) ++ return dev_err_probe(dev, ret, "Failed to request interrupt\n"); ++ ++ platform_set_drvdata(pdev, lvts_td); ++ ++ return 0; ++} ++ ++static int lvts_remove(struct platform_device *pdev) ++{ ++ struct lvts_domain *lvts_td; ++ int i; ++ ++ lvts_td = platform_get_drvdata(pdev); ++ ++ for (i = 0; i < lvts_td->num_lvts_ctrl; i++) ++ lvts_ctrl_set_enable(&lvts_td->lvts_ctrl[i], false); ++ ++ lvts_debugfs_exit(lvts_td); ++ ++ return 0; ++} ++ ++static const struct lvts_ctrl_data mt8195_lvts_data_ctrl[] = { ++ { ++ .cal_offset = { 0x04, 0x07 }, ++ .lvts_sensor = { ++ { .dt_id = MT8195_MCU_BIG_CPU0 }, ++ { .dt_id = MT8195_MCU_BIG_CPU1 } ++ }, ++ .num_lvts_sensor = 2, ++ .offset = 0x0, ++ .hw_tshut_temp = LVTS_HW_SHUTDOWN_MT8195, ++ }, ++ { ++ .cal_offset = { 0x0d, 0x10 }, ++ .lvts_sensor = { ++ { .dt_id = MT8195_MCU_BIG_CPU2 }, ++ { .dt_id = MT8195_MCU_BIG_CPU3 } ++ }, ++ .num_lvts_sensor = 2, ++ .offset = 0x100, ++ .hw_tshut_temp = LVTS_HW_SHUTDOWN_MT8195, ++ }, ++ { ++ .cal_offset = { 0x16, 0x19, 0x1c, 0x1f }, ++ .lvts_sensor = { ++ { .dt_id = MT8195_MCU_LITTLE_CPU0 }, ++ { .dt_id = MT8195_MCU_LITTLE_CPU1 }, ++ { .dt_id = MT8195_MCU_LITTLE_CPU2 }, ++ { .dt_id = MT8195_MCU_LITTLE_CPU3 } ++ }, ++ .num_lvts_sensor = 4, ++ .offset = 0x200, ++ .hw_tshut_temp = LVTS_HW_SHUTDOWN_MT8195, ++ } ++}; ++ ++static const struct lvts_data mt8195_lvts_mcu_data = { ++ .lvts_ctrl = mt8195_lvts_data_ctrl, ++ .num_lvts_ctrl = ARRAY_SIZE(mt8195_lvts_data_ctrl), ++}; ++ ++static const struct of_device_id lvts_of_match[] = { ++ { .compatible = "mediatek,mt8195-lvts-mcu", .data = &mt8195_lvts_mcu_data }, ++ {}, ++}; ++MODULE_DEVICE_TABLE(of, lvts_of_match); ++ ++static struct platform_driver lvts_driver = { ++ .probe = lvts_probe, ++ .remove = lvts_remove, ++ .driver = { ++ .name = "mtk-lvts-thermal", ++ .of_match_table = lvts_of_match, ++ }, ++}; ++module_platform_driver(lvts_driver); ++ ++MODULE_AUTHOR("Balsam CHIHI "); ++MODULE_DESCRIPTION("MediaTek LVTS Thermal Driver"); ++MODULE_LICENSE("GPL"); diff --git a/lede/target/linux/mediatek/patches-6.1/830-v6.4-07-dt-bindings-thermal-mediatek-Add-LVTS-thermal-contro.patch b/lede/target/linux/mediatek/patches-6.1/830-v6.4-07-dt-bindings-thermal-mediatek-Add-LVTS-thermal-contro.patch new file mode 100644 index 0000000000..b6a5f64090 --- /dev/null +++ b/lede/target/linux/mediatek/patches-6.1/830-v6.4-07-dt-bindings-thermal-mediatek-Add-LVTS-thermal-contro.patch @@ -0,0 +1,186 @@ +From 498e2f7a6e69dcbca24715de2b4b97569fdfeff4 Mon Sep 17 00:00:00 2001 +From: Balsam CHIHI +Date: Thu, 9 Feb 2023 11:56:24 +0100 +Subject: [PATCH] dt-bindings: thermal: mediatek: Add LVTS thermal controllers + +Add LVTS thermal controllers dt-binding definition for mt8192 and mt8195. + +Signed-off-by: Balsam CHIHI +Reviewed-by: Rob Herring +Link: https://lore.kernel.org/r/20230209105628.50294-3-bchihi@baylibre.com +Signed-off-by: Daniel Lezcano +Signed-off-by: Rafael J. Wysocki +--- + .../thermal/mediatek,lvts-thermal.yaml | 142 ++++++++++++++++++ + .../thermal/mediatek,lvts-thermal.h | 19 +++ + 2 files changed, 161 insertions(+) + create mode 100644 Documentation/devicetree/bindings/thermal/mediatek,lvts-thermal.yaml + create mode 100644 include/dt-bindings/thermal/mediatek,lvts-thermal.h + +--- /dev/null ++++ b/Documentation/devicetree/bindings/thermal/mediatek,lvts-thermal.yaml +@@ -0,0 +1,142 @@ ++# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) ++%YAML 1.2 ++--- ++$id: http://devicetree.org/schemas/thermal/mediatek,lvts-thermal.yaml# ++$schema: http://devicetree.org/meta-schemas/core.yaml# ++ ++title: MediaTek SoC Low Voltage Thermal Sensor (LVTS) ++ ++maintainers: ++ - Balsam CHIHI ++ ++description: | ++ LVTS is a thermal management architecture composed of three subsystems, ++ a Sensing device - Thermal Sensing Micro Circuit Unit (TSMCU), ++ a Converter - Low Voltage Thermal Sensor converter (LVTS), and ++ a Digital controller (LVTS_CTRL). ++ ++properties: ++ compatible: ++ enum: ++ - mediatek,mt8192-lvts-ap ++ - mediatek,mt8192-lvts-mcu ++ - mediatek,mt8195-lvts-ap ++ - mediatek,mt8195-lvts-mcu ++ ++ reg: ++ maxItems: 1 ++ ++ interrupts: ++ maxItems: 1 ++ ++ clocks: ++ maxItems: 1 ++ ++ resets: ++ maxItems: 1 ++ description: LVTS reset for clearing temporary data on AP/MCU. ++ ++ nvmem-cells: ++ minItems: 1 ++ items: ++ - description: Calibration eFuse data 1 for LVTS ++ - description: Calibration eFuse data 2 for LVTS ++ ++ nvmem-cell-names: ++ minItems: 1 ++ items: ++ - const: lvts-calib-data-1 ++ - const: lvts-calib-data-2 ++ ++ "#thermal-sensor-cells": ++ const: 1 ++ ++allOf: ++ - $ref: thermal-sensor.yaml# ++ ++ - if: ++ properties: ++ compatible: ++ contains: ++ enum: ++ - mediatek,mt8192-lvts-ap ++ - mediatek,mt8192-lvts-mcu ++ then: ++ properties: ++ nvmem-cells: ++ maxItems: 1 ++ ++ nvmem-cell-names: ++ maxItems: 1 ++ ++ - if: ++ properties: ++ compatible: ++ contains: ++ enum: ++ - mediatek,mt8195-lvts-ap ++ - mediatek,mt8195-lvts-mcu ++ then: ++ properties: ++ nvmem-cells: ++ minItems: 2 ++ ++ nvmem-cell-names: ++ minItems: 2 ++ ++required: ++ - compatible ++ - reg ++ - interrupts ++ - clocks ++ - resets ++ - nvmem-cells ++ - nvmem-cell-names ++ - "#thermal-sensor-cells" ++ ++additionalProperties: false ++ ++examples: ++ - | ++ #include ++ #include ++ #include ++ #include ++ ++ soc { ++ #address-cells = <2>; ++ #size-cells = <2>; ++ ++ lvts_mcu: thermal-sensor@11278000 { ++ compatible = "mediatek,mt8195-lvts-mcu"; ++ reg = <0 0x11278000 0 0x1000>; ++ interrupts = ; ++ clocks = <&infracfg_ao CLK_INFRA_AO_THERM>; ++ resets = <&infracfg_ao MT8195_INFRA_RST4_THERM_CTRL_MCU_SWRST>; ++ nvmem-cells = <&lvts_efuse_data1 &lvts_efuse_data2>; ++ nvmem-cell-names = "lvts-calib-data-1", "lvts-calib-data-2"; ++ #thermal-sensor-cells = <1>; ++ }; ++ }; ++ ++ thermal_zones: thermal-zones { ++ cpu0-thermal { ++ polling-delay = <1000>; ++ polling-delay-passive = <250>; ++ thermal-sensors = <&lvts_mcu MT8195_MCU_LITTLE_CPU0>; ++ ++ trips { ++ cpu0_alert: trip-alert { ++ temperature = <85000>; ++ hysteresis = <2000>; ++ type = "passive"; ++ }; ++ ++ cpu0_crit: trip-crit { ++ temperature = <100000>; ++ hysteresis = <2000>; ++ type = "critical"; ++ }; ++ }; ++ }; ++ }; +--- /dev/null ++++ b/include/dt-bindings/thermal/mediatek,lvts-thermal.h +@@ -0,0 +1,19 @@ ++/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ ++/* ++ * Copyright (c) 2023 MediaTek Inc. ++ * Author: Balsam CHIHI ++ */ ++ ++#ifndef __MEDIATEK_LVTS_DT_H ++#define __MEDIATEK_LVTS_DT_H ++ ++#define MT8195_MCU_BIG_CPU0 0 ++#define MT8195_MCU_BIG_CPU1 1 ++#define MT8195_MCU_BIG_CPU2 2 ++#define MT8195_MCU_BIG_CPU3 3 ++#define MT8195_MCU_LITTLE_CPU0 4 ++#define MT8195_MCU_LITTLE_CPU1 5 ++#define MT8195_MCU_LITTLE_CPU2 6 ++#define MT8195_MCU_LITTLE_CPU3 7 ++ ++#endif /* __MEDIATEK_LVTS_DT_H */ diff --git a/lede/target/linux/mediatek/patches-6.1/830-v6.4-08-dt-bindings-thermal-mediatek-Add-AP-domain-to-LVTS-t.patch b/lede/target/linux/mediatek/patches-6.1/830-v6.4-08-dt-bindings-thermal-mediatek-Add-AP-domain-to-LVTS-t.patch new file mode 100644 index 0000000000..efb0d8b64f --- /dev/null +++ b/lede/target/linux/mediatek/patches-6.1/830-v6.4-08-dt-bindings-thermal-mediatek-Add-AP-domain-to-LVTS-t.patch @@ -0,0 +1,35 @@ +From 05aaa7fdb0736262e224369b9b9f1410320fc71b Mon Sep 17 00:00:00 2001 +From: Balsam CHIHI +Date: Tue, 7 Mar 2023 16:45:21 +0100 +Subject: [PATCH] dt-bindings: thermal: mediatek: Add AP domain to LVTS thermal + controllers for mt8195 + +Add AP Domain to LVTS thermal controllers dt-binding definition for mt8195. + +Signed-off-by: Balsam CHIHI +Acked-by: Rob Herring +Reviewed-by: AngeloGioacchino Del Regno +Tested-by: Chen-Yu Tsai +Signed-off-by: Daniel Lezcano +Link: https://lore.kernel.org/r/20230307154524.118541-2-bchihi@baylibre.com +--- + include/dt-bindings/thermal/mediatek,lvts-thermal.h | 10 ++++++++++ + 1 file changed, 10 insertions(+) + +--- a/include/dt-bindings/thermal/mediatek,lvts-thermal.h ++++ b/include/dt-bindings/thermal/mediatek,lvts-thermal.h +@@ -16,4 +16,14 @@ + #define MT8195_MCU_LITTLE_CPU2 6 + #define MT8195_MCU_LITTLE_CPU3 7 + ++#define MT8195_AP_VPU0 8 ++#define MT8195_AP_VPU1 9 ++#define MT8195_AP_GPU0 10 ++#define MT8195_AP_GPU1 11 ++#define MT8195_AP_VDEC 12 ++#define MT8195_AP_IMG 13 ++#define MT8195_AP_INFRA 14 ++#define MT8195_AP_CAM0 15 ++#define MT8195_AP_CAM1 16 ++ + #endif /* __MEDIATEK_LVTS_DT_H */ diff --git a/lede/target/linux/mediatek/patches-6.1/830-v6.4-09-thermal-core-Add-a-thermal-zone-devdata-accessor.patch b/lede/target/linux/mediatek/patches-6.1/830-v6.4-09-thermal-core-Add-a-thermal-zone-devdata-accessor.patch new file mode 100644 index 0000000000..c68969321e --- /dev/null +++ b/lede/target/linux/mediatek/patches-6.1/830-v6.4-09-thermal-core-Add-a-thermal-zone-devdata-accessor.patch @@ -0,0 +1,65 @@ +From a6ff3c0021468721b96e84892a8cae24bde8d65f Mon Sep 17 00:00:00 2001 +From: Daniel Lezcano +Date: Wed, 1 Mar 2023 21:14:29 +0100 +Subject: [PATCH] thermal/core: Add a thermal zone 'devdata' accessor + +The thermal zone device structure is exposed to the different drivers +and obviously they access the internals while that should be +restricted to the core thermal code. + +In order to self-encapsulate the thermal core code, we need to prevent +the drivers accessing directly the thermal zone structure and provide +accessor functions to deal with. + +Provide an accessor to the 'devdata' structure and make use of it in +the different drivers. + +No functional changes intended. + +Signed-off-by: Daniel Lezcano +Acked-by: Rafael J. Wysocki +Acked-by: Mark Brown +Signed-off-by: Rafael J. Wysocki +--- + drivers/thermal/thermal_core.c | 6 ++++++ + include/linux/thermal.h | 7 +++++++ + 2 files changed, 13 insertions(+) + +--- a/drivers/thermal/thermal_core.c ++++ b/drivers/thermal/thermal_core.c +@@ -1346,6 +1346,12 @@ struct thermal_zone_device *thermal_zone + } + EXPORT_SYMBOL_GPL(thermal_zone_device_register); + ++void *thermal_zone_device_priv(struct thermal_zone_device *tzd) ++{ ++ return tzd->devdata; ++} ++EXPORT_SYMBOL_GPL(thermal_zone_device_priv); ++ + /** + * thermal_zone_device_unregister - removes the registered thermal zone device + * @tz: the thermal zone device to remove +--- a/include/linux/thermal.h ++++ b/include/linux/thermal.h +@@ -346,6 +346,8 @@ thermal_zone_device_register_with_trips( + void *, struct thermal_zone_device_ops *, + struct thermal_zone_params *, int, int); + ++void *thermal_zone_device_priv(struct thermal_zone_device *tzd); ++ + int thermal_zone_bind_cooling_device(struct thermal_zone_device *, int, + struct thermal_cooling_device *, + unsigned long, unsigned long, +@@ -417,6 +419,11 @@ static inline int thermal_zone_get_offse + struct thermal_zone_device *tz) + { return -ENODEV; } + ++static inline void *thermal_zone_device_priv(struct thermal_zone_device *tz) ++{ ++ return NULL; ++} ++ + static inline int thermal_zone_device_enable(struct thermal_zone_device *tz) + { return -ENODEV; } + diff --git a/lede/target/linux/mediatek/patches-6.1/830-v6.4-10-thermal-core-Add-thermal_zone_device-structure-type-.patch b/lede/target/linux/mediatek/patches-6.1/830-v6.4-10-thermal-core-Add-thermal_zone_device-structure-type-.patch new file mode 100644 index 0000000000..66d3c9e302 --- /dev/null +++ b/lede/target/linux/mediatek/patches-6.1/830-v6.4-10-thermal-core-Add-thermal_zone_device-structure-type-.patch @@ -0,0 +1,55 @@ +From 072e35c98806100182c0a7263cf4cba09ce43463 Mon Sep 17 00:00:00 2001 +From: Daniel Lezcano +Date: Wed, 1 Mar 2023 21:14:38 +0100 +Subject: [PATCH] thermal/core: Add thermal_zone_device structure 'type' + accessor + +The thermal zone device structure is exposed via the exported +thermal.h header. This structure should stay private the thermal core +code. In order to encapsulate the structure, let's add an accessor to +get the 'type' of the thermal zone. + +Signed-off-by: Daniel Lezcano +Signed-off-by: Rafael J. Wysocki +--- + drivers/thermal/thermal_core.c | 6 ++++++ + include/linux/thermal.h | 6 ++++++ + 2 files changed, 12 insertions(+) + +--- a/drivers/thermal/thermal_core.c ++++ b/drivers/thermal/thermal_core.c +@@ -1352,6 +1352,12 @@ void *thermal_zone_device_priv(struct th + } + EXPORT_SYMBOL_GPL(thermal_zone_device_priv); + ++const char *thermal_zone_device_type(struct thermal_zone_device *tzd) ++{ ++ return tzd->type; ++} ++EXPORT_SYMBOL_GPL(thermal_zone_device_type); ++ + /** + * thermal_zone_device_unregister - removes the registered thermal zone device + * @tz: the thermal zone device to remove +--- a/include/linux/thermal.h ++++ b/include/linux/thermal.h +@@ -347,6 +347,7 @@ thermal_zone_device_register_with_trips( + struct thermal_zone_params *, int, int); + + void *thermal_zone_device_priv(struct thermal_zone_device *tzd); ++const char *thermal_zone_device_type(struct thermal_zone_device *tzd); + + int thermal_zone_bind_cooling_device(struct thermal_zone_device *, int, + struct thermal_cooling_device *, +@@ -423,6 +424,11 @@ static inline void *thermal_zone_device_ + { + return NULL; + } ++ ++static inline const char *thermal_zone_device_type(struct thermal_zone_device *tzd) ++{ ++ return NULL; ++} + + static inline int thermal_zone_device_enable(struct thermal_zone_device *tz) + { return -ENODEV; } diff --git a/lede/target/linux/mediatek/patches-6.1/830-v6.4-11-thermal-core-Use-the-thermal-zone-devdata-accessor-i.patch b/lede/target/linux/mediatek/patches-6.1/830-v6.4-11-thermal-core-Use-the-thermal-zone-devdata-accessor-i.patch new file mode 100644 index 0000000000..57bc910d3e --- /dev/null +++ b/lede/target/linux/mediatek/patches-6.1/830-v6.4-11-thermal-core-Use-the-thermal-zone-devdata-accessor-i.patch @@ -0,0 +1,74 @@ +From 7d78bab533eb9aa0e5240e25a204e8f416723ed6 Mon Sep 17 00:00:00 2001 +From: Daniel Lezcano +Date: Wed, 1 Mar 2023 21:14:30 +0100 +Subject: [PATCH 07/42] thermal/core: Use the thermal zone 'devdata' accessor + in thermal located drivers +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +The thermal zone device structure is exposed to the different drivers +and obviously they access the internals while that should be +restricted to the core thermal code. + +In order to self-encapsulate the thermal core code, we need to prevent +the drivers accessing directly the thermal zone structure and provide +accessor functions to deal with. + +Use the devdata accessor introduced in the previous patch. + +No functional changes intended. + +[skipped drivers not relevant for mediatek target] + +Signed-off-by: Daniel Lezcano +Reviewed-by: Niklas Söderlund #R-Car +Acked-by: Mark Brown +Reviewed-by: AngeloGioacchino Del Regno #MediaTek auxadc and lvts +Reviewed-by: Balsam CHIHI #Mediatek lvts +Reviewed-by: Adam Ward #da9062 +Reviewed-by: Baolin Wang #spread +Acked-by: Jernej Skrabec #sun8i_thermal +Acked-by: Rafael J. Wysocki +Acked-by: Florian Fainelli #Broadcom +Reviewed-by: Dhruva Gole # K3 bandgap +Acked-by: Linus Walleij +Acked-by: Heiko Stuebner #rockchip +Reviewed-by: Kunihiko Hayashi #uniphier +Signed-off-by: Rafael J. Wysocki +--- + drivers/thermal/mediatek/auxadc_thermal.c | 2 +- + drivers/thermal/mediatek/lvts_thermal.c | 4 ++-- + 43 files changed, 71 insertions(+), 73 deletions(-) + +--- a/drivers/thermal/mediatek/auxadc_thermal.c ++++ b/drivers/thermal/mediatek/auxadc_thermal.c +@@ -763,7 +763,7 @@ static int mtk_thermal_bank_temperature( + + static int mtk_read_temp(struct thermal_zone_device *tz, int *temperature) + { +- struct mtk_thermal *mt = tz->devdata; ++ struct mtk_thermal *mt = thermal_zone_device_priv(tz); + int i; + int tempmax = INT_MIN; + +--- a/drivers/thermal/mediatek/lvts_thermal.c ++++ b/drivers/thermal/mediatek/lvts_thermal.c +@@ -252,7 +252,7 @@ static u32 lvts_temp_to_raw(int temperat + + static int lvts_get_temp(struct thermal_zone_device *tz, int *temp) + { +- struct lvts_sensor *lvts_sensor = tz->devdata; ++ struct lvts_sensor *lvts_sensor = thermal_zone_device_priv(tz); + void __iomem *msr = lvts_sensor->msr; + u32 value; + +@@ -290,7 +290,7 @@ static int lvts_get_temp(struct thermal_ + + static int lvts_set_trips(struct thermal_zone_device *tz, int low, int high) + { +- struct lvts_sensor *lvts_sensor = tz->devdata; ++ struct lvts_sensor *lvts_sensor = thermal_zone_device_priv(tz); + void __iomem *base = lvts_sensor->base; + u32 raw_low = lvts_temp_to_raw(low); + u32 raw_high = lvts_temp_to_raw(high); diff --git a/lede/target/linux/mediatek/patches-6.1/830-v6.4-12-thermal-hwmon-Use-the-right-device-for-devm_thermal_.patch b/lede/target/linux/mediatek/patches-6.1/830-v6.4-12-thermal-hwmon-Use-the-right-device-for-devm_thermal_.patch new file mode 100644 index 0000000000..647b3b0eca --- /dev/null +++ b/lede/target/linux/mediatek/patches-6.1/830-v6.4-12-thermal-hwmon-Use-the-right-device-for-devm_thermal_.patch @@ -0,0 +1,201 @@ +From cc9c60e9cfeeac45d63361fa8c085c43c4bdfe3a Mon Sep 17 00:00:00 2001 +From: Daniel Lezcano +Date: Wed, 1 Mar 2023 21:14:36 +0100 +Subject: [PATCH 08/42] thermal/hwmon: Use the right device for + devm_thermal_add_hwmon_sysfs() + +The devres variant of thermal_add_hwmon_sysfs() only takes the thermal +zone structure pointer as parameter. + +Actually, it uses the tz->device to add it in the devres list. + +It is preferable to use the device registering the thermal zone +instead of the thermal zone device itself. That prevents the driver +accessing the thermal zone structure internals and it is from my POV +more correct regarding how devm_ is used. + +[skipped imx thermal which did not apply cleanly and irrelevant on +mediatek target] + +Signed-off-by: Daniel Lezcano +Acked-by: Martin Blumenstingl #amlogic_thermal +Acked-by: Jernej Skrabec #sun8i_thermal +Reviewed-by: AngeloGioacchino Del Regno #MediaTek auxadc +Signed-off-by: Rafael J. Wysocki +--- + drivers/thermal/amlogic_thermal.c | 2 +- + drivers/thermal/imx_sc_thermal.c | 2 +- + drivers/thermal/k3_bandgap.c | 2 +- + drivers/thermal/mediatek/auxadc_thermal.c | 2 +- + drivers/thermal/qcom/qcom-spmi-adc-tm5.c | 2 +- + drivers/thermal/qcom/qcom-spmi-temp-alarm.c | 2 +- + drivers/thermal/qcom/tsens.c | 2 +- + drivers/thermal/qoriq_thermal.c | 2 +- + drivers/thermal/sun8i_thermal.c | 2 +- + drivers/thermal/tegra/tegra30-tsensor.c | 2 +- + drivers/thermal/thermal_hwmon.c | 4 ++-- + drivers/thermal/thermal_hwmon.h | 4 ++-- + drivers/thermal/ti-soc-thermal/ti-thermal-common.c | 2 +- + 13 files changed, 15 insertions(+), 15 deletions(-) + +--- a/drivers/thermal/amlogic_thermal.c ++++ b/drivers/thermal/amlogic_thermal.c +@@ -286,7 +286,7 @@ static int amlogic_thermal_probe(struct + return ret; + } + +- if (devm_thermal_add_hwmon_sysfs(pdata->tzd)) ++ if (devm_thermal_add_hwmon_sysfs(&pdev->dev, pdata->tzd)) + dev_warn(&pdev->dev, "Failed to add hwmon sysfs attributes\n"); + + ret = amlogic_thermal_initialize(pdata); +--- a/drivers/thermal/imx_sc_thermal.c ++++ b/drivers/thermal/imx_sc_thermal.c +@@ -120,7 +120,7 @@ static int imx_sc_thermal_probe(struct p + return ret; + } + +- if (devm_thermal_add_hwmon_sysfs(sensor->tzd)) ++ if (devm_thermal_add_hwmon_sysfs(&pdev->dev, sensor->tzd)) + dev_warn(&pdev->dev, "failed to add hwmon sysfs attributes\n"); + } + +--- a/drivers/thermal/k3_bandgap.c ++++ b/drivers/thermal/k3_bandgap.c +@@ -222,7 +222,7 @@ static int k3_bandgap_probe(struct platf + goto err_alloc; + } + +- if (devm_thermal_add_hwmon_sysfs(data[id].tzd)) ++ if (devm_thermal_add_hwmon_sysfs(dev, data[id].tzd)) + dev_warn(dev, "Failed to add hwmon sysfs attributes\n"); + } + +--- a/drivers/thermal/mediatek/auxadc_thermal.c ++++ b/drivers/thermal/mediatek/auxadc_thermal.c +@@ -1210,7 +1210,7 @@ static int mtk_thermal_probe(struct plat + goto err_disable_clk_peri_therm; + } + +- ret = devm_thermal_add_hwmon_sysfs(tzdev); ++ ret = devm_thermal_add_hwmon_sysfs(&pdev->dev, tzdev); + if (ret) + dev_warn(&pdev->dev, "error in thermal_add_hwmon_sysfs"); + +--- a/drivers/thermal/qcom/qcom-spmi-adc-tm5.c ++++ b/drivers/thermal/qcom/qcom-spmi-adc-tm5.c +@@ -688,7 +688,7 @@ static int adc_tm5_register_tzd(struct a + return PTR_ERR(tzd); + } + adc_tm->channels[i].tzd = tzd; +- if (devm_thermal_add_hwmon_sysfs(tzd)) ++ if (devm_thermal_add_hwmon_sysfs(adc_tm->dev, tzd)) + dev_warn(adc_tm->dev, + "Failed to add hwmon sysfs attributes\n"); + } +--- a/drivers/thermal/qcom/qcom-spmi-temp-alarm.c ++++ b/drivers/thermal/qcom/qcom-spmi-temp-alarm.c +@@ -460,7 +460,7 @@ static int qpnp_tm_probe(struct platform + return ret; + } + +- if (devm_thermal_add_hwmon_sysfs(chip->tz_dev)) ++ if (devm_thermal_add_hwmon_sysfs(&pdev->dev, chip->tz_dev)) + dev_warn(&pdev->dev, + "Failed to add hwmon sysfs attributes\n"); + +--- a/drivers/thermal/qcom/tsens.c ++++ b/drivers/thermal/qcom/tsens.c +@@ -1056,7 +1056,7 @@ static int tsens_register(struct tsens_p + if (priv->ops->enable) + priv->ops->enable(priv, i); + +- if (devm_thermal_add_hwmon_sysfs(tzd)) ++ if (devm_thermal_add_hwmon_sysfs(priv->dev, tzd)) + dev_warn(priv->dev, + "Failed to add hwmon sysfs attributes\n"); + } +--- a/drivers/thermal/qoriq_thermal.c ++++ b/drivers/thermal/qoriq_thermal.c +@@ -158,7 +158,7 @@ static int qoriq_tmu_register_tmu_zone(s + return ret; + } + +- if (devm_thermal_add_hwmon_sysfs(tzd)) ++ if (devm_thermal_add_hwmon_sysfs(dev, tzd)) + dev_warn(dev, + "Failed to add hwmon sysfs attributes\n"); + +--- a/drivers/thermal/sun8i_thermal.c ++++ b/drivers/thermal/sun8i_thermal.c +@@ -468,7 +468,7 @@ static int sun8i_ths_register(struct ths + if (IS_ERR(tmdev->sensor[i].tzd)) + return PTR_ERR(tmdev->sensor[i].tzd); + +- if (devm_thermal_add_hwmon_sysfs(tmdev->sensor[i].tzd)) ++ if (devm_thermal_add_hwmon_sysfs(tmdev->dev, tmdev->sensor[i].tzd)) + dev_warn(tmdev->dev, + "Failed to add hwmon sysfs attributes\n"); + } +--- a/drivers/thermal/tegra/tegra30-tsensor.c ++++ b/drivers/thermal/tegra/tegra30-tsensor.c +@@ -530,7 +530,7 @@ static int tegra_tsensor_register_channe + return 0; + } + +- if (devm_thermal_add_hwmon_sysfs(tsc->tzd)) ++ if (devm_thermal_add_hwmon_sysfs(ts->dev, tsc->tzd)) + dev_warn(ts->dev, "failed to add hwmon sysfs attributes\n"); + + return 0; +--- a/drivers/thermal/thermal_hwmon.c ++++ b/drivers/thermal/thermal_hwmon.c +@@ -255,7 +255,7 @@ static void devm_thermal_hwmon_release(s + thermal_remove_hwmon_sysfs(*(struct thermal_zone_device **)res); + } + +-int devm_thermal_add_hwmon_sysfs(struct thermal_zone_device *tz) ++int devm_thermal_add_hwmon_sysfs(struct device *dev, struct thermal_zone_device *tz) + { + struct thermal_zone_device **ptr; + int ret; +@@ -272,7 +272,7 @@ int devm_thermal_add_hwmon_sysfs(struct + } + + *ptr = tz; +- devres_add(&tz->device, ptr); ++ devres_add(dev, ptr); + + return ret; + } +--- a/drivers/thermal/thermal_hwmon.h ++++ b/drivers/thermal/thermal_hwmon.h +@@ -17,7 +17,7 @@ + + #ifdef CONFIG_THERMAL_HWMON + int thermal_add_hwmon_sysfs(struct thermal_zone_device *tz); +-int devm_thermal_add_hwmon_sysfs(struct thermal_zone_device *tz); ++int devm_thermal_add_hwmon_sysfs(struct device *dev, struct thermal_zone_device *tz); + void thermal_remove_hwmon_sysfs(struct thermal_zone_device *tz); + #else + static inline int +@@ -27,7 +27,7 @@ thermal_add_hwmon_sysfs(struct thermal_z + } + + static inline int +-devm_thermal_add_hwmon_sysfs(struct thermal_zone_device *tz) ++devm_thermal_add_hwmon_sysfs(struct device *dev, struct thermal_zone_device *tz) + { + return 0; + } +--- a/drivers/thermal/ti-soc-thermal/ti-thermal-common.c ++++ b/drivers/thermal/ti-soc-thermal/ti-thermal-common.c +@@ -182,7 +182,7 @@ int ti_thermal_expose_sensor(struct ti_b + ti_bandgap_set_sensor_data(bgp, id, data); + ti_bandgap_write_update_interval(bgp, data->sensor_id, interval); + +- if (devm_thermal_add_hwmon_sysfs(data->ti_thermal)) ++ if (devm_thermal_add_hwmon_sysfs(bgp->dev, data->ti_thermal)) + dev_warn(bgp->dev, "failed to add hwmon sysfs attributes\n"); + + return 0; diff --git a/lede/target/linux/mediatek/patches-6.1/830-v6.4-13-thermal-Don-t-use-device-internal-thermal-zone-struc.patch b/lede/target/linux/mediatek/patches-6.1/830-v6.4-13-thermal-Don-t-use-device-internal-thermal-zone-struc.patch new file mode 100644 index 0000000000..9dedc2cb68 --- /dev/null +++ b/lede/target/linux/mediatek/patches-6.1/830-v6.4-13-thermal-Don-t-use-device-internal-thermal-zone-struc.patch @@ -0,0 +1,79 @@ +From 5a72b8e4bac753e4dc74dc0a1335d120f63df97a Mon Sep 17 00:00:00 2001 +From: Daniel Lezcano +Date: Wed, 1 Mar 2023 21:14:37 +0100 +Subject: [PATCH 09/42] thermal: Don't use 'device' internal thermal zone + structure field + +Some drivers are directly using the thermal zone's 'device' structure +field. + +Use the driver device pointer instead of the thermal zone device when +it is available. + +Remove the traces when they are duplicate with the traces in the core +code. + +[again skipped imx_thermal.c] + +Cc: Jean Delvare +Cc: Guenter Roeck +Signed-off-by: Daniel Lezcano +Reviewed-by: Balsam CHIHI #Mediatek LVTS +Reviewed-by: AngeloGioacchino Del Regno #MediaTek LVTS +Signed-off-by: Rafael J. Wysocki +--- + drivers/thermal/mediatek/lvts_thermal.c | 4 ++-- + drivers/thermal/thermal_hwmon.c | 4 ++-- + drivers/thermal/ti-soc-thermal/ti-thermal-common.c | 2 +- + 3 files changed, 5 insertions(+), 5 deletions(-) + +--- a/drivers/thermal/mediatek/lvts_thermal.c ++++ b/drivers/thermal/mediatek/lvts_thermal.c +@@ -305,7 +305,7 @@ static int lvts_set_trips(struct thermal + * 14-0 : Raw temperature for threshold + */ + if (low != -INT_MAX) { +- dev_dbg(&tz->device, "Setting low limit temperature interrupt: %d\n", low); ++ pr_debug("%s: Setting low limit temperature interrupt: %d\n", tz->type, low); + writel(raw_low, LVTS_H2NTHRE(base)); + } + +@@ -318,7 +318,7 @@ static int lvts_set_trips(struct thermal + * + * 14-0 : Raw temperature for threshold + */ +- dev_dbg(&tz->device, "Setting high limit temperature interrupt: %d\n", high); ++ pr_debug("%s: Setting high limit temperature interrupt: %d\n", tz->type, high); + writel(raw_high, LVTS_HTHRE(base)); + + return 0; +--- a/drivers/thermal/thermal_hwmon.c ++++ b/drivers/thermal/thermal_hwmon.c +@@ -220,14 +220,14 @@ void thermal_remove_hwmon_sysfs(struct t + hwmon = thermal_hwmon_lookup_by_type(tz); + if (unlikely(!hwmon)) { + /* Should never happen... */ +- dev_dbg(&tz->device, "hwmon device lookup failed!\n"); ++ dev_dbg(hwmon->device, "hwmon device lookup failed!\n"); + return; + } + + temp = thermal_hwmon_lookup_temp(hwmon, tz); + if (unlikely(!temp)) { + /* Should never happen... */ +- dev_dbg(&tz->device, "temperature input lookup failed!\n"); ++ dev_dbg(hwmon->device, "temperature input lookup failed!\n"); + return; + } + +--- a/drivers/thermal/ti-soc-thermal/ti-thermal-common.c ++++ b/drivers/thermal/ti-soc-thermal/ti-thermal-common.c +@@ -43,7 +43,7 @@ static void ti_thermal_work(struct work_ + + thermal_zone_device_update(data->ti_thermal, THERMAL_EVENT_UNSPECIFIED); + +- dev_dbg(&data->ti_thermal->device, "updated thermal zone %s\n", ++ dev_dbg(data->bgp->dev, "updated thermal zone %s\n", + data->ti_thermal->type); + } + diff --git a/lede/target/linux/mediatek/patches-6.1/830-v6.4-14-thermal-Use-thermal_zone_device_type-accessor.patch b/lede/target/linux/mediatek/patches-6.1/830-v6.4-14-thermal-Use-thermal_zone_device_type-accessor.patch new file mode 100644 index 0000000000..8cec9aba97 --- /dev/null +++ b/lede/target/linux/mediatek/patches-6.1/830-v6.4-14-thermal-Use-thermal_zone_device_type-accessor.patch @@ -0,0 +1,62 @@ +From 66b3a292d3fc749e8ec7ac5278a17e8a5757ecbc Mon Sep 17 00:00:00 2001 +From: Daniel Lezcano +Date: Wed, 1 Mar 2023 21:14:41 +0100 +Subject: [PATCH 10/42] thermal: Use thermal_zone_device_type() accessor + +Replace the accesses to 'tz->type' by its accessor version in order to +self-encapsulate the thermal_zone_device structure. + +Signed-off-by: Daniel Lezcano +Reviewed-by: Ido Schimmel #mlxsw +Reviewed-by: AngeloGioacchino Del Regno #MediaTek LVTS +Signed-off-by: Rafael J. Wysocki +--- + drivers/net/ethernet/mellanox/mlxsw/core_thermal.c | 2 +- + drivers/thermal/mediatek/lvts_thermal.c | 6 ++++-- + drivers/thermal/ti-soc-thermal/ti-thermal-common.c | 2 +- + 3 files changed, 6 insertions(+), 4 deletions(-) + +--- a/drivers/net/ethernet/mellanox/mlxsw/core_thermal.c ++++ b/drivers/net/ethernet/mellanox/mlxsw/core_thermal.c +@@ -168,7 +168,7 @@ mlxsw_thermal_module_trips_update(struct + + if (crit_temp > emerg_temp) { + dev_warn(dev, "%s : Critical threshold %d is above emergency threshold %d\n", +- tz->tzdev->type, crit_temp, emerg_temp); ++ thermal_zone_device_type(tz->tzdev), crit_temp, emerg_temp); + return 0; + } + +--- a/drivers/thermal/mediatek/lvts_thermal.c ++++ b/drivers/thermal/mediatek/lvts_thermal.c +@@ -305,7 +305,8 @@ static int lvts_set_trips(struct thermal + * 14-0 : Raw temperature for threshold + */ + if (low != -INT_MAX) { +- pr_debug("%s: Setting low limit temperature interrupt: %d\n", tz->type, low); ++ pr_debug("%s: Setting low limit temperature interrupt: %d\n", ++ thermal_zone_device_type(tz), low); + writel(raw_low, LVTS_H2NTHRE(base)); + } + +@@ -318,7 +319,8 @@ static int lvts_set_trips(struct thermal + * + * 14-0 : Raw temperature for threshold + */ +- pr_debug("%s: Setting high limit temperature interrupt: %d\n", tz->type, high); ++ pr_debug("%s: Setting high limit temperature interrupt: %d\n", ++ thermal_zone_device_type(tz), high); + writel(raw_high, LVTS_HTHRE(base)); + + return 0; +--- a/drivers/thermal/ti-soc-thermal/ti-thermal-common.c ++++ b/drivers/thermal/ti-soc-thermal/ti-thermal-common.c +@@ -44,7 +44,7 @@ static void ti_thermal_work(struct work_ + thermal_zone_device_update(data->ti_thermal, THERMAL_EVENT_UNSPECIFIED); + + dev_dbg(data->bgp->dev, "updated thermal zone %s\n", +- data->ti_thermal->type); ++ thermal_zone_device_type(data->ti_thermal)); + } + + /** diff --git a/lede/target/linux/mediatek/patches-6.1/830-v6.4-15-thermal-drivers-mediatek-Control-buffer-enablement-t.patch b/lede/target/linux/mediatek/patches-6.1/830-v6.4-15-thermal-drivers-mediatek-Control-buffer-enablement-t.patch new file mode 100644 index 0000000000..68f41fdd16 --- /dev/null +++ b/lede/target/linux/mediatek/patches-6.1/830-v6.4-15-thermal-drivers-mediatek-Control-buffer-enablement-t.patch @@ -0,0 +1,81 @@ +From f6658c1c4ae98477d6be00495226c0617354fe76 Mon Sep 17 00:00:00 2001 +From: Markus Schneider-Pargmann +Date: Fri, 27 Jan 2023 16:44:43 +0100 +Subject: [PATCH 11/42] thermal/drivers/mediatek: Control buffer enablement + tweaks + +Add logic in order to be able to turn on the control buffer on MT8365. +This change now allows to have control buffer support for MTK_THERMAL_V1, +and it allows to define the register offset, and mask used to enable it. + +Signed-off-by: Markus Schneider-Pargmann +Signed-off-by: Fabien Parent +Signed-off-by: Amjad Ouled-Ameur +Reviewed-by: AngeloGioacchino Del Regno +Link: https://lore.kernel.org/r/20221018-up-i350-thermal-bringup-v9-2-55a1ae14af74@baylibre.com +Signed-off-by: Daniel Lezcano +--- + drivers/thermal/mediatek/auxadc_thermal.c | 28 +++++++++++++++-------- + 1 file changed, 19 insertions(+), 9 deletions(-) + +--- a/drivers/thermal/mediatek/auxadc_thermal.c ++++ b/drivers/thermal/mediatek/auxadc_thermal.c +@@ -307,6 +307,9 @@ struct mtk_thermal_data { + bool need_switch_bank; + struct thermal_bank_cfg bank_data[MAX_NUM_ZONES]; + enum mtk_thermal_version version; ++ u32 apmixed_buffer_ctl_reg; ++ u32 apmixed_buffer_ctl_mask; ++ u32 apmixed_buffer_ctl_set; + }; + + struct mtk_thermal { +@@ -560,6 +563,9 @@ static const struct mtk_thermal_data mt7 + .adcpnp = mt7622_adcpnp, + .sensor_mux_values = mt7622_mux_values, + .version = MTK_THERMAL_V2, ++ .apmixed_buffer_ctl_reg = APMIXED_SYS_TS_CON1, ++ .apmixed_buffer_ctl_mask = GENMASK(31, 6) | BIT(3), ++ .apmixed_buffer_ctl_set = BIT(0), + }; + + /* +@@ -1079,14 +1085,18 @@ static const struct of_device_id mtk_the + }; + MODULE_DEVICE_TABLE(of, mtk_thermal_of_match); + +-static void mtk_thermal_turn_on_buffer(void __iomem *apmixed_base) ++static void mtk_thermal_turn_on_buffer(struct mtk_thermal *mt, ++ void __iomem *apmixed_base) + { +- int tmp; ++ u32 tmp; ++ ++ if (!mt->conf->apmixed_buffer_ctl_reg) ++ return; + +- tmp = readl(apmixed_base + APMIXED_SYS_TS_CON1); +- tmp &= ~(0x37); +- tmp |= 0x1; +- writel(tmp, apmixed_base + APMIXED_SYS_TS_CON1); ++ tmp = readl(apmixed_base + mt->conf->apmixed_buffer_ctl_reg); ++ tmp &= mt->conf->apmixed_buffer_ctl_mask; ++ tmp |= mt->conf->apmixed_buffer_ctl_set; ++ writel(tmp, apmixed_base + mt->conf->apmixed_buffer_ctl_reg); + udelay(200); + } + +@@ -1184,10 +1194,10 @@ static int mtk_thermal_probe(struct plat + goto err_disable_clk_auxadc; + } + +- if (mt->conf->version != MTK_THERMAL_V1) { +- mtk_thermal_turn_on_buffer(apmixed_base); ++ mtk_thermal_turn_on_buffer(mt, apmixed_base); ++ ++ if (mt->conf->version != MTK_THERMAL_V2) + mtk_thermal_release_periodic_ts(mt, auxadc_base); +- } + + if (mt->conf->version == MTK_THERMAL_V1) + mt->raw_to_mcelsius = raw_to_mcelsius_v1; diff --git a/lede/target/linux/mediatek/patches-6.1/830-v6.4-16-thermal-drivers-mediatek-Add-support-for-MT8365-SoC.patch b/lede/target/linux/mediatek/patches-6.1/830-v6.4-16-thermal-drivers-mediatek-Add-support-for-MT8365-SoC.patch new file mode 100644 index 0000000000..285c6f6a7b --- /dev/null +++ b/lede/target/linux/mediatek/patches-6.1/830-v6.4-16-thermal-drivers-mediatek-Add-support-for-MT8365-SoC.patch @@ -0,0 +1,123 @@ +From c4eff784465f88218dc5eb51320320464db83d3f Mon Sep 17 00:00:00 2001 +From: Fabien Parent +Date: Fri, 27 Jan 2023 16:44:44 +0100 +Subject: [PATCH 12/42] thermal/drivers/mediatek: Add support for MT8365 SoC + +MT8365 is similar to the other SoCs supported by the driver. It has only +one bank and 3 actual sensors that can be multiplexed. There is another +one sensor that does not have usable data. + +Signed-off-by: Fabien Parent +Signed-off-by: Amjad Ouled-Ameur +Reviewed-by: AngeloGioacchino Del Regno +Link: https://lore.kernel.org/r/20221018-up-i350-thermal-bringup-v9-3-55a1ae14af74@baylibre.com +Signed-off-by: Daniel Lezcano +--- + drivers/thermal/mediatek/auxadc_thermal.c | 68 +++++++++++++++++++++++ + 1 file changed, 68 insertions(+) + +--- a/drivers/thermal/mediatek/auxadc_thermal.c ++++ b/drivers/thermal/mediatek/auxadc_thermal.c +@@ -31,6 +31,7 @@ + #define AUXADC_CON2_V 0x010 + #define AUXADC_DATA(channel) (0x14 + (channel) * 4) + ++#define APMIXED_SYS_TS_CON0 0x600 + #define APMIXED_SYS_TS_CON1 0x604 + + /* Thermal Controller Registers */ +@@ -281,6 +282,17 @@ enum mtk_thermal_version { + /* The calibration coefficient of sensor */ + #define MT7986_CALIBRATION 165 + ++/* MT8365 */ ++#define MT8365_TEMP_AUXADC_CHANNEL 11 ++#define MT8365_CALIBRATION 164 ++#define MT8365_NUM_CONTROLLER 1 ++#define MT8365_NUM_BANKS 1 ++#define MT8365_NUM_SENSORS 3 ++#define MT8365_NUM_SENSORS_PER_ZONE 3 ++#define MT8365_TS1 0 ++#define MT8365_TS2 1 ++#define MT8365_TS3 2 ++ + struct mtk_thermal; + + struct thermal_bank_cfg { +@@ -435,6 +447,24 @@ static const int mt7986_mux_values[MT798 + static const int mt7986_vts_index[MT7986_NUM_SENSORS] = { VTS1 }; + static const int mt7986_tc_offset[MT7986_NUM_CONTROLLER] = { 0x0, }; + ++/* MT8365 thermal sensor data */ ++static const int mt8365_bank_data[MT8365_NUM_SENSORS] = { ++ MT8365_TS1, MT8365_TS2, MT8365_TS3 ++}; ++ ++static const int mt8365_msr[MT8365_NUM_SENSORS_PER_ZONE] = { ++ TEMP_MSR0, TEMP_MSR1, TEMP_MSR2 ++}; ++ ++static const int mt8365_adcpnp[MT8365_NUM_SENSORS_PER_ZONE] = { ++ TEMP_ADCPNP0, TEMP_ADCPNP1, TEMP_ADCPNP2 ++}; ++ ++static const int mt8365_mux_values[MT8365_NUM_SENSORS] = { 0, 1, 2 }; ++static const int mt8365_tc_offset[MT8365_NUM_CONTROLLER] = { 0 }; ++ ++static const int mt8365_vts_index[MT8365_NUM_SENSORS] = { VTS1, VTS2, VTS3 }; ++ + /* + * The MT8173 thermal controller has four banks. Each bank can read up to + * four temperature sensors simultaneously. The MT8173 has a total of 5 +@@ -510,6 +540,40 @@ static const struct mtk_thermal_data mt2 + }; + + /* ++ * The MT8365 thermal controller has one bank, which can read up to ++ * four temperature sensors simultaneously. The MT8365 has a total of 3 ++ * temperature sensors. ++ * ++ * The thermal core only gets the maximum temperature of this one bank, ++ * so the bank concept wouldn't be necessary here. However, the SVS (Smart ++ * Voltage Scaling) unit makes its decisions based on the same bank ++ * data. ++ */ ++static const struct mtk_thermal_data mt8365_thermal_data = { ++ .auxadc_channel = MT8365_TEMP_AUXADC_CHANNEL, ++ .num_banks = MT8365_NUM_BANKS, ++ .num_sensors = MT8365_NUM_SENSORS, ++ .vts_index = mt8365_vts_index, ++ .cali_val = MT8365_CALIBRATION, ++ .num_controller = MT8365_NUM_CONTROLLER, ++ .controller_offset = mt8365_tc_offset, ++ .need_switch_bank = false, ++ .bank_data = { ++ { ++ .num_sensors = MT8365_NUM_SENSORS, ++ .sensors = mt8365_bank_data ++ }, ++ }, ++ .msr = mt8365_msr, ++ .adcpnp = mt8365_adcpnp, ++ .sensor_mux_values = mt8365_mux_values, ++ .version = MTK_THERMAL_V1, ++ .apmixed_buffer_ctl_reg = APMIXED_SYS_TS_CON0, ++ .apmixed_buffer_ctl_mask = (u32) ~GENMASK(29, 28), ++ .apmixed_buffer_ctl_set = 0, ++}; ++ ++/* + * The MT2712 thermal controller has one bank, which can read up to + * four temperature sensors simultaneously. The MT2712 has a total of 4 + * temperature sensors. +@@ -1080,6 +1144,10 @@ static const struct of_device_id mtk_the + { + .compatible = "mediatek,mt8183-thermal", + .data = (void *)&mt8183_thermal_data, ++ }, ++ { ++ .compatible = "mediatek,mt8365-thermal", ++ .data = (void *)&mt8365_thermal_data, + }, { + }, + }; diff --git a/lede/target/linux/mediatek/patches-6.1/830-v6.4-17-thermal-drivers-mediatek-Add-delay-after-thermal-ban.patch b/lede/target/linux/mediatek/patches-6.1/830-v6.4-17-thermal-drivers-mediatek-Add-delay-after-thermal-ban.patch new file mode 100644 index 0000000000..5c99aa80c1 --- /dev/null +++ b/lede/target/linux/mediatek/patches-6.1/830-v6.4-17-thermal-drivers-mediatek-Add-delay-after-thermal-ban.patch @@ -0,0 +1,50 @@ +From 4eead70db74922bc61e9d0b4591524369a335751 Mon Sep 17 00:00:00 2001 +From: Amjad Ouled-Ameur +Date: Fri, 27 Jan 2023 16:44:46 +0100 +Subject: [PATCH 13/42] thermal/drivers/mediatek: Add delay after thermal banks + initialization + +Thermal sensor reads performed immediately after thermal bank +initialization returns bogus values. This is currently tackled by returning +0 if the temperature is bogus (exceeding 200000). + +Instead, add a delay between the bank init and the thermal zone device +register to properly fix this. + +Signed-off-by: Michael Kao +Signed-off-by: Hsin-Yi Wang +Signed-off-by: Amjad Ouled-Ameur +Reviewed-by: AngeloGioacchino Del Regno +Link: https://lore.kernel.org/r/20221018-up-i350-thermal-bringup-v9-5-55a1ae14af74@baylibre.com +Signed-off-by: Daniel Lezcano +--- + drivers/thermal/mediatek/auxadc_thermal.c | 11 +++-------- + 1 file changed, 3 insertions(+), 8 deletions(-) + +--- a/drivers/thermal/mediatek/auxadc_thermal.c ++++ b/drivers/thermal/mediatek/auxadc_thermal.c +@@ -816,14 +816,6 @@ static int mtk_thermal_bank_temperature( + mt, conf->bank_data[bank->id].sensors[i], raw); + + +- /* +- * The first read of a sensor often contains very high bogus +- * temperature value. Filter these out so that the system does +- * not immediately shut down. +- */ +- if (temp > 200000) +- temp = 0; +- + if (temp > max) + max = temp; + } +@@ -1281,6 +1273,9 @@ static int mtk_thermal_probe(struct plat + + platform_set_drvdata(pdev, mt); + ++ /* Delay for thermal banks to be ready */ ++ msleep(30); ++ + tzdev = devm_thermal_of_zone_register(&pdev->dev, 0, mt, + &mtk_thermal_ops); + if (IS_ERR(tzdev)) { diff --git a/lede/target/linux/mediatek/patches-6.1/830-v6.4-18-thermal-drivers-mediatek-lvts_thermal-Fix-sensor-1-i.patch b/lede/target/linux/mediatek/patches-6.1/830-v6.4-18-thermal-drivers-mediatek-lvts_thermal-Fix-sensor-1-i.patch new file mode 100644 index 0000000000..734f5c1e77 --- /dev/null +++ b/lede/target/linux/mediatek/patches-6.1/830-v6.4-18-thermal-drivers-mediatek-lvts_thermal-Fix-sensor-1-i.patch @@ -0,0 +1,46 @@ +From ad9dc9e92367803a4f9576aea0dab110d03fc510 Mon Sep 17 00:00:00 2001 +From: Chen-Yu Tsai +Date: Tue, 28 Mar 2023 11:10:17 +0800 +Subject: [PATCH 14/42] thermal/drivers/mediatek/lvts_thermal: Fix sensor 1 + interrupt status bitmask + +The binary representation for sensor 1 interrupt status was incorrectly +assembled, when compared to the full table given in the same comment +section. The conversion into hex was also incorrect, leading to +incorrect interrupt status bitmask for sensor 1. This would cause the +driver to incorrectly identify changes for sensor 1, when in fact it +was sensor 0, or a sensor access time out. + +Fix the binary and hex representations in the comments, and the actual +bitmask macro. + +Fixes: f5f633b18234 ("thermal/drivers/mediatek: Add the Low Voltage Thermal Sensor driver") +Signed-off-by: Chen-Yu Tsai +Signed-off-by: Daniel Lezcano +Link: https://lore.kernel.org/r/20230328031017.1360976-1-wenst@chromium.org +--- + drivers/thermal/mediatek/lvts_thermal.c | 6 +++--- + 1 file changed, 3 insertions(+), 3 deletions(-) + +--- a/drivers/thermal/mediatek/lvts_thermal.c ++++ b/drivers/thermal/mediatek/lvts_thermal.c +@@ -66,7 +66,7 @@ + #define LVTS_MONINT_CONF 0x9FBF7BDE + + #define LVTS_INT_SENSOR0 0x0009001F +-#define LVTS_INT_SENSOR1 0X000881F0 ++#define LVTS_INT_SENSOR1 0x001203E0 + #define LVTS_INT_SENSOR2 0x00247C00 + #define LVTS_INT_SENSOR3 0x1FC00000 + +@@ -395,8 +395,8 @@ static irqreturn_t lvts_ctrl_irq_handler + * => 0x1FC00000 + * sensor 2 interrupt: 0000 0000 0010 0100 0111 1100 0000 0000 + * => 0x00247C00 +- * sensor 1 interrupt: 0000 0000 0001 0001 0000 0011 1110 0000 +- * => 0X000881F0 ++ * sensor 1 interrupt: 0000 0000 0001 0010 0000 0011 1110 0000 ++ * => 0X001203E0 + * sensor 0 interrupt: 0000 0000 0000 1001 0000 0000 0001 1111 + * => 0x0009001F + */ diff --git a/lede/target/linux/mediatek/patches-6.1/830-v6.4-19-thermal-drivers-mediatek-lvts_thermal-Add-AP-domain-.patch b/lede/target/linux/mediatek/patches-6.1/830-v6.4-19-thermal-drivers-mediatek-lvts_thermal-Add-AP-domain-.patch new file mode 100644 index 0000000000..d09c2055a3 --- /dev/null +++ b/lede/target/linux/mediatek/patches-6.1/830-v6.4-19-thermal-drivers-mediatek-lvts_thermal-Add-AP-domain-.patch @@ -0,0 +1,149 @@ +From 9aad43ad3285fc21158fb416830a6156a9a31fa5 Mon Sep 17 00:00:00 2001 +From: Balsam CHIHI +Date: Tue, 7 Mar 2023 16:45:22 +0100 +Subject: [PATCH 15/42] thermal/drivers/mediatek/lvts_thermal: Add AP domain + for mt8195 + +Add MT8195 AP Domain support to LVTS Driver. + +Take the opportunity to update the comments to show calibration data +information related to the new domain. + +[dlezcano]: Massaged a bit the changelog + +Signed-off-by: Balsam CHIHI +Tested-by: Chen-Yu Tsai +Signed-off-by: Daniel Lezcano +Link: https://lore.kernel.org/r/20230307154524.118541-3-bchihi@baylibre.com +--- + drivers/thermal/mediatek/lvts_thermal.c | 94 +++++++++++++++++++------ + 1 file changed, 74 insertions(+), 20 deletions(-) + +--- a/drivers/thermal/mediatek/lvts_thermal.c ++++ b/drivers/thermal/mediatek/lvts_thermal.c +@@ -530,29 +530,33 @@ static int lvts_sensor_init(struct devic + * The efuse blob values follows the sensor enumeration per thermal + * controller. The decoding of the stream is as follow: + * +- * <--?-> <----big0 ???---> <-sensor0-> <-0-> +- * ------------------------------------------ +- * index in the stream: : | 0x0 | 0x1 | 0x2 | 0x3 | 0x4 | 0x5 | 0x6 | +- * ------------------------------------------ ++ * stream index map for MCU Domain : + * +- * <--sensor1--><-0-> <----big1 ???---> <-sen +- * ------------------------------------------ +- * | 0x7 | 0x8 | 0x9 | 0xA | 0xB | OxC | OxD | +- * ------------------------------------------ ++ * <-----mcu-tc#0-----> <-----sensor#0-----> <-----sensor#1-----> ++ * 0x01 | 0x02 | 0x03 | 0x04 | 0x05 | 0x06 | 0x07 | 0x08 | 0x09 + * +- * sor0-> <-0-> <-sensor1-> <-0-> .......... +- * ------------------------------------------ +- * | 0x7 | 0x8 | 0x9 | 0xA | 0xB | OxC | OxD | +- * ------------------------------------------ ++ * <-----mcu-tc#1-----> <-----sensor#2-----> <-----sensor#3-----> ++ * 0x0A | 0x0B | 0x0C | 0x0D | 0x0E | 0x0F | 0x10 | 0x11 | 0x12 + * +- * And so on ... ++ * <-----mcu-tc#2-----> <-----sensor#4-----> <-----sensor#5-----> <-----sensor#6-----> <-----sensor#7-----> ++ * 0x13 | 0x14 | 0x15 | 0x16 | 0x17 | 0x18 | 0x19 | 0x1A | 0x1B | 0x1C | 0x1D | 0x1E | 0x1F | 0x20 | 0x21 ++ * ++ * stream index map for AP Domain : ++ * ++ * <-----ap--tc#0-----> <-----sensor#0-----> <-----sensor#1-----> ++ * 0x22 | 0x23 | 0x24 | 0x25 | 0x26 | 0x27 | 0x28 | 0x29 | 0x2A ++ * ++ * <-----ap--tc#1-----> <-----sensor#2-----> <-----sensor#3-----> ++ * 0x2B | 0x2C | 0x2D | 0x2E | 0x2F | 0x30 | 0x31 | 0x32 | 0x33 ++ * ++ * <-----ap--tc#2-----> <-----sensor#4-----> <-----sensor#5-----> <-----sensor#6-----> ++ * 0x34 | 0x35 | 0x36 | 0x37 | 0x38 | 0x39 | 0x3A | 0x3B | 0x3C | 0x3D | 0x3E | 0x3F ++ * ++ * <-----ap--tc#3-----> <-----sensor#7-----> <-----sensor#8-----> ++ * 0x40 | 0x41 | 0x42 | 0x43 | 0x44 | 0x45 | 0x46 | 0x47 | 0x48 + * + * The data description gives the offset of the calibration data in + * this bytes stream for each sensor. +- * +- * Each thermal controller can handle up to 4 sensors max, we don't +- * care if there are less as the array of calibration is sized to 4 +- * anyway. The unused sensor slot will be zeroed. + */ + static int lvts_calibration_init(struct device *dev, struct lvts_ctrl *lvts_ctrl, + const struct lvts_ctrl_data *lvts_ctrl_data, +@@ -1165,7 +1169,7 @@ static int lvts_remove(struct platform_d + return 0; + } + +-static const struct lvts_ctrl_data mt8195_lvts_data_ctrl[] = { ++static const struct lvts_ctrl_data mt8195_lvts_mcu_data_ctrl[] = { + { + .cal_offset = { 0x04, 0x07 }, + .lvts_sensor = { +@@ -1200,13 +1204,63 @@ static const struct lvts_ctrl_data mt819 + } + }; + ++static const struct lvts_ctrl_data mt8195_lvts_ap_data_ctrl[] = { ++ { ++ .cal_offset = { 0x25, 0x28 }, ++ .lvts_sensor = { ++ { .dt_id = MT8195_AP_VPU0 }, ++ { .dt_id = MT8195_AP_VPU1 } ++ }, ++ .num_lvts_sensor = 2, ++ .offset = 0x0, ++ .hw_tshut_temp = LVTS_HW_SHUTDOWN_MT8195, ++ }, ++ { ++ .cal_offset = { 0x2e, 0x31 }, ++ .lvts_sensor = { ++ { .dt_id = MT8195_AP_GPU0 }, ++ { .dt_id = MT8195_AP_GPU1 } ++ }, ++ .num_lvts_sensor = 2, ++ .offset = 0x100, ++ .hw_tshut_temp = LVTS_HW_SHUTDOWN_MT8195, ++ }, ++ { ++ .cal_offset = { 0x37, 0x3a, 0x3d }, ++ .lvts_sensor = { ++ { .dt_id = MT8195_AP_VDEC }, ++ { .dt_id = MT8195_AP_IMG }, ++ { .dt_id = MT8195_AP_INFRA }, ++ }, ++ .num_lvts_sensor = 3, ++ .offset = 0x200, ++ .hw_tshut_temp = LVTS_HW_SHUTDOWN_MT8195, ++ }, ++ { ++ .cal_offset = { 0x43, 0x46 }, ++ .lvts_sensor = { ++ { .dt_id = MT8195_AP_CAM0 }, ++ { .dt_id = MT8195_AP_CAM1 } ++ }, ++ .num_lvts_sensor = 2, ++ .offset = 0x300, ++ .hw_tshut_temp = LVTS_HW_SHUTDOWN_MT8195, ++ } ++}; ++ + static const struct lvts_data mt8195_lvts_mcu_data = { +- .lvts_ctrl = mt8195_lvts_data_ctrl, +- .num_lvts_ctrl = ARRAY_SIZE(mt8195_lvts_data_ctrl), ++ .lvts_ctrl = mt8195_lvts_mcu_data_ctrl, ++ .num_lvts_ctrl = ARRAY_SIZE(mt8195_lvts_mcu_data_ctrl), ++}; ++ ++static const struct lvts_data mt8195_lvts_ap_data = { ++ .lvts_ctrl = mt8195_lvts_ap_data_ctrl, ++ .num_lvts_ctrl = ARRAY_SIZE(mt8195_lvts_ap_data_ctrl), + }; + + static const struct of_device_id lvts_of_match[] = { + { .compatible = "mediatek,mt8195-lvts-mcu", .data = &mt8195_lvts_mcu_data }, ++ { .compatible = "mediatek,mt8195-lvts-ap", .data = &mt8195_lvts_ap_data }, + {}, + }; + MODULE_DEVICE_TABLE(of, lvts_of_match); diff --git a/lede/target/linux/mediatek/patches-6.1/830-v6.4-20-Revert-thermal-drivers-mediatek-Add-delay-after-ther.patch b/lede/target/linux/mediatek/patches-6.1/830-v6.4-20-Revert-thermal-drivers-mediatek-Add-delay-after-ther.patch new file mode 100644 index 0000000000..a48ea3742b --- /dev/null +++ b/lede/target/linux/mediatek/patches-6.1/830-v6.4-20-Revert-thermal-drivers-mediatek-Add-delay-after-ther.patch @@ -0,0 +1,53 @@ +From 7105a86760bd9e4d107075cefc75016b693a5542 Mon Sep 17 00:00:00 2001 +From: AngeloGioacchino Del Regno +Date: Wed, 19 Apr 2023 08:11:45 +0200 +Subject: [PATCH 16/42] Revert "thermal/drivers/mediatek: Add delay after + thermal banks initialization" + +Some more testing revealed that this commit introduces a regression on some +MT8173 Chromebooks and at least on one MT6795 Sony Xperia M5 smartphone due +to the delay being apparently variable and machine specific. + +Another solution would be to delay for a bit more (~70ms) but this is not +feasible for two reasons: first of all, we're adding an even bigger delay +in a probe function; second, some machines need less, some may need even +more, making the msleep at probe solution highly suboptimal. + +This reverts commit 10debf8c2da8011c8009dd4b3f6d0ab85891c81b. + +Fixes: 10debf8c2da8 ("thermal/drivers/mediatek: Add delay after thermal banks initialization") +Reported-by: "kernelci.org bot" +Signed-off-by: AngeloGioacchino Del Regno +Signed-off-by: Daniel Lezcano +Link: https://lore.kernel.org/r/20230419061146.22246-2-angelogioacchino.delregno@collabora.com +--- + drivers/thermal/mediatek/auxadc_thermal.c | 11 ++++++++--- + 1 file changed, 8 insertions(+), 3 deletions(-) + +--- a/drivers/thermal/mediatek/auxadc_thermal.c ++++ b/drivers/thermal/mediatek/auxadc_thermal.c +@@ -816,6 +816,14 @@ static int mtk_thermal_bank_temperature( + mt, conf->bank_data[bank->id].sensors[i], raw); + + ++ /* ++ * The first read of a sensor often contains very high bogus ++ * temperature value. Filter these out so that the system does ++ * not immediately shut down. ++ */ ++ if (temp > 200000) ++ temp = 0; ++ + if (temp > max) + max = temp; + } +@@ -1273,9 +1281,6 @@ static int mtk_thermal_probe(struct plat + + platform_set_drvdata(pdev, mt); + +- /* Delay for thermal banks to be ready */ +- msleep(30); +- + tzdev = devm_thermal_of_zone_register(&pdev->dev, 0, mt, + &mtk_thermal_ops); + if (IS_ERR(tzdev)) { diff --git a/lede/target/linux/mediatek/patches-6.1/830-v6.4-21-thermal-drivers-mediatek-Add-temperature-constraints.patch b/lede/target/linux/mediatek/patches-6.1/830-v6.4-21-thermal-drivers-mediatek-Add-temperature-constraints.patch new file mode 100644 index 0000000000..aae87af5d1 --- /dev/null +++ b/lede/target/linux/mediatek/patches-6.1/830-v6.4-21-thermal-drivers-mediatek-Add-temperature-constraints.patch @@ -0,0 +1,78 @@ +From 681b652c9dfc4037d4a55b2733e091a4e1a5de18 Mon Sep 17 00:00:00 2001 +From: AngeloGioacchino Del Regno +Date: Wed, 19 Apr 2023 08:11:46 +0200 +Subject: [PATCH 17/42] thermal/drivers/mediatek: Add temperature constraints + to validate read +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +The AUXADC thermal v1 allows reading temperature range between -20°C to +150°C and any value out of this range is invalid. + +Add new definitions for MT8173_TEMP_{MIN_MAX} and a new small helper +mtk_thermal_temp_is_valid() to check if new readings are in range: if +not, we tell to the API that the reading is invalid by returning +THERMAL_TEMP_INVALID. + +It was chosen to introduce the helper function because, even though this +temperature range is realistically ok for all, it comes from a downstream +kernel driver for version 1, but here we also support v2 and v3 which may +may have wider constraints. + +Signed-off-by: AngeloGioacchino Del Regno +Signed-off-by: Daniel Lezcano +Link: https://lore.kernel.org/r/20230419061146.22246-3-angelogioacchino.delregno@collabora.com +--- + drivers/thermal/mediatek/auxadc_thermal.c | 24 +++++++++++++++++------ + 1 file changed, 18 insertions(+), 6 deletions(-) + +--- a/drivers/thermal/mediatek/auxadc_thermal.c ++++ b/drivers/thermal/mediatek/auxadc_thermal.c +@@ -116,6 +116,10 @@ + /* The calibration coefficient of sensor */ + #define MT8173_CALIBRATION 165 + ++/* Valid temperatures range */ ++#define MT8173_TEMP_MIN -20000 ++#define MT8173_TEMP_MAX 150000 ++ + /* + * Layout of the fuses providing the calibration data + * These macros could be used for MT8183, MT8173, MT2701, and MT2712. +@@ -689,6 +693,11 @@ static const struct mtk_thermal_data mt7 + .version = MTK_THERMAL_V3, + }; + ++static bool mtk_thermal_temp_is_valid(int temp) ++{ ++ return (temp >= MT8173_TEMP_MIN) && (temp <= MT8173_TEMP_MAX); ++} ++ + /** + * raw_to_mcelsius_v1 - convert a raw ADC value to mcelsius + * @mt: The thermal controller +@@ -815,14 +824,17 @@ static int mtk_thermal_bank_temperature( + temp = mt->raw_to_mcelsius( + mt, conf->bank_data[bank->id].sensors[i], raw); + +- + /* +- * The first read of a sensor often contains very high bogus +- * temperature value. Filter these out so that the system does +- * not immediately shut down. ++ * Depending on the filt/sen intervals and ADC polling time, ++ * we may need up to 60 milliseconds after initialization: this ++ * will result in the first reading containing an out of range ++ * temperature value. ++ * Validate the reading to both address the aforementioned issue ++ * and to eventually avoid bogus readings during runtime in the ++ * event that the AUXADC gets unstable due to high EMI, etc. + */ +- if (temp > 200000) +- temp = 0; ++ if (!mtk_thermal_temp_is_valid(temp)) ++ temp = THERMAL_TEMP_INVALID; + + if (temp > max) + max = temp; diff --git a/lede/target/linux/mediatek/patches-6.1/830-v6.4-22-thermal-drivers-mediatek-Use-devm_of_iomap-to-avoid-.patch b/lede/target/linux/mediatek/patches-6.1/830-v6.4-22-thermal-drivers-mediatek-Use-devm_of_iomap-to-avoid-.patch new file mode 100644 index 0000000000..782684aacc --- /dev/null +++ b/lede/target/linux/mediatek/patches-6.1/830-v6.4-22-thermal-drivers-mediatek-Use-devm_of_iomap-to-avoid-.patch @@ -0,0 +1,53 @@ +From 458fa1d508de3f17e49d974a0158d9aeff273a58 Mon Sep 17 00:00:00 2001 +From: Kang Chen +Date: Wed, 19 Apr 2023 10:07:48 +0800 +Subject: [PATCH 18/42] thermal/drivers/mediatek: Use devm_of_iomap to avoid + resource leak in mtk_thermal_probe + +Smatch reports: +1. mtk_thermal_probe() warn: 'apmixed_base' from of_iomap() not released. +2. mtk_thermal_probe() warn: 'auxadc_base' from of_iomap() not released. + +The original code forgets to release iomap resource when handling errors, +fix it by switch to devm_of_iomap. + +Fixes: 89945047b166 ("thermal: mediatek: Add tsensor support for V2 thermal system") +Signed-off-by: Kang Chen +Reviewed-by: Dongliang Mu +Reviewed-by: AngeloGioacchino Del Regno +Signed-off-by: Daniel Lezcano +Link: https://lore.kernel.org/r/20230419020749.621257-1-void0red@hust.edu.cn +--- + drivers/thermal/mediatek/auxadc_thermal.c | 14 ++++++++++++-- + 1 file changed, 12 insertions(+), 2 deletions(-) + +--- a/drivers/thermal/mediatek/auxadc_thermal.c ++++ b/drivers/thermal/mediatek/auxadc_thermal.c +@@ -1232,7 +1232,12 @@ static int mtk_thermal_probe(struct plat + return -ENODEV; + } + +- auxadc_base = of_iomap(auxadc, 0); ++ auxadc_base = devm_of_iomap(&pdev->dev, auxadc, 0, NULL); ++ if (IS_ERR(auxadc_base)) { ++ of_node_put(auxadc); ++ return PTR_ERR(auxadc_base); ++ } ++ + auxadc_phys_base = of_get_phys_base(auxadc); + + of_node_put(auxadc); +@@ -1248,7 +1253,12 @@ static int mtk_thermal_probe(struct plat + return -ENODEV; + } + +- apmixed_base = of_iomap(apmixedsys, 0); ++ apmixed_base = devm_of_iomap(&pdev->dev, apmixedsys, 0, NULL); ++ if (IS_ERR(apmixed_base)) { ++ of_node_put(apmixedsys); ++ return PTR_ERR(apmixed_base); ++ } ++ + apmixed_phys_base = of_get_phys_base(apmixedsys); + + of_node_put(apmixedsys); diff --git a/lede/target/linux/mediatek/patches-6.1/830-v6.4-23-thermal-drivers-mediatek-Change-clk_prepare_enable-t.patch b/lede/target/linux/mediatek/patches-6.1/830-v6.4-23-thermal-drivers-mediatek-Change-clk_prepare_enable-t.patch new file mode 100644 index 0000000000..d7896dbd60 --- /dev/null +++ b/lede/target/linux/mediatek/patches-6.1/830-v6.4-23-thermal-drivers-mediatek-Change-clk_prepare_enable-t.patch @@ -0,0 +1,100 @@ +From 227d1856924ec00a4f5bdf5afcf77bc7f3f04e86 Mon Sep 17 00:00:00 2001 +From: Kang Chen +Date: Wed, 19 Apr 2023 10:07:49 +0800 +Subject: [PATCH 19/42] thermal/drivers/mediatek: Change clk_prepare_enable to + devm_clk_get_enabled in mtk_thermal_probe + +Use devm_clk_get_enabled to do automatic resource management. +Meanwhile, remove error handling labels in the probe function and +the whole remove function. + +Signed-off-by: Kang Chen +Reviewed-by: Dongliang Mu +Signed-off-by: Daniel Lezcano +Link: https://lore.kernel.org/r/20230419020749.621257-2-void0red@hust.edu.cn +--- + drivers/thermal/mediatek/auxadc_thermal.c | 44 +++++------------------ + 1 file changed, 9 insertions(+), 35 deletions(-) + +--- a/drivers/thermal/mediatek/auxadc_thermal.c ++++ b/drivers/thermal/mediatek/auxadc_thermal.c +@@ -1206,14 +1206,6 @@ static int mtk_thermal_probe(struct plat + + mt->conf = of_device_get_match_data(&pdev->dev); + +- mt->clk_peri_therm = devm_clk_get(&pdev->dev, "therm"); +- if (IS_ERR(mt->clk_peri_therm)) +- return PTR_ERR(mt->clk_peri_therm); +- +- mt->clk_auxadc = devm_clk_get(&pdev->dev, "auxadc"); +- if (IS_ERR(mt->clk_auxadc)) +- return PTR_ERR(mt->clk_auxadc); +- + mt->thermal_base = devm_platform_get_and_ioremap_resource(pdev, 0, NULL); + if (IS_ERR(mt->thermal_base)) + return PTR_ERR(mt->thermal_base); +@@ -1272,16 +1264,18 @@ static int mtk_thermal_probe(struct plat + if (ret) + return ret; + +- ret = clk_prepare_enable(mt->clk_auxadc); +- if (ret) { ++ mt->clk_auxadc = devm_clk_get_enabled(&pdev->dev, "auxadc"); ++ if (IS_ERR(mt->clk_auxadc)) { ++ ret = PTR_ERR(mt->clk_auxadc); + dev_err(&pdev->dev, "Can't enable auxadc clk: %d\n", ret); + return ret; + } + +- ret = clk_prepare_enable(mt->clk_peri_therm); +- if (ret) { ++ mt->clk_peri_therm = devm_clk_get_enabled(&pdev->dev, "therm"); ++ if (IS_ERR(mt->clk_peri_therm)) { ++ ret = PTR_ERR(mt->clk_peri_therm); + dev_err(&pdev->dev, "Can't enable peri clk: %d\n", ret); +- goto err_disable_clk_auxadc; ++ return ret; + } + + mtk_thermal_turn_on_buffer(mt, apmixed_base); +@@ -1305,38 +1299,18 @@ static int mtk_thermal_probe(struct plat + + tzdev = devm_thermal_of_zone_register(&pdev->dev, 0, mt, + &mtk_thermal_ops); +- if (IS_ERR(tzdev)) { +- ret = PTR_ERR(tzdev); +- goto err_disable_clk_peri_therm; +- } ++ if (IS_ERR(tzdev)) ++ return PTR_ERR(tzdev); + + ret = devm_thermal_add_hwmon_sysfs(&pdev->dev, tzdev); + if (ret) + dev_warn(&pdev->dev, "error in thermal_add_hwmon_sysfs"); + + return 0; +- +-err_disable_clk_peri_therm: +- clk_disable_unprepare(mt->clk_peri_therm); +-err_disable_clk_auxadc: +- clk_disable_unprepare(mt->clk_auxadc); +- +- return ret; +-} +- +-static int mtk_thermal_remove(struct platform_device *pdev) +-{ +- struct mtk_thermal *mt = platform_get_drvdata(pdev); +- +- clk_disable_unprepare(mt->clk_peri_therm); +- clk_disable_unprepare(mt->clk_auxadc); +- +- return 0; + } + + static struct platform_driver mtk_thermal_driver = { + .probe = mtk_thermal_probe, +- .remove = mtk_thermal_remove, + .driver = { + .name = "mtk-thermal", + .of_match_table = mtk_thermal_of_match, diff --git a/lede/target/linux/mediatek/patches-6.1/830-v6.4-24-thermal-drivers-mediatek-Use-of_address_to_resource.patch b/lede/target/linux/mediatek/patches-6.1/830-v6.4-24-thermal-drivers-mediatek-Use-of_address_to_resource.patch new file mode 100644 index 0000000000..fd18a5365c --- /dev/null +++ b/lede/target/linux/mediatek/patches-6.1/830-v6.4-24-thermal-drivers-mediatek-Use-of_address_to_resource.patch @@ -0,0 +1,36 @@ +From 655fe2533ac05323a07c19ba079bf2064e7741af Mon Sep 17 00:00:00 2001 +From: Rob Herring +Date: Sun, 19 Mar 2023 11:32:31 -0500 +Subject: [PATCH 20/42] thermal/drivers/mediatek: Use of_address_to_resource() + +Replace of_get_address() and of_translate_address() calls with single +call to of_address_to_resource(). + +Signed-off-by: Rob Herring +Reviewed-by: AngeloGioacchino Del Regno +Signed-off-by: Daniel Lezcano +Link: https://lore.kernel.org/r/20230319163231.226738-1-robh@kernel.org +--- + drivers/thermal/mediatek/auxadc_thermal.c | 8 +++----- + 1 file changed, 3 insertions(+), 5 deletions(-) + +--- a/drivers/thermal/mediatek/auxadc_thermal.c ++++ b/drivers/thermal/mediatek/auxadc_thermal.c +@@ -979,14 +979,12 @@ static void mtk_thermal_init_bank(struct + + static u64 of_get_phys_base(struct device_node *np) + { +- u64 size64; +- const __be32 *regaddr_p; ++ struct resource res; + +- regaddr_p = of_get_address(np, 0, &size64, NULL); +- if (!regaddr_p) ++ if (of_address_to_resource(np, 0, &res)) + return OF_BAD_ADDR; + +- return of_translate_address(np, regaddr_p); ++ return res.start; + } + + static int mtk_thermal_extract_efuse_v1(struct mtk_thermal *mt, u32 *buf) diff --git a/lede/target/linux/mediatek/patches-6.1/830-v6.4-25-Revert-thermal-drivers-mediatek-Use-devm_of_iomap-to.patch b/lede/target/linux/mediatek/patches-6.1/830-v6.4-25-Revert-thermal-drivers-mediatek-Use-devm_of_iomap-to.patch new file mode 100644 index 0000000000..c3ff17d517 --- /dev/null +++ b/lede/target/linux/mediatek/patches-6.1/830-v6.4-25-Revert-thermal-drivers-mediatek-Use-devm_of_iomap-to.patch @@ -0,0 +1,57 @@ +From 2c380d07215e6fce3ac66cc5af059bc2c2a69f7a Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Ricardo=20Ca=C3=B1uelo?= +Date: Thu, 25 May 2023 14:18:11 +0200 +Subject: [PATCH 21/42] Revert "thermal/drivers/mediatek: Use devm_of_iomap to + avoid resource leak in mtk_thermal_probe" +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +This reverts commit f05c7b7d9ea9477fcc388476c6f4ade8c66d2d26. + +That change was causing a regression in the generic-adc-thermal-probed +bootrr test as reported in the kernelci-results list [1]. +A proper rework will take longer, so revert it for now. + +[1] https://groups.io/g/kernelci-results/message/42660 + +Fixes: f05c7b7d9ea9 ("thermal/drivers/mediatek: Use devm_of_iomap to avoid resource leak in mtk_thermal_probe") +Signed-off-by: Ricardo Cañuelo +Suggested-by: AngeloGioacchino Del Regno +Reviewed-by: AngeloGioacchino Del Regno +Signed-off-by: Daniel Lezcano +Link: https://lore.kernel.org/r/20230525121811.3360268-1-ricardo.canuelo@collabora.com +--- + drivers/thermal/mediatek/auxadc_thermal.c | 14 ++------------ + 1 file changed, 2 insertions(+), 12 deletions(-) + +--- a/drivers/thermal/mediatek/auxadc_thermal.c ++++ b/drivers/thermal/mediatek/auxadc_thermal.c +@@ -1222,12 +1222,7 @@ static int mtk_thermal_probe(struct plat + return -ENODEV; + } + +- auxadc_base = devm_of_iomap(&pdev->dev, auxadc, 0, NULL); +- if (IS_ERR(auxadc_base)) { +- of_node_put(auxadc); +- return PTR_ERR(auxadc_base); +- } +- ++ auxadc_base = of_iomap(auxadc, 0); + auxadc_phys_base = of_get_phys_base(auxadc); + + of_node_put(auxadc); +@@ -1243,12 +1238,7 @@ static int mtk_thermal_probe(struct plat + return -ENODEV; + } + +- apmixed_base = devm_of_iomap(&pdev->dev, apmixedsys, 0, NULL); +- if (IS_ERR(apmixed_base)) { +- of_node_put(apmixedsys); +- return PTR_ERR(apmixed_base); +- } +- ++ apmixed_base = of_iomap(apmixedsys, 0); + apmixed_phys_base = of_get_phys_base(apmixedsys); + + of_node_put(apmixedsys); diff --git a/lede/target/linux/mediatek/patches-6.1/830-v6.4-26-thermal-drivers-mediatek-lvts_thermal-Register-therm.patch b/lede/target/linux/mediatek/patches-6.1/830-v6.4-26-thermal-drivers-mediatek-lvts_thermal-Register-therm.patch new file mode 100644 index 0000000000..c4456529c1 --- /dev/null +++ b/lede/target/linux/mediatek/patches-6.1/830-v6.4-26-thermal-drivers-mediatek-lvts_thermal-Register-therm.patch @@ -0,0 +1,37 @@ +From 496f4b08981d8a788ad5a2073fa1c65a2af1862b Mon Sep 17 00:00:00 2001 +From: Chen-Yu Tsai +Date: Tue, 13 Jun 2023 17:13:16 +0800 +Subject: [PATCH 22/42] thermal/drivers/mediatek/lvts_thermal: Register thermal + zones as hwmon sensors + +Register thermal zones as hwmon sensors to let userspace read +temperatures using standard hwmon interface. + +Signed-off-by: Chen-Yu Tsai +Signed-off-by: Daniel Lezcano +Link: https://lore.kernel.org/r/20230613091317.1691247-1-wenst@chromium.org +--- + drivers/thermal/mediatek/lvts_thermal.c | 5 +++++ + 1 file changed, 5 insertions(+) + +--- a/drivers/thermal/mediatek/lvts_thermal.c ++++ b/drivers/thermal/mediatek/lvts_thermal.c +@@ -19,6 +19,8 @@ + #include + #include + ++#include "../thermal_hwmon.h" ++ + #define LVTS_MONCTL0(__base) (__base + 0x0000) + #define LVTS_MONCTL1(__base) (__base + 0x0004) + #define LVTS_MONCTL2(__base) (__base + 0x0008) +@@ -996,6 +998,9 @@ static int lvts_ctrl_start(struct device + return PTR_ERR(tz); + } + ++ if (devm_thermal_add_hwmon_sysfs(dev, tz)) ++ dev_warn(dev, "zone %d: Failed to add hwmon sysfs attributes\n", dt_id); ++ + /* + * The thermal zone pointer will be needed in the + * interrupt handler, we store it in the sensor diff --git a/lede/target/linux/mediatek/patches-6.1/830-v6.4-27-thermal-drivers-mediatek-lvts_thermal-Remove-redunda.patch b/lede/target/linux/mediatek/patches-6.1/830-v6.4-27-thermal-drivers-mediatek-lvts_thermal-Remove-redunda.patch new file mode 100644 index 0000000000..22e7a954ed --- /dev/null +++ b/lede/target/linux/mediatek/patches-6.1/830-v6.4-27-thermal-drivers-mediatek-lvts_thermal-Remove-redunda.patch @@ -0,0 +1,28 @@ +From 885b9768ce2a66ed5d250822aed53d5114c895da Mon Sep 17 00:00:00 2001 +From: Yangtao Li +Date: Tue, 20 Jun 2023 17:07:31 +0800 +Subject: [PATCH 23/42] thermal/drivers/mediatek/lvts_thermal: Remove redundant + msg in lvts_ctrl_start() + +The upper-layer devm_thermal_add_hwmon_sysfs() function can directly +print error information. + +Signed-off-by: Yangtao Li +Signed-off-by: Daniel Lezcano +Link: https://lore.kernel.org/r/20230620090732.50025-10-frank.li@vivo.com +--- + drivers/thermal/mediatek/lvts_thermal.c | 3 +-- + 1 file changed, 1 insertion(+), 2 deletions(-) + +--- a/drivers/thermal/mediatek/lvts_thermal.c ++++ b/drivers/thermal/mediatek/lvts_thermal.c +@@ -998,8 +998,7 @@ static int lvts_ctrl_start(struct device + return PTR_ERR(tz); + } + +- if (devm_thermal_add_hwmon_sysfs(dev, tz)) +- dev_warn(dev, "zone %d: Failed to add hwmon sysfs attributes\n", dt_id); ++ devm_thermal_add_hwmon_sysfs(dev, tz); + + /* + * The thermal zone pointer will be needed in the diff --git a/lede/target/linux/mediatek/patches-6.1/830-v6.4-29-thermal-drivers-mediatek-lvts_thermal-Handle-IRQ-on-.patch b/lede/target/linux/mediatek/patches-6.1/830-v6.4-29-thermal-drivers-mediatek-lvts_thermal-Handle-IRQ-on-.patch new file mode 100644 index 0000000000..bc67727423 --- /dev/null +++ b/lede/target/linux/mediatek/patches-6.1/830-v6.4-29-thermal-drivers-mediatek-lvts_thermal-Handle-IRQ-on-.patch @@ -0,0 +1,40 @@ +From 27b389d9f62c2174f95fe4002b11e77d4cb3ce80 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?N=C3=ADcolas=20F=2E=20R=2E=20A=2E=20Prado?= + +Date: Thu, 6 Jul 2023 11:37:32 -0400 +Subject: [PATCH 25/42] thermal/drivers/mediatek/lvts_thermal: Handle IRQ on + all controllers +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +There is a single IRQ handler for each LVTS thermal domain, and it is +supposed to check each of its underlying controllers for the origin of +the interrupt and clear its status. However due to a typo, only the +first controller was ever being handled, which resulted in the interrupt +never being cleared when it happened on the other controllers. Add the +missing index so interrupts are handled for all controllers. + +Fixes: f5f633b18234 ("thermal/drivers/mediatek: Add the Low Voltage Thermal Sensor driver") +Reviewed-by: Matthias Brugger +Reviewed-by: AngeloGioacchino Del Regno +Tested-by: Chen-Yu Tsai +Signed-off-by: Nícolas F. R. A. Prado +Reviewed-by: Alexandre Mergnat +Signed-off-by: Daniel Lezcano +Link: https://lore.kernel.org/r/20230706153823.201943-2-nfraprado@collabora.com +--- + drivers/thermal/mediatek/lvts_thermal.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/drivers/thermal/mediatek/lvts_thermal.c ++++ b/drivers/thermal/mediatek/lvts_thermal.c +@@ -451,7 +451,7 @@ static irqreturn_t lvts_irq_handler(int + + for (i = 0; i < lvts_td->num_lvts_ctrl; i++) { + +- aux = lvts_ctrl_irq_handler(lvts_td->lvts_ctrl); ++ aux = lvts_ctrl_irq_handler(&lvts_td->lvts_ctrl[i]); + if (aux != IRQ_HANDLED) + continue; + diff --git a/lede/target/linux/mediatek/patches-6.1/830-v6.4-30-thermal-drivers-mediatek-lvts_thermal-Honor-sensors-.patch b/lede/target/linux/mediatek/patches-6.1/830-v6.4-30-thermal-drivers-mediatek-lvts_thermal-Honor-sensors-.patch new file mode 100644 index 0000000000..51d119c05b --- /dev/null +++ b/lede/target/linux/mediatek/patches-6.1/830-v6.4-30-thermal-drivers-mediatek-lvts_thermal-Honor-sensors-.patch @@ -0,0 +1,120 @@ +From 6d827142643ee10c13ff9a1d90f38fb399aa9fff Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?N=C3=ADcolas=20F=2E=20R=2E=20A=2E=20Prado?= + +Date: Thu, 6 Jul 2023 11:37:33 -0400 +Subject: [PATCH 26/42] thermal/drivers/mediatek/lvts_thermal: Honor sensors in + immediate mode +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Each controller can be configured to operate on immediate or filtered +mode. On filtered mode, the sensors are enabled by setting the +corresponding bits in MONCTL0, while on immediate mode, by setting +MSRCTL1. + +Previously, the code would set MSRCTL1 for all four sensors when +configured to immediate mode, but given that the controller might not +have all four sensors connected, this would cause interrupts to trigger +for non-existent sensors. Fix this by handling the MSRCTL1 register +analogously to the MONCTL0: only enable the sensors that were declared. + +Fixes: f5f633b18234 ("thermal/drivers/mediatek: Add the Low Voltage Thermal Sensor driver") +Reviewed-by: AngeloGioacchino Del Regno +Tested-by: Chen-Yu Tsai +Signed-off-by: Nícolas F. R. A. Prado +Reviewed-by: Alexandre Mergnat +Signed-off-by: Daniel Lezcano +Link: https://lore.kernel.org/r/20230706153823.201943-3-nfraprado@collabora.com +--- + drivers/thermal/mediatek/lvts_thermal.c | 57 ++++++++++++++----------- + 1 file changed, 33 insertions(+), 24 deletions(-) + +--- a/drivers/thermal/mediatek/lvts_thermal.c ++++ b/drivers/thermal/mediatek/lvts_thermal.c +@@ -897,24 +897,6 @@ static int lvts_ctrl_configure(struct de + writel(value, LVTS_MSRCTL0(lvts_ctrl->base)); + + /* +- * LVTS_MSRCTL1 : Measurement control +- * +- * Bits: +- * +- * 9: Ignore MSRCTL0 config and do immediate measurement on sensor3 +- * 6: Ignore MSRCTL0 config and do immediate measurement on sensor2 +- * 5: Ignore MSRCTL0 config and do immediate measurement on sensor1 +- * 4: Ignore MSRCTL0 config and do immediate measurement on sensor0 +- * +- * That configuration will ignore the filtering and the delays +- * introduced below in MONCTL1 and MONCTL2 +- */ +- if (lvts_ctrl->mode == LVTS_MSR_IMMEDIATE_MODE) { +- value = BIT(9) | BIT(6) | BIT(5) | BIT(4); +- writel(value, LVTS_MSRCTL1(lvts_ctrl->base)); +- } +- +- /* + * LVTS_MONCTL1 : Period unit and group interval configuration + * + * The clock source of LVTS thermal controller is 26MHz. +@@ -979,6 +961,15 @@ static int lvts_ctrl_start(struct device + struct thermal_zone_device *tz; + u32 sensor_map = 0; + int i; ++ /* ++ * Bitmaps to enable each sensor on immediate and filtered modes, as ++ * described in MSRCTL1 and MONCTL0 registers below, respectively. ++ */ ++ u32 sensor_imm_bitmap[] = { BIT(4), BIT(5), BIT(6), BIT(9) }; ++ u32 sensor_filt_bitmap[] = { BIT(0), BIT(1), BIT(2), BIT(3) }; ++ ++ u32 *sensor_bitmap = lvts_ctrl->mode == LVTS_MSR_IMMEDIATE_MODE ? ++ sensor_imm_bitmap : sensor_filt_bitmap; + + for (i = 0; i < lvts_ctrl->num_lvts_sensor; i++) { + +@@ -1016,20 +1007,38 @@ static int lvts_ctrl_start(struct device + * map, so we can enable the temperature monitoring in + * the hardware thermal controller. + */ +- sensor_map |= BIT(i); ++ sensor_map |= sensor_bitmap[i]; + } + + /* +- * Bits: +- * 9: Single point access flow +- * 0-3: Enable sensing point 0-3 +- * + * The initialization of the thermal zones give us + * which sensor point to enable. If any thermal zone + * was not described in the device tree, it won't be + * enabled here in the sensor map. + */ +- writel(sensor_map | BIT(9), LVTS_MONCTL0(lvts_ctrl->base)); ++ if (lvts_ctrl->mode == LVTS_MSR_IMMEDIATE_MODE) { ++ /* ++ * LVTS_MSRCTL1 : Measurement control ++ * ++ * Bits: ++ * ++ * 9: Ignore MSRCTL0 config and do immediate measurement on sensor3 ++ * 6: Ignore MSRCTL0 config and do immediate measurement on sensor2 ++ * 5: Ignore MSRCTL0 config and do immediate measurement on sensor1 ++ * 4: Ignore MSRCTL0 config and do immediate measurement on sensor0 ++ * ++ * That configuration will ignore the filtering and the delays ++ * introduced in MONCTL1 and MONCTL2 ++ */ ++ writel(sensor_map, LVTS_MSRCTL1(lvts_ctrl->base)); ++ } else { ++ /* ++ * Bits: ++ * 9: Single point access flow ++ * 0-3: Enable sensing point 0-3 ++ */ ++ writel(sensor_map | BIT(9), LVTS_MONCTL0(lvts_ctrl->base)); ++ } + + return 0; + } diff --git a/lede/target/linux/mediatek/patches-6.1/830-v6.4-31-thermal-drivers-mediatek-lvts_thermal-Use-offset-thr.patch b/lede/target/linux/mediatek/patches-6.1/830-v6.4-31-thermal-drivers-mediatek-lvts_thermal-Use-offset-thr.patch new file mode 100644 index 0000000000..bfbadee350 --- /dev/null +++ b/lede/target/linux/mediatek/patches-6.1/830-v6.4-31-thermal-drivers-mediatek-lvts_thermal-Use-offset-thr.patch @@ -0,0 +1,77 @@ +From 93bb11dd19bdcc1fc97c7ceababd0db9fde128ad Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?N=C3=ADcolas=20F=2E=20R=2E=20A=2E=20Prado?= + +Date: Thu, 6 Jul 2023 11:37:34 -0400 +Subject: [PATCH 27/42] thermal/drivers/mediatek/lvts_thermal: Use offset + threshold for IRQ +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +There are two kinds of temperature monitoring interrupts available: +* High Offset, Low Offset +* Hot, Hot to normal, Cold + +The code currently uses the hot/h2n/cold interrupts, however in a way +that doesn't work: the cold threshold is left uninitialized, which +prevents the other thresholds from ever triggering, and the h2n +interrupt is used as the lower threshold, which prevents the hot +interrupt from triggering again after the thresholds are updated by the +thermal framework, since a hot interrupt can only trigger again after +the hot to normal interrupt has been triggered. + +But better yet than addressing those issues, is to use the high/low +offset interrupts instead. This way only two thresholds need to be +managed, which have a simpler state machine, making them a better match +to the thermal framework's high and low thresholds. + +Fixes: f5f633b18234 ("thermal/drivers/mediatek: Add the Low Voltage Thermal Sensor driver") +Signed-off-by: Nícolas F. R. A. Prado +Reviewed-by: Alexandre Mergnat +Reviewed-by: AngeloGioacchino Del Regno +Signed-off-by: Daniel Lezcano +Link: https://lore.kernel.org/r/20230706153823.201943-4-nfraprado@collabora.com +--- + drivers/thermal/mediatek/lvts_thermal.c | 12 ++++++------ + 1 file changed, 6 insertions(+), 6 deletions(-) + +--- a/drivers/thermal/mediatek/lvts_thermal.c ++++ b/drivers/thermal/mediatek/lvts_thermal.c +@@ -298,9 +298,9 @@ static int lvts_set_trips(struct thermal + u32 raw_high = lvts_temp_to_raw(high); + + /* +- * Hot to normal temperature threshold ++ * Low offset temperature threshold + * +- * LVTS_H2NTHRE ++ * LVTS_OFFSETL + * + * Bits: + * +@@ -309,13 +309,13 @@ static int lvts_set_trips(struct thermal + if (low != -INT_MAX) { + pr_debug("%s: Setting low limit temperature interrupt: %d\n", + thermal_zone_device_type(tz), low); +- writel(raw_low, LVTS_H2NTHRE(base)); ++ writel(raw_low, LVTS_OFFSETL(base)); + } + + /* +- * Hot temperature threshold ++ * High offset temperature threshold + * +- * LVTS_HTHRE ++ * LVTS_OFFSETH + * + * Bits: + * +@@ -323,7 +323,7 @@ static int lvts_set_trips(struct thermal + */ + pr_debug("%s: Setting high limit temperature interrupt: %d\n", + thermal_zone_device_type(tz), high); +- writel(raw_high, LVTS_HTHRE(base)); ++ writel(raw_high, LVTS_OFFSETH(base)); + + return 0; + } diff --git a/lede/target/linux/mediatek/patches-6.1/830-v6.4-32-thermal-drivers-mediatek-lvts_thermal-Disable-undesi.patch b/lede/target/linux/mediatek/patches-6.1/830-v6.4-32-thermal-drivers-mediatek-lvts_thermal-Disable-undesi.patch new file mode 100644 index 0000000000..1c35d0ad19 --- /dev/null +++ b/lede/target/linux/mediatek/patches-6.1/830-v6.4-32-thermal-drivers-mediatek-lvts_thermal-Disable-undesi.patch @@ -0,0 +1,51 @@ +From 8f8cab9d3e90acf1db278ef44ad05f10aefb973f Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?N=C3=ADcolas=20F=2E=20R=2E=20A=2E=20Prado?= + +Date: Thu, 6 Jul 2023 11:37:35 -0400 +Subject: [PATCH 28/42] thermal/drivers/mediatek/lvts_thermal: Disable + undesired interrupts +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Out of the many interrupts supported by the hardware, the only ones of +interest to the driver currently are: +* The temperature went over the high offset threshold, for any of the + sensors +* The temperature went below the low offset threshold, for any of the + sensors +* The temperature went over the stage3 threshold + +These are the only thresholds configured by the driver through the +OFFSETH, OFFSETL, and PROTTC registers, respectively. + +The current interrupt mask in LVTS_MONINT_CONF, enables many more +interrupts, including data ready on sensors for both filtered and +immediate mode. These are not only not handled by the driver, but they +are also triggered too often, causing unneeded overhead. Disable these +unnecessary interrupts. + +The meaning of each bit can be seen in the comment describing +LVTS_MONINTST in the IRQ handler. + +Fixes: f5f633b18234 ("thermal/drivers/mediatek: Add the Low Voltage Thermal Sensor driver") +Signed-off-by: Nícolas F. R. A. Prado +Reviewed-by: AngeloGioacchino Del Regno +Reviewed-by: Alexandre Mergnat +Signed-off-by: Daniel Lezcano +Link: https://lore.kernel.org/r/20230706153823.201943-5-nfraprado@collabora.com +--- + drivers/thermal/mediatek/lvts_thermal.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/drivers/thermal/mediatek/lvts_thermal.c ++++ b/drivers/thermal/mediatek/lvts_thermal.c +@@ -65,7 +65,7 @@ + #define LVTS_HW_FILTER 0x2 + #define LVTS_TSSEL_CONF 0x13121110 + #define LVTS_CALSCALE_CONF 0x300 +-#define LVTS_MONINT_CONF 0x9FBF7BDE ++#define LVTS_MONINT_CONF 0x8300318C + + #define LVTS_INT_SENSOR0 0x0009001F + #define LVTS_INT_SENSOR1 0x001203E0 diff --git a/lede/target/linux/mediatek/patches-6.1/830-v6.4-33-thermal-drivers-mediatek-lvts_thermal-Don-t-leave-th.patch b/lede/target/linux/mediatek/patches-6.1/830-v6.4-33-thermal-drivers-mediatek-lvts_thermal-Don-t-leave-th.patch new file mode 100644 index 0000000000..60942fdb89 --- /dev/null +++ b/lede/target/linux/mediatek/patches-6.1/830-v6.4-33-thermal-drivers-mediatek-lvts_thermal-Don-t-leave-th.patch @@ -0,0 +1,70 @@ +From bd1ccf9408e6155564530af5e09b53ae497fe332 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?N=C3=ADcolas=20F=2E=20R=2E=20A=2E=20Prado?= + +Date: Thu, 6 Jul 2023 11:37:36 -0400 +Subject: [PATCH 29/42] thermal/drivers/mediatek/lvts_thermal: Don't leave + threshold zeroed +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +The thermal framework might leave the low threshold unset if there +aren't any lower trip points. This leaves the register zeroed, which +translates to a very high temperature for the low threshold. The +interrupt for this threshold is then immediately triggered, and the +state machine gets stuck, preventing any other temperature monitoring +interrupts to ever trigger. + +(The same happens by not setting the Cold or Hot to Normal thresholds +when using those) + +Set the unused threshold to a valid low value. This value was chosen so +that for any valid golden temperature read from the efuse, when the +value is converted to raw and back again to milliCelsius, the result +doesn't underflow. + +Fixes: f5f633b18234 ("thermal/drivers/mediatek: Add the Low Voltage Thermal Sensor driver") +Signed-off-by: Nícolas F. R. A. Prado +Reviewed-by: Alexandre Mergnat +Reviewed-by: AngeloGioacchino Del Regno +Signed-off-by: Daniel Lezcano +Link: https://lore.kernel.org/r/20230706153823.201943-6-nfraprado@collabora.com +--- + drivers/thermal/mediatek/lvts_thermal.c | 12 ++++++------ + 1 file changed, 6 insertions(+), 6 deletions(-) + +--- a/drivers/thermal/mediatek/lvts_thermal.c ++++ b/drivers/thermal/mediatek/lvts_thermal.c +@@ -83,6 +83,8 @@ + + #define LVTS_HW_SHUTDOWN_MT8195 105000 + ++#define LVTS_MINIMUM_THRESHOLD 20000 ++ + static int golden_temp = LVTS_GOLDEN_TEMP_DEFAULT; + static int coeff_b = LVTS_COEFF_B; + +@@ -294,7 +296,7 @@ static int lvts_set_trips(struct thermal + { + struct lvts_sensor *lvts_sensor = thermal_zone_device_priv(tz); + void __iomem *base = lvts_sensor->base; +- u32 raw_low = lvts_temp_to_raw(low); ++ u32 raw_low = lvts_temp_to_raw(low != -INT_MAX ? low : LVTS_MINIMUM_THRESHOLD); + u32 raw_high = lvts_temp_to_raw(high); + + /* +@@ -306,11 +308,9 @@ static int lvts_set_trips(struct thermal + * + * 14-0 : Raw temperature for threshold + */ +- if (low != -INT_MAX) { +- pr_debug("%s: Setting low limit temperature interrupt: %d\n", +- thermal_zone_device_type(tz), low); +- writel(raw_low, LVTS_OFFSETL(base)); +- } ++ pr_debug("%s: Setting low limit temperature interrupt: %d\n", ++ thermal_zone_device_type(tz), low); ++ writel(raw_low, LVTS_OFFSETL(base)); + + /* + * High offset temperature threshold diff --git a/lede/target/linux/mediatek/patches-6.1/830-v6.4-34-thermal-drivers-mediatek-lvts_thermal-Manage-thresho.patch b/lede/target/linux/mediatek/patches-6.1/830-v6.4-34-thermal-drivers-mediatek-lvts_thermal-Manage-thresho.patch new file mode 100644 index 0000000000..e99aa0cdfd --- /dev/null +++ b/lede/target/linux/mediatek/patches-6.1/830-v6.4-34-thermal-drivers-mediatek-lvts_thermal-Manage-thresho.patch @@ -0,0 +1,156 @@ +From d4dd09968cab3249e6148e1c3fccb51824edb411 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?N=C3=ADcolas=20F=2E=20R=2E=20A=2E=20Prado?= + +Date: Thu, 6 Jul 2023 11:37:37 -0400 +Subject: [PATCH 30/42] thermal/drivers/mediatek/lvts_thermal: Manage threshold + between sensors +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Each LVTS thermal controller can have up to four sensors, each capable +of triggering its own interrupt when its measured temperature crosses +the configured threshold. The threshold for each sensor is handled +separately by the thermal framework, since each one is registered with +its own thermal zone and trips. However, the temperature thresholds are +configured on the controller, and therefore are shared between all +sensors on that controller. + +When the temperature measured by the sensors is different enough to +cause the thermal framework to configure different thresholds for each +one, interrupts start triggering on sensors outside the last threshold +configured. + +To address the issue, track the thresholds required by each sensor and +only actually set the highest one in the hardware, and disable +interrupts for all sensors outside the current configured range. + +Fixes: f5f633b18234 ("thermal/drivers/mediatek: Add the Low Voltage Thermal Sensor driver") +Signed-off-by: Nícolas F. R. A. Prado +Reviewed-by: Alexandre Mergnat +Reviewed-by: AngeloGioacchino Del Regno +Signed-off-by: Daniel Lezcano +Link: https://lore.kernel.org/r/20230706153823.201943-7-nfraprado@collabora.com +--- + drivers/thermal/mediatek/lvts_thermal.c | 69 +++++++++++++++++++++++++ + 1 file changed, 69 insertions(+) + +--- a/drivers/thermal/mediatek/lvts_thermal.c ++++ b/drivers/thermal/mediatek/lvts_thermal.c +@@ -67,6 +67,11 @@ + #define LVTS_CALSCALE_CONF 0x300 + #define LVTS_MONINT_CONF 0x8300318C + ++#define LVTS_MONINT_OFFSET_SENSOR0 0xC ++#define LVTS_MONINT_OFFSET_SENSOR1 0x180 ++#define LVTS_MONINT_OFFSET_SENSOR2 0x3000 ++#define LVTS_MONINT_OFFSET_SENSOR3 0x3000000 ++ + #define LVTS_INT_SENSOR0 0x0009001F + #define LVTS_INT_SENSOR1 0x001203E0 + #define LVTS_INT_SENSOR2 0x00247C00 +@@ -112,6 +117,8 @@ struct lvts_sensor { + void __iomem *base; + int id; + int dt_id; ++ int low_thresh; ++ int high_thresh; + }; + + struct lvts_ctrl { +@@ -121,6 +128,8 @@ struct lvts_ctrl { + int num_lvts_sensor; + int mode; + void __iomem *base; ++ int low_thresh; ++ int high_thresh; + }; + + struct lvts_domain { +@@ -292,12 +301,66 @@ static int lvts_get_temp(struct thermal_ + return 0; + } + ++static void lvts_update_irq_mask(struct lvts_ctrl *lvts_ctrl) ++{ ++ u32 masks[] = { ++ LVTS_MONINT_OFFSET_SENSOR0, ++ LVTS_MONINT_OFFSET_SENSOR1, ++ LVTS_MONINT_OFFSET_SENSOR2, ++ LVTS_MONINT_OFFSET_SENSOR3, ++ }; ++ u32 value = 0; ++ int i; ++ ++ value = readl(LVTS_MONINT(lvts_ctrl->base)); ++ ++ for (i = 0; i < ARRAY_SIZE(masks); i++) { ++ if (lvts_ctrl->sensors[i].high_thresh == lvts_ctrl->high_thresh ++ && lvts_ctrl->sensors[i].low_thresh == lvts_ctrl->low_thresh) ++ value |= masks[i]; ++ else ++ value &= ~masks[i]; ++ } ++ ++ writel(value, LVTS_MONINT(lvts_ctrl->base)); ++} ++ ++static bool lvts_should_update_thresh(struct lvts_ctrl *lvts_ctrl, int high) ++{ ++ int i; ++ ++ if (high > lvts_ctrl->high_thresh) ++ return true; ++ ++ for (i = 0; i < lvts_ctrl->num_lvts_sensor; i++) ++ if (lvts_ctrl->sensors[i].high_thresh == lvts_ctrl->high_thresh ++ && lvts_ctrl->sensors[i].low_thresh == lvts_ctrl->low_thresh) ++ return false; ++ ++ return true; ++} ++ + static int lvts_set_trips(struct thermal_zone_device *tz, int low, int high) + { + struct lvts_sensor *lvts_sensor = thermal_zone_device_priv(tz); ++ struct lvts_ctrl *lvts_ctrl = container_of(lvts_sensor, struct lvts_ctrl, sensors[lvts_sensor->id]); + void __iomem *base = lvts_sensor->base; + u32 raw_low = lvts_temp_to_raw(low != -INT_MAX ? low : LVTS_MINIMUM_THRESHOLD); + u32 raw_high = lvts_temp_to_raw(high); ++ bool should_update_thresh; ++ ++ lvts_sensor->low_thresh = low; ++ lvts_sensor->high_thresh = high; ++ ++ should_update_thresh = lvts_should_update_thresh(lvts_ctrl, high); ++ if (should_update_thresh) { ++ lvts_ctrl->high_thresh = high; ++ lvts_ctrl->low_thresh = low; ++ } ++ lvts_update_irq_mask(lvts_ctrl); ++ ++ if (!should_update_thresh) ++ return 0; + + /* + * Low offset temperature threshold +@@ -521,6 +584,9 @@ static int lvts_sensor_init(struct devic + */ + lvts_sensor[i].msr = lvts_ctrl_data->mode == LVTS_MSR_IMMEDIATE_MODE ? + imm_regs[i] : msr_regs[i]; ++ ++ lvts_sensor[i].low_thresh = INT_MIN; ++ lvts_sensor[i].high_thresh = INT_MIN; + }; + + lvts_ctrl->num_lvts_sensor = lvts_ctrl_data->num_lvts_sensor; +@@ -688,6 +754,9 @@ static int lvts_ctrl_init(struct device + */ + lvts_ctrl[i].hw_tshut_raw_temp = + lvts_temp_to_raw(lvts_data->lvts_ctrl[i].hw_tshut_temp); ++ ++ lvts_ctrl[i].low_thresh = INT_MIN; ++ lvts_ctrl[i].high_thresh = INT_MIN; + } + + /* diff --git a/lede/target/linux/mediatek/patches-6.1/830-v6.4-35-thermal-drivers-mediatek-lvts-Fix-parameter-check-in.patch b/lede/target/linux/mediatek/patches-6.1/830-v6.4-35-thermal-drivers-mediatek-lvts-Fix-parameter-check-in.patch new file mode 100644 index 0000000000..9ce3eeb74b --- /dev/null +++ b/lede/target/linux/mediatek/patches-6.1/830-v6.4-35-thermal-drivers-mediatek-lvts-Fix-parameter-check-in.patch @@ -0,0 +1,29 @@ +From 5af4904adc8b840987000724977c13c706d3b7d8 Mon Sep 17 00:00:00 2001 +From: Minjie Du +Date: Thu, 13 Jul 2023 12:24:12 +0800 +Subject: [PATCH 31/42] thermal/drivers/mediatek/lvts: Fix parameter check in + lvts_debugfs_init() + +The documentation says "If an error occurs, ERR_PTR(-ERROR) will be +returned" but the current code checks against a NULL pointer returned. + +Fix this by checking if IS_ERR(). + +Signed-off-by: Minjie Du +Signed-off-by: Daniel Lezcano +Link: https://lore.kernel.org/r/20230713042413.2519-1-duminjie@vivo.com +--- + drivers/thermal/mediatek/lvts_thermal.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/drivers/thermal/mediatek/lvts_thermal.c ++++ b/drivers/thermal/mediatek/lvts_thermal.c +@@ -201,7 +201,7 @@ static int lvts_debugfs_init(struct devi + int i; + + lvts_td->dom_dentry = debugfs_create_dir(dev_name(dev), NULL); +- if (!lvts_td->dom_dentry) ++ if (IS_ERR(lvts_td->dom_dentry)) + return 0; + + for (i = 0; i < lvts_td->num_lvts_ctrl; i++) { diff --git a/lede/target/linux/mediatek/patches-6.1/830-v6.4-36-thermal-drivers-mediatek-Clean-up-redundant-dev_err_.patch b/lede/target/linux/mediatek/patches-6.1/830-v6.4-36-thermal-drivers-mediatek-Clean-up-redundant-dev_err_.patch new file mode 100644 index 0000000000..4841054917 --- /dev/null +++ b/lede/target/linux/mediatek/patches-6.1/830-v6.4-36-thermal-drivers-mediatek-Clean-up-redundant-dev_err_.patch @@ -0,0 +1,33 @@ +From 6186be80317d1dbda34d35c06c084a083938f2d3 Mon Sep 17 00:00:00 2001 +From: Chen Jiahao +Date: Wed, 2 Aug 2023 17:45:27 +0800 +Subject: [PATCH 32/42] thermal/drivers/mediatek: Clean up redundant + dev_err_probe() + +Referring to platform_get_irq()'s definition, the return value has +already been checked if ret < 0, and printed via dev_err_probe(). +Calling dev_err_probe() one more time outside platform_get_irq() +is obviously redundant. + +Removing dev_err_probe() outside platform_get_irq() to clean up +above problem. + +Signed-off-by: Chen Jiahao +Reviewed-by: AngeloGioacchino Del Regno +Signed-off-by: Daniel Lezcano +Link: https://lore.kernel.org/r/20230802094527.988842-1-chenjiahao16@huawei.com +--- + drivers/thermal/mediatek/lvts_thermal.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/drivers/thermal/mediatek/lvts_thermal.c ++++ b/drivers/thermal/mediatek/lvts_thermal.c +@@ -1216,7 +1216,7 @@ static int lvts_probe(struct platform_de + + irq = platform_get_irq(pdev, 0); + if (irq < 0) +- return dev_err_probe(dev, irq, "No irq resource\n"); ++ return irq; + + ret = lvts_domain_init(dev, lvts_td, lvts_data); + if (ret) diff --git a/lede/target/linux/mediatek/patches-6.1/830-v6.4-37-thermal-drivers-mediatek-lvts_thermal-Make-readings-.patch b/lede/target/linux/mediatek/patches-6.1/830-v6.4-37-thermal-drivers-mediatek-lvts_thermal-Make-readings-.patch new file mode 100644 index 0000000000..c88bf984fa --- /dev/null +++ b/lede/target/linux/mediatek/patches-6.1/830-v6.4-37-thermal-drivers-mediatek-lvts_thermal-Make-readings-.patch @@ -0,0 +1,95 @@ +From c2ab54ab0425388e65901a7af2fbf69ead968708 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?N=C3=ADcolas=20F=2E=20R=2E=20A=2E=20Prado?= + +Date: Thu, 13 Jul 2023 11:42:37 -0400 +Subject: [PATCH 33/42] thermal/drivers/mediatek/lvts_thermal: Make readings + valid in filtered mode +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Currently, when a controller is configured to use filtered mode, thermal +readings are valid only about 30% of the time. + +Upon testing, it was noticed that lowering any of the interval settings +resulted in an improved rate of valid data. The same was observed when +decreasing the number of samples for each sensor (which also results in +quicker measurements). + +Retrying the read with a timeout longer than the time it takes to +resample (about 344us with these settings and 4 sensors) also improves +the rate. + +Lower all timing settings to the minimum, configure the filtering to +single sample, and poll the measurement register for at least one period +to improve the data validity on filtered mode. With these changes in +place, out of 100000 reads, a single one failed, ie 99.999% of the data +was valid. + +Reviewed-by: Chen-Yu Tsai +Tested-by: Chen-Yu Tsai +Signed-off-by: Nícolas F. R. A. Prado +Reviewed-by: Alexandre Mergnat +Reviewed-by: AngeloGioacchino Del Regno +Signed-off-by: Daniel Lezcano +Link: https://lore.kernel.org/r/20230713154743.611870-1-nfraprado@collabora.com +--- + drivers/thermal/mediatek/lvts_thermal.c | 19 ++++++++++++------- + 1 file changed, 12 insertions(+), 7 deletions(-) + +--- a/drivers/thermal/mediatek/lvts_thermal.c ++++ b/drivers/thermal/mediatek/lvts_thermal.c +@@ -58,11 +58,11 @@ + #define LVTS_PROTTC(__base) (__base + 0x00CC) + #define LVTS_CLKEN(__base) (__base + 0x00E4) + +-#define LVTS_PERIOD_UNIT ((118 * 1000) / (256 * 38)) +-#define LVTS_GROUP_INTERVAL 1 +-#define LVTS_FILTER_INTERVAL 1 +-#define LVTS_SENSOR_INTERVAL 1 +-#define LVTS_HW_FILTER 0x2 ++#define LVTS_PERIOD_UNIT 0 ++#define LVTS_GROUP_INTERVAL 0 ++#define LVTS_FILTER_INTERVAL 0 ++#define LVTS_SENSOR_INTERVAL 0 ++#define LVTS_HW_FILTER 0x0 + #define LVTS_TSSEL_CONF 0x13121110 + #define LVTS_CALSCALE_CONF 0x300 + #define LVTS_MONINT_CONF 0x8300318C +@@ -86,6 +86,9 @@ + #define LVTS_MSR_IMMEDIATE_MODE 0 + #define LVTS_MSR_FILTERED_MODE 1 + ++#define LVTS_MSR_READ_TIMEOUT_US 400 ++#define LVTS_MSR_READ_WAIT_US (LVTS_MSR_READ_TIMEOUT_US / 2) ++ + #define LVTS_HW_SHUTDOWN_MT8195 105000 + + #define LVTS_MINIMUM_THRESHOLD 20000 +@@ -268,6 +271,7 @@ static int lvts_get_temp(struct thermal_ + struct lvts_sensor *lvts_sensor = thermal_zone_device_priv(tz); + void __iomem *msr = lvts_sensor->msr; + u32 value; ++ int rc; + + /* + * Measurement registers: +@@ -280,7 +284,8 @@ static int lvts_get_temp(struct thermal_ + * 16 : Valid temperature + * 15-0 : Raw temperature + */ +- value = readl(msr); ++ rc = readl_poll_timeout(msr, value, value & BIT(16), ++ LVTS_MSR_READ_WAIT_US, LVTS_MSR_READ_TIMEOUT_US); + + /* + * As the thermal zone temperature will read before the +@@ -293,7 +298,7 @@ static int lvts_get_temp(struct thermal_ + * functionning temperature and directly jump to a system + * shutdown. + */ +- if (!(value & BIT(16))) ++ if (rc) + return -EAGAIN; + + *temp = lvts_raw_to_temp(value & 0xFFFF); diff --git a/lede/target/linux/mediatek/patches-6.1/830-v6.6-38-thermal-drivers-mediatek-auxadc_thermal-Removed-call.patch b/lede/target/linux/mediatek/patches-6.1/830-v6.6-38-thermal-drivers-mediatek-auxadc_thermal-Removed-call.patch new file mode 100644 index 0000000000..994461cdb1 --- /dev/null +++ b/lede/target/linux/mediatek/patches-6.1/830-v6.6-38-thermal-drivers-mediatek-auxadc_thermal-Removed-call.patch @@ -0,0 +1,30 @@ +From c864ff9de3b225b43bb8e08dedb223632323e059 Mon Sep 17 00:00:00 2001 +From: Andrei Coardos +Date: Fri, 11 Aug 2023 22:28:47 +0300 +Subject: [PATCH 34/42] thermal/drivers/mediatek/auxadc_thermal: Removed call + to platform_set_drvdata() + +This function call was found to be unnecessary as there is no equivalent +platform_get_drvdata() call to access the private data of the driver. Also, +the private data is defined in this driver, so there is no risk of it being +accessed outside of this driver file. + +Signed-off-by: Andrei Coardos +Reviewed-by: Alexandru Ardelean +Signed-off-by: Daniel Lezcano +Link: https://lore.kernel.org/r/20230811192847.3838-1-aboutphysycs@gmail.com +--- + drivers/thermal/mediatek/auxadc_thermal.c | 2 -- + 1 file changed, 2 deletions(-) + +--- a/drivers/thermal/mediatek/auxadc_thermal.c ++++ b/drivers/thermal/mediatek/auxadc_thermal.c +@@ -1283,8 +1283,6 @@ static int mtk_thermal_probe(struct plat + mtk_thermal_init_bank(mt, i, apmixed_phys_base, + auxadc_phys_base, ctrl_id); + +- platform_set_drvdata(pdev, mt); +- + tzdev = devm_thermal_of_zone_register(&pdev->dev, 0, mt, + &mtk_thermal_ops); + if (IS_ERR(tzdev)) diff --git a/lede/target/linux/mediatek/patches-6.1/830-v6.7-39-thermal-lvts-Convert-to-platform-remove-callback-ret.patch b/lede/target/linux/mediatek/patches-6.1/830-v6.7-39-thermal-lvts-Convert-to-platform-remove-callback-ret.patch new file mode 100644 index 0000000000..b3bfa37458 --- /dev/null +++ b/lede/target/linux/mediatek/patches-6.1/830-v6.7-39-thermal-lvts-Convert-to-platform-remove-callback-ret.patch @@ -0,0 +1,58 @@ +From 6cf96078969ec00b873db99bae4e47001290685e Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= +Date: Wed, 27 Sep 2023 21:37:23 +0200 +Subject: [PATCH 35/42] thermal: lvts: Convert to platform remove callback + returning void +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +The .remove() callback for a platform driver returns an int which makes +many driver authors wrongly assume it's possible to do error handling by +returning an error code. However the value returned is ignored (apart +from emitting a warning) and this typically results in resource leaks. + +To improve here there is a quest to make the remove callback return +void. In the first step of this quest all drivers are converted to +.remove_new(), which already returns void. Eventually after all drivers +are converted, .remove_new() will be renamed to .remove(). + +Trivially convert this driver from always returning zero in the remove +callback to the void returning variant. + +Signed-off-by: Uwe Kleine-König +Acked-by: Daniel Lezcano +Signed-off-by: Rafael J. Wysocki +--- + drivers/thermal/mediatek/lvts_thermal.c | 6 ++---- + 1 file changed, 2 insertions(+), 4 deletions(-) + +--- a/drivers/thermal/mediatek/lvts_thermal.c ++++ b/drivers/thermal/mediatek/lvts_thermal.c +@@ -1241,7 +1241,7 @@ static int lvts_probe(struct platform_de + return 0; + } + +-static int lvts_remove(struct platform_device *pdev) ++static void lvts_remove(struct platform_device *pdev) + { + struct lvts_domain *lvts_td; + int i; +@@ -1252,8 +1252,6 @@ static int lvts_remove(struct platform_d + lvts_ctrl_set_enable(&lvts_td->lvts_ctrl[i], false); + + lvts_debugfs_exit(lvts_td); +- +- return 0; + } + + static const struct lvts_ctrl_data mt8195_lvts_mcu_data_ctrl[] = { +@@ -1354,7 +1352,7 @@ MODULE_DEVICE_TABLE(of, lvts_of_match); + + static struct platform_driver lvts_driver = { + .probe = lvts_probe, +- .remove = lvts_remove, ++ .remove_new = lvts_remove, + .driver = { + .name = "mtk-lvts-thermal", + .of_match_table = lvts_of_match, diff --git a/lede/target/linux/mediatek/patches-6.1/830-v6.7-40-thermal-drivers-mediatek-lvts_thermal-Make-coeff-con.patch b/lede/target/linux/mediatek/patches-6.1/830-v6.7-40-thermal-drivers-mediatek-lvts_thermal-Make-coeff-con.patch new file mode 100644 index 0000000000..16a32f564b --- /dev/null +++ b/lede/target/linux/mediatek/patches-6.1/830-v6.7-40-thermal-drivers-mediatek-lvts_thermal-Make-coeff-con.patch @@ -0,0 +1,198 @@ +From 26cc18a3d6d9eac21c4f4b4bb96147b2c6617c86 Mon Sep 17 00:00:00 2001 +From: Frank Wunderlich +Date: Fri, 22 Sep 2023 07:50:19 +0200 +Subject: [PATCH 36/42] thermal/drivers/mediatek/lvts_thermal: Make coeff + configurable + +The upcoming mt7988 has different temperature coefficients so we +cannot use constants in the functions lvts_golden_temp_init, +lvts_golden_temp_init and lvts_raw_to_temp anymore. + +Add a field in the lvts_ctrl pointing to the lvts_data which now +contains the soc-specific temperature coefficents. + +To make the code better readable, rename static int coeff_b to +golden_temp_offset, COEFF_A to temp_factor and COEFF_B to temp_offset. + +Signed-off-by: Frank Wunderlich +Reviewed-by: AngeloGioacchino Del Regno +Tested-by: Daniel Golle +Signed-off-by: Daniel Lezcano +Link: https://lore.kernel.org/r/20230922055020.6436-4-linux@fw-web.de +--- + drivers/thermal/mediatek/lvts_thermal.c | 51 ++++++++++++++++--------- + 1 file changed, 34 insertions(+), 17 deletions(-) + +--- a/drivers/thermal/mediatek/lvts_thermal.c ++++ b/drivers/thermal/mediatek/lvts_thermal.c +@@ -80,8 +80,8 @@ + #define LVTS_SENSOR_MAX 4 + #define LVTS_GOLDEN_TEMP_MAX 62 + #define LVTS_GOLDEN_TEMP_DEFAULT 50 +-#define LVTS_COEFF_A -250460 +-#define LVTS_COEFF_B 250460 ++#define LVTS_COEFF_A_MT8195 -250460 ++#define LVTS_COEFF_B_MT8195 250460 + + #define LVTS_MSR_IMMEDIATE_MODE 0 + #define LVTS_MSR_FILTERED_MODE 1 +@@ -94,7 +94,7 @@ + #define LVTS_MINIMUM_THRESHOLD 20000 + + static int golden_temp = LVTS_GOLDEN_TEMP_DEFAULT; +-static int coeff_b = LVTS_COEFF_B; ++static int golden_temp_offset; + + struct lvts_sensor_data { + int dt_id; +@@ -112,6 +112,8 @@ struct lvts_ctrl_data { + struct lvts_data { + const struct lvts_ctrl_data *lvts_ctrl; + int num_lvts_ctrl; ++ int temp_factor; ++ int temp_offset; + }; + + struct lvts_sensor { +@@ -126,6 +128,7 @@ struct lvts_sensor { + + struct lvts_ctrl { + struct lvts_sensor sensors[LVTS_SENSOR_MAX]; ++ const struct lvts_data *lvts_data; + u32 calibration[LVTS_SENSOR_MAX]; + u32 hw_tshut_raw_temp; + int num_lvts_sensor; +@@ -247,21 +250,21 @@ static void lvts_debugfs_exit(struct lvt + + #endif + +-static int lvts_raw_to_temp(u32 raw_temp) ++static int lvts_raw_to_temp(u32 raw_temp, int temp_factor) + { + int temperature; + +- temperature = ((s64)(raw_temp & 0xFFFF) * LVTS_COEFF_A) >> 14; +- temperature += coeff_b; ++ temperature = ((s64)(raw_temp & 0xFFFF) * temp_factor) >> 14; ++ temperature += golden_temp_offset; + + return temperature; + } + +-static u32 lvts_temp_to_raw(int temperature) ++static u32 lvts_temp_to_raw(int temperature, int temp_factor) + { +- u32 raw_temp = ((s64)(coeff_b - temperature)) << 14; ++ u32 raw_temp = ((s64)(golden_temp_offset - temperature)) << 14; + +- raw_temp = div_s64(raw_temp, -LVTS_COEFF_A); ++ raw_temp = div_s64(raw_temp, -temp_factor); + + return raw_temp; + } +@@ -269,6 +272,9 @@ static u32 lvts_temp_to_raw(int temperat + static int lvts_get_temp(struct thermal_zone_device *tz, int *temp) + { + struct lvts_sensor *lvts_sensor = thermal_zone_device_priv(tz); ++ struct lvts_ctrl *lvts_ctrl = container_of(lvts_sensor, struct lvts_ctrl, ++ sensors[lvts_sensor->id]); ++ const struct lvts_data *lvts_data = lvts_ctrl->lvts_data; + void __iomem *msr = lvts_sensor->msr; + u32 value; + int rc; +@@ -301,7 +307,7 @@ static int lvts_get_temp(struct thermal_ + if (rc) + return -EAGAIN; + +- *temp = lvts_raw_to_temp(value & 0xFFFF); ++ *temp = lvts_raw_to_temp(value & 0xFFFF, lvts_data->temp_factor); + + return 0; + } +@@ -348,10 +354,13 @@ static bool lvts_should_update_thresh(st + static int lvts_set_trips(struct thermal_zone_device *tz, int low, int high) + { + struct lvts_sensor *lvts_sensor = thermal_zone_device_priv(tz); +- struct lvts_ctrl *lvts_ctrl = container_of(lvts_sensor, struct lvts_ctrl, sensors[lvts_sensor->id]); ++ struct lvts_ctrl *lvts_ctrl = container_of(lvts_sensor, struct lvts_ctrl, ++ sensors[lvts_sensor->id]); ++ const struct lvts_data *lvts_data = lvts_ctrl->lvts_data; + void __iomem *base = lvts_sensor->base; +- u32 raw_low = lvts_temp_to_raw(low != -INT_MAX ? low : LVTS_MINIMUM_THRESHOLD); +- u32 raw_high = lvts_temp_to_raw(high); ++ u32 raw_low = lvts_temp_to_raw(low != -INT_MAX ? low : LVTS_MINIMUM_THRESHOLD, ++ lvts_data->temp_factor); ++ u32 raw_high = lvts_temp_to_raw(high, lvts_data->temp_factor); + bool should_update_thresh; + + lvts_sensor->low_thresh = low; +@@ -692,7 +701,7 @@ static int lvts_calibration_read(struct + return 0; + } + +-static int lvts_golden_temp_init(struct device *dev, u32 *value) ++static int lvts_golden_temp_init(struct device *dev, u32 *value, int temp_offset) + { + u32 gt; + +@@ -701,7 +710,7 @@ static int lvts_golden_temp_init(struct + if (gt && gt < LVTS_GOLDEN_TEMP_MAX) + golden_temp = gt; + +- coeff_b = golden_temp * 500 + LVTS_COEFF_B; ++ golden_temp_offset = golden_temp * 500 + temp_offset; + + return 0; + } +@@ -724,7 +733,7 @@ static int lvts_ctrl_init(struct device + * The golden temp information is contained in the first chunk + * of efuse data. + */ +- ret = lvts_golden_temp_init(dev, (u32 *)lvts_td->calib); ++ ret = lvts_golden_temp_init(dev, (u32 *)lvts_td->calib, lvts_data->temp_offset); + if (ret) + return ret; + +@@ -735,6 +744,7 @@ static int lvts_ctrl_init(struct device + for (i = 0; i < lvts_data->num_lvts_ctrl; i++) { + + lvts_ctrl[i].base = lvts_td->base + lvts_data->lvts_ctrl[i].offset; ++ lvts_ctrl[i].lvts_data = lvts_data; + + ret = lvts_sensor_init(dev, &lvts_ctrl[i], + &lvts_data->lvts_ctrl[i]); +@@ -758,7 +768,8 @@ static int lvts_ctrl_init(struct device + * after initializing the calibration. + */ + lvts_ctrl[i].hw_tshut_raw_temp = +- lvts_temp_to_raw(lvts_data->lvts_ctrl[i].hw_tshut_temp); ++ lvts_temp_to_raw(lvts_data->lvts_ctrl[i].hw_tshut_temp, ++ lvts_data->temp_factor); + + lvts_ctrl[i].low_thresh = INT_MIN; + lvts_ctrl[i].high_thresh = INT_MIN; +@@ -1223,6 +1234,8 @@ static int lvts_probe(struct platform_de + if (irq < 0) + return irq; + ++ golden_temp_offset = lvts_data->temp_offset; ++ + ret = lvts_domain_init(dev, lvts_td, lvts_data); + if (ret) + return dev_err_probe(dev, ret, "Failed to initialize the lvts domain\n"); +@@ -1336,11 +1349,15 @@ static const struct lvts_ctrl_data mt819 + static const struct lvts_data mt8195_lvts_mcu_data = { + .lvts_ctrl = mt8195_lvts_mcu_data_ctrl, + .num_lvts_ctrl = ARRAY_SIZE(mt8195_lvts_mcu_data_ctrl), ++ .temp_factor = LVTS_COEFF_A_MT8195, ++ .temp_offset = LVTS_COEFF_B_MT8195, + }; + + static const struct lvts_data mt8195_lvts_ap_data = { + .lvts_ctrl = mt8195_lvts_ap_data_ctrl, + .num_lvts_ctrl = ARRAY_SIZE(mt8195_lvts_ap_data_ctrl), ++ .temp_factor = LVTS_COEFF_A_MT8195, ++ .temp_offset = LVTS_COEFF_B_MT8195, + }; + + static const struct of_device_id lvts_of_match[] = { diff --git a/lede/target/linux/mediatek/patches-6.1/830-v6.7-41-dt-bindings-thermal-mediatek-Add-LVTS-thermal-sensor.patch b/lede/target/linux/mediatek/patches-6.1/830-v6.7-41-dt-bindings-thermal-mediatek-Add-LVTS-thermal-sensor.patch new file mode 100644 index 0000000000..1c2146f43f --- /dev/null +++ b/lede/target/linux/mediatek/patches-6.1/830-v6.7-41-dt-bindings-thermal-mediatek-Add-LVTS-thermal-sensor.patch @@ -0,0 +1,35 @@ +From be2cc09bd5b46f13629d4fcdeac7ad1b18bb1a0b Mon Sep 17 00:00:00 2001 +From: Frank Wunderlich +Date: Fri, 22 Sep 2023 07:50:18 +0200 +Subject: [PATCH] dt-bindings: thermal: mediatek: Add LVTS thermal sensors for + mt7988 + +Add sensor constants for MT7988. + +Signed-off-by: Frank Wunderlich +Reviewed-by: AngeloGioacchino Del Regno +Acked-by: Conor Dooley +Signed-off-by: Daniel Lezcano +Link: https://lore.kernel.org/r/20230922055020.6436-3-linux@fw-web.de +--- + include/dt-bindings/thermal/mediatek,lvts-thermal.h | 9 +++++++++ + 1 file changed, 9 insertions(+) + +--- a/include/dt-bindings/thermal/mediatek,lvts-thermal.h ++++ b/include/dt-bindings/thermal/mediatek,lvts-thermal.h +@@ -7,6 +7,15 @@ + #ifndef __MEDIATEK_LVTS_DT_H + #define __MEDIATEK_LVTS_DT_H + ++#define MT7988_CPU_0 0 ++#define MT7988_CPU_1 1 ++#define MT7988_ETH2P5G_0 2 ++#define MT7988_ETH2P5G_1 3 ++#define MT7988_TOPS_0 4 ++#define MT7988_TOPS_1 5 ++#define MT7988_ETHWARP_0 6 ++#define MT7988_ETHWARP_1 7 ++ + #define MT8195_MCU_BIG_CPU0 0 + #define MT8195_MCU_BIG_CPU1 1 + #define MT8195_MCU_BIG_CPU2 2 diff --git a/lede/target/linux/mediatek/patches-6.1/830-v6.7-42-thermal-drivers-mediatek-lvts_thermal-Add-mt7988-sup.patch b/lede/target/linux/mediatek/patches-6.1/830-v6.7-42-thermal-drivers-mediatek-lvts_thermal-Add-mt7988-sup.patch new file mode 100644 index 0000000000..97c803a820 --- /dev/null +++ b/lede/target/linux/mediatek/patches-6.1/830-v6.7-42-thermal-drivers-mediatek-lvts_thermal-Add-mt7988-sup.patch @@ -0,0 +1,91 @@ +From 9924e9b91b43aaa1610a1d59c4caa43785948cf6 Mon Sep 17 00:00:00 2001 +From: Frank Wunderlich +Date: Fri, 22 Sep 2023 07:50:20 +0200 +Subject: [PATCH 37/42] thermal/drivers/mediatek/lvts_thermal: Add mt7988 + support + +Add Support for Mediatek Filogic 880/MT7988 LVTS. + +Signed-off-by: Frank Wunderlich +Tested-by: Daniel Golle +Signed-off-by: Daniel Lezcano +Link: https://lore.kernel.org/r/20230922055020.6436-5-linux@fw-web.de +--- + drivers/thermal/mediatek/lvts_thermal.c | 38 +++++++++++++++++++++++++ + 1 file changed, 38 insertions(+) + +--- a/drivers/thermal/mediatek/lvts_thermal.c ++++ b/drivers/thermal/mediatek/lvts_thermal.c +@@ -82,6 +82,8 @@ + #define LVTS_GOLDEN_TEMP_DEFAULT 50 + #define LVTS_COEFF_A_MT8195 -250460 + #define LVTS_COEFF_B_MT8195 250460 ++#define LVTS_COEFF_A_MT7988 -204650 ++#define LVTS_COEFF_B_MT7988 204650 + + #define LVTS_MSR_IMMEDIATE_MODE 0 + #define LVTS_MSR_FILTERED_MODE 1 +@@ -89,6 +91,7 @@ + #define LVTS_MSR_READ_TIMEOUT_US 400 + #define LVTS_MSR_READ_WAIT_US (LVTS_MSR_READ_TIMEOUT_US / 2) + ++#define LVTS_HW_SHUTDOWN_MT7988 105000 + #define LVTS_HW_SHUTDOWN_MT8195 105000 + + #define LVTS_MINIMUM_THRESHOLD 20000 +@@ -1267,6 +1270,33 @@ static void lvts_remove(struct platform_ + lvts_debugfs_exit(lvts_td); + } + ++static const struct lvts_ctrl_data mt7988_lvts_ap_data_ctrl[] = { ++ { ++ .cal_offset = { 0x00, 0x04, 0x08, 0x0c }, ++ .lvts_sensor = { ++ { .dt_id = MT7988_CPU_0 }, ++ { .dt_id = MT7988_CPU_1 }, ++ { .dt_id = MT7988_ETH2P5G_0 }, ++ { .dt_id = MT7988_ETH2P5G_1 } ++ }, ++ .num_lvts_sensor = 4, ++ .offset = 0x0, ++ .hw_tshut_temp = LVTS_HW_SHUTDOWN_MT7988, ++ }, ++ { ++ .cal_offset = { 0x14, 0x18, 0x1c, 0x20 }, ++ .lvts_sensor = { ++ { .dt_id = MT7988_TOPS_0}, ++ { .dt_id = MT7988_TOPS_1}, ++ { .dt_id = MT7988_ETHWARP_0}, ++ { .dt_id = MT7988_ETHWARP_1} ++ }, ++ .num_lvts_sensor = 4, ++ .offset = 0x100, ++ .hw_tshut_temp = LVTS_HW_SHUTDOWN_MT7988, ++ } ++}; ++ + static const struct lvts_ctrl_data mt8195_lvts_mcu_data_ctrl[] = { + { + .cal_offset = { 0x04, 0x07 }, +@@ -1346,6 +1376,13 @@ static const struct lvts_ctrl_data mt819 + } + }; + ++static const struct lvts_data mt7988_lvts_ap_data = { ++ .lvts_ctrl = mt7988_lvts_ap_data_ctrl, ++ .num_lvts_ctrl = ARRAY_SIZE(mt7988_lvts_ap_data_ctrl), ++ .temp_factor = LVTS_COEFF_A_MT7988, ++ .temp_offset = LVTS_COEFF_B_MT7988, ++}; ++ + static const struct lvts_data mt8195_lvts_mcu_data = { + .lvts_ctrl = mt8195_lvts_mcu_data_ctrl, + .num_lvts_ctrl = ARRAY_SIZE(mt8195_lvts_mcu_data_ctrl), +@@ -1361,6 +1398,7 @@ static const struct lvts_data mt8195_lvt + }; + + static const struct of_device_id lvts_of_match[] = { ++ { .compatible = "mediatek,mt7988-lvts-ap", .data = &mt7988_lvts_ap_data }, + { .compatible = "mediatek,mt8195-lvts-mcu", .data = &mt8195_lvts_mcu_data }, + { .compatible = "mediatek,mt8195-lvts-ap", .data = &mt8195_lvts_ap_data }, + {}, diff --git a/lede/target/linux/mediatek/patches-6.1/830-v6.7-43-thermal-drivers-mediatek-lvts_thermal-Fix-error-chec.patch b/lede/target/linux/mediatek/patches-6.1/830-v6.7-43-thermal-drivers-mediatek-lvts_thermal-Fix-error-chec.patch new file mode 100644 index 0000000000..5b212a2a37 --- /dev/null +++ b/lede/target/linux/mediatek/patches-6.1/830-v6.7-43-thermal-drivers-mediatek-lvts_thermal-Fix-error-chec.patch @@ -0,0 +1,30 @@ +From fb1bbb5b63e4e3c788a978724749ced57d208054 Mon Sep 17 00:00:00 2001 +From: Minjie Du +Date: Thu, 21 Sep 2023 17:10:50 +0800 +Subject: [PATCH 38/42] thermal/drivers/mediatek/lvts_thermal: Fix error check + in lvts_debugfs_init() + +debugfs_create_dir() function returns an error value embedded in +the pointer (PTR_ERR). Evaluate the return value using IS_ERR +rather than checking for NULL. + +Signed-off-by: Minjie Du +Reviewed-by: Alexandre Mergnat +Reviewed-by: Chen-Yu Tsai +Signed-off-by: Daniel Lezcano +Link: https://lore.kernel.org/r/20230921091057.3812-1-duminjie@vivo.com +--- + drivers/thermal/mediatek/lvts_thermal.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/drivers/thermal/mediatek/lvts_thermal.c ++++ b/drivers/thermal/mediatek/lvts_thermal.c +@@ -219,7 +219,7 @@ static int lvts_debugfs_init(struct devi + + sprintf(name, "controller%d", i); + dentry = debugfs_create_dir(name, lvts_td->dom_dentry); +- if (!dentry) ++ if (IS_ERR(dentry)) + continue; + + regset = devm_kzalloc(dev, sizeof(*regset), GFP_KERNEL); diff --git a/lede/target/linux/mediatek/patches-6.1/830-v6.7-44-thermal-drivers-mediatek-Fix-probe-for-THERMAL_V2.patch b/lede/target/linux/mediatek/patches-6.1/830-v6.7-44-thermal-drivers-mediatek-Fix-probe-for-THERMAL_V2.patch new file mode 100644 index 0000000000..88f383c4ae --- /dev/null +++ b/lede/target/linux/mediatek/patches-6.1/830-v6.7-44-thermal-drivers-mediatek-Fix-probe-for-THERMAL_V2.patch @@ -0,0 +1,33 @@ +From e6f43063f2fe9f08b34797bc6d223f7d63b01910 Mon Sep 17 00:00:00 2001 +From: Markus Schneider-Pargmann +Date: Mon, 18 Sep 2023 12:07:06 +0200 +Subject: [PATCH 39/42] thermal/drivers/mediatek: Fix probe for THERMAL_V2 + +Fix the probe function to call mtk_thermal_release_periodic_ts for +everything != MTK_THERMAL_V1. This was accidentally changed from V1 +to V2 in the original patch. + +Reported-by: Frank Wunderlich +Closes: https://lore.kernel.org/lkml/B0B3775B-B8D1-4284-814F-4F41EC22F532@public-files.de/ +Reported-by: Daniel Lezcano +Closes: https://lore.kernel.org/lkml/07a569b9-e691-64ea-dd65-3b49842af33d@linaro.org/ +Fixes: 33140e668b10 ("thermal/drivers/mediatek: Control buffer enablement tweaks") +Signed-off-by: Markus Schneider-Pargmann +Reviewed-by: AngeloGioacchino Del Regno +Signed-off-by: Daniel Lezcano +Link: https://lore.kernel.org/r/20230918100706.1229239-1-msp@baylibre.com +--- + drivers/thermal/mediatek/auxadc_thermal.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/drivers/thermal/mediatek/auxadc_thermal.c ++++ b/drivers/thermal/mediatek/auxadc_thermal.c +@@ -1268,7 +1268,7 @@ static int mtk_thermal_probe(struct plat + + mtk_thermal_turn_on_buffer(mt, apmixed_base); + +- if (mt->conf->version != MTK_THERMAL_V2) ++ if (mt->conf->version != MTK_THERMAL_V1) + mtk_thermal_release_periodic_ts(mt, auxadc_base); + + if (mt->conf->version == MTK_THERMAL_V1) diff --git a/lede/target/linux/mediatek/patches-6.1/830-v6.7-45-thermal-drivers-mediatek-lvts_thermal-Add-suspend-an.patch b/lede/target/linux/mediatek/patches-6.1/830-v6.7-45-thermal-drivers-mediatek-lvts_thermal-Add-suspend-an.patch new file mode 100644 index 0000000000..7b4b124b56 --- /dev/null +++ b/lede/target/linux/mediatek/patches-6.1/830-v6.7-45-thermal-drivers-mediatek-lvts_thermal-Add-suspend-an.patch @@ -0,0 +1,83 @@ +From a1d874ef3376295ee8ed89b3b5315f4c840ff00b Mon Sep 17 00:00:00 2001 +From: Balsam CHIHI +Date: Tue, 17 Oct 2023 21:05:42 +0200 +Subject: [PATCH 40/42] thermal/drivers/mediatek/lvts_thermal: Add suspend and + resume +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Add suspend and resume support to LVTS driver. + +Signed-off-by: Balsam CHIHI +[bero@baylibre.com: suspend/resume in noirq phase] +Co-developed-by: Bernhard Rosenkränzer +Signed-off-by: Bernhard Rosenkränzer +Reviewed-by: Matthias Brugger +Reviewed-by: Alexandre Mergnat +Reviewed-by: AngeloGioacchino Del Regno +Signed-off-by: Daniel Lezcano +Link: https://lore.kernel.org/r/20231017190545.157282-3-bero@baylibre.com +--- + drivers/thermal/mediatek/lvts_thermal.c | 37 +++++++++++++++++++++++++ + 1 file changed, 37 insertions(+) + +--- a/drivers/thermal/mediatek/lvts_thermal.c ++++ b/drivers/thermal/mediatek/lvts_thermal.c +@@ -1297,6 +1297,38 @@ static const struct lvts_ctrl_data mt798 + } + }; + ++static int lvts_suspend(struct device *dev) ++{ ++ struct lvts_domain *lvts_td; ++ int i; ++ ++ lvts_td = dev_get_drvdata(dev); ++ ++ for (i = 0; i < lvts_td->num_lvts_ctrl; i++) ++ lvts_ctrl_set_enable(&lvts_td->lvts_ctrl[i], false); ++ ++ clk_disable_unprepare(lvts_td->clk); ++ ++ return 0; ++} ++ ++static int lvts_resume(struct device *dev) ++{ ++ struct lvts_domain *lvts_td; ++ int i, ret; ++ ++ lvts_td = dev_get_drvdata(dev); ++ ++ ret = clk_prepare_enable(lvts_td->clk); ++ if (ret) ++ return ret; ++ ++ for (i = 0; i < lvts_td->num_lvts_ctrl; i++) ++ lvts_ctrl_set_enable(&lvts_td->lvts_ctrl[i], true); ++ ++ return 0; ++} ++ + static const struct lvts_ctrl_data mt8195_lvts_mcu_data_ctrl[] = { + { + .cal_offset = { 0x04, 0x07 }, +@@ -1405,12 +1437,17 @@ static const struct of_device_id lvts_of + }; + MODULE_DEVICE_TABLE(of, lvts_of_match); + ++static const struct dev_pm_ops lvts_pm_ops = { ++ NOIRQ_SYSTEM_SLEEP_PM_OPS(lvts_suspend, lvts_resume) ++}; ++ + static struct platform_driver lvts_driver = { + .probe = lvts_probe, + .remove_new = lvts_remove, + .driver = { + .name = "mtk-lvts-thermal", + .of_match_table = lvts_of_match, ++ .pm = &lvts_pm_ops, + }, + }; + module_platform_driver(lvts_driver); diff --git a/lede/target/linux/mediatek/patches-6.1/830-v6.7-46-dt-bindings-thermal-mediatek-Add-LVTS-thermal-contro.patch b/lede/target/linux/mediatek/patches-6.1/830-v6.7-46-dt-bindings-thermal-mediatek-Add-LVTS-thermal-contro.patch new file mode 100644 index 0000000000..c278168610 --- /dev/null +++ b/lede/target/linux/mediatek/patches-6.1/830-v6.7-46-dt-bindings-thermal-mediatek-Add-LVTS-thermal-contro.patch @@ -0,0 +1,49 @@ +From 0bb4937b58ab712f158588376dbac97f8e9df68e Mon Sep 17 00:00:00 2001 +From: Balsam CHIHI +Date: Tue, 17 Oct 2023 21:05:41 +0200 +Subject: [PATCH] dt-bindings: thermal: mediatek: Add LVTS thermal controller + definition for mt8192 +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Add LVTS thermal controller definition for MT8192. + +Signed-off-by: Balsam CHIHI +Reviewed-by: AngeloGioacchino Del Regno +Acked-by: Krzysztof Kozlowski +Signed-off-by: Bernhard Rosenkränzer +Reviewed-by: Matthias Brugger +Reviewed-by: Alexandre Mergnat +Signed-off-by: Daniel Lezcano +Link: https://lore.kernel.org/r/20231017190545.157282-2-bero@baylibre.com +--- + .../thermal/mediatek,lvts-thermal.h | 19 +++++++++++++++++++ + 1 file changed, 19 insertions(+) + +--- a/include/dt-bindings/thermal/mediatek,lvts-thermal.h ++++ b/include/dt-bindings/thermal/mediatek,lvts-thermal.h +@@ -35,4 +35,23 @@ + #define MT8195_AP_CAM0 15 + #define MT8195_AP_CAM1 16 + ++#define MT8192_MCU_BIG_CPU0 0 ++#define MT8192_MCU_BIG_CPU1 1 ++#define MT8192_MCU_BIG_CPU2 2 ++#define MT8192_MCU_BIG_CPU3 3 ++#define MT8192_MCU_LITTLE_CPU0 4 ++#define MT8192_MCU_LITTLE_CPU1 5 ++#define MT8192_MCU_LITTLE_CPU2 6 ++#define MT8192_MCU_LITTLE_CPU3 7 ++ ++#define MT8192_AP_VPU0 8 ++#define MT8192_AP_VPU1 9 ++#define MT8192_AP_GPU0 10 ++#define MT8192_AP_GPU1 11 ++#define MT8192_AP_INFRA 12 ++#define MT8192_AP_CAM 13 ++#define MT8192_AP_MD0 14 ++#define MT8192_AP_MD1 15 ++#define MT8192_AP_MD2 16 ++ + #endif /* __MEDIATEK_LVTS_DT_H */ diff --git a/lede/target/linux/mediatek/patches-6.1/830-v6.7-47-thermal-drivers-mediatek-lvts_thermal-Add-mt8192-sup.patch b/lede/target/linux/mediatek/patches-6.1/830-v6.7-47-thermal-drivers-mediatek-lvts_thermal-Add-mt8192-sup.patch new file mode 100644 index 0000000000..6d68a6cd57 --- /dev/null +++ b/lede/target/linux/mediatek/patches-6.1/830-v6.7-47-thermal-drivers-mediatek-lvts_thermal-Add-mt8192-sup.patch @@ -0,0 +1,151 @@ +From 7d8b3864b38d881cf105328ff8569f47446811ad Mon Sep 17 00:00:00 2001 +From: Balsam CHIHI +Date: Tue, 17 Oct 2023 21:05:43 +0200 +Subject: [PATCH 41/42] thermal/drivers/mediatek/lvts_thermal: Add mt8192 + support +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Add LVTS Driver support for MT8192. + +Co-developed-by: Nícolas F. R. A. Prado +Signed-off-by: Nícolas F. R. A. Prado +Signed-off-by: Balsam CHIHI +Reviewed-by: Nícolas F. R. A. Prado +[bero@baylibre.com: cosmetic changes, rebase] +Signed-off-by: Bernhard Rosenkränzer +Reviewed-by: Matthias Brugger +Reviewed-by: Alexandre Mergnat +Reviewed-by: AngeloGioacchino Del Regno +Signed-off-by: Daniel Lezcano +Link: https://lore.kernel.org/r/20231017190545.157282-4-bero@baylibre.com +--- + drivers/thermal/mediatek/lvts_thermal.c | 95 +++++++++++++++++++++++++ + 1 file changed, 95 insertions(+) + +--- a/drivers/thermal/mediatek/lvts_thermal.c ++++ b/drivers/thermal/mediatek/lvts_thermal.c +@@ -92,6 +92,7 @@ + #define LVTS_MSR_READ_WAIT_US (LVTS_MSR_READ_TIMEOUT_US / 2) + + #define LVTS_HW_SHUTDOWN_MT7988 105000 ++#define LVTS_HW_SHUTDOWN_MT8192 105000 + #define LVTS_HW_SHUTDOWN_MT8195 105000 + + #define LVTS_MINIMUM_THRESHOLD 20000 +@@ -1329,6 +1330,88 @@ static int lvts_resume(struct device *de + return 0; + } + ++static const struct lvts_ctrl_data mt8192_lvts_mcu_data_ctrl[] = { ++ { ++ .cal_offset = { 0x04, 0x08 }, ++ .lvts_sensor = { ++ { .dt_id = MT8192_MCU_BIG_CPU0 }, ++ { .dt_id = MT8192_MCU_BIG_CPU1 } ++ }, ++ .num_lvts_sensor = 2, ++ .offset = 0x0, ++ .hw_tshut_temp = LVTS_HW_SHUTDOWN_MT8192, ++ .mode = LVTS_MSR_FILTERED_MODE, ++ }, ++ { ++ .cal_offset = { 0x0c, 0x10 }, ++ .lvts_sensor = { ++ { .dt_id = MT8192_MCU_BIG_CPU2 }, ++ { .dt_id = MT8192_MCU_BIG_CPU3 } ++ }, ++ .num_lvts_sensor = 2, ++ .offset = 0x100, ++ .hw_tshut_temp = LVTS_HW_SHUTDOWN_MT8192, ++ .mode = LVTS_MSR_FILTERED_MODE, ++ }, ++ { ++ .cal_offset = { 0x14, 0x18, 0x1c, 0x20 }, ++ .lvts_sensor = { ++ { .dt_id = MT8192_MCU_LITTLE_CPU0 }, ++ { .dt_id = MT8192_MCU_LITTLE_CPU1 }, ++ { .dt_id = MT8192_MCU_LITTLE_CPU2 }, ++ { .dt_id = MT8192_MCU_LITTLE_CPU3 } ++ }, ++ .num_lvts_sensor = 4, ++ .offset = 0x200, ++ .hw_tshut_temp = LVTS_HW_SHUTDOWN_MT8192, ++ .mode = LVTS_MSR_FILTERED_MODE, ++ } ++}; ++ ++static const struct lvts_ctrl_data mt8192_lvts_ap_data_ctrl[] = { ++ { ++ .cal_offset = { 0x24, 0x28 }, ++ .lvts_sensor = { ++ { .dt_id = MT8192_AP_VPU0 }, ++ { .dt_id = MT8192_AP_VPU1 } ++ }, ++ .num_lvts_sensor = 2, ++ .offset = 0x0, ++ .hw_tshut_temp = LVTS_HW_SHUTDOWN_MT8192, ++ }, ++ { ++ .cal_offset = { 0x2c, 0x30 }, ++ .lvts_sensor = { ++ { .dt_id = MT8192_AP_GPU0 }, ++ { .dt_id = MT8192_AP_GPU1 } ++ }, ++ .num_lvts_sensor = 2, ++ .offset = 0x100, ++ .hw_tshut_temp = LVTS_HW_SHUTDOWN_MT8192, ++ }, ++ { ++ .cal_offset = { 0x34, 0x38 }, ++ .lvts_sensor = { ++ { .dt_id = MT8192_AP_INFRA }, ++ { .dt_id = MT8192_AP_CAM }, ++ }, ++ .num_lvts_sensor = 2, ++ .offset = 0x200, ++ .hw_tshut_temp = LVTS_HW_SHUTDOWN_MT8192, ++ }, ++ { ++ .cal_offset = { 0x3c, 0x40, 0x44 }, ++ .lvts_sensor = { ++ { .dt_id = MT8192_AP_MD0 }, ++ { .dt_id = MT8192_AP_MD1 }, ++ { .dt_id = MT8192_AP_MD2 } ++ }, ++ .num_lvts_sensor = 3, ++ .offset = 0x300, ++ .hw_tshut_temp = LVTS_HW_SHUTDOWN_MT8192, ++ } ++}; ++ + static const struct lvts_ctrl_data mt8195_lvts_mcu_data_ctrl[] = { + { + .cal_offset = { 0x04, 0x07 }, +@@ -1415,6 +1498,16 @@ static const struct lvts_data mt7988_lvt + .temp_offset = LVTS_COEFF_B_MT7988, + }; + ++static const struct lvts_data mt8192_lvts_mcu_data = { ++ .lvts_ctrl = mt8192_lvts_mcu_data_ctrl, ++ .num_lvts_ctrl = ARRAY_SIZE(mt8192_lvts_mcu_data_ctrl), ++}; ++ ++static const struct lvts_data mt8192_lvts_ap_data = { ++ .lvts_ctrl = mt8192_lvts_ap_data_ctrl, ++ .num_lvts_ctrl = ARRAY_SIZE(mt8192_lvts_ap_data_ctrl), ++}; ++ + static const struct lvts_data mt8195_lvts_mcu_data = { + .lvts_ctrl = mt8195_lvts_mcu_data_ctrl, + .num_lvts_ctrl = ARRAY_SIZE(mt8195_lvts_mcu_data_ctrl), +@@ -1431,6 +1524,8 @@ static const struct lvts_data mt8195_lvt + + static const struct of_device_id lvts_of_match[] = { + { .compatible = "mediatek,mt7988-lvts-ap", .data = &mt7988_lvts_ap_data }, ++ { .compatible = "mediatek,mt8192-lvts-mcu", .data = &mt8192_lvts_mcu_data }, ++ { .compatible = "mediatek,mt8192-lvts-ap", .data = &mt8192_lvts_ap_data }, + { .compatible = "mediatek,mt8195-lvts-mcu", .data = &mt8195_lvts_mcu_data }, + { .compatible = "mediatek,mt8195-lvts-ap", .data = &mt8195_lvts_ap_data }, + {}, diff --git a/lede/target/linux/mediatek/patches-6.1/830-v6.7-48-thermal-drivers-mediatek-lvts_thermal-Update-calibra.patch b/lede/target/linux/mediatek/patches-6.1/830-v6.7-48-thermal-drivers-mediatek-lvts_thermal-Update-calibra.patch new file mode 100644 index 0000000000..c20c0b5f2e --- /dev/null +++ b/lede/target/linux/mediatek/patches-6.1/830-v6.7-48-thermal-drivers-mediatek-lvts_thermal-Update-calibra.patch @@ -0,0 +1,70 @@ +From 5d126a3c87cf7964b28bacf3826eea4266265bce Mon Sep 17 00:00:00 2001 +From: Balsam CHIHI +Date: Tue, 17 Oct 2023 21:05:45 +0200 +Subject: [PATCH 42/42] thermal/drivers/mediatek/lvts_thermal: Update + calibration data documentation +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Update LVTS calibration data documentation for mt8192 and mt8195. + +Signed-off-by: Balsam CHIHI +Reviewed-by: Nícolas F. R. A. Prado +[bero@baylibre.com: Fix issues pointed out by Nícolas F. R. A. Prado ] +Signed-off-by: Bernhard Rosenkränzer +Reviewed-by: AngeloGioacchino Del Regno +Reviewed-by: Alexandre Mergnat +Signed-off-by: Daniel Lezcano +Link: https://lore.kernel.org/r/20231017190545.157282-6-bero@baylibre.com +--- + drivers/thermal/mediatek/lvts_thermal.c | 31 +++++++++++++++++++++++-- + 1 file changed, 29 insertions(+), 2 deletions(-) + +--- a/drivers/thermal/mediatek/lvts_thermal.c ++++ b/drivers/thermal/mediatek/lvts_thermal.c +@@ -616,7 +616,34 @@ static int lvts_sensor_init(struct devic + * The efuse blob values follows the sensor enumeration per thermal + * controller. The decoding of the stream is as follow: + * +- * stream index map for MCU Domain : ++ * MT8192 : ++ * Stream index map for MCU Domain mt8192 : ++ * ++ * <-----mcu-tc#0-----> <-----sensor#0-----> <-----sensor#1-----> ++ * 0x01 | 0x02 | 0x03 | 0x04 | 0x05 | 0x06 | 0x07 | 0x08 | 0x09 | 0x0A | 0x0B ++ * ++ * <-----sensor#2-----> <-----sensor#3-----> ++ * 0x0C | 0x0D | 0x0E | 0x0F | 0x10 | 0x11 | 0x12 | 0x13 ++ * ++ * <-----sensor#4-----> <-----sensor#5-----> <-----sensor#6-----> <-----sensor#7-----> ++ * 0x14 | 0x15 | 0x16 | 0x17 | 0x18 | 0x19 | 0x1A | 0x1B | 0x1C | 0x1D | 0x1E | 0x1F | 0x20 | 0x21 | 0x22 | 0x23 ++ * ++ * Stream index map for AP Domain mt8192 : ++ * ++ * <-----sensor#0-----> <-----sensor#1-----> ++ * 0x24 | 0x25 | 0x26 | 0x27 | 0x28 | 0x29 | 0x2A | 0x2B ++ * ++ * <-----sensor#2-----> <-----sensor#3-----> ++ * 0x2C | 0x2D | 0x2E | 0x2F | 0x30 | 0x31 | 0x32 | 0x33 ++ * ++ * <-----sensor#4-----> <-----sensor#5-----> ++ * 0x34 | 0x35 | 0x36 | 0x37 | 0x38 | 0x39 | 0x3A | 0x3B ++ * ++ * <-----sensor#6-----> <-----sensor#7-----> <-----sensor#8-----> ++ * 0x3C | 0x3D | 0x3E | 0x3F | 0x40 | 0x41 | 0x42 | 0x43 | 0x44 | 0x45 | 0x46 | 0x47 ++ * ++ * MT8195 : ++ * Stream index map for MCU Domain mt8195 : + * + * <-----mcu-tc#0-----> <-----sensor#0-----> <-----sensor#1-----> + * 0x01 | 0x02 | 0x03 | 0x04 | 0x05 | 0x06 | 0x07 | 0x08 | 0x09 +@@ -627,7 +654,7 @@ static int lvts_sensor_init(struct devic + * <-----mcu-tc#2-----> <-----sensor#4-----> <-----sensor#5-----> <-----sensor#6-----> <-----sensor#7-----> + * 0x13 | 0x14 | 0x15 | 0x16 | 0x17 | 0x18 | 0x19 | 0x1A | 0x1B | 0x1C | 0x1D | 0x1E | 0x1F | 0x20 | 0x21 + * +- * stream index map for AP Domain : ++ * Stream index map for AP Domain mt8195 : + * + * <-----ap--tc#0-----> <-----sensor#0-----> <-----sensor#1-----> + * 0x22 | 0x23 | 0x24 | 0x25 | 0x26 | 0x27 | 0x28 | 0x29 | 0x2A diff --git a/lede/target/linux/mediatek/patches-6.1/831-thermal-drivers-mediatek-Fix-control-buffer-enablement-on-MT7896.patch b/lede/target/linux/mediatek/patches-6.1/831-thermal-drivers-mediatek-Fix-control-buffer-enablement-on-MT7896.patch new file mode 100644 index 0000000000..fc173646e0 --- /dev/null +++ b/lede/target/linux/mediatek/patches-6.1/831-thermal-drivers-mediatek-Fix-control-buffer-enablement-on-MT7896.patch @@ -0,0 +1,59 @@ +From patchwork Thu Sep 7 11:20:18 2023 +Content-Type: text/plain; charset="utf-8" +MIME-Version: 1.0 +Content-Transfer-Encoding: 7bit +X-Patchwork-Submitter: Frank Wunderlich +X-Patchwork-Id: 13376356 +From: Frank Wunderlich +To: linux-mediatek@lists.infradead.org +Subject: [PATCH] thermal/drivers/mediatek: Fix control buffer enablement on + MT7896 +Date: Thu, 7 Sep 2023 13:20:18 +0200 +Message-Id: <20230907112018.52811-1-linux@fw-web.de> +X-Mailer: git-send-email 2.34.1 +MIME-Version: 1.0 +X-Mail-ID: e7eeb8e1-00de-41f6-a5df-ce2e9164136e +X-BeenThere: linux-mediatek@lists.infradead.org +X-Mailman-Version: 2.1.34 +Precedence: list +List-Id: +Cc: Daniel Lezcano , + "Rafael J. Wysocki" , linux-pm@vger.kernel.org, + Amit Kucheria , Daniel Golle , + stable@vger.kernel.org, linux-kernel@vger.kernel.org, + Matthias Brugger , Zhang Rui , + linux-arm-kernel@lists.infradead.org, + AngeloGioacchino Del Regno +Sender: "Linux-mediatek" + +From: Frank Wunderlich + +Reading thermal sensor on mt7986 devices returns invalid temperature: + +bpi-r3 ~ # cat /sys/class/thermal/thermal_zone0/temp + -274000 + +Fix this by adding missing members in mtk_thermal_data struct which were +used in mtk_thermal_turn_on_buffer after commit 33140e668b10. + +Cc: stable@vger.kernel.org +Fixes: 33140e668b10 ("thermal/drivers/mediatek: Control buffer enablement tweaks") +Signed-off-by: Frank Wunderlich +Reviewed-by: AngeloGioacchino Del Regno +Reviewed-by: Markus Schneider-Pargmann +--- + drivers/thermal/mediatek/auxadc_thermal.c | 3 +++ + 1 file changed, 3 insertions(+) + +--- a/drivers/thermal/mediatek/auxadc_thermal.c ++++ b/drivers/thermal/mediatek/auxadc_thermal.c +@@ -691,6 +691,9 @@ static const struct mtk_thermal_data mt7 + .adcpnp = mt7986_adcpnp, + .sensor_mux_values = mt7986_mux_values, + .version = MTK_THERMAL_V3, ++ .apmixed_buffer_ctl_reg = APMIXED_SYS_TS_CON1, ++ .apmixed_buffer_ctl_mask = GENMASK(31, 6) | BIT(3), ++ .apmixed_buffer_ctl_set = BIT(0), + }; + + static bool mtk_thermal_temp_is_valid(int temp) diff --git a/lede/target/linux/mediatek/patches-6.1/855-i2c-mt65xx-allow-optional-pmic-clock.patch b/lede/target/linux/mediatek/patches-6.1/855-i2c-mt65xx-allow-optional-pmic-clock.patch new file mode 100644 index 0000000000..69cc155d8d --- /dev/null +++ b/lede/target/linux/mediatek/patches-6.1/855-i2c-mt65xx-allow-optional-pmic-clock.patch @@ -0,0 +1,45 @@ +From 3bf827929a44c17bfb1bf1000b143c02ce26a929 Mon Sep 17 00:00:00 2001 +From: Daniel Golle +Date: Sat, 26 Aug 2023 21:56:51 +0100 +Subject: [PATCH] i2c: mt65xx: allow optional pmic clock + +Using the I2C host controller on the MT7981 SoC requires 4 clocks to +be enabled. One of them, the pmic clk, is only enabled in case +'mediatek,have-pmic' is also set which has other consequences which +are not desired in this case. + +Allow defining a pmic clk even in case the 'mediatek,have-pmic' propterty +is not present and the bus is not used to connect to a pmic, but may +still require to enable the pmic clock. + +Signed-off-by: Daniel Golle +--- + drivers/i2c/busses/i2c-mt65xx.c | 12 ++++++++---- + 1 file changed, 8 insertions(+), 4 deletions(-) + +--- a/drivers/i2c/busses/i2c-mt65xx.c ++++ b/drivers/i2c/busses/i2c-mt65xx.c +@@ -1444,15 +1444,19 @@ static int mtk_i2c_probe(struct platform + if (IS_ERR(i2c->clocks[I2C_MT65XX_CLK_ARB].clk)) + return PTR_ERR(i2c->clocks[I2C_MT65XX_CLK_ARB].clk); + ++ i2c->clocks[I2C_MT65XX_CLK_PMIC].clk = devm_clk_get_optional(&pdev->dev, "pmic"); ++ if (IS_ERR(i2c->clocks[I2C_MT65XX_CLK_PMIC].clk)) { ++ dev_err(&pdev->dev, "cannot get pmic clock\n"); ++ return PTR_ERR(i2c->clocks[I2C_MT65XX_CLK_PMIC].clk); ++ } ++ + if (i2c->have_pmic) { +- i2c->clocks[I2C_MT65XX_CLK_PMIC].clk = devm_clk_get(&pdev->dev, "pmic"); +- if (IS_ERR(i2c->clocks[I2C_MT65XX_CLK_PMIC].clk)) { ++ if (!i2c->clocks[I2C_MT65XX_CLK_PMIC].clk) { + dev_err(&pdev->dev, "cannot get pmic clock\n"); +- return PTR_ERR(i2c->clocks[I2C_MT65XX_CLK_PMIC].clk); ++ return -ENODEV; + } + speed_clk = I2C_MT65XX_CLK_PMIC; + } else { +- i2c->clocks[I2C_MT65XX_CLK_PMIC].clk = NULL; + speed_clk = I2C_MT65XX_CLK_MAIN; + } + diff --git a/lede/target/linux/mediatek/patches-6.1/860-v6.6-01-ASoC-mediatek-mt7986-add-common-header.patch b/lede/target/linux/mediatek/patches-6.1/860-v6.6-01-ASoC-mediatek-mt7986-add-common-header.patch new file mode 100644 index 0000000000..9607eec821 --- /dev/null +++ b/lede/target/linux/mediatek/patches-6.1/860-v6.6-01-ASoC-mediatek-mt7986-add-common-header.patch @@ -0,0 +1,269 @@ +From d35469096915f2551ed1d26da1ab12ff500fc963 Mon Sep 17 00:00:00 2001 +From: Maso Huang +Date: Thu, 17 Aug 2023 18:13:33 +0800 +Subject: [PATCH 1/9] ASoC: mediatek: mt7986: add common header + +Add header files for register definition and structure. + +Signed-off-by: Maso Huang +Reviewed-by: AngeloGioacchino Del Regno +Link: https://lore.kernel.org/r/20230817101338.18782-2-maso.huang@mediatek.com +Signed-off-by: Mark Brown +--- + sound/soc/mediatek/mt7986/mt7986-afe-common.h | 49 +++++ + sound/soc/mediatek/mt7986/mt7986-reg.h | 196 ++++++++++++++++++ + 2 files changed, 245 insertions(+) + create mode 100644 sound/soc/mediatek/mt7986/mt7986-afe-common.h + create mode 100644 sound/soc/mediatek/mt7986/mt7986-reg.h + +--- /dev/null ++++ b/sound/soc/mediatek/mt7986/mt7986-afe-common.h +@@ -0,0 +1,49 @@ ++/* SPDX-License-Identifier: GPL-2.0 */ ++/* ++ * mt7986-afe-common.h -- MediaTek 7986 audio driver definitions ++ * ++ * Copyright (c) 2023 MediaTek Inc. ++ * Authors: Vic Wu ++ * Maso Huang ++ */ ++ ++#ifndef _MT_7986_AFE_COMMON_H_ ++#define _MT_7986_AFE_COMMON_H_ ++ ++#include ++#include ++#include ++#include ++#include "../common/mtk-base-afe.h" ++ ++enum { ++ MT7986_MEMIF_DL1, ++ MT7986_MEMIF_VUL12, ++ MT7986_MEMIF_NUM, ++ MT7986_DAI_ETDM = MT7986_MEMIF_NUM, ++ MT7986_DAI_NUM, ++}; ++ ++enum { ++ MT7986_IRQ_0, ++ MT7986_IRQ_1, ++ MT7986_IRQ_2, ++ MT7986_IRQ_NUM, ++}; ++ ++struct mt7986_afe_private { ++ struct clk_bulk_data *clks; ++ int num_clks; ++ ++ int pm_runtime_bypass_reg_ctl; ++ ++ /* dai */ ++ void *dai_priv[MT7986_DAI_NUM]; ++}; ++ ++unsigned int mt7986_afe_rate_transform(struct device *dev, ++ unsigned int rate); ++ ++/* dai register */ ++int mt7986_dai_etdm_register(struct mtk_base_afe *afe); ++#endif +--- /dev/null ++++ b/sound/soc/mediatek/mt7986/mt7986-reg.h +@@ -0,0 +1,196 @@ ++/* SPDX-License-Identifier: GPL-2.0 */ ++/* ++ * mt7986-reg.h -- MediaTek 7986 audio driver reg definition ++ * ++ * Copyright (c) 2023 MediaTek Inc. ++ * Authors: Vic Wu ++ * Maso Huang ++ */ ++ ++#ifndef _MT7986_REG_H_ ++#define _MT7986_REG_H_ ++ ++#define AUDIO_TOP_CON2 0x0008 ++#define AUDIO_TOP_CON4 0x0010 ++#define AUDIO_ENGEN_CON0 0x0014 ++#define AFE_IRQ_MCU_EN 0x0100 ++#define AFE_IRQ_MCU_STATUS 0x0120 ++#define AFE_IRQ_MCU_CLR 0x0128 ++#define AFE_IRQ0_MCU_CFG0 0x0140 ++#define AFE_IRQ0_MCU_CFG1 0x0144 ++#define AFE_IRQ1_MCU_CFG0 0x0148 ++#define AFE_IRQ1_MCU_CFG1 0x014c ++#define AFE_IRQ2_MCU_CFG0 0x0150 ++#define AFE_IRQ2_MCU_CFG1 0x0154 ++#define ETDM_IN5_CON0 0x13f0 ++#define ETDM_IN5_CON1 0x13f4 ++#define ETDM_IN5_CON2 0x13f8 ++#define ETDM_IN5_CON3 0x13fc ++#define ETDM_IN5_CON4 0x1400 ++#define ETDM_OUT5_CON0 0x1570 ++#define ETDM_OUT5_CON4 0x1580 ++#define ETDM_OUT5_CON5 0x1584 ++#define ETDM_4_7_COWORK_CON0 0x15e0 ++#define ETDM_4_7_COWORK_CON1 0x15e4 ++#define AFE_CONN018_1 0x1b44 ++#define AFE_CONN018_4 0x1b50 ++#define AFE_CONN019_1 0x1b64 ++#define AFE_CONN019_4 0x1b70 ++#define AFE_CONN124_1 0x2884 ++#define AFE_CONN124_4 0x2890 ++#define AFE_CONN125_1 0x28a4 ++#define AFE_CONN125_4 0x28b0 ++#define AFE_CONN_RS_0 0x3920 ++#define AFE_CONN_RS_3 0x392c ++#define AFE_CONN_16BIT_0 0x3960 ++#define AFE_CONN_16BIT_3 0x396c ++#define AFE_CONN_24BIT_0 0x3980 ++#define AFE_CONN_24BIT_3 0x398c ++#define AFE_MEMIF_CON0 0x3d98 ++#define AFE_MEMIF_RD_MON 0x3da0 ++#define AFE_MEMIF_WR_MON 0x3da4 ++#define AFE_DL0_BASE_MSB 0x3e40 ++#define AFE_DL0_BASE 0x3e44 ++#define AFE_DL0_CUR_MSB 0x3e48 ++#define AFE_DL0_CUR 0x3e4c ++#define AFE_DL0_END_MSB 0x3e50 ++#define AFE_DL0_END 0x3e54 ++#define AFE_DL0_RCH_MON 0x3e58 ++#define AFE_DL0_LCH_MON 0x3e5c ++#define AFE_DL0_CON0 0x3e60 ++#define AFE_VUL0_BASE_MSB 0x4220 ++#define AFE_VUL0_BASE 0x4224 ++#define AFE_VUL0_CUR_MSB 0x4228 ++#define AFE_VUL0_CUR 0x422c ++#define AFE_VUL0_END_MSB 0x4230 ++#define AFE_VUL0_END 0x4234 ++#define AFE_VUL0_CON0 0x4238 ++ ++#define AFE_MAX_REGISTER AFE_VUL0_CON0 ++#define AFE_IRQ_STATUS_BITS 0x7 ++#define AFE_IRQ_CNT_SHIFT 0 ++#define AFE_IRQ_CNT_MASK 0xffffff ++ ++/* AUDIO_TOP_CON2 */ ++#define CLK_OUT5_PDN BIT(14) ++#define CLK_OUT5_PDN_MASK BIT(14) ++#define CLK_IN5_PDN BIT(7) ++#define CLK_IN5_PDN_MASK BIT(7) ++ ++/* AUDIO_TOP_CON4 */ ++#define PDN_APLL_TUNER2 BIT(12) ++#define PDN_APLL_TUNER2_MASK BIT(12) ++ ++/* AUDIO_ENGEN_CON0 */ ++#define AUD_APLL2_EN BIT(3) ++#define AUD_APLL2_EN_MASK BIT(3) ++#define AUD_26M_EN BIT(0) ++#define AUD_26M_EN_MASK BIT(0) ++ ++/* AFE_DL0_CON0 */ ++#define DL0_ON_SFT 28 ++#define DL0_ON_MASK 0x1 ++#define DL0_ON_MASK_SFT BIT(28) ++#define DL0_MINLEN_SFT 20 ++#define DL0_MINLEN_MASK 0xf ++#define DL0_MINLEN_MASK_SFT (0xf << 20) ++#define DL0_MODE_SFT 8 ++#define DL0_MODE_MASK 0x1f ++#define DL0_MODE_MASK_SFT (0x1f << 8) ++#define DL0_PBUF_SIZE_SFT 5 ++#define DL0_PBUF_SIZE_MASK 0x3 ++#define DL0_PBUF_SIZE_MASK_SFT (0x3 << 5) ++#define DL0_MONO_SFT 4 ++#define DL0_MONO_MASK 0x1 ++#define DL0_MONO_MASK_SFT BIT(4) ++#define DL0_HALIGN_SFT 2 ++#define DL0_HALIGN_MASK 0x1 ++#define DL0_HALIGN_MASK_SFT BIT(2) ++#define DL0_HD_MODE_SFT 0 ++#define DL0_HD_MODE_MASK 0x3 ++#define DL0_HD_MODE_MASK_SFT (0x3 << 0) ++ ++/* AFE_VUL0_CON0 */ ++#define VUL0_ON_SFT 28 ++#define VUL0_ON_MASK 0x1 ++#define VUL0_ON_MASK_SFT BIT(28) ++#define VUL0_MODE_SFT 8 ++#define VUL0_MODE_MASK 0x1f ++#define VUL0_MODE_MASK_SFT (0x1f << 8) ++#define VUL0_MONO_SFT 4 ++#define VUL0_MONO_MASK 0x1 ++#define VUL0_MONO_MASK_SFT BIT(4) ++#define VUL0_HALIGN_SFT 2 ++#define VUL0_HALIGN_MASK 0x1 ++#define VUL0_HALIGN_MASK_SFT BIT(2) ++#define VUL0_HD_MODE_SFT 0 ++#define VUL0_HD_MODE_MASK 0x3 ++#define VUL0_HD_MODE_MASK_SFT (0x3 << 0) ++ ++/* AFE_IRQ_MCU_CON */ ++#define IRQ_MCU_MODE_SFT 4 ++#define IRQ_MCU_MODE_MASK 0x1f ++#define IRQ_MCU_MODE_MASK_SFT (0x1f << 4) ++#define IRQ_MCU_ON_SFT 0 ++#define IRQ_MCU_ON_MASK 0x1 ++#define IRQ_MCU_ON_MASK_SFT BIT(0) ++#define IRQ0_MCU_CLR_SFT 0 ++#define IRQ0_MCU_CLR_MASK 0x1 ++#define IRQ0_MCU_CLR_MASK_SFT BIT(0) ++#define IRQ1_MCU_CLR_SFT 1 ++#define IRQ1_MCU_CLR_MASK 0x1 ++#define IRQ1_MCU_CLR_MASK_SFT BIT(1) ++#define IRQ2_MCU_CLR_SFT 2 ++#define IRQ2_MCU_CLR_MASK 0x1 ++#define IRQ2_MCU_CLR_MASK_SFT BIT(2) ++ ++/* ETDM_IN5_CON2 */ ++#define IN_CLK_SRC(x) ((x) << 10) ++#define IN_CLK_SRC_SFT 10 ++#define IN_CLK_SRC_MASK GENMASK(12, 10) ++ ++/* ETDM_IN5_CON3 */ ++#define IN_SEL_FS(x) ((x) << 26) ++#define IN_SEL_FS_SFT 26 ++#define IN_SEL_FS_MASK GENMASK(30, 26) ++ ++/* ETDM_IN5_CON4 */ ++#define IN_RELATCH(x) ((x) << 20) ++#define IN_RELATCH_SFT 20 ++#define IN_RELATCH_MASK GENMASK(24, 20) ++#define IN_CLK_INV BIT(18) ++#define IN_CLK_INV_MASK BIT(18) ++ ++/* ETDM_IN5_CON0 & ETDM_OUT5_CON0 */ ++#define RELATCH_SRC_MASK GENMASK(30, 28) ++#define ETDM_CH_NUM_MASK GENMASK(27, 23) ++#define ETDM_WRD_LEN_MASK GENMASK(20, 16) ++#define ETDM_BIT_LEN_MASK GENMASK(15, 11) ++#define ETDM_FMT_MASK GENMASK(8, 6) ++#define ETDM_SYNC BIT(1) ++#define ETDM_SYNC_MASK BIT(1) ++#define ETDM_EN BIT(0) ++#define ETDM_EN_MASK BIT(0) ++ ++/* ETDM_OUT5_CON4 */ ++#define OUT_RELATCH(x) ((x) << 24) ++#define OUT_RELATCH_SFT 24 ++#define OUT_RELATCH_MASK GENMASK(28, 24) ++#define OUT_CLK_SRC(x) ((x) << 6) ++#define OUT_CLK_SRC_SFT 6 ++#define OUT_CLK_SRC_MASK GENMASK(8, 6) ++#define OUT_SEL_FS(x) (x) ++#define OUT_SEL_FS_SFT 0 ++#define OUT_SEL_FS_MASK GENMASK(4, 0) ++ ++/* ETDM_OUT5_CON5 */ ++#define ETDM_CLK_DIV BIT(12) ++#define ETDM_CLK_DIV_MASK BIT(12) ++#define OUT_CLK_INV BIT(9) ++#define OUT_CLK_INV_MASK BIT(9) ++ ++/* ETDM_4_7_COWORK_CON0 */ ++#define OUT_SEL(x) ((x) << 12) ++#define OUT_SEL_SFT 12 ++#define OUT_SEL_MASK GENMASK(15, 12) ++#endif diff --git a/lede/target/linux/mediatek/patches-6.1/860-v6.6-02-ASoC-mediatek-mt7986-support-etdm-in-platform-driver.patch b/lede/target/linux/mediatek/patches-6.1/860-v6.6-02-ASoC-mediatek-mt7986-support-etdm-in-platform-driver.patch new file mode 100644 index 0000000000..f22add580f --- /dev/null +++ b/lede/target/linux/mediatek/patches-6.1/860-v6.6-02-ASoC-mediatek-mt7986-support-etdm-in-platform-driver.patch @@ -0,0 +1,430 @@ +From 948a288897015fb3ee63b3f720b396b590c17fd7 Mon Sep 17 00:00:00 2001 +From: Maso Huang +Date: Thu, 17 Aug 2023 18:13:34 +0800 +Subject: [PATCH 2/9] ASoC: mediatek: mt7986: support etdm in platform driver + +Add mt7986 etdm dai driver support. + +Signed-off-by: Maso Huang +Reviewed-by: AngeloGioacchino Del Regno +Link: https://lore.kernel.org/r/20230817101338.18782-3-maso.huang@mediatek.com +Signed-off-by: Mark Brown +--- + sound/soc/mediatek/mt7986/mt7986-dai-etdm.c | 411 ++++++++++++++++++++ + 1 file changed, 411 insertions(+) + create mode 100644 sound/soc/mediatek/mt7986/mt7986-dai-etdm.c + +--- /dev/null ++++ b/sound/soc/mediatek/mt7986/mt7986-dai-etdm.c +@@ -0,0 +1,411 @@ ++// SPDX-License-Identifier: GPL-2.0 ++/* ++ * MediaTek ALSA SoC Audio DAI eTDM Control ++ * ++ * Copyright (c) 2023 MediaTek Inc. ++ * Authors: Vic Wu ++ * Maso Huang ++ */ ++ ++#include ++#include ++#include ++#include ++#include "mt7986-afe-common.h" ++#include "mt7986-reg.h" ++ ++#define HOPPING_CLK 0 ++#define APLL_CLK 1 ++#define MTK_DAI_ETDM_FORMAT_I2S 0 ++#define MTK_DAI_ETDM_FORMAT_DSPA 4 ++#define MTK_DAI_ETDM_FORMAT_DSPB 5 ++ ++enum { ++ MTK_ETDM_RATE_8K = 0, ++ MTK_ETDM_RATE_12K = 1, ++ MTK_ETDM_RATE_16K = 2, ++ MTK_ETDM_RATE_24K = 3, ++ MTK_ETDM_RATE_32K = 4, ++ MTK_ETDM_RATE_48K = 5, ++ MTK_ETDM_RATE_96K = 7, ++ MTK_ETDM_RATE_192K = 9, ++ MTK_ETDM_RATE_11K = 16, ++ MTK_ETDM_RATE_22K = 17, ++ MTK_ETDM_RATE_44K = 18, ++ MTK_ETDM_RATE_88K = 19, ++ MTK_ETDM_RATE_176K = 20, ++}; ++ ++struct mtk_dai_etdm_priv { ++ bool bck_inv; ++ bool lrck_inv; ++ bool slave_mode; ++ unsigned int format; ++}; ++ ++static unsigned int mt7986_etdm_rate_transform(struct device *dev, unsigned int rate) ++{ ++ switch (rate) { ++ case 8000: ++ return MTK_ETDM_RATE_8K; ++ case 11025: ++ return MTK_ETDM_RATE_11K; ++ case 12000: ++ return MTK_ETDM_RATE_12K; ++ case 16000: ++ return MTK_ETDM_RATE_16K; ++ case 22050: ++ return MTK_ETDM_RATE_22K; ++ case 24000: ++ return MTK_ETDM_RATE_24K; ++ case 32000: ++ return MTK_ETDM_RATE_32K; ++ case 44100: ++ return MTK_ETDM_RATE_44K; ++ case 48000: ++ return MTK_ETDM_RATE_48K; ++ case 88200: ++ return MTK_ETDM_RATE_88K; ++ case 96000: ++ return MTK_ETDM_RATE_96K; ++ case 176400: ++ return MTK_ETDM_RATE_176K; ++ case 192000: ++ return MTK_ETDM_RATE_192K; ++ default: ++ dev_warn(dev, "%s(), rate %u invalid, using %d!!!\n", ++ __func__, rate, MTK_ETDM_RATE_48K); ++ return MTK_ETDM_RATE_48K; ++ } ++} ++ ++static int get_etdm_wlen(unsigned int bitwidth) ++{ ++ return bitwidth <= 16 ? 16 : 32; ++} ++ ++/* dai component */ ++/* interconnection */ ++ ++static const struct snd_kcontrol_new o124_mix[] = { ++ SOC_DAPM_SINGLE_AUTODISABLE("I032_Switch", AFE_CONN124_1, 0, 1, 0), ++}; ++ ++static const struct snd_kcontrol_new o125_mix[] = { ++ SOC_DAPM_SINGLE_AUTODISABLE("I033_Switch", AFE_CONN125_1, 1, 1, 0), ++}; ++ ++static const struct snd_soc_dapm_widget mtk_dai_etdm_widgets[] = { ++ ++ /* DL */ ++ SND_SOC_DAPM_MIXER("I150", SND_SOC_NOPM, 0, 0, NULL, 0), ++ SND_SOC_DAPM_MIXER("I151", SND_SOC_NOPM, 0, 0, NULL, 0), ++ /* UL */ ++ SND_SOC_DAPM_MIXER("O124", SND_SOC_NOPM, 0, 0, o124_mix, ARRAY_SIZE(o124_mix)), ++ SND_SOC_DAPM_MIXER("O125", SND_SOC_NOPM, 0, 0, o125_mix, ARRAY_SIZE(o125_mix)), ++}; ++ ++static const struct snd_soc_dapm_route mtk_dai_etdm_routes[] = { ++ {"I150", NULL, "ETDM Capture"}, ++ {"I151", NULL, "ETDM Capture"}, ++ {"ETDM Playback", NULL, "O124"}, ++ {"ETDM Playback", NULL, "O125"}, ++ {"O124", "I032_Switch", "I032"}, ++ {"O125", "I033_Switch", "I033"}, ++}; ++ ++/* dai ops */ ++static int mtk_dai_etdm_startup(struct snd_pcm_substream *substream, ++ struct snd_soc_dai *dai) ++{ ++ struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai); ++ struct mt7986_afe_private *afe_priv = afe->platform_priv; ++ int ret; ++ ++ ret = clk_bulk_prepare_enable(afe_priv->num_clks, afe_priv->clks); ++ if (ret) ++ return dev_err_probe(afe->dev, ret, "Failed to enable clocks\n"); ++ ++ regmap_update_bits(afe->regmap, AUDIO_TOP_CON2, CLK_OUT5_PDN_MASK, 0); ++ regmap_update_bits(afe->regmap, AUDIO_TOP_CON2, CLK_IN5_PDN_MASK, 0); ++ ++ return 0; ++} ++ ++static void mtk_dai_etdm_shutdown(struct snd_pcm_substream *substream, ++ struct snd_soc_dai *dai) ++{ ++ struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai); ++ struct mt7986_afe_private *afe_priv = afe->platform_priv; ++ ++ regmap_update_bits(afe->regmap, AUDIO_TOP_CON2, CLK_OUT5_PDN_MASK, ++ CLK_OUT5_PDN); ++ regmap_update_bits(afe->regmap, AUDIO_TOP_CON2, CLK_IN5_PDN_MASK, ++ CLK_IN5_PDN); ++ ++ clk_bulk_disable_unprepare(afe_priv->num_clks, afe_priv->clks); ++} ++ ++static unsigned int get_etdm_ch_fixup(unsigned int channels) ++{ ++ if (channels > 16) ++ return 24; ++ else if (channels > 8) ++ return 16; ++ else if (channels > 4) ++ return 8; ++ else if (channels > 2) ++ return 4; ++ else ++ return 2; ++} ++ ++static int mtk_dai_etdm_config(struct mtk_base_afe *afe, ++ struct snd_pcm_hw_params *params, ++ struct snd_soc_dai *dai, ++ int stream) ++{ ++ struct mt7986_afe_private *afe_priv = afe->platform_priv; ++ struct mtk_dai_etdm_priv *etdm_data = afe_priv->dai_priv[dai->id]; ++ unsigned int rate = params_rate(params); ++ unsigned int etdm_rate = mt7986_etdm_rate_transform(afe->dev, rate); ++ unsigned int afe_rate = mt7986_afe_rate_transform(afe->dev, rate); ++ unsigned int channels = params_channels(params); ++ unsigned int bit_width = params_width(params); ++ unsigned int wlen = get_etdm_wlen(bit_width); ++ unsigned int val = 0; ++ unsigned int mask = 0; ++ ++ dev_dbg(afe->dev, "%s(), stream %d, rate %u, bitwidth %u\n", ++ __func__, stream, rate, bit_width); ++ ++ /* CON0 */ ++ mask |= ETDM_BIT_LEN_MASK; ++ val |= FIELD_PREP(ETDM_BIT_LEN_MASK, bit_width - 1); ++ mask |= ETDM_WRD_LEN_MASK; ++ val |= FIELD_PREP(ETDM_WRD_LEN_MASK, wlen - 1); ++ mask |= ETDM_FMT_MASK; ++ val |= FIELD_PREP(ETDM_FMT_MASK, etdm_data->format); ++ mask |= ETDM_CH_NUM_MASK; ++ val |= FIELD_PREP(ETDM_CH_NUM_MASK, get_etdm_ch_fixup(channels) - 1); ++ mask |= RELATCH_SRC_MASK; ++ val |= FIELD_PREP(RELATCH_SRC_MASK, APLL_CLK); ++ ++ switch (stream) { ++ case SNDRV_PCM_STREAM_PLAYBACK: ++ /* set ETDM_OUT5_CON0 */ ++ regmap_update_bits(afe->regmap, ETDM_OUT5_CON0, mask, val); ++ ++ /* set ETDM_OUT5_CON4 */ ++ regmap_update_bits(afe->regmap, ETDM_OUT5_CON4, ++ OUT_RELATCH_MASK, OUT_RELATCH(afe_rate)); ++ regmap_update_bits(afe->regmap, ETDM_OUT5_CON4, ++ OUT_CLK_SRC_MASK, OUT_CLK_SRC(APLL_CLK)); ++ regmap_update_bits(afe->regmap, ETDM_OUT5_CON4, ++ OUT_SEL_FS_MASK, OUT_SEL_FS(etdm_rate)); ++ ++ /* set ETDM_OUT5_CON5 */ ++ regmap_update_bits(afe->regmap, ETDM_OUT5_CON5, ++ ETDM_CLK_DIV_MASK, ETDM_CLK_DIV); ++ break; ++ case SNDRV_PCM_STREAM_CAPTURE: ++ /* set ETDM_IN5_CON0 */ ++ regmap_update_bits(afe->regmap, ETDM_IN5_CON0, mask, val); ++ regmap_update_bits(afe->regmap, ETDM_IN5_CON0, ++ ETDM_SYNC_MASK, ETDM_SYNC); ++ ++ /* set ETDM_IN5_CON2 */ ++ regmap_update_bits(afe->regmap, ETDM_IN5_CON2, ++ IN_CLK_SRC_MASK, IN_CLK_SRC(APLL_CLK)); ++ ++ /* set ETDM_IN5_CON3 */ ++ regmap_update_bits(afe->regmap, ETDM_IN5_CON3, ++ IN_SEL_FS_MASK, IN_SEL_FS(etdm_rate)); ++ ++ /* set ETDM_IN5_CON4 */ ++ regmap_update_bits(afe->regmap, ETDM_IN5_CON4, ++ IN_RELATCH_MASK, IN_RELATCH(afe_rate)); ++ break; ++ default: ++ break; ++ } ++ ++ return 0; ++} ++ ++static int mtk_dai_etdm_hw_params(struct snd_pcm_substream *substream, ++ struct snd_pcm_hw_params *params, ++ struct snd_soc_dai *dai) ++{ ++ struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai); ++ ++ mtk_dai_etdm_config(afe, params, dai, SNDRV_PCM_STREAM_PLAYBACK); ++ mtk_dai_etdm_config(afe, params, dai, SNDRV_PCM_STREAM_CAPTURE); ++ ++ return 0; ++} ++ ++static int mtk_dai_etdm_trigger(struct snd_pcm_substream *substream, int cmd, ++ struct snd_soc_dai *dai) ++{ ++ struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai); ++ ++ dev_dbg(afe->dev, "%s(), cmd %d, dai id %d\n", __func__, cmd, dai->id); ++ switch (cmd) { ++ case SNDRV_PCM_TRIGGER_START: ++ case SNDRV_PCM_TRIGGER_RESUME: ++ regmap_update_bits(afe->regmap, ETDM_IN5_CON0, ETDM_EN_MASK, ++ ETDM_EN); ++ regmap_update_bits(afe->regmap, ETDM_OUT5_CON0, ETDM_EN_MASK, ++ ETDM_EN); ++ break; ++ case SNDRV_PCM_TRIGGER_STOP: ++ case SNDRV_PCM_TRIGGER_SUSPEND: ++ regmap_update_bits(afe->regmap, ETDM_IN5_CON0, ETDM_EN_MASK, ++ 0); ++ regmap_update_bits(afe->regmap, ETDM_OUT5_CON0, ETDM_EN_MASK, ++ 0); ++ break; ++ default: ++ break; ++ } ++ ++ return 0; ++} ++ ++static int mtk_dai_etdm_set_fmt(struct snd_soc_dai *dai, unsigned int fmt) ++{ ++ struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai); ++ struct mt7986_afe_private *afe_priv = afe->platform_priv; ++ struct mtk_dai_etdm_priv *etdm_data; ++ void *priv_data; ++ ++ switch (dai->id) { ++ case MT7986_DAI_ETDM: ++ break; ++ default: ++ dev_warn(afe->dev, "%s(), id %d not support\n", ++ __func__, dai->id); ++ return -EINVAL; ++ } ++ ++ priv_data = devm_kzalloc(afe->dev, sizeof(struct mtk_dai_etdm_priv), ++ GFP_KERNEL); ++ if (!priv_data) ++ return -ENOMEM; ++ ++ afe_priv->dai_priv[dai->id] = priv_data; ++ etdm_data = afe_priv->dai_priv[dai->id]; ++ ++ switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { ++ case SND_SOC_DAIFMT_I2S: ++ etdm_data->format = MTK_DAI_ETDM_FORMAT_I2S; ++ break; ++ case SND_SOC_DAIFMT_DSP_A: ++ etdm_data->format = MTK_DAI_ETDM_FORMAT_DSPA; ++ break; ++ case SND_SOC_DAIFMT_DSP_B: ++ etdm_data->format = MTK_DAI_ETDM_FORMAT_DSPB; ++ break; ++ default: ++ return -EINVAL; ++ } ++ ++ switch (fmt & SND_SOC_DAIFMT_INV_MASK) { ++ case SND_SOC_DAIFMT_NB_NF: ++ etdm_data->bck_inv = false; ++ etdm_data->lrck_inv = false; ++ break; ++ case SND_SOC_DAIFMT_NB_IF: ++ etdm_data->bck_inv = false; ++ etdm_data->lrck_inv = true; ++ break; ++ case SND_SOC_DAIFMT_IB_NF: ++ etdm_data->bck_inv = true; ++ etdm_data->lrck_inv = false; ++ break; ++ case SND_SOC_DAIFMT_IB_IF: ++ etdm_data->bck_inv = true; ++ etdm_data->lrck_inv = true; ++ break; ++ default: ++ return -EINVAL; ++ } ++ ++ switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { ++ case SND_SOC_DAIFMT_CBM_CFM: ++ etdm_data->slave_mode = true; ++ break; ++ case SND_SOC_DAIFMT_CBS_CFS: ++ etdm_data->slave_mode = false; ++ break; ++ default: ++ return -EINVAL; ++ } ++ ++ return 0; ++} ++ ++static const struct snd_soc_dai_ops mtk_dai_etdm_ops = { ++ .startup = mtk_dai_etdm_startup, ++ .shutdown = mtk_dai_etdm_shutdown, ++ .hw_params = mtk_dai_etdm_hw_params, ++ .trigger = mtk_dai_etdm_trigger, ++ .set_fmt = mtk_dai_etdm_set_fmt, ++}; ++ ++/* dai driver */ ++#define MTK_ETDM_RATES (SNDRV_PCM_RATE_8000_48000 |\ ++ SNDRV_PCM_RATE_88200 |\ ++ SNDRV_PCM_RATE_96000 |\ ++ SNDRV_PCM_RATE_176400 |\ ++ SNDRV_PCM_RATE_192000) ++ ++#define MTK_ETDM_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\ ++ SNDRV_PCM_FMTBIT_S24_LE |\ ++ SNDRV_PCM_FMTBIT_S32_LE) ++ ++static struct snd_soc_dai_driver mtk_dai_etdm_driver[] = { ++ { ++ .name = "ETDM", ++ .id = MT7986_DAI_ETDM, ++ .capture = { ++ .stream_name = "ETDM Capture", ++ .channels_min = 1, ++ .channels_max = 2, ++ .rates = MTK_ETDM_RATES, ++ .formats = MTK_ETDM_FORMATS, ++ }, ++ .playback = { ++ .stream_name = "ETDM Playback", ++ .channels_min = 1, ++ .channels_max = 2, ++ .rates = MTK_ETDM_RATES, ++ .formats = MTK_ETDM_FORMATS, ++ }, ++ .ops = &mtk_dai_etdm_ops, ++ .symmetric_rate = 1, ++ .symmetric_sample_bits = 1, ++ }, ++}; ++ ++int mt7986_dai_etdm_register(struct mtk_base_afe *afe) ++{ ++ struct mtk_base_afe_dai *dai; ++ ++ dai = devm_kzalloc(afe->dev, sizeof(*dai), GFP_KERNEL); ++ if (!dai) ++ return -ENOMEM; ++ ++ list_add(&dai->list, &afe->sub_dais); ++ ++ dai->dai_drivers = mtk_dai_etdm_driver; ++ dai->num_dai_drivers = ARRAY_SIZE(mtk_dai_etdm_driver); ++ ++ dai->dapm_widgets = mtk_dai_etdm_widgets; ++ dai->num_dapm_widgets = ARRAY_SIZE(mtk_dai_etdm_widgets); ++ dai->dapm_routes = mtk_dai_etdm_routes; ++ dai->num_dapm_routes = ARRAY_SIZE(mtk_dai_etdm_routes); ++ ++ return 0; ++} diff --git a/lede/target/linux/mediatek/patches-6.1/860-v6.6-03-ASoC-mediatek-mt7986-add-platform-driver.patch b/lede/target/linux/mediatek/patches-6.1/860-v6.6-03-ASoC-mediatek-mt7986-add-platform-driver.patch new file mode 100644 index 0000000000..b899b963d2 --- /dev/null +++ b/lede/target/linux/mediatek/patches-6.1/860-v6.6-03-ASoC-mediatek-mt7986-add-platform-driver.patch @@ -0,0 +1,685 @@ +From fc7776dee86bc07d22820a904760a95f49a2f12e Mon Sep 17 00:00:00 2001 +From: Maso Huang +Date: Thu, 17 Aug 2023 18:13:35 +0800 +Subject: [PATCH 3/9] ASoC: mediatek: mt7986: add platform driver + +Add mt7986 platform driver. + +Signed-off-by: Maso Huang +Reviewed-by: AngeloGioacchino Del Regno +Link: https://lore.kernel.org/r/20230817101338.18782-4-maso.huang@mediatek.com +Signed-off-by: Mark Brown +--- + sound/soc/mediatek/Kconfig | 10 + + sound/soc/mediatek/Makefile | 1 + + sound/soc/mediatek/mt7986/Makefile | 8 + + sound/soc/mediatek/mt7986/mt7986-afe-pcm.c | 622 +++++++++++++++++++++ + 4 files changed, 641 insertions(+) + create mode 100644 sound/soc/mediatek/mt7986/Makefile + create mode 100644 sound/soc/mediatek/mt7986/mt7986-afe-pcm.c + +--- a/sound/soc/mediatek/Kconfig ++++ b/sound/soc/mediatek/Kconfig +@@ -54,6 +54,16 @@ config SND_SOC_MT6797_MT6351 + Select Y if you have such device. + If unsure select "N". + ++config SND_SOC_MT7986 ++ tristate "ASoC support for Mediatek MT7986 chip" ++ depends on ARCH_MEDIATEK ++ select SND_SOC_MEDIATEK ++ help ++ This adds ASoC platform driver support for MediaTek MT7986 chip ++ that can be used with other codecs. ++ Select Y if you have such device. ++ If unsure select "N". ++ + config SND_SOC_MT8173 + tristate "ASoC support for Mediatek MT8173 chip" + depends on ARCH_MEDIATEK +--- a/sound/soc/mediatek/Makefile ++++ b/sound/soc/mediatek/Makefile +@@ -2,6 +2,7 @@ + obj-$(CONFIG_SND_SOC_MEDIATEK) += common/ + obj-$(CONFIG_SND_SOC_MT2701) += mt2701/ + obj-$(CONFIG_SND_SOC_MT6797) += mt6797/ ++obj-$(CONFIG_SND_SOC_MT7986) += mt7986/ + obj-$(CONFIG_SND_SOC_MT8173) += mt8173/ + obj-$(CONFIG_SND_SOC_MT8183) += mt8183/ + obj-$(CONFIG_SND_SOC_MT8186) += mt8186/ +--- /dev/null ++++ b/sound/soc/mediatek/mt7986/Makefile +@@ -0,0 +1,8 @@ ++# SPDX-License-Identifier: GPL-2.0 ++ ++# platform driver ++snd-soc-mt7986-afe-objs := \ ++ mt7986-afe-pcm.o \ ++ mt7986-dai-etdm.o ++ ++obj-$(CONFIG_SND_SOC_MT7986) += snd-soc-mt7986-afe.o +--- /dev/null ++++ b/sound/soc/mediatek/mt7986/mt7986-afe-pcm.c +@@ -0,0 +1,622 @@ ++// SPDX-License-Identifier: GPL-2.0 ++/* ++ * MediaTek ALSA SoC AFE platform driver for MT7986 ++ * ++ * Copyright (c) 2023 MediaTek Inc. ++ * Authors: Vic Wu ++ * Maso Huang ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "mt7986-afe-common.h" ++#include "mt7986-reg.h" ++#include "../common/mtk-afe-platform-driver.h" ++#include "../common/mtk-afe-fe-dai.h" ++ ++enum { ++ MTK_AFE_RATE_8K = 0, ++ MTK_AFE_RATE_11K = 1, ++ MTK_AFE_RATE_12K = 2, ++ MTK_AFE_RATE_16K = 4, ++ MTK_AFE_RATE_22K = 5, ++ MTK_AFE_RATE_24K = 6, ++ MTK_AFE_RATE_32K = 8, ++ MTK_AFE_RATE_44K = 9, ++ MTK_AFE_RATE_48K = 10, ++ MTK_AFE_RATE_88K = 13, ++ MTK_AFE_RATE_96K = 14, ++ MTK_AFE_RATE_176K = 17, ++ MTK_AFE_RATE_192K = 18, ++}; ++ ++enum { ++ CLK_INFRA_AUD_BUS_CK = 0, ++ CLK_INFRA_AUD_26M_CK, ++ CLK_INFRA_AUD_L_CK, ++ CLK_INFRA_AUD_AUD_CK, ++ CLK_INFRA_AUD_EG2_CK, ++ CLK_NUM ++}; ++ ++static const char *aud_clks[CLK_NUM] = { ++ [CLK_INFRA_AUD_BUS_CK] = "aud_bus_ck", ++ [CLK_INFRA_AUD_26M_CK] = "aud_26m_ck", ++ [CLK_INFRA_AUD_L_CK] = "aud_l_ck", ++ [CLK_INFRA_AUD_AUD_CK] = "aud_aud_ck", ++ [CLK_INFRA_AUD_EG2_CK] = "aud_eg2_ck", ++}; ++ ++unsigned int mt7986_afe_rate_transform(struct device *dev, unsigned int rate) ++{ ++ switch (rate) { ++ case 8000: ++ return MTK_AFE_RATE_8K; ++ case 11025: ++ return MTK_AFE_RATE_11K; ++ case 12000: ++ return MTK_AFE_RATE_12K; ++ case 16000: ++ return MTK_AFE_RATE_16K; ++ case 22050: ++ return MTK_AFE_RATE_22K; ++ case 24000: ++ return MTK_AFE_RATE_24K; ++ case 32000: ++ return MTK_AFE_RATE_32K; ++ case 44100: ++ return MTK_AFE_RATE_44K; ++ case 48000: ++ return MTK_AFE_RATE_48K; ++ case 88200: ++ return MTK_AFE_RATE_88K; ++ case 96000: ++ return MTK_AFE_RATE_96K; ++ case 176400: ++ return MTK_AFE_RATE_176K; ++ case 192000: ++ return MTK_AFE_RATE_192K; ++ default: ++ dev_warn(dev, "%s(), rate %u invalid, using %d!!!\n", ++ __func__, rate, MTK_AFE_RATE_48K); ++ return MTK_AFE_RATE_48K; ++ } ++} ++ ++static const struct snd_pcm_hardware mt7986_afe_hardware = { ++ .info = SNDRV_PCM_INFO_MMAP | ++ SNDRV_PCM_INFO_INTERLEAVED | ++ SNDRV_PCM_INFO_MMAP_VALID, ++ .formats = SNDRV_PCM_FMTBIT_S16_LE | ++ SNDRV_PCM_FMTBIT_S24_LE | ++ SNDRV_PCM_FMTBIT_S32_LE, ++ .period_bytes_min = 256, ++ .period_bytes_max = 4 * 48 * 1024, ++ .periods_min = 2, ++ .periods_max = 256, ++ .buffer_bytes_max = 8 * 48 * 1024, ++ .fifo_size = 0, ++}; ++ ++static int mt7986_memif_fs(struct snd_pcm_substream *substream, ++ unsigned int rate) ++{ ++ struct snd_soc_pcm_runtime *rtd = substream->private_data; ++ struct snd_soc_component *component = snd_soc_rtdcom_lookup(rtd, AFE_PCM_NAME); ++ struct mtk_base_afe *afe = snd_soc_component_get_drvdata(component); ++ ++ return mt7986_afe_rate_transform(afe->dev, rate); ++} ++ ++static int mt7986_irq_fs(struct snd_pcm_substream *substream, ++ unsigned int rate) ++{ ++ struct snd_soc_pcm_runtime *rtd = substream->private_data; ++ struct snd_soc_component *component = snd_soc_rtdcom_lookup(rtd, AFE_PCM_NAME); ++ struct mtk_base_afe *afe = snd_soc_component_get_drvdata(component); ++ ++ return mt7986_afe_rate_transform(afe->dev, rate); ++} ++ ++#define MTK_PCM_RATES (SNDRV_PCM_RATE_8000_48000 |\ ++ SNDRV_PCM_RATE_88200 |\ ++ SNDRV_PCM_RATE_96000 |\ ++ SNDRV_PCM_RATE_176400 |\ ++ SNDRV_PCM_RATE_192000) ++ ++#define MTK_PCM_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\ ++ SNDRV_PCM_FMTBIT_S24_LE |\ ++ SNDRV_PCM_FMTBIT_S32_LE) ++ ++static struct snd_soc_dai_driver mt7986_memif_dai_driver[] = { ++ /* FE DAIs: memory intefaces to CPU */ ++ { ++ .name = "DL1", ++ .id = MT7986_MEMIF_DL1, ++ .playback = { ++ .stream_name = "DL1", ++ .channels_min = 1, ++ .channels_max = 2, ++ .rates = MTK_PCM_RATES, ++ .formats = MTK_PCM_FORMATS, ++ }, ++ .ops = &mtk_afe_fe_ops, ++ }, ++ { ++ .name = "UL1", ++ .id = MT7986_MEMIF_VUL12, ++ .capture = { ++ .stream_name = "UL1", ++ .channels_min = 1, ++ .channels_max = 2, ++ .rates = MTK_PCM_RATES, ++ .formats = MTK_PCM_FORMATS, ++ }, ++ .ops = &mtk_afe_fe_ops, ++ }, ++}; ++ ++static const struct snd_kcontrol_new o018_mix[] = { ++ SOC_DAPM_SINGLE_AUTODISABLE("I150_Switch", AFE_CONN018_4, 22, 1, 0), ++}; ++ ++static const struct snd_kcontrol_new o019_mix[] = { ++ SOC_DAPM_SINGLE_AUTODISABLE("I151_Switch", AFE_CONN019_4, 23, 1, 0), ++}; ++ ++static const struct snd_soc_dapm_widget mt7986_memif_widgets[] = { ++ /* DL */ ++ SND_SOC_DAPM_MIXER("I032", SND_SOC_NOPM, 0, 0, NULL, 0), ++ SND_SOC_DAPM_MIXER("I033", SND_SOC_NOPM, 0, 0, NULL, 0), ++ ++ /* UL */ ++ SND_SOC_DAPM_MIXER("O018", SND_SOC_NOPM, 0, 0, ++ o018_mix, ARRAY_SIZE(o018_mix)), ++ SND_SOC_DAPM_MIXER("O019", SND_SOC_NOPM, 0, 0, ++ o019_mix, ARRAY_SIZE(o019_mix)), ++}; ++ ++static const struct snd_soc_dapm_route mt7986_memif_routes[] = { ++ {"I032", NULL, "DL1"}, ++ {"I033", NULL, "DL1"}, ++ {"UL1", NULL, "O018"}, ++ {"UL1", NULL, "O019"}, ++ {"O018", "I150_Switch", "I150"}, ++ {"O019", "I151_Switch", "I151"}, ++}; ++ ++static const struct snd_soc_component_driver mt7986_afe_pcm_dai_component = { ++ .name = "mt7986-afe-pcm-dai", ++}; ++ ++static const struct mtk_base_memif_data memif_data[MT7986_MEMIF_NUM] = { ++ [MT7986_MEMIF_DL1] = { ++ .name = "DL1", ++ .id = MT7986_MEMIF_DL1, ++ .reg_ofs_base = AFE_DL0_BASE, ++ .reg_ofs_cur = AFE_DL0_CUR, ++ .reg_ofs_end = AFE_DL0_END, ++ .reg_ofs_base_msb = AFE_DL0_BASE_MSB, ++ .reg_ofs_cur_msb = AFE_DL0_CUR_MSB, ++ .reg_ofs_end_msb = AFE_DL0_END_MSB, ++ .fs_reg = AFE_DL0_CON0, ++ .fs_shift = DL0_MODE_SFT, ++ .fs_maskbit = DL0_MODE_MASK, ++ .mono_reg = AFE_DL0_CON0, ++ .mono_shift = DL0_MONO_SFT, ++ .enable_reg = AFE_DL0_CON0, ++ .enable_shift = DL0_ON_SFT, ++ .hd_reg = AFE_DL0_CON0, ++ .hd_shift = DL0_HD_MODE_SFT, ++ .hd_align_reg = AFE_DL0_CON0, ++ .hd_align_mshift = DL0_HALIGN_SFT, ++ .pbuf_reg = AFE_DL0_CON0, ++ .pbuf_shift = DL0_PBUF_SIZE_SFT, ++ .minlen_reg = AFE_DL0_CON0, ++ .minlen_shift = DL0_MINLEN_SFT, ++ }, ++ [MT7986_MEMIF_VUL12] = { ++ .name = "VUL12", ++ .id = MT7986_MEMIF_VUL12, ++ .reg_ofs_base = AFE_VUL0_BASE, ++ .reg_ofs_cur = AFE_VUL0_CUR, ++ .reg_ofs_end = AFE_VUL0_END, ++ .reg_ofs_base_msb = AFE_VUL0_BASE_MSB, ++ .reg_ofs_cur_msb = AFE_VUL0_CUR_MSB, ++ .reg_ofs_end_msb = AFE_VUL0_END_MSB, ++ .fs_reg = AFE_VUL0_CON0, ++ .fs_shift = VUL0_MODE_SFT, ++ .fs_maskbit = VUL0_MODE_MASK, ++ .mono_reg = AFE_VUL0_CON0, ++ .mono_shift = VUL0_MONO_SFT, ++ .enable_reg = AFE_VUL0_CON0, ++ .enable_shift = VUL0_ON_SFT, ++ .hd_reg = AFE_VUL0_CON0, ++ .hd_shift = VUL0_HD_MODE_SFT, ++ .hd_align_reg = AFE_VUL0_CON0, ++ .hd_align_mshift = VUL0_HALIGN_SFT, ++ }, ++}; ++ ++static const struct mtk_base_irq_data irq_data[MT7986_IRQ_NUM] = { ++ [MT7986_IRQ_0] = { ++ .id = MT7986_IRQ_0, ++ .irq_cnt_reg = AFE_IRQ0_MCU_CFG1, ++ .irq_cnt_shift = AFE_IRQ_CNT_SHIFT, ++ .irq_cnt_maskbit = AFE_IRQ_CNT_MASK, ++ .irq_fs_reg = AFE_IRQ0_MCU_CFG0, ++ .irq_fs_shift = IRQ_MCU_MODE_SFT, ++ .irq_fs_maskbit = IRQ_MCU_MODE_MASK, ++ .irq_en_reg = AFE_IRQ0_MCU_CFG0, ++ .irq_en_shift = IRQ_MCU_ON_SFT, ++ .irq_clr_reg = AFE_IRQ_MCU_CLR, ++ .irq_clr_shift = IRQ0_MCU_CLR_SFT, ++ }, ++ [MT7986_IRQ_1] = { ++ .id = MT7986_IRQ_1, ++ .irq_cnt_reg = AFE_IRQ1_MCU_CFG1, ++ .irq_cnt_shift = AFE_IRQ_CNT_SHIFT, ++ .irq_cnt_maskbit = AFE_IRQ_CNT_MASK, ++ .irq_fs_reg = AFE_IRQ1_MCU_CFG0, ++ .irq_fs_shift = IRQ_MCU_MODE_SFT, ++ .irq_fs_maskbit = IRQ_MCU_MODE_MASK, ++ .irq_en_reg = AFE_IRQ1_MCU_CFG0, ++ .irq_en_shift = IRQ_MCU_ON_SFT, ++ .irq_clr_reg = AFE_IRQ_MCU_CLR, ++ .irq_clr_shift = IRQ1_MCU_CLR_SFT, ++ }, ++ [MT7986_IRQ_2] = { ++ .id = MT7986_IRQ_2, ++ .irq_cnt_reg = AFE_IRQ2_MCU_CFG1, ++ .irq_cnt_shift = AFE_IRQ_CNT_SHIFT, ++ .irq_cnt_maskbit = AFE_IRQ_CNT_MASK, ++ .irq_fs_reg = AFE_IRQ2_MCU_CFG0, ++ .irq_fs_shift = IRQ_MCU_MODE_SFT, ++ .irq_fs_maskbit = IRQ_MCU_MODE_MASK, ++ .irq_en_reg = AFE_IRQ2_MCU_CFG0, ++ .irq_en_shift = IRQ_MCU_ON_SFT, ++ .irq_clr_reg = AFE_IRQ_MCU_CLR, ++ .irq_clr_shift = IRQ2_MCU_CLR_SFT, ++ }, ++}; ++ ++static bool mt7986_is_volatile_reg(struct device *dev, unsigned int reg) ++{ ++ /* ++ * Those auto-gen regs are read-only, so put it as volatile because ++ * volatile registers cannot be cached, which means that they cannot ++ * be set when power is off ++ */ ++ ++ switch (reg) { ++ case AFE_DL0_CUR_MSB: ++ case AFE_DL0_CUR: ++ case AFE_DL0_RCH_MON: ++ case AFE_DL0_LCH_MON: ++ case AFE_VUL0_CUR_MSB: ++ case AFE_VUL0_CUR: ++ case AFE_IRQ_MCU_STATUS: ++ case AFE_MEMIF_RD_MON: ++ case AFE_MEMIF_WR_MON: ++ return true; ++ default: ++ return false; ++ }; ++} ++ ++static const struct regmap_config mt7986_afe_regmap_config = { ++ .reg_bits = 32, ++ .reg_stride = 4, ++ .val_bits = 32, ++ .volatile_reg = mt7986_is_volatile_reg, ++ .max_register = AFE_MAX_REGISTER, ++ .num_reg_defaults_raw = ((AFE_MAX_REGISTER / 4) + 1), ++}; ++ ++static int mt7986_init_clock(struct mtk_base_afe *afe) ++{ ++ struct mt7986_afe_private *afe_priv = afe->platform_priv; ++ int ret, i; ++ ++ afe_priv->clks = devm_kcalloc(afe->dev, CLK_NUM, ++ sizeof(*afe_priv->clks), GFP_KERNEL); ++ if (!afe_priv->clks) ++ return -ENOMEM; ++ afe_priv->num_clks = CLK_NUM; ++ ++ for (i = 0; i < afe_priv->num_clks; i++) ++ afe_priv->clks[i].id = aud_clks[i]; ++ ++ ret = devm_clk_bulk_get(afe->dev, afe_priv->num_clks, afe_priv->clks); ++ if (ret) ++ return dev_err_probe(afe->dev, ret, "Failed to get clocks\n"); ++ ++ return 0; ++} ++ ++static irqreturn_t mt7986_afe_irq_handler(int irq_id, void *dev) ++{ ++ struct mtk_base_afe *afe = dev; ++ struct mtk_base_afe_irq *irq; ++ u32 mcu_en, status, status_mcu; ++ int i, ret; ++ irqreturn_t irq_ret = IRQ_HANDLED; ++ ++ /* get irq that is sent to MCU */ ++ regmap_read(afe->regmap, AFE_IRQ_MCU_EN, &mcu_en); ++ ++ ret = regmap_read(afe->regmap, AFE_IRQ_MCU_STATUS, &status); ++ /* only care IRQ which is sent to MCU */ ++ status_mcu = status & mcu_en & AFE_IRQ_STATUS_BITS; ++ ++ if (ret || status_mcu == 0) { ++ dev_err(afe->dev, "%s(), irq status err, ret %d, status 0x%x, mcu_en 0x%x\n", ++ __func__, ret, status, mcu_en); ++ ++ irq_ret = IRQ_NONE; ++ goto err_irq; ++ } ++ ++ for (i = 0; i < MT7986_MEMIF_NUM; i++) { ++ struct mtk_base_afe_memif *memif = &afe->memif[i]; ++ ++ if (!memif->substream) ++ continue; ++ ++ if (memif->irq_usage < 0) ++ continue; ++ ++ irq = &afe->irqs[memif->irq_usage]; ++ ++ if (status_mcu & (1 << irq->irq_data->irq_en_shift)) ++ snd_pcm_period_elapsed(memif->substream); ++ } ++ ++err_irq: ++ /* clear irq */ ++ regmap_write(afe->regmap, AFE_IRQ_MCU_CLR, status_mcu); ++ ++ return irq_ret; ++} ++ ++static int mt7986_afe_runtime_suspend(struct device *dev) ++{ ++ struct mtk_base_afe *afe = dev_get_drvdata(dev); ++ struct mt7986_afe_private *afe_priv = afe->platform_priv; ++ ++ if (!afe->regmap || afe_priv->pm_runtime_bypass_reg_ctl) ++ goto skip_regmap; ++ ++ /* disable clk*/ ++ regmap_update_bits(afe->regmap, AUDIO_TOP_CON4, 0x3fff, 0x3fff); ++ regmap_update_bits(afe->regmap, AUDIO_ENGEN_CON0, AUD_APLL2_EN_MASK, 0); ++ regmap_update_bits(afe->regmap, AUDIO_ENGEN_CON0, AUD_26M_EN_MASK, 0); ++ ++ /* make sure all irq status are cleared, twice intended */ ++ regmap_update_bits(afe->regmap, AFE_IRQ_MCU_CLR, 0xffff, 0xffff); ++ ++skip_regmap: ++ clk_bulk_disable_unprepare(afe_priv->num_clks, afe_priv->clks); ++ ++ return 0; ++} ++ ++static int mt7986_afe_runtime_resume(struct device *dev) ++{ ++ struct mtk_base_afe *afe = dev_get_drvdata(dev); ++ struct mt7986_afe_private *afe_priv = afe->platform_priv; ++ int ret; ++ ++ ret = clk_bulk_prepare_enable(afe_priv->num_clks, afe_priv->clks); ++ if (ret) ++ return dev_err_probe(afe->dev, ret, "Failed to enable clocks\n"); ++ ++ if (!afe->regmap || afe_priv->pm_runtime_bypass_reg_ctl) ++ return 0; ++ ++ /* enable clk*/ ++ regmap_update_bits(afe->regmap, AUDIO_TOP_CON4, 0x3fff, 0); ++ regmap_update_bits(afe->regmap, AUDIO_ENGEN_CON0, AUD_APLL2_EN_MASK, ++ AUD_APLL2_EN); ++ regmap_update_bits(afe->regmap, AUDIO_ENGEN_CON0, AUD_26M_EN_MASK, ++ AUD_26M_EN); ++ ++ return 0; ++} ++ ++static int mt7986_afe_component_probe(struct snd_soc_component *component) ++{ ++ return mtk_afe_add_sub_dai_control(component); ++} ++ ++static const struct snd_soc_component_driver mt7986_afe_component = { ++ .name = AFE_PCM_NAME, ++ .probe = mt7986_afe_component_probe, ++ .pointer = mtk_afe_pcm_pointer, ++ .pcm_construct = mtk_afe_pcm_new, ++}; ++ ++static int mt7986_dai_memif_register(struct mtk_base_afe *afe) ++{ ++ struct mtk_base_afe_dai *dai; ++ ++ dai = devm_kzalloc(afe->dev, sizeof(*dai), GFP_KERNEL); ++ if (!dai) ++ return -ENOMEM; ++ ++ list_add(&dai->list, &afe->sub_dais); ++ ++ dai->dai_drivers = mt7986_memif_dai_driver; ++ dai->num_dai_drivers = ARRAY_SIZE(mt7986_memif_dai_driver); ++ ++ dai->dapm_widgets = mt7986_memif_widgets; ++ dai->num_dapm_widgets = ARRAY_SIZE(mt7986_memif_widgets); ++ dai->dapm_routes = mt7986_memif_routes; ++ dai->num_dapm_routes = ARRAY_SIZE(mt7986_memif_routes); ++ ++ return 0; ++} ++ ++typedef int (*dai_register_cb)(struct mtk_base_afe *); ++static const dai_register_cb dai_register_cbs[] = { ++ mt7986_dai_etdm_register, ++ mt7986_dai_memif_register, ++}; ++ ++static int mt7986_afe_pcm_dev_probe(struct platform_device *pdev) ++{ ++ struct mtk_base_afe *afe; ++ struct mt7986_afe_private *afe_priv; ++ struct device *dev; ++ int i, irq_id, ret; ++ ++ afe = devm_kzalloc(&pdev->dev, sizeof(*afe), GFP_KERNEL); ++ if (!afe) ++ return -ENOMEM; ++ platform_set_drvdata(pdev, afe); ++ ++ afe->platform_priv = devm_kzalloc(&pdev->dev, sizeof(*afe_priv), ++ GFP_KERNEL); ++ if (!afe->platform_priv) ++ return -ENOMEM; ++ ++ afe_priv = afe->platform_priv; ++ afe->dev = &pdev->dev; ++ dev = afe->dev; ++ ++ afe->base_addr = devm_platform_ioremap_resource(pdev, 0); ++ if (IS_ERR(afe->base_addr)) ++ return PTR_ERR(afe->base_addr); ++ ++ /* initial audio related clock */ ++ ret = mt7986_init_clock(afe); ++ if (ret) ++ return dev_err_probe(dev, ret, "Cannot initialize clocks\n"); ++ ++ ret = devm_pm_runtime_enable(dev); ++ if (ret) ++ return ret; ++ ++ /* enable clock for regcache get default value from hw */ ++ afe_priv->pm_runtime_bypass_reg_ctl = true; ++ pm_runtime_get_sync(&pdev->dev); ++ ++ afe->regmap = devm_regmap_init_mmio(&pdev->dev, afe->base_addr, ++ &mt7986_afe_regmap_config); ++ ++ pm_runtime_put_sync(&pdev->dev); ++ if (IS_ERR(afe->regmap)) ++ return PTR_ERR(afe->regmap); ++ ++ afe_priv->pm_runtime_bypass_reg_ctl = false; ++ ++ /* init memif */ ++ afe->memif_size = MT7986_MEMIF_NUM; ++ afe->memif = devm_kcalloc(dev, afe->memif_size, sizeof(*afe->memif), ++ GFP_KERNEL); ++ if (!afe->memif) ++ return -ENOMEM; ++ ++ for (i = 0; i < afe->memif_size; i++) { ++ afe->memif[i].data = &memif_data[i]; ++ afe->memif[i].irq_usage = -1; ++ } ++ ++ mutex_init(&afe->irq_alloc_lock); ++ ++ /* irq initialize */ ++ afe->irqs_size = MT7986_IRQ_NUM; ++ afe->irqs = devm_kcalloc(dev, afe->irqs_size, sizeof(*afe->irqs), ++ GFP_KERNEL); ++ if (!afe->irqs) ++ return -ENOMEM; ++ ++ for (i = 0; i < afe->irqs_size; i++) ++ afe->irqs[i].irq_data = &irq_data[i]; ++ ++ /* request irq */ ++ irq_id = platform_get_irq(pdev, 0); ++ if (irq_id < 0) { ++ ret = irq_id; ++ return dev_err_probe(dev, ret, "No irq found\n"); ++ } ++ ret = devm_request_irq(dev, irq_id, mt7986_afe_irq_handler, ++ IRQF_TRIGGER_NONE, "asys-isr", (void *)afe); ++ if (ret) ++ return dev_err_probe(dev, ret, "Failed to request irq for asys-isr\n"); ++ ++ /* init sub_dais */ ++ INIT_LIST_HEAD(&afe->sub_dais); ++ ++ for (i = 0; i < ARRAY_SIZE(dai_register_cbs); i++) { ++ ret = dai_register_cbs[i](afe); ++ if (ret) ++ return dev_err_probe(dev, ret, "DAI register failed, i: %d\n", i); ++ } ++ ++ /* init dai_driver and component_driver */ ++ ret = mtk_afe_combine_sub_dai(afe); ++ if (ret) ++ return dev_err_probe(dev, ret, "mtk_afe_combine_sub_dai fail\n"); ++ ++ afe->mtk_afe_hardware = &mt7986_afe_hardware; ++ afe->memif_fs = mt7986_memif_fs; ++ afe->irq_fs = mt7986_irq_fs; ++ ++ afe->runtime_resume = mt7986_afe_runtime_resume; ++ afe->runtime_suspend = mt7986_afe_runtime_suspend; ++ ++ /* register component */ ++ ret = devm_snd_soc_register_component(&pdev->dev, ++ &mt7986_afe_component, ++ NULL, 0); ++ if (ret) ++ return dev_err_probe(dev, ret, "Cannot register AFE component\n"); ++ ++ ret = devm_snd_soc_register_component(afe->dev, ++ &mt7986_afe_pcm_dai_component, ++ afe->dai_drivers, ++ afe->num_dai_drivers); ++ if (ret) ++ return dev_err_probe(dev, ret, "Cannot register PCM DAI component\n"); ++ ++ return 0; ++} ++ ++static void mt7986_afe_pcm_dev_remove(struct platform_device *pdev) ++{ ++ pm_runtime_disable(&pdev->dev); ++ if (!pm_runtime_status_suspended(&pdev->dev)) ++ mt7986_afe_runtime_suspend(&pdev->dev); ++} ++ ++static const struct of_device_id mt7986_afe_pcm_dt_match[] = { ++ { .compatible = "mediatek,mt7986-afe" }, ++ { /* sentinel */ } ++}; ++MODULE_DEVICE_TABLE(of, mt7986_afe_pcm_dt_match); ++ ++static const struct dev_pm_ops mt7986_afe_pm_ops = { ++ SET_RUNTIME_PM_OPS(mt7986_afe_runtime_suspend, ++ mt7986_afe_runtime_resume, NULL) ++}; ++ ++static struct platform_driver mt7986_afe_pcm_driver = { ++ .driver = { ++ .name = "mt7986-audio", ++ .of_match_table = mt7986_afe_pcm_dt_match, ++ .pm = &mt7986_afe_pm_ops, ++ }, ++ .probe = mt7986_afe_pcm_dev_probe, ++ .remove_new = mt7986_afe_pcm_dev_remove, ++}; ++module_platform_driver(mt7986_afe_pcm_driver); ++ ++MODULE_DESCRIPTION("MediaTek SoC AFE platform driver for ALSA MT7986"); ++MODULE_AUTHOR("Vic Wu "); ++MODULE_LICENSE("GPL"); diff --git a/lede/target/linux/mediatek/patches-6.1/860-v6.6-04-ASoC-mediatek-mt7986-add-machine-driver-with-wm8960.patch b/lede/target/linux/mediatek/patches-6.1/860-v6.6-04-ASoC-mediatek-mt7986-add-machine-driver-with-wm8960.patch new file mode 100644 index 0000000000..dd354c04e3 --- /dev/null +++ b/lede/target/linux/mediatek/patches-6.1/860-v6.6-04-ASoC-mediatek-mt7986-add-machine-driver-with-wm8960.patch @@ -0,0 +1,243 @@ +From ddf6abc1c78072f8ccad59166be95f0ca5af8ca4 Mon Sep 17 00:00:00 2001 +From: Maso Huang +Date: Thu, 17 Aug 2023 18:13:36 +0800 +Subject: [PATCH 4/9] ASoC: mediatek: mt7986: add machine driver with wm8960 + +Add support for mt7986 board with wm8960. + +Signed-off-by: Maso Huang +Reviewed-by: AngeloGioacchino Del Regno +Link: https://lore.kernel.org/r/20230817101338.18782-5-maso.huang@mediatek.com +Signed-off-by: Mark Brown +--- + sound/soc/mediatek/Kconfig | 10 ++ + sound/soc/mediatek/mt7986/Makefile | 1 + + sound/soc/mediatek/mt7986/mt7986-wm8960.c | 196 ++++++++++++++++++++++ + 3 files changed, 207 insertions(+) + create mode 100644 sound/soc/mediatek/mt7986/mt7986-wm8960.c + +--- a/sound/soc/mediatek/Kconfig ++++ b/sound/soc/mediatek/Kconfig +@@ -64,6 +64,16 @@ config SND_SOC_MT7986 + Select Y if you have such device. + If unsure select "N". + ++config SND_SOC_MT7986_WM8960 ++ tristate "ASoc Audio driver for MT7986 with WM8960 codec" ++ depends on SND_SOC_MT7986 && I2C ++ select SND_SOC_WM8960 ++ help ++ This adds support for ASoC machine driver for MediaTek MT7986 ++ boards with the WM8960 codecs. ++ Select Y if you have such device. ++ If unsure select "N". ++ + config SND_SOC_MT8173 + tristate "ASoC support for Mediatek MT8173 chip" + depends on ARCH_MEDIATEK +--- a/sound/soc/mediatek/mt7986/Makefile ++++ b/sound/soc/mediatek/mt7986/Makefile +@@ -6,3 +6,4 @@ snd-soc-mt7986-afe-objs := \ + mt7986-dai-etdm.o + + obj-$(CONFIG_SND_SOC_MT7986) += snd-soc-mt7986-afe.o ++obj-$(CONFIG_SND_SOC_MT7986_WM8960) += mt7986-wm8960.o +--- /dev/null ++++ b/sound/soc/mediatek/mt7986/mt7986-wm8960.c +@@ -0,0 +1,196 @@ ++// SPDX-License-Identifier: GPL-2.0 ++/* ++ * mt7986-wm8960.c -- MT7986-WM8960 ALSA SoC machine driver ++ * ++ * Copyright (c) 2023 MediaTek Inc. ++ * Authors: Vic Wu ++ * Maso Huang ++ */ ++ ++#include ++#include ++ ++#include "mt7986-afe-common.h" ++ ++struct mt7986_wm8960_priv { ++ struct device_node *platform_node; ++ struct device_node *codec_node; ++}; ++ ++static const struct snd_soc_dapm_widget mt7986_wm8960_widgets[] = { ++ SND_SOC_DAPM_HP("Headphone", NULL), ++ SND_SOC_DAPM_MIC("AMIC", NULL), ++}; ++ ++static const struct snd_kcontrol_new mt7986_wm8960_controls[] = { ++ SOC_DAPM_PIN_SWITCH("Headphone"), ++ SOC_DAPM_PIN_SWITCH("AMIC"), ++}; ++ ++SND_SOC_DAILINK_DEFS(playback, ++ DAILINK_COMP_ARRAY(COMP_CPU("DL1")), ++ DAILINK_COMP_ARRAY(COMP_DUMMY()), ++ DAILINK_COMP_ARRAY(COMP_EMPTY())); ++ ++SND_SOC_DAILINK_DEFS(capture, ++ DAILINK_COMP_ARRAY(COMP_CPU("UL1")), ++ DAILINK_COMP_ARRAY(COMP_DUMMY()), ++ DAILINK_COMP_ARRAY(COMP_EMPTY())); ++ ++SND_SOC_DAILINK_DEFS(codec, ++ DAILINK_COMP_ARRAY(COMP_CPU("ETDM")), ++ DAILINK_COMP_ARRAY(COMP_CODEC(NULL, "wm8960-hifi")), ++ DAILINK_COMP_ARRAY(COMP_EMPTY())); ++ ++static struct snd_soc_dai_link mt7986_wm8960_dai_links[] = { ++ /* FE */ ++ { ++ .name = "wm8960-playback", ++ .stream_name = "wm8960-playback", ++ .trigger = {SND_SOC_DPCM_TRIGGER_POST, ++ SND_SOC_DPCM_TRIGGER_POST}, ++ .dynamic = 1, ++ .dpcm_playback = 1, ++ SND_SOC_DAILINK_REG(playback), ++ }, ++ { ++ .name = "wm8960-capture", ++ .stream_name = "wm8960-capture", ++ .trigger = {SND_SOC_DPCM_TRIGGER_POST, ++ SND_SOC_DPCM_TRIGGER_POST}, ++ .dynamic = 1, ++ .dpcm_capture = 1, ++ SND_SOC_DAILINK_REG(capture), ++ }, ++ /* BE */ ++ { ++ .name = "wm8960-codec", ++ .no_pcm = 1, ++ .dai_fmt = SND_SOC_DAIFMT_I2S | ++ SND_SOC_DAIFMT_NB_NF | ++ SND_SOC_DAIFMT_CBS_CFS | ++ SND_SOC_DAIFMT_GATED, ++ .dpcm_playback = 1, ++ .dpcm_capture = 1, ++ SND_SOC_DAILINK_REG(codec), ++ }, ++}; ++ ++static struct snd_soc_card mt7986_wm8960_card = { ++ .name = "mt7986-wm8960", ++ .owner = THIS_MODULE, ++ .dai_link = mt7986_wm8960_dai_links, ++ .num_links = ARRAY_SIZE(mt7986_wm8960_dai_links), ++ .controls = mt7986_wm8960_controls, ++ .num_controls = ARRAY_SIZE(mt7986_wm8960_controls), ++ .dapm_widgets = mt7986_wm8960_widgets, ++ .num_dapm_widgets = ARRAY_SIZE(mt7986_wm8960_widgets), ++}; ++ ++static int mt7986_wm8960_machine_probe(struct platform_device *pdev) ++{ ++ struct snd_soc_card *card = &mt7986_wm8960_card; ++ struct snd_soc_dai_link *dai_link; ++ struct device_node *platform, *codec; ++ struct mt7986_wm8960_priv *priv; ++ int ret, i; ++ ++ priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); ++ if (!priv) ++ return -ENOMEM; ++ ++ platform = of_get_child_by_name(pdev->dev.of_node, "platform"); ++ ++ if (platform) { ++ priv->platform_node = of_parse_phandle(platform, "sound-dai", 0); ++ of_node_put(platform); ++ ++ if (!priv->platform_node) { ++ dev_err(&pdev->dev, "Failed to parse platform/sound-dai property\n"); ++ return -EINVAL; ++ } ++ } else { ++ dev_err(&pdev->dev, "Property 'platform' missing or invalid\n"); ++ return -EINVAL; ++ } ++ ++ for_each_card_prelinks(card, i, dai_link) { ++ if (dai_link->platforms->name) ++ continue; ++ dai_link->platforms->of_node = priv->platform_node; ++ } ++ ++ card->dev = &pdev->dev; ++ ++ codec = of_get_child_by_name(pdev->dev.of_node, "codec"); ++ ++ if (codec) { ++ priv->codec_node = of_parse_phandle(codec, "sound-dai", 0); ++ of_node_put(codec); ++ ++ if (!priv->codec_node) { ++ of_node_put(priv->platform_node); ++ dev_err(&pdev->dev, "Failed to parse codec/sound-dai property\n"); ++ return -EINVAL; ++ } ++ } else { ++ of_node_put(priv->platform_node); ++ dev_err(&pdev->dev, "Property 'codec' missing or invalid\n"); ++ return -EINVAL; ++ } ++ ++ for_each_card_prelinks(card, i, dai_link) { ++ if (dai_link->codecs->name) ++ continue; ++ dai_link->codecs->of_node = priv->codec_node; ++ } ++ ++ ret = snd_soc_of_parse_audio_routing(card, "audio-routing"); ++ if (ret) { ++ dev_err(&pdev->dev, "Failed to parse audio-routing: %d\n", ret); ++ goto err_of_node_put; ++ } ++ ++ ret = devm_snd_soc_register_card(&pdev->dev, card); ++ if (ret) { ++ dev_err(&pdev->dev, "%s snd_soc_register_card fail: %d\n", __func__, ret); ++ goto err_of_node_put; ++ } ++ ++err_of_node_put: ++ of_node_put(priv->codec_node); ++ of_node_put(priv->platform_node); ++ return ret; ++} ++ ++static void mt7986_wm8960_machine_remove(struct platform_device *pdev) ++{ ++ struct snd_soc_card *card = platform_get_drvdata(pdev); ++ struct mt7986_wm8960_priv *priv = snd_soc_card_get_drvdata(card); ++ ++ of_node_put(priv->codec_node); ++ of_node_put(priv->platform_node); ++} ++ ++static const struct of_device_id mt7986_wm8960_machine_dt_match[] = { ++ {.compatible = "mediatek,mt7986-wm8960-sound"}, ++ { /* sentinel */ } ++}; ++MODULE_DEVICE_TABLE(of, mt7986_wm8960_machine_dt_match); ++ ++static struct platform_driver mt7986_wm8960_machine = { ++ .driver = { ++ .name = "mt7986-wm8960", ++ .of_match_table = mt7986_wm8960_machine_dt_match, ++ }, ++ .probe = mt7986_wm8960_machine_probe, ++ .remove_new = mt7986_wm8960_machine_remove, ++}; ++ ++module_platform_driver(mt7986_wm8960_machine); ++ ++/* Module information */ ++MODULE_DESCRIPTION("MT7986 WM8960 ALSA SoC machine driver"); ++MODULE_AUTHOR("Vic Wu "); ++MODULE_LICENSE("GPL"); ++MODULE_ALIAS("mt7986 wm8960 soc card"); diff --git a/lede/target/linux/mediatek/patches-6.1/860-v6.6-05-ASoC-dt-bindings-mediatek-mt7986-wm8960-add-mt7986-w.patch b/lede/target/linux/mediatek/patches-6.1/860-v6.6-05-ASoC-dt-bindings-mediatek-mt7986-wm8960-add-mt7986-w.patch new file mode 100644 index 0000000000..8cf0b5464a --- /dev/null +++ b/lede/target/linux/mediatek/patches-6.1/860-v6.6-05-ASoC-dt-bindings-mediatek-mt7986-wm8960-add-mt7986-w.patch @@ -0,0 +1,87 @@ +From 72469f950b629e57e60fbcbefed45e083619b986 Mon Sep 17 00:00:00 2001 +From: Maso Huang +Date: Thu, 17 Aug 2023 18:13:37 +0800 +Subject: [PATCH 5/9] ASoC: dt-bindings: mediatek,mt7986-wm8960: add + mt7986-wm8960 document + +Add document for mt7986 board with wm8960. + +Signed-off-by: Maso Huang +Reviewed-by: AngeloGioacchino Del Regno +Link: https://lore.kernel.org/r/20230817101338.18782-6-maso.huang@mediatek.com +Signed-off-by: Mark Brown +--- + .../sound/mediatek,mt7986-wm8960.yaml | 67 +++++++++++++++++++ + 1 file changed, 67 insertions(+) + create mode 100644 Documentation/devicetree/bindings/sound/mediatek,mt7986-wm8960.yaml + +--- /dev/null ++++ b/Documentation/devicetree/bindings/sound/mediatek,mt7986-wm8960.yaml +@@ -0,0 +1,67 @@ ++# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) ++%YAML 1.2 ++--- ++$id: http://devicetree.org/schemas/sound/mediatek,mt7986-wm8960.yaml# ++$schema: http://devicetree.org/meta-schemas/core.yaml# ++ ++title: MediaTek MT7986 sound card with WM8960 codec ++ ++maintainers: ++ - Maso Huang ++ ++allOf: ++ - $ref: sound-card-common.yaml# ++ ++properties: ++ compatible: ++ const: mediatek,mt7986-wm8960-sound ++ ++ platform: ++ type: object ++ additionalProperties: false ++ properties: ++ sound-dai: ++ description: The phandle of MT7986 platform. ++ maxItems: 1 ++ required: ++ - sound-dai ++ ++ codec: ++ type: object ++ additionalProperties: false ++ properties: ++ sound-dai: ++ description: The phandle of wm8960 codec. ++ maxItems: 1 ++ required: ++ - sound-dai ++ ++unevaluatedProperties: false ++ ++required: ++ - compatible ++ - audio-routing ++ - platform ++ - codec ++ ++examples: ++ - | ++ sound { ++ compatible = "mediatek,mt7986-wm8960-sound"; ++ model = "mt7986-wm8960"; ++ audio-routing = ++ "Headphone", "HP_L", ++ "Headphone", "HP_R", ++ "LINPUT1", "AMIC", ++ "RINPUT1", "AMIC"; ++ ++ platform { ++ sound-dai = <&afe>; ++ }; ++ ++ codec { ++ sound-dai = <&wm8960>; ++ }; ++ }; ++ ++... diff --git a/lede/target/linux/mediatek/patches-6.1/860-v6.6-06-ASoC-dt-bindings-mediatek-mt7986-afe-add-audio-afe-d.patch b/lede/target/linux/mediatek/patches-6.1/860-v6.6-06-ASoC-dt-bindings-mediatek-mt7986-afe-add-audio-afe-d.patch new file mode 100644 index 0000000000..236d6a217c --- /dev/null +++ b/lede/target/linux/mediatek/patches-6.1/860-v6.6-06-ASoC-dt-bindings-mediatek-mt7986-afe-add-audio-afe-d.patch @@ -0,0 +1,180 @@ +From d16202eb38585adbc16e32d11188dbc2127015de Mon Sep 17 00:00:00 2001 +From: Maso Huang +Date: Thu, 17 Aug 2023 18:13:38 +0800 +Subject: [PATCH 6/9] ASoC: dt-bindings: mediatek,mt7986-afe: add audio afe + document + +Add mt7986 audio afe document. + +Signed-off-by: Maso Huang +Reviewed-by: AngeloGioacchino Del Regno +Link: https://lore.kernel.org/r/20230817101338.18782-7-maso.huang@mediatek.com +Signed-off-by: Mark Brown +--- + .../bindings/sound/mediatek,mt7986-afe.yaml | 160 ++++++++++++++++++ + 1 file changed, 160 insertions(+) + create mode 100644 Documentation/devicetree/bindings/sound/mediatek,mt7986-afe.yaml + +--- /dev/null ++++ b/Documentation/devicetree/bindings/sound/mediatek,mt7986-afe.yaml +@@ -0,0 +1,160 @@ ++# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) ++%YAML 1.2 ++--- ++$id: http://devicetree.org/schemas/sound/mediatek,mt7986-afe.yaml# ++$schema: http://devicetree.org/meta-schemas/core.yaml# ++ ++title: MediaTek AFE PCM controller for MT7986 ++ ++maintainers: ++ - Maso Huang ++ ++properties: ++ compatible: ++ oneOf: ++ - const: mediatek,mt7986-afe ++ - items: ++ - enum: ++ - mediatek,mt7981-afe ++ - mediatek,mt7988-afe ++ - const: mediatek,mt7986-afe ++ ++ reg: ++ maxItems: 1 ++ ++ interrupts: ++ maxItems: 1 ++ ++ clocks: ++ minItems: 5 ++ items: ++ - description: audio bus clock ++ - description: audio 26M clock ++ - description: audio intbus clock ++ - description: audio hopping clock ++ - description: audio pll clock ++ - description: mux for pcm_mck ++ - description: audio i2s/pcm mck ++ ++ clock-names: ++ minItems: 5 ++ items: ++ - const: bus_ck ++ - const: 26m_ck ++ - const: l_ck ++ - const: aud_ck ++ - const: eg2_ck ++ - const: sel ++ - const: i2s_m ++ ++required: ++ - compatible ++ - reg ++ - interrupts ++ - clocks ++ - clock-names ++ ++allOf: ++ - if: ++ properties: ++ compatible: ++ contains: ++ const: mediatek,mt7986-afe ++ then: ++ properties: ++ clocks: ++ items: ++ - description: audio bus clock ++ - description: audio 26M clock ++ - description: audio intbus clock ++ - description: audio hopping clock ++ - description: audio pll clock ++ clock-names: ++ items: ++ - const: bus_ck ++ - const: 26m_ck ++ - const: l_ck ++ - const: aud_ck ++ - const: eg2_ck ++ ++ - if: ++ properties: ++ compatible: ++ contains: ++ const: mediatek,mt7981-afe ++ then: ++ properties: ++ clocks: ++ items: ++ - description: audio bus clock ++ - description: audio 26M clock ++ - description: audio intbus clock ++ - description: audio hopping clock ++ - description: audio pll clock ++ - description: mux for pcm_mck ++ clock-names: ++ items: ++ - const: bus_ck ++ - const: 26m_ck ++ - const: l_ck ++ - const: aud_ck ++ - const: eg2_ck ++ - const: sel ++ ++ - if: ++ properties: ++ compatible: ++ contains: ++ const: mediatek,mt7988-afe ++ then: ++ properties: ++ clocks: ++ items: ++ - description: audio bus clock ++ - description: audio 26M clock ++ - description: audio intbus clock ++ - description: audio hopping clock ++ - description: audio pll clock ++ - description: mux for pcm_mck ++ - description: audio i2s/pcm mck ++ clock-names: ++ items: ++ - const: bus_ck ++ - const: 26m_ck ++ - const: l_ck ++ - const: aud_ck ++ - const: eg2_ck ++ - const: sel ++ - const: i2s_m ++ ++additionalProperties: false ++ ++examples: ++ - | ++ #include ++ #include ++ #include ++ ++ afe@11210000 { ++ compatible = "mediatek,mt7986-afe"; ++ reg = <0x11210000 0x9000>; ++ interrupts = ; ++ clocks = <&infracfg_ao CLK_INFRA_AUD_BUS_CK>, ++ <&infracfg_ao CLK_INFRA_AUD_26M_CK>, ++ <&infracfg_ao CLK_INFRA_AUD_L_CK>, ++ <&infracfg_ao CLK_INFRA_AUD_AUD_CK>, ++ <&infracfg_ao CLK_INFRA_AUD_EG2_CK>; ++ clock-names = "bus_ck", ++ "26m_ck", ++ "l_ck", ++ "aud_ck", ++ "eg2_ck"; ++ assigned-clocks = <&topckgen CLK_TOP_A1SYS_SEL>, ++ <&topckgen CLK_TOP_AUD_L_SEL>, ++ <&topckgen CLK_TOP_A_TUNER_SEL>; ++ assigned-clock-parents = <&topckgen CLK_TOP_APLL2_D4>, ++ <&apmixedsys CLK_APMIXED_APLL2>, ++ <&topckgen CLK_TOP_APLL2_D4>; ++ }; ++ ++... diff --git a/lede/target/linux/mediatek/patches-6.1/860-v6.7-07-ASoC-mediatek-mt7986-drop-the-remove-callback-of-mt7.patch b/lede/target/linux/mediatek/patches-6.1/860-v6.7-07-ASoC-mediatek-mt7986-drop-the-remove-callback-of-mt7.patch new file mode 100644 index 0000000000..413db8233f --- /dev/null +++ b/lede/target/linux/mediatek/patches-6.1/860-v6.7-07-ASoC-mediatek-mt7986-drop-the-remove-callback-of-mt7.patch @@ -0,0 +1,42 @@ +From f3f0934e5c7b9c16e0cb2435be3555382e6293ad Mon Sep 17 00:00:00 2001 +From: Maso Huang +Date: Tue, 24 Oct 2023 11:50:17 +0800 +Subject: [PATCH 7/9] ASoC: mediatek: mt7986: drop the remove callback of + mt7986_wm8960 + +Drop the remove callback of mt7986_wm8960. + +Signed-off-by: Maso Huang +Reviewed-by: AngeloGioacchino Del Regno +Link: https://lore.kernel.org/r/20231024035019.11732-2-maso.huang@mediatek.com +Signed-off-by: Mark Brown +--- + sound/soc/mediatek/mt7986/mt7986-wm8960.c | 10 ---------- + 1 file changed, 10 deletions(-) + +--- a/sound/soc/mediatek/mt7986/mt7986-wm8960.c ++++ b/sound/soc/mediatek/mt7986/mt7986-wm8960.c +@@ -163,15 +163,6 @@ err_of_node_put: + return ret; + } + +-static void mt7986_wm8960_machine_remove(struct platform_device *pdev) +-{ +- struct snd_soc_card *card = platform_get_drvdata(pdev); +- struct mt7986_wm8960_priv *priv = snd_soc_card_get_drvdata(card); +- +- of_node_put(priv->codec_node); +- of_node_put(priv->platform_node); +-} +- + static const struct of_device_id mt7986_wm8960_machine_dt_match[] = { + {.compatible = "mediatek,mt7986-wm8960-sound"}, + { /* sentinel */ } +@@ -184,7 +175,6 @@ static struct platform_driver mt7986_wm8 + .of_match_table = mt7986_wm8960_machine_dt_match, + }, + .probe = mt7986_wm8960_machine_probe, +- .remove_new = mt7986_wm8960_machine_remove, + }; + + module_platform_driver(mt7986_wm8960_machine); diff --git a/lede/target/linux/mediatek/patches-6.1/860-v6.7-08-ASoC-mediatek-mt7986-remove-the-mt7986_wm8960_priv-s.patch b/lede/target/linux/mediatek/patches-6.1/860-v6.7-08-ASoC-mediatek-mt7986-remove-the-mt7986_wm8960_priv-s.patch new file mode 100644 index 0000000000..5c596fc49c --- /dev/null +++ b/lede/target/linux/mediatek/patches-6.1/860-v6.7-08-ASoC-mediatek-mt7986-remove-the-mt7986_wm8960_priv-s.patch @@ -0,0 +1,105 @@ +From 98b8fb2cb4fcab1903d0baf611bf0c3f822a08dc Mon Sep 17 00:00:00 2001 +From: Maso Huang +Date: Tue, 24 Oct 2023 11:50:18 +0800 +Subject: [PATCH 8/9] ASoC: mediatek: mt7986: remove the mt7986_wm8960_priv + structure + +Remove the mt7986_wm8960_priv structure. + +Signed-off-by: Maso Huang +Reviewed-by: AngeloGioacchino Del Regno +Link: https://lore.kernel.org/r/20231024035019.11732-3-maso.huang@mediatek.com +Signed-off-by: Mark Brown +--- + sound/soc/mediatek/mt7986/mt7986-wm8960.c | 33 +++++++++-------------- + 1 file changed, 12 insertions(+), 21 deletions(-) + +--- a/sound/soc/mediatek/mt7986/mt7986-wm8960.c ++++ b/sound/soc/mediatek/mt7986/mt7986-wm8960.c +@@ -12,11 +12,6 @@ + + #include "mt7986-afe-common.h" + +-struct mt7986_wm8960_priv { +- struct device_node *platform_node; +- struct device_node *codec_node; +-}; +- + static const struct snd_soc_dapm_widget mt7986_wm8960_widgets[] = { + SND_SOC_DAPM_HP("Headphone", NULL), + SND_SOC_DAPM_MIC("AMIC", NULL), +@@ -92,20 +87,18 @@ static int mt7986_wm8960_machine_probe(s + struct snd_soc_card *card = &mt7986_wm8960_card; + struct snd_soc_dai_link *dai_link; + struct device_node *platform, *codec; +- struct mt7986_wm8960_priv *priv; ++ struct device_node *platform_dai_node, *codec_dai_node; + int ret, i; + +- priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); +- if (!priv) +- return -ENOMEM; ++ card->dev = &pdev->dev; + + platform = of_get_child_by_name(pdev->dev.of_node, "platform"); + + if (platform) { +- priv->platform_node = of_parse_phandle(platform, "sound-dai", 0); ++ platform_dai_node = of_parse_phandle(platform, "sound-dai", 0); + of_node_put(platform); + +- if (!priv->platform_node) { ++ if (!platform_dai_node) { + dev_err(&pdev->dev, "Failed to parse platform/sound-dai property\n"); + return -EINVAL; + } +@@ -117,24 +110,22 @@ static int mt7986_wm8960_machine_probe(s + for_each_card_prelinks(card, i, dai_link) { + if (dai_link->platforms->name) + continue; +- dai_link->platforms->of_node = priv->platform_node; ++ dai_link->platforms->of_node = platform_dai_node; + } + +- card->dev = &pdev->dev; +- + codec = of_get_child_by_name(pdev->dev.of_node, "codec"); + + if (codec) { +- priv->codec_node = of_parse_phandle(codec, "sound-dai", 0); ++ codec_dai_node = of_parse_phandle(codec, "sound-dai", 0); + of_node_put(codec); + +- if (!priv->codec_node) { +- of_node_put(priv->platform_node); ++ if (!codec_dai_node) { ++ of_node_put(platform_dai_node); + dev_err(&pdev->dev, "Failed to parse codec/sound-dai property\n"); + return -EINVAL; + } + } else { +- of_node_put(priv->platform_node); ++ of_node_put(platform_dai_node); + dev_err(&pdev->dev, "Property 'codec' missing or invalid\n"); + return -EINVAL; + } +@@ -142,7 +133,7 @@ static int mt7986_wm8960_machine_probe(s + for_each_card_prelinks(card, i, dai_link) { + if (dai_link->codecs->name) + continue; +- dai_link->codecs->of_node = priv->codec_node; ++ dai_link->codecs->of_node = codec_dai_node; + } + + ret = snd_soc_of_parse_audio_routing(card, "audio-routing"); +@@ -158,8 +149,8 @@ static int mt7986_wm8960_machine_probe(s + } + + err_of_node_put: +- of_node_put(priv->codec_node); +- of_node_put(priv->platform_node); ++ of_node_put(platform_dai_node); ++ of_node_put(codec_dai_node); + return ret; + } + diff --git a/lede/target/linux/mediatek/patches-6.1/860-v6.7-09-ASoC-mediatek-mt7986-add-sample-rate-checker.patch b/lede/target/linux/mediatek/patches-6.1/860-v6.7-09-ASoC-mediatek-mt7986-add-sample-rate-checker.patch new file mode 100644 index 0000000000..d4128deabc --- /dev/null +++ b/lede/target/linux/mediatek/patches-6.1/860-v6.7-09-ASoC-mediatek-mt7986-add-sample-rate-checker.patch @@ -0,0 +1,49 @@ +From 4e229f4264f4be7a6a554487714c0913ef59cf7f Mon Sep 17 00:00:00 2001 +From: Maso Huang +Date: Tue, 24 Oct 2023 11:50:19 +0800 +Subject: [PATCH 9/9] ASoC: mediatek: mt7986: add sample rate checker + +mt7986 only supports 8/12/16/24/32/48/96/192 kHz + +Signed-off-by: Maso Huang +Reviewed-by: AngeloGioacchino Del Regno +Link: https://lore.kernel.org/r/20231024035019.11732-4-maso.huang@mediatek.com +Signed-off-by: Mark Brown +--- + sound/soc/mediatek/mt7986/mt7986-dai-etdm.c | 23 +++++++++++++++++---- + 1 file changed, 19 insertions(+), 4 deletions(-) + +--- a/sound/soc/mediatek/mt7986/mt7986-dai-etdm.c ++++ b/sound/soc/mediatek/mt7986/mt7986-dai-etdm.c +@@ -237,12 +237,27 @@ static int mtk_dai_etdm_hw_params(struct + struct snd_pcm_hw_params *params, + struct snd_soc_dai *dai) + { ++ unsigned int rate = params_rate(params); + struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai); + +- mtk_dai_etdm_config(afe, params, dai, SNDRV_PCM_STREAM_PLAYBACK); +- mtk_dai_etdm_config(afe, params, dai, SNDRV_PCM_STREAM_CAPTURE); +- +- return 0; ++ switch (rate) { ++ case 8000: ++ case 12000: ++ case 16000: ++ case 24000: ++ case 32000: ++ case 48000: ++ case 96000: ++ case 192000: ++ mtk_dai_etdm_config(afe, params, dai, SNDRV_PCM_STREAM_PLAYBACK); ++ mtk_dai_etdm_config(afe, params, dai, SNDRV_PCM_STREAM_CAPTURE); ++ return 0; ++ default: ++ dev_err(afe->dev, ++ "Sample rate %d invalid. Supported rates: 8/12/16/24/32/48/96/192 kHz\n", ++ rate); ++ return -EINVAL; ++ } + } + + static int mtk_dai_etdm_trigger(struct snd_pcm_substream *substream, int cmd, diff --git a/lede/target/linux/mediatek/patches-6.1/861-pending-10-ASoC-mediatek-mt7986-silence-error-in-case-of-EPROBE.patch b/lede/target/linux/mediatek/patches-6.1/861-pending-10-ASoC-mediatek-mt7986-silence-error-in-case-of-EPROBE.patch new file mode 100644 index 0000000000..a40c249257 --- /dev/null +++ b/lede/target/linux/mediatek/patches-6.1/861-pending-10-ASoC-mediatek-mt7986-silence-error-in-case-of-EPROBE.patch @@ -0,0 +1,26 @@ +From e4cde335d1771863a60b6931e51357b8470e85c4 Mon Sep 17 00:00:00 2001 +From: Daniel Golle +Date: Sun, 10 Dec 2023 22:41:39 +0000 +Subject: [PATCH] ASoC: mediatek: mt7986: silence error in case of + -EPROBE_DEFER + +If probe is defered no error should be printed. Mute it. + +Signed-off-by: Daniel Golle +--- + sound/soc/mediatek/mt7986/mt7986-wm8960.c | 4 +++- + 1 file changed, 3 insertions(+), 1 deletion(-) + +--- a/sound/soc/mediatek/mt7986/mt7986-wm8960.c ++++ b/sound/soc/mediatek/mt7986/mt7986-wm8960.c +@@ -144,7 +144,9 @@ static int mt7986_wm8960_machine_probe(s + + ret = devm_snd_soc_register_card(&pdev->dev, card); + if (ret) { +- dev_err(&pdev->dev, "%s snd_soc_register_card fail: %d\n", __func__, ret); ++ if (ret != -EPROBE_DEFER) ++ dev_err(&pdev->dev, "%s snd_soc_register_card fail: %d\n", __func__, ret); ++ + goto err_of_node_put; + } + diff --git a/lede/target/linux/mediatek/patches-6.1/862-arm64-dts-mt7986-add-afe.patch b/lede/target/linux/mediatek/patches-6.1/862-arm64-dts-mt7986-add-afe.patch new file mode 100644 index 0000000000..e40dca2a7d --- /dev/null +++ b/lede/target/linux/mediatek/patches-6.1/862-arm64-dts-mt7986-add-afe.patch @@ -0,0 +1,40 @@ +From 1c09b694a1e9378931085e77d834a4d9786a5356 Mon Sep 17 00:00:00 2001 +From: Maso Huang +Date: Thu, 7 Sep 2023 10:54:37 +0800 +Subject: [PATCH] arm64: dts: mt7986: add afe + +--- + arch/arm64/boot/dts/mediatek/mt7986a.dtsi | 23 +++++++++++ + 1 files changed, 23 insertions(+) + +--- a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi ++++ b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi +@@ -249,6 +249,28 @@ + status = "disabled"; + }; + ++ afe: audio-controller@11210000 { ++ compatible = "mediatek,mt7986-afe"; ++ reg = <0 0x11210000 0 0x9000>; ++ interrupts = ; ++ clocks = <&infracfg CLK_INFRA_AUD_BUS_CK>, ++ <&infracfg CLK_INFRA_AUD_26M_CK>, ++ <&infracfg CLK_INFRA_AUD_L_CK>, ++ <&infracfg CLK_INFRA_AUD_AUD_CK>, ++ <&infracfg CLK_INFRA_AUD_EG2_CK>; ++ clock-names = "aud_bus_ck", ++ "aud_26m_ck", ++ "aud_l_ck", ++ "aud_aud_ck", ++ "aud_eg2_ck"; ++ assigned-clocks = <&topckgen CLK_TOP_A1SYS_SEL>, ++ <&topckgen CLK_TOP_AUD_L_SEL>, ++ <&topckgen CLK_TOP_A_TUNER_SEL>; ++ assigned-clock-parents = <&topckgen CLK_TOP_APLL2_D4>, ++ <&apmixedsys CLK_APMIXED_APLL2>, ++ <&topckgen CLK_TOP_APLL2_D4>; ++ }; ++ + pwm: pwm@10048000 { + compatible = "mediatek,mt7986-pwm"; + reg = <0 0x10048000 0 0x1000>; diff --git a/lede/target/linux/mediatek/patches-6.1/863-arm64-dts-mt7986-add-sound-wm8960.patch b/lede/target/linux/mediatek/patches-6.1/863-arm64-dts-mt7986-add-sound-wm8960.patch new file mode 100644 index 0000000000..15e30dec56 --- /dev/null +++ b/lede/target/linux/mediatek/patches-6.1/863-arm64-dts-mt7986-add-sound-wm8960.patch @@ -0,0 +1,61 @@ +From 1c09b694a1e9378931085e77d834a4d9786a5356 Mon Sep 17 00:00:00 2001 +From: Maso Huang +Date: Thu, 7 Sep 2023 10:54:37 +0800 +Subject: [PATCH] arm64: dts: mt7986: add sound wm8960 + +--- + .../dts/mediatek/mt7986a-rfb-spim-nand.dts | 39 +++++++++++++++++++ + 1 files changed, 39 insertions(+) + +--- a/arch/arm64/boot/dts/mediatek/mt7986a-rfb-spim-nand.dts ++++ b/arch/arm64/boot/dts/mediatek/mt7986a-rfb-spim-nand.dts +@@ -4,6 +4,35 @@ + + / { + compatible = "mediatek,mt7986a-rfb-snand"; ++ ++ sound_wm8960 { ++ compatible = "mediatek,mt7986-wm8960-sound"; ++ audio-routing = "Headphone", "HP_L", ++ "Headphone", "HP_R", ++ "LINPUT1", "AMIC", ++ "RINPUT1", "AMIC"; ++ ++ status = "okay"; ++ ++ platform { ++ sound-dai = <&afe>; ++ }; ++ ++ codec { ++ sound-dai = <&wm8960>; ++ }; ++ }; ++}; ++ ++&i2c0 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&i2c_pins>; ++ status = "okay"; ++ ++ wm8960: wm8960@1a { ++ compatible = "wlf,wm8960"; ++ reg = <0x1a>; ++ }; + }; + + &spi0 { +@@ -50,3 +79,13 @@ + &wifi { + mediatek,mtd-eeprom = <&factory 0>; + }; ++ ++&pio { ++ i2c_pins: i2c-pins-3-4 { ++ mux { ++ function = "i2c"; ++ groups = "i2c"; ++ }; ++ }; ++}; ++ diff --git a/lede/target/linux/mediatek/patches-6.1/864-arm64-dts-mt7986-add-sound-overlay-for-bpi-r3.patch b/lede/target/linux/mediatek/patches-6.1/864-arm64-dts-mt7986-add-sound-overlay-for-bpi-r3.patch new file mode 100644 index 0000000000..bddcd4bb0c --- /dev/null +++ b/lede/target/linux/mediatek/patches-6.1/864-arm64-dts-mt7986-add-sound-overlay-for-bpi-r3.patch @@ -0,0 +1,75 @@ +--- /dev/null ++++ b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-respeaker-2mics.dtso +@@ -0,0 +1,62 @@ ++// SPDX-License-Identifier: (GPL-2.0 OR MIT) ++/* ++ * Copyright (C) 2023 MediaTek Inc. ++ * Author: Maso Huang ++ */ ++ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "bananapi,bpi-r3", "mediatek,mt7986a"; ++ ++ fragment@0 { ++ target-path = "/"; ++ __overlay__ { ++ sound_wm8960 { ++ compatible = "mediatek,mt7986-wm8960-sound"; ++ audio-routing = "Headphone", "HP_L", ++ "Headphone", "HP_R", ++ "LINPUT1", "AMIC", ++ "RINPUT1", "AMIC"; ++ ++ status = "okay"; ++ ++ platform { ++ sound-dai = <&afe>; ++ }; ++ ++ codec { ++ sound-dai = <&wm8960>; ++ }; ++ }; ++ }; ++ }; ++ ++ fragment@1 { ++ target = <&i2c0>; ++ __overlay__ { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&i2c_pins>; ++ clock-frequency = <400000>; ++ status = "okay"; ++ ++ wm8960: wm8960@1a { ++ compatible = "wlf,wm8960"; ++ reg = <0x1a>; ++ }; ++ }; ++ }; ++ ++ fragment@2 { ++ target = <&pio>; ++ __overlay__ { ++ i2c_pins: i2c-pins-3-4 { ++ mux { ++ function = "i2c"; ++ groups = "i2c"; ++ }; ++ }; ++ }; ++ }; ++}; +--- a/arch/arm64/boot/dts/mediatek/Makefile ++++ b/arch/arm64/boot/dts/mediatek/Makefile +@@ -12,6 +12,7 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986a-b + dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986a-bananapi-bpi-r3-nand.dtbo + dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986a-bananapi-bpi-r3-nor.dtbo + dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986a-bananapi-bpi-r3-sd.dtbo ++dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986a-bananapi-bpi-r3-respeaker-2mics.dtbo + dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986a-rfb.dtb + dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986b-rfb.dtb + dtb-$(CONFIG_ARCH_MEDIATEK) += mt8167-pumpkin.dtb diff --git a/lede/target/linux/mediatek/patches-6.1/900-dts-mt7622-bpi-r64-aliases-for-dtoverlay.patch b/lede/target/linux/mediatek/patches-6.1/900-dts-mt7622-bpi-r64-aliases-for-dtoverlay.patch index 2ee9c6299f..87a937be05 100644 --- a/lede/target/linux/mediatek/patches-6.1/900-dts-mt7622-bpi-r64-aliases-for-dtoverlay.patch +++ b/lede/target/linux/mediatek/patches-6.1/900-dts-mt7622-bpi-r64-aliases-for-dtoverlay.patch @@ -1,6 +1,6 @@ --- a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts +++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts -@@ -315,7 +315,7 @@ +@@ -313,7 +313,7 @@ /* Attention: GPIO 90 is used to switch between PCIe@1,0 and * SATA functions. i.e. output-high: PCIe, output-low: SATA */ diff --git a/lede/target/linux/mediatek/patches-6.1/901-arm-add-cmdline-override.patch b/lede/target/linux/mediatek/patches-6.1/901-arm-add-cmdline-override.patch index f8857bdf72..bfca4b6389 100644 --- a/lede/target/linux/mediatek/patches-6.1/901-arm-add-cmdline-override.patch +++ b/lede/target/linux/mediatek/patches-6.1/901-arm-add-cmdline-override.patch @@ -37,7 +37,7 @@ * CONFIG_CMDLINE is meant to be a default in case nothing else --- a/arch/arm64/Kconfig +++ b/arch/arm64/Kconfig -@@ -2239,6 +2239,14 @@ config CMDLINE_FORCE +@@ -2240,6 +2240,14 @@ config CMDLINE_FORCE endchoice diff --git a/lede/target/linux/mediatek/patches-6.1/910-dts-mt7622-bpi-r64-wifi-eeprom.patch b/lede/target/linux/mediatek/patches-6.1/910-dts-mt7622-bpi-r64-wifi-eeprom.patch index 0c7e64a5ee..d1f6a96720 100644 --- a/lede/target/linux/mediatek/patches-6.1/910-dts-mt7622-bpi-r64-wifi-eeprom.patch +++ b/lede/target/linux/mediatek/patches-6.1/910-dts-mt7622-bpi-r64-wifi-eeprom.patch @@ -1,6 +1,6 @@ --- a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts +++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts -@@ -642,5 +642,28 @@ +@@ -640,5 +640,28 @@ }; &wmac { diff --git a/lede/target/linux/mediatek/patches-6.1/911-dts-mt7622-bpi-r64-add-rootdisk.patch b/lede/target/linux/mediatek/patches-6.1/911-dts-mt7622-bpi-r64-add-rootdisk.patch new file mode 100644 index 0000000000..014342aad5 --- /dev/null +++ b/lede/target/linux/mediatek/patches-6.1/911-dts-mt7622-bpi-r64-add-rootdisk.patch @@ -0,0 +1,103 @@ +--- a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts ++++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts +@@ -32,6 +32,9 @@ + chosen { + stdout-path = "serial0:115200n8"; + bootargs = "earlycon=uart8250,mmio32,0x11002000 console=ttyS0,115200n1 swiotlb=512"; ++ rootdisk-emmc = <&emmc_rootfs>; ++ rootdisk-sd = <&sd_rootfs>; ++ rootdisk-snfi = <&ubi_rootfs>; + }; + + cpus { +@@ -234,6 +237,26 @@ + assigned-clocks = <&topckgen CLK_TOP_MSDC30_0_SEL>; + assigned-clock-parents = <&topckgen CLK_TOP_UNIV48M>; + non-removable; ++ ++ card@0 { ++ compatible = "mmc-card"; ++ reg = <0>; ++ ++ block { ++ compatible = "block-device"; ++ partitions { ++ block-partition-env { ++ partname = "ubootenv"; ++ nvmem-layout { ++ compatible = "u-boot,env-layout"; ++ }; ++ }; ++ emmc_rootfs: block-partition-production { ++ partname = "production"; ++ }; ++ }; ++ }; ++ }; + }; + + &mmc1 { +@@ -250,6 +273,26 @@ + vqmmc-supply = <®_3p3v>; + assigned-clocks = <&topckgen CLK_TOP_MSDC30_1_SEL>; + assigned-clock-parents = <&topckgen CLK_TOP_UNIV48M>; ++ ++ card@0 { ++ compatible = "mmc-card"; ++ reg = <0>; ++ ++ block { ++ compatible = "block-device"; ++ partitions { ++ block-partition-env { ++ partname = "ubootenv"; ++ nvmem-layout { ++ compatible = "u-boot,env-layout"; ++ }; ++ }; ++ sd_rootfs: block-partition-production { ++ partname = "production"; ++ }; ++ }; ++ }; ++ }; + }; + + &nandc { +@@ -284,14 +327,29 @@ + }; + + partition@80000 { +- label = "fip"; +- reg = <0x80000 0x200000>; +- read-only; +- }; +- +- ubi: partition@280000 { + label = "ubi"; +- reg = <0x280000 0x7d80000>; ++ reg = <0x80000 0x7f80000>; ++ compatible = "linux,ubi"; ++ ++ volumes { ++ ubi-volume-ubootenv { ++ volname = "ubootenv"; ++ nvmem-layout { ++ compatible = "u-boot,env-redundant-bool-layout"; ++ }; ++ }; ++ ++ ubi-volume-ubootenv2 { ++ volname = "ubootenv2"; ++ nvmem-layout { ++ compatible = "u-boot,env-redundant-bool-layout"; ++ }; ++ }; ++ ++ ubi_rootfs: ubi-volume-fit { ++ volname = "fit"; ++ }; ++ }; + }; + }; + }; diff --git a/lede/target/linux/mediatek/patches-6.1/941-arm64-dts-mt7986-move-cpuboot-in-a-dedicated-node.patch b/lede/target/linux/mediatek/patches-6.1/941-arm64-dts-mt7986-move-cpuboot-in-a-dedicated-node.patch index 7b791b88da..da61f1c050 100644 --- a/lede/target/linux/mediatek/patches-6.1/941-arm64-dts-mt7986-move-cpuboot-in-a-dedicated-node.patch +++ b/lede/target/linux/mediatek/patches-6.1/941-arm64-dts-mt7986-move-cpuboot-in-a-dedicated-node.patch @@ -24,7 +24,7 @@ Signed-off-by: Lorenzo Bianconi }; timer { -@@ -519,10 +513,11 @@ +@@ -541,10 +535,11 @@ interrupt-parent = <&gic>; interrupts = ; memory-region = <&wo_emi0>, <&wo_ilm0>, <&wo_dlm0>, @@ -38,7 +38,7 @@ Signed-off-by: Lorenzo Bianconi }; wed1: wed@15011000 { -@@ -532,10 +527,11 @@ +@@ -554,10 +549,11 @@ interrupt-parent = <&gic>; interrupts = ; memory-region = <&wo_emi1>, <&wo_ilm1>, <&wo_dlm1>, @@ -52,7 +52,7 @@ Signed-off-by: Lorenzo Bianconi }; wo_ccif0: syscon@151a5000 { -@@ -552,6 +548,11 @@ +@@ -574,6 +570,11 @@ interrupts = ; }; diff --git a/lede/target/linux/mediatek/patches-6.1/945-arm64-dts-mt7986-move-ilm-in-a-dedicated-node.patch b/lede/target/linux/mediatek/patches-6.1/945-arm64-dts-mt7986-move-ilm-in-a-dedicated-node.patch index 8accda584f..2f1becd1b8 100644 --- a/lede/target/linux/mediatek/patches-6.1/945-arm64-dts-mt7986-move-ilm-in-a-dedicated-node.patch +++ b/lede/target/linux/mediatek/patches-6.1/945-arm64-dts-mt7986-move-ilm-in-a-dedicated-node.patch @@ -34,7 +34,7 @@ Signed-off-by: Lorenzo Bianconi wo_data: wo-data@4fd80000 { reg = <0 0x4fd80000 0 0x240000>; no-map; -@@ -512,11 +502,10 @@ +@@ -534,11 +524,10 @@ reg = <0 0x15010000 0 0x1000>; interrupt-parent = <&gic>; interrupts = ; @@ -49,7 +49,7 @@ Signed-off-by: Lorenzo Bianconi mediatek,wo-cpuboot = <&wo_cpuboot>; }; -@@ -526,11 +515,10 @@ +@@ -548,11 +537,10 @@ reg = <0 0x15011000 0 0x1000>; interrupt-parent = <&gic>; interrupts = ; @@ -64,7 +64,7 @@ Signed-off-by: Lorenzo Bianconi mediatek,wo-cpuboot = <&wo_cpuboot>; }; -@@ -548,6 +536,16 @@ +@@ -570,6 +558,16 @@ interrupts = ; }; diff --git a/lede/target/linux/mediatek/patches-6.1/946-arm64-dts-mt7986-move-dlm-in-a-dedicated-node.patch b/lede/target/linux/mediatek/patches-6.1/946-arm64-dts-mt7986-move-dlm-in-a-dedicated-node.patch index 6bf7515914..5b52a4934e 100644 --- a/lede/target/linux/mediatek/patches-6.1/946-arm64-dts-mt7986-move-dlm-in-a-dedicated-node.patch +++ b/lede/target/linux/mediatek/patches-6.1/946-arm64-dts-mt7986-move-dlm-in-a-dedicated-node.patch @@ -34,7 +34,7 @@ Signed-off-by: Lorenzo Bianconi }; timer { -@@ -502,10 +492,11 @@ +@@ -524,10 +514,11 @@ reg = <0 0x15010000 0 0x1000>; interrupt-parent = <&gic>; interrupts = ; @@ -48,7 +48,7 @@ Signed-off-by: Lorenzo Bianconi mediatek,wo-cpuboot = <&wo_cpuboot>; }; -@@ -515,10 +506,11 @@ +@@ -537,10 +528,11 @@ reg = <0 0x15011000 0 0x1000>; interrupt-parent = <&gic>; interrupts = ; @@ -62,7 +62,7 @@ Signed-off-by: Lorenzo Bianconi mediatek,wo-cpuboot = <&wo_cpuboot>; }; -@@ -546,6 +538,16 @@ +@@ -568,6 +560,16 @@ reg = <0 0x151f0000 0 0x8000>; }; diff --git a/lede/target/linux/mediatek/patches-6.1/950-smartrg-i2c-led-driver.patch b/lede/target/linux/mediatek/patches-6.1/950-smartrg-i2c-led-driver.patch new file mode 100644 index 0000000000..8b86c50429 --- /dev/null +++ b/lede/target/linux/mediatek/patches-6.1/950-smartrg-i2c-led-driver.patch @@ -0,0 +1,34 @@ +--- + drivers/leds/Kconfig | 10 ++++++++++ + drivers/leds/Makefile | 1 + + 2 files changed, 11 insertions(+) + +--- a/drivers/leds/Kconfig ++++ b/drivers/leds/Kconfig +@@ -874,6 +874,16 @@ source "drivers/leds/flash/Kconfig" + comment "RGB LED drivers" + source "drivers/leds/rgb/Kconfig" + ++config LEDS_SMARTRG_LED ++ tristate "LED support for Adtran SmartRG" ++ depends on LEDS_CLASS && I2C && OF ++ help ++ This option enables support for the Adtran SmartRG platform ++ system LED driver. ++ ++ To compile this driver as a module, choose M here: the module ++ will be called leds-smartrg-system. ++ + comment "LED Triggers" + source "drivers/leds/trigger/Kconfig" + +--- a/drivers/leds/Makefile ++++ b/drivers/leds/Makefile +@@ -76,6 +76,7 @@ obj-$(CONFIG_LEDS_PWM) += leds-pwm.o + obj-$(CONFIG_LEDS_REGULATOR) += leds-regulator.o + obj-$(CONFIG_LEDS_S3C24XX) += leds-s3c24xx.o + obj-$(CONFIG_LEDS_SC27XX_BLTC) += leds-sc27xx-bltc.o ++obj-$(CONFIG_LEDS_SMARTRG_LED) += leds-smartrg-system.o + obj-$(CONFIG_LEDS_SUNFIRE) += leds-sunfire.o + obj-$(CONFIG_LEDS_SYSCON) += leds-syscon.o + obj-$(CONFIG_LEDS_TCA6507) += leds-tca6507.o diff --git a/lede/target/linux/mediatek/patches-6.1/961-net-ethernet-mediatek-split-tx-and-rx-fields-in-mtk_.patch b/lede/target/linux/mediatek/patches-6.1/961-net-ethernet-mediatek-split-tx-and-rx-fields-in-mtk_.patch new file mode 100644 index 0000000000..71cb3006ab --- /dev/null +++ b/lede/target/linux/mediatek/patches-6.1/961-net-ethernet-mediatek-split-tx-and-rx-fields-in-mtk_.patch @@ -0,0 +1,599 @@ +From: Lorenzo Bianconi +Date: Thu, 2 Nov 2023 16:47:07 +0100 +Subject: [PATCH net-next 1/2] net: ethernet: mediatek: split tx and rx fields + in mtk_soc_data struct + +Split tx and rx fields in mtk_soc_data struct. This is a preliminary +patch to roll back to QDMA for MT7986 SoC in order to fix a hw hang +if the device receives a corrupted packet. + +Signed-off-by: Lorenzo Bianconi +--- + drivers/net/ethernet/mediatek/mtk_eth_soc.c | 210 ++++++++++++-------- + drivers/net/ethernet/mediatek/mtk_eth_soc.h | 29 +-- + 2 files changed, 139 insertions(+), 100 deletions(-) + +--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c ++++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c +@@ -1264,7 +1264,7 @@ static int mtk_init_fq_dma(struct mtk_et + eth->scratch_ring = eth->sram_base; + else + eth->scratch_ring = dma_alloc_coherent(eth->dma_dev, +- cnt * soc->txrx.txd_size, ++ cnt * soc->tx.desc_size, + ð->phy_scratch_ring, + GFP_KERNEL); + if (unlikely(!eth->scratch_ring)) +@@ -1280,16 +1280,16 @@ static int mtk_init_fq_dma(struct mtk_et + if (unlikely(dma_mapping_error(eth->dma_dev, dma_addr))) + return -ENOMEM; + +- phy_ring_tail = eth->phy_scratch_ring + soc->txrx.txd_size * (cnt - 1); ++ phy_ring_tail = eth->phy_scratch_ring + soc->tx.desc_size * (cnt - 1); + + for (i = 0; i < cnt; i++) { + struct mtk_tx_dma_v2 *txd; + +- txd = eth->scratch_ring + i * soc->txrx.txd_size; ++ txd = eth->scratch_ring + i * soc->tx.desc_size; + txd->txd1 = dma_addr + i * MTK_QDMA_PAGE_SIZE; + if (i < cnt - 1) + txd->txd2 = eth->phy_scratch_ring + +- (i + 1) * soc->txrx.txd_size; ++ (i + 1) * soc->tx.desc_size; + + txd->txd3 = TX_DMA_PLEN0(MTK_QDMA_PAGE_SIZE); + txd->txd4 = 0; +@@ -1538,7 +1538,7 @@ static int mtk_tx_map(struct sk_buff *sk + if (itxd == ring->last_free) + return -ENOMEM; + +- itx_buf = mtk_desc_to_tx_buf(ring, itxd, soc->txrx.txd_size); ++ itx_buf = mtk_desc_to_tx_buf(ring, itxd, soc->tx.desc_size); + memset(itx_buf, 0, sizeof(*itx_buf)); + + txd_info.addr = dma_map_single(eth->dma_dev, skb->data, txd_info.size, +@@ -1579,7 +1579,7 @@ static int mtk_tx_map(struct sk_buff *sk + + memset(&txd_info, 0, sizeof(struct mtk_tx_dma_desc_info)); + txd_info.size = min_t(unsigned int, frag_size, +- soc->txrx.dma_max_len); ++ soc->tx.dma_max_len); + txd_info.qid = queue; + txd_info.last = i == skb_shinfo(skb)->nr_frags - 1 && + !(frag_size - txd_info.size); +@@ -1592,7 +1592,7 @@ static int mtk_tx_map(struct sk_buff *sk + mtk_tx_set_dma_desc(dev, txd, &txd_info); + + tx_buf = mtk_desc_to_tx_buf(ring, txd, +- soc->txrx.txd_size); ++ soc->tx.desc_size); + if (new_desc) + memset(tx_buf, 0, sizeof(*tx_buf)); + tx_buf->data = (void *)MTK_DMA_DUMMY_DESC; +@@ -1635,7 +1635,7 @@ static int mtk_tx_map(struct sk_buff *sk + } else { + int next_idx; + +- next_idx = NEXT_DESP_IDX(txd_to_idx(ring, txd, soc->txrx.txd_size), ++ next_idx = NEXT_DESP_IDX(txd_to_idx(ring, txd, soc->tx.desc_size), + ring->dma_size); + mtk_w32(eth, next_idx, MT7628_TX_CTX_IDX0); + } +@@ -1644,7 +1644,7 @@ static int mtk_tx_map(struct sk_buff *sk + + err_dma: + do { +- tx_buf = mtk_desc_to_tx_buf(ring, itxd, soc->txrx.txd_size); ++ tx_buf = mtk_desc_to_tx_buf(ring, itxd, soc->tx.desc_size); + + /* unmap dma */ + mtk_tx_unmap(eth, tx_buf, NULL, false); +@@ -1669,7 +1669,7 @@ static int mtk_cal_txd_req(struct mtk_et + for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { + frag = &skb_shinfo(skb)->frags[i]; + nfrags += DIV_ROUND_UP(skb_frag_size(frag), +- eth->soc->txrx.dma_max_len); ++ eth->soc->tx.dma_max_len); + } + } else { + nfrags += skb_shinfo(skb)->nr_frags; +@@ -1810,7 +1810,7 @@ static struct mtk_rx_ring *mtk_get_rx_ri + + ring = ð->rx_ring[i]; + idx = NEXT_DESP_IDX(ring->calc_idx, ring->dma_size); +- rxd = ring->dma + idx * eth->soc->txrx.rxd_size; ++ rxd = ring->dma + idx * eth->soc->rx.desc_size; + if (rxd->rxd2 & RX_DMA_DONE) { + ring->calc_idx_update = true; + return ring; +@@ -1978,7 +1978,7 @@ static int mtk_xdp_submit_frame(struct m + } + htxd = txd; + +- tx_buf = mtk_desc_to_tx_buf(ring, txd, soc->txrx.txd_size); ++ tx_buf = mtk_desc_to_tx_buf(ring, txd, soc->tx.desc_size); + memset(tx_buf, 0, sizeof(*tx_buf)); + htx_buf = tx_buf; + +@@ -1997,7 +1997,7 @@ static int mtk_xdp_submit_frame(struct m + goto unmap; + + tx_buf = mtk_desc_to_tx_buf(ring, txd, +- soc->txrx.txd_size); ++ soc->tx.desc_size); + memset(tx_buf, 0, sizeof(*tx_buf)); + n_desc++; + } +@@ -2035,7 +2035,7 @@ static int mtk_xdp_submit_frame(struct m + } else { + int idx; + +- idx = txd_to_idx(ring, txd, soc->txrx.txd_size); ++ idx = txd_to_idx(ring, txd, soc->tx.desc_size); + mtk_w32(eth, NEXT_DESP_IDX(idx, ring->dma_size), + MT7628_TX_CTX_IDX0); + } +@@ -2046,7 +2046,7 @@ static int mtk_xdp_submit_frame(struct m + + unmap: + while (htxd != txd) { +- tx_buf = mtk_desc_to_tx_buf(ring, htxd, soc->txrx.txd_size); ++ tx_buf = mtk_desc_to_tx_buf(ring, htxd, soc->tx.desc_size); + mtk_tx_unmap(eth, tx_buf, NULL, false); + + htxd->txd3 = TX_DMA_LS0 | TX_DMA_OWNER_CPU; +@@ -2177,7 +2177,7 @@ static int mtk_poll_rx(struct napi_struc + goto rx_done; + + idx = NEXT_DESP_IDX(ring->calc_idx, ring->dma_size); +- rxd = ring->dma + idx * eth->soc->txrx.rxd_size; ++ rxd = ring->dma + idx * eth->soc->rx.desc_size; + data = ring->data[idx]; + + if (!mtk_rx_get_desc(eth, &trxd, rxd)) +@@ -2312,7 +2312,7 @@ static int mtk_poll_rx(struct napi_struc + rxdcsum = &trxd.rxd4; + } + +- if (*rxdcsum & eth->soc->txrx.rx_dma_l4_valid) ++ if (*rxdcsum & eth->soc->rx.dma_l4_valid) + skb->ip_summed = CHECKSUM_UNNECESSARY; + else + skb_checksum_none_assert(skb); +@@ -2436,7 +2436,7 @@ static int mtk_poll_tx_qdma(struct mtk_e + break; + + tx_buf = mtk_desc_to_tx_buf(ring, desc, +- eth->soc->txrx.txd_size); ++ eth->soc->tx.desc_size); + if (!tx_buf->data) + break; + +@@ -2487,7 +2487,7 @@ static int mtk_poll_tx_pdma(struct mtk_e + } + mtk_tx_unmap(eth, tx_buf, &bq, true); + +- desc = ring->dma + cpu * eth->soc->txrx.txd_size; ++ desc = ring->dma + cpu * eth->soc->tx.desc_size; + ring->last_free = desc; + atomic_inc(&ring->free_count); + +@@ -2577,7 +2577,7 @@ static int mtk_napi_rx(struct napi_struc + do { + int rx_done; + +- mtk_w32(eth, eth->soc->txrx.rx_irq_done_mask, ++ mtk_w32(eth, eth->soc->rx.irq_done_mask, + reg_map->pdma.irq_status); + rx_done = mtk_poll_rx(napi, budget - rx_done_total, eth); + rx_done_total += rx_done; +@@ -2593,10 +2593,10 @@ static int mtk_napi_rx(struct napi_struc + return budget; + + } while (mtk_r32(eth, reg_map->pdma.irq_status) & +- eth->soc->txrx.rx_irq_done_mask); ++ eth->soc->rx.irq_done_mask); + + if (napi_complete_done(napi, rx_done_total)) +- mtk_rx_irq_enable(eth, eth->soc->txrx.rx_irq_done_mask); ++ mtk_rx_irq_enable(eth, eth->soc->rx.irq_done_mask); + + return rx_done_total; + } +@@ -2605,7 +2605,7 @@ static int mtk_tx_alloc(struct mtk_eth * + { + const struct mtk_soc_data *soc = eth->soc; + struct mtk_tx_ring *ring = ð->tx_ring; +- int i, sz = soc->txrx.txd_size; ++ int i, sz = soc->tx.desc_size; + struct mtk_tx_dma_v2 *txd; + int ring_size; + u32 ofs, val; +@@ -2728,14 +2728,14 @@ static void mtk_tx_clean(struct mtk_eth + } + if (!MTK_HAS_CAPS(soc->caps, MTK_SRAM) && ring->dma) { + dma_free_coherent(eth->dma_dev, +- ring->dma_size * soc->txrx.txd_size, ++ ring->dma_size * soc->tx.desc_size, + ring->dma, ring->phys); + ring->dma = NULL; + } + + if (ring->dma_pdma) { + dma_free_coherent(eth->dma_dev, +- ring->dma_size * soc->txrx.txd_size, ++ ring->dma_size * soc->tx.desc_size, + ring->dma_pdma, ring->phys_pdma); + ring->dma_pdma = NULL; + } +@@ -2790,15 +2790,15 @@ static int mtk_rx_alloc(struct mtk_eth * + if (!MTK_HAS_CAPS(eth->soc->caps, MTK_SRAM) || + rx_flag != MTK_RX_FLAGS_NORMAL) { + ring->dma = dma_alloc_coherent(eth->dma_dev, +- rx_dma_size * eth->soc->txrx.rxd_size, +- &ring->phys, GFP_KERNEL); ++ rx_dma_size * eth->soc->rx.desc_size, ++ &ring->phys, GFP_KERNEL); + } else { + struct mtk_tx_ring *tx_ring = ð->tx_ring; + + ring->dma = tx_ring->dma + tx_ring_size * +- eth->soc->txrx.txd_size * (ring_no + 1); ++ eth->soc->tx.desc_size * (ring_no + 1); + ring->phys = tx_ring->phys + tx_ring_size * +- eth->soc->txrx.txd_size * (ring_no + 1); ++ eth->soc->tx.desc_size * (ring_no + 1); + } + + if (!ring->dma) +@@ -2809,7 +2809,7 @@ static int mtk_rx_alloc(struct mtk_eth * + dma_addr_t dma_addr; + void *data; + +- rxd = ring->dma + i * eth->soc->txrx.rxd_size; ++ rxd = ring->dma + i * eth->soc->rx.desc_size; + if (ring->page_pool) { + data = mtk_page_pool_get_buff(ring->page_pool, + &dma_addr, GFP_KERNEL); +@@ -2900,7 +2900,7 @@ static void mtk_rx_clean(struct mtk_eth + if (!ring->data[i]) + continue; + +- rxd = ring->dma + i * eth->soc->txrx.rxd_size; ++ rxd = ring->dma + i * eth->soc->rx.desc_size; + if (!rxd->rxd1) + continue; + +@@ -2917,7 +2917,7 @@ static void mtk_rx_clean(struct mtk_eth + + if (!in_sram && ring->dma) { + dma_free_coherent(eth->dma_dev, +- ring->dma_size * eth->soc->txrx.rxd_size, ++ ring->dma_size * eth->soc->rx.desc_size, + ring->dma, ring->phys); + ring->dma = NULL; + } +@@ -3280,7 +3280,7 @@ static void mtk_dma_free(struct mtk_eth + netdev_reset_queue(eth->netdev[i]); + if (!MTK_HAS_CAPS(soc->caps, MTK_SRAM) && eth->scratch_ring) { + dma_free_coherent(eth->dma_dev, +- MTK_QDMA_RING_SIZE * soc->txrx.txd_size, ++ MTK_QDMA_RING_SIZE * soc->tx.desc_size, + eth->scratch_ring, eth->phy_scratch_ring); + eth->scratch_ring = NULL; + eth->phy_scratch_ring = 0; +@@ -3330,7 +3330,7 @@ static irqreturn_t mtk_handle_irq_rx(int + + eth->rx_events++; + if (likely(napi_schedule_prep(ð->rx_napi))) { +- mtk_rx_irq_disable(eth, eth->soc->txrx.rx_irq_done_mask); ++ mtk_rx_irq_disable(eth, eth->soc->rx.irq_done_mask); + __napi_schedule(ð->rx_napi); + } + +@@ -3356,9 +3356,9 @@ static irqreturn_t mtk_handle_irq(int ir + const struct mtk_reg_map *reg_map = eth->soc->reg_map; + + if (mtk_r32(eth, reg_map->pdma.irq_mask) & +- eth->soc->txrx.rx_irq_done_mask) { ++ eth->soc->rx.irq_done_mask) { + if (mtk_r32(eth, reg_map->pdma.irq_status) & +- eth->soc->txrx.rx_irq_done_mask) ++ eth->soc->rx.irq_done_mask) + mtk_handle_irq_rx(irq, _eth); + } + if (mtk_r32(eth, reg_map->tx_irq_mask) & MTK_TX_DONE_INT) { +@@ -3376,10 +3376,10 @@ static void mtk_poll_controller(struct n + struct mtk_eth *eth = mac->hw; + + mtk_tx_irq_disable(eth, MTK_TX_DONE_INT); +- mtk_rx_irq_disable(eth, eth->soc->txrx.rx_irq_done_mask); ++ mtk_rx_irq_disable(eth, eth->soc->rx.irq_done_mask); + mtk_handle_irq_rx(eth->irq[2], dev); + mtk_tx_irq_enable(eth, MTK_TX_DONE_INT); +- mtk_rx_irq_enable(eth, eth->soc->txrx.rx_irq_done_mask); ++ mtk_rx_irq_enable(eth, eth->soc->rx.irq_done_mask); + } + #endif + +@@ -3545,7 +3545,7 @@ static int mtk_open(struct net_device *d + napi_enable(ð->tx_napi); + napi_enable(ð->rx_napi); + mtk_tx_irq_enable(eth, MTK_TX_DONE_INT); +- mtk_rx_irq_enable(eth, soc->txrx.rx_irq_done_mask); ++ mtk_rx_irq_enable(eth, soc->rx.irq_done_mask); + refcount_set(ð->dma_refcnt, 1); + } + else +@@ -3628,7 +3628,7 @@ static int mtk_stop(struct net_device *d + mtk_gdm_config(eth, MTK_GDMA_DROP_ALL); + + mtk_tx_irq_disable(eth, MTK_TX_DONE_INT); +- mtk_rx_irq_disable(eth, eth->soc->txrx.rx_irq_done_mask); ++ mtk_rx_irq_disable(eth, eth->soc->rx.irq_done_mask); + napi_disable(ð->tx_napi); + napi_disable(ð->rx_napi); + +@@ -4107,9 +4107,9 @@ static int mtk_hw_init(struct mtk_eth *e + + /* FE int grouping */ + mtk_w32(eth, MTK_TX_DONE_INT, reg_map->pdma.int_grp); +- mtk_w32(eth, eth->soc->txrx.rx_irq_done_mask, reg_map->pdma.int_grp + 4); ++ mtk_w32(eth, eth->soc->rx.irq_done_mask, reg_map->pdma.int_grp + 4); + mtk_w32(eth, MTK_TX_DONE_INT, reg_map->qdma.int_grp); +- mtk_w32(eth, eth->soc->txrx.rx_irq_done_mask, reg_map->qdma.int_grp + 4); ++ mtk_w32(eth, eth->soc->rx.irq_done_mask, reg_map->qdma.int_grp + 4); + mtk_w32(eth, 0x21021000, MTK_FE_INT_GRP); + + if (mtk_is_netsys_v3_or_greater(eth)) { +@@ -5270,11 +5270,15 @@ static const struct mtk_soc_data mt2701_ + .required_clks = MT7623_CLKS_BITMAP, + .required_pctl = true, + .version = 1, +- .txrx = { +- .txd_size = sizeof(struct mtk_tx_dma), +- .rxd_size = sizeof(struct mtk_rx_dma), +- .rx_irq_done_mask = MTK_RX_DONE_INT, +- .rx_dma_l4_valid = RX_DMA_L4_VALID, ++ .tx = { ++ .desc_size = sizeof(struct mtk_tx_dma), ++ .dma_max_len = MTK_TX_DMA_BUF_LEN, ++ .dma_len_offset = 16, ++ }, ++ .rx = { ++ .desc_size = sizeof(struct mtk_rx_dma), ++ .irq_done_mask = MTK_RX_DONE_INT, ++ .dma_l4_valid = RX_DMA_L4_VALID, + .dma_max_len = MTK_TX_DMA_BUF_LEN, + .dma_len_offset = 16, + }, +@@ -5290,11 +5294,15 @@ static const struct mtk_soc_data mt7621_ + .offload_version = 1, + .hash_offset = 2, + .foe_entry_size = MTK_FOE_ENTRY_V1_SIZE, +- .txrx = { +- .txd_size = sizeof(struct mtk_tx_dma), +- .rxd_size = sizeof(struct mtk_rx_dma), +- .rx_irq_done_mask = MTK_RX_DONE_INT, +- .rx_dma_l4_valid = RX_DMA_L4_VALID, ++ .tx = { ++ .desc_size = sizeof(struct mtk_tx_dma), ++ .dma_max_len = MTK_TX_DMA_BUF_LEN, ++ .dma_len_offset = 16, ++ }, ++ .rx = { ++ .desc_size = sizeof(struct mtk_rx_dma), ++ .irq_done_mask = MTK_RX_DONE_INT, ++ .dma_l4_valid = RX_DMA_L4_VALID, + .dma_max_len = MTK_TX_DMA_BUF_LEN, + .dma_len_offset = 16, + }, +@@ -5312,11 +5320,15 @@ static const struct mtk_soc_data mt7622_ + .hash_offset = 2, + .has_accounting = true, + .foe_entry_size = MTK_FOE_ENTRY_V1_SIZE, +- .txrx = { +- .txd_size = sizeof(struct mtk_tx_dma), +- .rxd_size = sizeof(struct mtk_rx_dma), +- .rx_irq_done_mask = MTK_RX_DONE_INT, +- .rx_dma_l4_valid = RX_DMA_L4_VALID, ++ .tx = { ++ .desc_size = sizeof(struct mtk_tx_dma), ++ .dma_max_len = MTK_TX_DMA_BUF_LEN, ++ .dma_len_offset = 16, ++ }, ++ .rx = { ++ .desc_size = sizeof(struct mtk_rx_dma), ++ .irq_done_mask = MTK_RX_DONE_INT, ++ .dma_l4_valid = RX_DMA_L4_VALID, + .dma_max_len = MTK_TX_DMA_BUF_LEN, + .dma_len_offset = 16, + }, +@@ -5333,11 +5345,15 @@ static const struct mtk_soc_data mt7623_ + .hash_offset = 2, + .foe_entry_size = MTK_FOE_ENTRY_V1_SIZE, + .disable_pll_modes = true, +- .txrx = { +- .txd_size = sizeof(struct mtk_tx_dma), +- .rxd_size = sizeof(struct mtk_rx_dma), +- .rx_irq_done_mask = MTK_RX_DONE_INT, +- .rx_dma_l4_valid = RX_DMA_L4_VALID, ++ .tx = { ++ .desc_size = sizeof(struct mtk_tx_dma), ++ .dma_max_len = MTK_TX_DMA_BUF_LEN, ++ .dma_len_offset = 16, ++ }, ++ .rx = { ++ .desc_size = sizeof(struct mtk_rx_dma), ++ .irq_done_mask = MTK_RX_DONE_INT, ++ .dma_l4_valid = RX_DMA_L4_VALID, + .dma_max_len = MTK_TX_DMA_BUF_LEN, + .dma_len_offset = 16, + }, +@@ -5352,11 +5368,15 @@ static const struct mtk_soc_data mt7629_ + .required_pctl = false, + .has_accounting = true, + .version = 1, +- .txrx = { +- .txd_size = sizeof(struct mtk_tx_dma), +- .rxd_size = sizeof(struct mtk_rx_dma), +- .rx_irq_done_mask = MTK_RX_DONE_INT, +- .rx_dma_l4_valid = RX_DMA_L4_VALID, ++ .tx = { ++ .desc_size = sizeof(struct mtk_tx_dma), ++ .dma_max_len = MTK_TX_DMA_BUF_LEN, ++ .dma_len_offset = 16, ++ }, ++ .rx = { ++ .desc_size = sizeof(struct mtk_rx_dma), ++ .irq_done_mask = MTK_RX_DONE_INT, ++ .dma_l4_valid = RX_DMA_L4_VALID, + .dma_max_len = MTK_TX_DMA_BUF_LEN, + .dma_len_offset = 16, + }, +@@ -5374,11 +5394,15 @@ static const struct mtk_soc_data mt7981_ + .hash_offset = 4, + .has_accounting = true, + .foe_entry_size = MTK_FOE_ENTRY_V2_SIZE, +- .txrx = { +- .txd_size = sizeof(struct mtk_tx_dma_v2), +- .rxd_size = sizeof(struct mtk_rx_dma_v2), +- .rx_irq_done_mask = MTK_RX_DONE_INT_V2, +- .rx_dma_l4_valid = RX_DMA_L4_VALID_V2, ++ .tx = { ++ .desc_size = sizeof(struct mtk_tx_dma_v2), ++ .dma_max_len = MTK_TX_DMA_BUF_LEN_V2, ++ .dma_len_offset = 8, ++ }, ++ .rx = { ++ .desc_size = sizeof(struct mtk_rx_dma_v2), ++ .irq_done_mask = MTK_RX_DONE_INT_V2, ++ .dma_l4_valid = RX_DMA_L4_VALID_V2, + .dma_max_len = MTK_TX_DMA_BUF_LEN_V2, + .dma_len_offset = 8, + }, +@@ -5396,11 +5420,15 @@ static const struct mtk_soc_data mt7986_ + .hash_offset = 4, + .has_accounting = true, + .foe_entry_size = MTK_FOE_ENTRY_V2_SIZE, +- .txrx = { +- .txd_size = sizeof(struct mtk_tx_dma_v2), +- .rxd_size = sizeof(struct mtk_rx_dma_v2), +- .rx_irq_done_mask = MTK_RX_DONE_INT_V2, +- .rx_dma_l4_valid = RX_DMA_L4_VALID_V2, ++ .tx = { ++ .desc_size = sizeof(struct mtk_tx_dma_v2), ++ .dma_max_len = MTK_TX_DMA_BUF_LEN_V2, ++ .dma_len_offset = 8, ++ }, ++ .rx = { ++ .desc_size = sizeof(struct mtk_rx_dma_v2), ++ .irq_done_mask = MTK_RX_DONE_INT_V2, ++ .dma_l4_valid = RX_DMA_L4_VALID_V2, + .dma_max_len = MTK_TX_DMA_BUF_LEN_V2, + .dma_len_offset = 8, + }, +@@ -5418,11 +5446,15 @@ static const struct mtk_soc_data mt7988_ + .hash_offset = 4, + .has_accounting = true, + .foe_entry_size = MTK_FOE_ENTRY_V3_SIZE, +- .txrx = { +- .txd_size = sizeof(struct mtk_tx_dma_v2), +- .rxd_size = sizeof(struct mtk_rx_dma_v2), +- .rx_irq_done_mask = MTK_RX_DONE_INT_V2, +- .rx_dma_l4_valid = RX_DMA_L4_VALID_V2, ++ .tx = { ++ .desc_size = sizeof(struct mtk_tx_dma_v2), ++ .dma_max_len = MTK_TX_DMA_BUF_LEN_V2, ++ .dma_len_offset = 8, ++ }, ++ .rx = { ++ .desc_size = sizeof(struct mtk_rx_dma_v2), ++ .irq_done_mask = MTK_RX_DONE_INT_V2, ++ .dma_l4_valid = RX_DMA_L4_VALID_V2, + .dma_max_len = MTK_TX_DMA_BUF_LEN_V2, + .dma_len_offset = 8, + }, +@@ -5435,11 +5467,15 @@ static const struct mtk_soc_data rt5350_ + .required_clks = MT7628_CLKS_BITMAP, + .required_pctl = false, + .version = 1, +- .txrx = { +- .txd_size = sizeof(struct mtk_tx_dma), +- .rxd_size = sizeof(struct mtk_rx_dma), +- .rx_irq_done_mask = MTK_RX_DONE_INT, +- .rx_dma_l4_valid = RX_DMA_L4_VALID_PDMA, ++ .tx = { ++ .desc_size = sizeof(struct mtk_tx_dma), ++ .dma_max_len = MTK_TX_DMA_BUF_LEN, ++ .dma_len_offset = 16, ++ }, ++ .rx = { ++ .desc_size = sizeof(struct mtk_rx_dma), ++ .irq_done_mask = MTK_RX_DONE_INT, ++ .dma_l4_valid = RX_DMA_L4_VALID_PDMA, + .dma_max_len = MTK_TX_DMA_BUF_LEN, + .dma_len_offset = 16, + }, +--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h ++++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h +@@ -327,8 +327,8 @@ + /* QDMA descriptor txd3 */ + #define TX_DMA_OWNER_CPU BIT(31) + #define TX_DMA_LS0 BIT(30) +-#define TX_DMA_PLEN0(x) (((x) & eth->soc->txrx.dma_max_len) << eth->soc->txrx.dma_len_offset) +-#define TX_DMA_PLEN1(x) ((x) & eth->soc->txrx.dma_max_len) ++#define TX_DMA_PLEN0(x) (((x) & eth->soc->tx.dma_max_len) << eth->soc->tx.dma_len_offset) ++#define TX_DMA_PLEN1(x) ((x) & eth->soc->tx.dma_max_len) + #define TX_DMA_SWC BIT(14) + #define TX_DMA_PQID GENMASK(3, 0) + #define TX_DMA_ADDR64_MASK GENMASK(3, 0) +@@ -348,8 +348,8 @@ + /* QDMA descriptor rxd2 */ + #define RX_DMA_DONE BIT(31) + #define RX_DMA_LSO BIT(30) +-#define RX_DMA_PREP_PLEN0(x) (((x) & eth->soc->txrx.dma_max_len) << eth->soc->txrx.dma_len_offset) +-#define RX_DMA_GET_PLEN0(x) (((x) >> eth->soc->txrx.dma_len_offset) & eth->soc->txrx.dma_max_len) ++#define RX_DMA_PREP_PLEN0(x) (((x) & eth->soc->rx.dma_max_len) << eth->soc->rx.dma_len_offset) ++#define RX_DMA_GET_PLEN0(x) (((x) >> eth->soc->rx.dma_len_offset) & eth->soc->rx.dma_max_len) + #define RX_DMA_VTAG BIT(15) + #define RX_DMA_ADDR64_MASK GENMASK(3, 0) + #if IS_ENABLED(CONFIG_64BIT) +@@ -1209,10 +1209,9 @@ struct mtk_reg_map { + * @foe_entry_size Foe table entry size. + * @has_accounting Bool indicating support for accounting of + * offloaded flows. +- * @txd_size Tx DMA descriptor size. +- * @rxd_size Rx DMA descriptor size. +- * @rx_irq_done_mask Rx irq done register mask. +- * @rx_dma_l4_valid Rx DMA valid register mask. ++ * @desc_size Tx/Rx DMA descriptor size. ++ * @irq_done_mask Rx irq done register mask. ++ * @dma_l4_valid Rx DMA valid register mask. + * @dma_max_len Max DMA tx/rx buffer length. + * @dma_len_offset Tx/Rx DMA length field offset. + */ +@@ -1230,13 +1229,17 @@ struct mtk_soc_data { + bool has_accounting; + bool disable_pll_modes; + struct { +- u32 txd_size; +- u32 rxd_size; +- u32 rx_irq_done_mask; +- u32 rx_dma_l4_valid; ++ u32 desc_size; + u32 dma_max_len; + u32 dma_len_offset; +- } txrx; ++ } tx; ++ struct { ++ u32 desc_size; ++ u32 irq_done_mask; ++ u32 dma_l4_valid; ++ u32 dma_max_len; ++ u32 dma_len_offset; ++ } rx; + }; + + #define MTK_DMA_MONITOR_TIMEOUT msecs_to_jiffies(1000) diff --git a/lede/target/linux/mediatek/patches-6.1/962-net-ethernet-mediatek-use-QDMA-instead-of-ADMAv2-on-.patch b/lede/target/linux/mediatek/patches-6.1/962-net-ethernet-mediatek-use-QDMA-instead-of-ADMAv2-on-.patch new file mode 100644 index 0000000000..8b7d5c0a1c --- /dev/null +++ b/lede/target/linux/mediatek/patches-6.1/962-net-ethernet-mediatek-use-QDMA-instead-of-ADMAv2-on-.patch @@ -0,0 +1,123 @@ +From: Daniel Golle +Date: Tue, 10 Oct 2023 21:06:43 +0200 +Subject: [PATCH net-next 2/2] net: ethernet: mediatek: use QDMA instead of + ADMAv2 on MT7981 and MT7986 + +ADMA is plagued by RX hangs which can't easily detected and happen upon +receival of a corrupted package. +Use QDMA just like on netsys v1 which is also still present and usable, and +doesn't suffer from that problem. + +Co-developed-by: Lorenzo Bianconi +Signed-off-by: Lorenzo Bianconi +Signed-off-by: Daniel Golle +--- + drivers/net/ethernet/mediatek/mtk_eth_soc.c | 46 ++++++++++----------- + 1 file changed, 23 insertions(+), 23 deletions(-) + +--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c ++++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c +@@ -110,16 +110,16 @@ static const struct mtk_reg_map mt7986_r + .tx_irq_mask = 0x461c, + .tx_irq_status = 0x4618, + .pdma = { +- .rx_ptr = 0x6100, +- .rx_cnt_cfg = 0x6104, +- .pcrx_ptr = 0x6108, +- .glo_cfg = 0x6204, +- .rst_idx = 0x6208, +- .delay_irq = 0x620c, +- .irq_status = 0x6220, +- .irq_mask = 0x6228, +- .adma_rx_dbg0 = 0x6238, +- .int_grp = 0x6250, ++ .rx_ptr = 0x4100, ++ .rx_cnt_cfg = 0x4104, ++ .pcrx_ptr = 0x4108, ++ .glo_cfg = 0x4204, ++ .rst_idx = 0x4208, ++ .delay_irq = 0x420c, ++ .irq_status = 0x4220, ++ .irq_mask = 0x4228, ++ .adma_rx_dbg0 = 0x4238, ++ .int_grp = 0x4250, + }, + .qdma = { + .qtx_cfg = 0x4400, +@@ -1232,7 +1232,7 @@ static bool mtk_rx_get_desc(struct mtk_e + rxd->rxd1 = READ_ONCE(dma_rxd->rxd1); + rxd->rxd3 = READ_ONCE(dma_rxd->rxd3); + rxd->rxd4 = READ_ONCE(dma_rxd->rxd4); +- if (mtk_is_netsys_v2_or_greater(eth)) { ++ if (mtk_is_netsys_v3_or_greater(eth)) { + rxd->rxd5 = READ_ONCE(dma_rxd->rxd5); + rxd->rxd6 = READ_ONCE(dma_rxd->rxd6); + } +@@ -2184,7 +2184,7 @@ static int mtk_poll_rx(struct napi_struc + break; + + /* find out which mac the packet come from. values start at 1 */ +- if (mtk_is_netsys_v2_or_greater(eth)) { ++ if (mtk_is_netsys_v3_or_greater(eth)) { + u32 val = RX_DMA_GET_SPORT_V2(trxd.rxd5); + + switch (val) { +@@ -2296,7 +2296,7 @@ static int mtk_poll_rx(struct napi_struc + skb->dev = netdev; + bytes += skb->len; + +- if (mtk_is_netsys_v2_or_greater(eth)) { ++ if (mtk_is_netsys_v3_or_greater(eth)) { + reason = FIELD_GET(MTK_RXD5_PPE_CPU_REASON, trxd.rxd5); + hash = trxd.rxd5 & MTK_RXD5_FOE_ENTRY; + if (hash != MTK_RXD5_FOE_ENTRY) +@@ -2846,7 +2846,7 @@ static int mtk_rx_alloc(struct mtk_eth * + + rxd->rxd3 = 0; + rxd->rxd4 = 0; +- if (mtk_is_netsys_v2_or_greater(eth)) { ++ if (mtk_is_netsys_v3_or_greater(eth)) { + rxd->rxd5 = 0; + rxd->rxd6 = 0; + rxd->rxd7 = 0; +@@ -4053,7 +4053,7 @@ static int mtk_hw_init(struct mtk_eth *e + else + mtk_hw_reset(eth); + +- if (mtk_is_netsys_v2_or_greater(eth)) { ++ if (mtk_is_netsys_v3_or_greater(eth)) { + /* Set FE to PDMAv2 if necessary */ + val = mtk_r32(eth, MTK_FE_GLO_MISC); + mtk_w32(eth, val | BIT(4), MTK_FE_GLO_MISC); +@@ -5400,11 +5400,11 @@ static const struct mtk_soc_data mt7981_ + .dma_len_offset = 8, + }, + .rx = { +- .desc_size = sizeof(struct mtk_rx_dma_v2), +- .irq_done_mask = MTK_RX_DONE_INT_V2, ++ .desc_size = sizeof(struct mtk_rx_dma), ++ .irq_done_mask = MTK_RX_DONE_INT, + .dma_l4_valid = RX_DMA_L4_VALID_V2, +- .dma_max_len = MTK_TX_DMA_BUF_LEN_V2, +- .dma_len_offset = 8, ++ .dma_max_len = MTK_TX_DMA_BUF_LEN, ++ .dma_len_offset = 16, + }, + }; + +@@ -5426,11 +5426,11 @@ static const struct mtk_soc_data mt7986_ + .dma_len_offset = 8, + }, + .rx = { +- .desc_size = sizeof(struct mtk_rx_dma_v2), +- .irq_done_mask = MTK_RX_DONE_INT_V2, ++ .desc_size = sizeof(struct mtk_rx_dma), ++ .irq_done_mask = MTK_RX_DONE_INT, + .dma_l4_valid = RX_DMA_L4_VALID_V2, +- .dma_max_len = MTK_TX_DMA_BUF_LEN_V2, +- .dma_len_offset = 8, ++ .dma_max_len = MTK_TX_DMA_BUF_LEN, ++ .dma_len_offset = 16, + }, + }; + diff --git a/lede/target/linux/mediatek/patches-6.1/963-net-ethernet-mtk_eth_soc-fix-WED-wifi-reset.patch b/lede/target/linux/mediatek/patches-6.1/963-net-ethernet-mtk_eth_soc-fix-WED-wifi-reset.patch new file mode 100644 index 0000000000..11b52d07ab --- /dev/null +++ b/lede/target/linux/mediatek/patches-6.1/963-net-ethernet-mtk_eth_soc-fix-WED-wifi-reset.patch @@ -0,0 +1,49 @@ +From: Felix Fietkau +Date: Thu, 18 Jan 2024 12:51:32 +0100 +Subject: [PATCH] net: ethernet: mtk_eth_soc: fix WED + wifi reset + +The WLAN + WED reset sequence relies on being able to receive interrupts from +the card, in order to synchronize individual steps with the firmware. +When WED is stopped, leave interrupts running and rely on the driver turning +off unwanted ones. +WED DMA also needs to be disabled before resetting. + +Fixes: f78cd9c783e0 ("net: ethernet: mtk_wed: update mtk_wed_stop") +Signed-off-by: Felix Fietkau +--- + +--- a/drivers/net/ethernet/mediatek/mtk_wed.c ++++ b/drivers/net/ethernet/mediatek/mtk_wed.c +@@ -1071,13 +1071,13 @@ mtk_wed_dma_disable(struct mtk_wed_devic + static void + mtk_wed_stop(struct mtk_wed_device *dev) + { ++ mtk_wed_dma_disable(dev); + mtk_wed_set_ext_int(dev, false); + + wed_w32(dev, MTK_WED_WPDMA_INT_TRIGGER, 0); + wed_w32(dev, MTK_WED_WDMA_INT_TRIGGER, 0); + wdma_w32(dev, MTK_WDMA_INT_MASK, 0); + wdma_w32(dev, MTK_WDMA_INT_GRP2, 0); +- wed_w32(dev, MTK_WED_WPDMA_INT_MASK, 0); + + if (!mtk_wed_get_rx_capa(dev)) + return; +@@ -1090,7 +1090,6 @@ static void + mtk_wed_deinit(struct mtk_wed_device *dev) + { + mtk_wed_stop(dev); +- mtk_wed_dma_disable(dev); + + wed_clr(dev, MTK_WED_CTRL, + MTK_WED_CTRL_WDMA_INT_AGENT_EN | +@@ -2621,9 +2620,6 @@ mtk_wed_irq_get(struct mtk_wed_device *d + static void + mtk_wed_irq_set_mask(struct mtk_wed_device *dev, u32 mask) + { +- if (!dev->running) +- return; +- + mtk_wed_set_ext_int(dev, !!mask); + wed_w32(dev, MTK_WED_INT_MASK, mask); + } diff --git a/openwrt-packages/adguardhome/Makefile b/openwrt-packages/adguardhome/Makefile index eb773a6404..f30b58dd29 100644 --- a/openwrt-packages/adguardhome/Makefile +++ b/openwrt-packages/adguardhome/Makefile @@ -6,12 +6,12 @@ include $(TOPDIR)/rules.mk PKG_NAME:=adguardhome -PKG_VERSION:=0.107.51 +PKG_VERSION:=0.107.52 PKG_RELEASE:=1 PKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.gz PKG_SOURCE_URL:=https://codeload.github.com/AdguardTeam/AdGuardHome/tar.gz/v$(PKG_VERSION)? -PKG_HASH:=dea9685282e55940925ff7211f7d72072de5b98134c8f01d5569c04284681650 +PKG_HASH:=de6d99c4420d131b76e5d22b58ac91159e74e5783f02ada8b2f993f353e254f9 PKG_LICENSE:=GPL-3.0-only PKG_LICENSE_FILES:=LICENSE.txt @@ -57,7 +57,7 @@ define Download/adguardhome-frontend URL:=https://github.com/AdguardTeam/AdGuardHome/releases/download/v$(PKG_VERSION)/ URL_FILE:=AdGuardHome_frontend.tar.gz FILE:=$(FRONTEND_FILE) - HASH:=253d05185865840e14e841e4245c3fdb0fdcca28649902303d3869e0bd07cfd7 + HASH:=af9ae57b55a09a0aaf7c9a69a46734827443f98135d4c4b176874de3f9a449d8 endef define Build/Prepare diff --git a/openwrt-packages/luci-app-store/Makefile b/openwrt-packages/luci-app-store/Makefile index 7bbdee446c..c26cb7abda 100644 --- a/openwrt-packages/luci-app-store/Makefile +++ b/openwrt-packages/luci-app-store/Makefile @@ -11,7 +11,7 @@ LUCI_DEPENDS:=+curl +opkg +luci-base +tar +coreutils +coreutils-stat +libuci-lua LUCI_EXTRA_DEPENDS:=luci-lib-taskd (>=1.0.19) LUCI_PKGARCH:=all -PKG_VERSION:=0.1.23-0 +PKG_VERSION:=0.1.24-0 # PKG_RELEASE MUST be empty for luci.mk PKG_RELEASE:= diff --git a/openwrt-packages/luci-app-store/luasrc/controller/store.lua b/openwrt-packages/luci-app-store/luasrc/controller/store.lua index b7561e6d85..dfa25459e0 100644 --- a/openwrt-packages/luci-app-store/luasrc/controller/store.lua +++ b/openwrt-packages/luci-app-store/luasrc/controller/store.lua @@ -102,23 +102,32 @@ local function vue_lang() return lang end +local function flock(file, type) + local nixio = require "nixio" + local oflags = nixio.open_flags("wronly", "creat") + local lock, code, msg = nixio.open(file, oflags) + if not lock then + return nil, "Open lock failed: " .. msg + end + + -- Acquire lock + local stat, code, msg = lock:lock(type) + if not stat then + lock:close() + return nil, "Lock failed: " .. msg + end + return lock, nil +end + local function is_exec(cmd, async) local nixio = require "nixio" local os = require "os" local fs = require "nixio.fs" local rshift = nixio.bit.rshift - local oflags = nixio.open_flags("wronly", "creat") - local lock, code, msg = nixio.open("/var/lock/istore.lock", oflags) - if not lock then - return 255, "", "Open lock failed: " .. msg - end - - -- Acquire lock - local stat, code, msg = lock:lock("tlock") - if not stat then - lock:close() - return 255, "", "Lock failed: " .. msg + local lock, msg = flock("/var/lock/istore.lock", "tlock") + if lock == nil then + return 255, "", msg end if async then @@ -229,6 +238,69 @@ function validate_pkgname(val) return (val ~= nil and val:match("^[a-zA-Z0-9_-]+$") ~= nil) end +local function get_installed_and_cache() + local metadir = "/usr/lib/opkg/meta" + local cachedir = "/tmp/cache/istore" + local cachefile = cachedir .. "/installed.json" + local metapkgpre = "app-meta-" + local nixio = require "nixio" + local fs = require "nixio.fs" + local ipkg = require "luci.model.ipkg" + local jsonc = require "luci.jsonc" + local result = {} + local lock, msg = flock("/var/lock/istore-installed.lock", "lock") + local ms = fs.stat(metadir) + local cs = fs.stat(cachefile) + if not ms then + result = {} + elseif not cs or ms["mtime"] > cs["mtime"] then + local itr = fs.dir(metadir) + local data = {} + if itr then + local i18n = require("luci.i18n") + local pkg + for pkg in itr do + if pkg:match("^.*%.json$") then + local metadata = fs.readfile(metadir .. "/" .. pkg) + if metadata ~= nil then + local meta = jsonc.parse(metadata) + if meta == nil then + local name = pkg:gsub("^(.-)%.json$", "%1") + meta = { + name = name, + title = "{ " .. name .. " }", + author = "", + version = "0.0.0", + description = i18n.translate("This package is broken! Please reinstall or uninstall it."), + depends = {}, + tags = {"broken"}, + broken = true, + } + end + local metapkg = metapkgpre .. meta.name + local status = ipkg.status(metapkg) + if next(status) ~= nil then + meta.time = tonumber(status[metapkg]["Installed-Time"]) + data[#data+1] = meta + end + end + end + end + end + result = data + fs.mkdirr(cachedir) + local oflags = nixio.open_flags("rdwr", "creat") + local mfile, code, msg = nixio.open(cachefile, oflags) + mfile:writeall(jsonc.stringify(result)) + mfile:close() + else + result = jsonc.parse(fs.readfile(cachefile) or "") + end + lock:lock("ulock") + lock:close() + return result +end + function store_action(param) local metadir = "/usr/lib/opkg/meta" local metapkgpre = "app-meta-" @@ -261,39 +333,7 @@ function store_action(param) ret = meta elseif action == "installed" then - local itr = fs.dir(metadir) - local data = {} - if itr then - local pkg - for pkg in itr do - if pkg:match("^.*%.json$") then - local metadata = fs.readfile(metadir .. "/" .. pkg) - if metadata ~= nil then - local meta = json_parse(metadata) - if meta == nil then - local i18n = require("luci.i18n") - local name = pkg:gsub("^(.-)%.json$", "%1") - meta = { - name = name, - title = "{ " .. name .. " }", - author = "", - version = "0.0.0", - description = i18n.translate("This package is broken! Please reinstall or uninstall it."), - depends = {}, - tags = {"broken"}, - broken = true, - } - end - local metapkg = metapkgpre .. meta.name - local status = ipkg.status(metapkg) - if next(status) ~= nil then - meta.time = tonumber(status[metapkg]["Installed-Time"]) - data[#data+1] = meta - end - end - end - end - end + local data = get_installed_and_cache() ret = data else local pkg = luci.http.formvalue("package") @@ -419,33 +459,71 @@ end function entrysh() local package = luci.http.formvalue("package") + local update = luci.http.formvalue("update") local hostname = luci.http.formvalue("hostname") - if hostname == nil or hostname == "" or not validate_pkgname(package) then + if hostname == nil or hostname == "" or not hostname:match("^[a-zA-Z0-9_%[][a-zA-Z0-9_%-%.%:%]]*$") then luci.http.status(400, "Bad Request") return end + local nixio = require "nixio" + local fs = require "nixio.fs" + local hostnameq = luci.util.shellquote(hostname) + local cachedir = "/tmp/cache/istore/entrysh/" .. hostname + fs.mkdirr(cachedir) - local result - local entryfile = "/usr/libexec/istoree/" .. package .. ".sh" - if nixio.fs.access(entryfile) then - local o = luci.util.exec(entryfile .. " status " .. luci.util.shellquote(hostname)) - if o == nil or o == "" then - result = {code=500, msg="entrysh execute failed"} - else - local jsonc = require "luci.jsonc" - local json_parse = jsonc.parse - local status = json_parse(o) - if status == nil then - result = {code=500, msg="json parse failed: " .. o} + local jsonc = require "luci.jsonc" + local results = {} + local errors = {} + local force = update == "1" + local candidate = nil + if package ~= nil and package ~= "" then + candidate = luci.util.split(package, ",") + end + local installed = get_installed_and_cache() + local lock, msg = flock("/var/lock/istore-entrysh.lock", "lock") + local meta + for _, meta in ipairs(installed) do + if meta.autoconf ~= nil and meta.uci ~= nil and luci.util.contains(meta.autoconf, "entrysh") + and (candidate == nil or luci.util.contains(candidate, meta.name)) then + local entryfile = "/usr/libexec/istoree/" .. meta.name .. ".sh" + local ucifile = "/etc/config/" .. meta.uci + local cachefile = cachedir .. "/" .. meta.name .. ".json" + local status = nil + if not force then + local us = fs.stat(ucifile) + local cs = fs.stat(cachefile) + if cs ~= nil and us["mtime"] <= cs["mtime"] then + status = jsonc.parse(fs.readfile(cachefile) or "") + end + end + if status ~= nil then + results[#results+1] = status + elseif fs.access(entryfile) then + local o = luci.util.exec(entryfile .. " status " .. hostnameq) + if o == nil or o == "" then + errors[#errors+1] = {app=meta.name, code=500, msg="entrysh execute failed"} + else + status = jsonc.parse(o) + if status == nil then + errors[#errors+1] = {app=meta.name, code=500, msg="json parse failed: " .. o} + else + results[#results+1] = status + local oflags = nixio.open_flags("rdwr", "creat") + local mfile, code, msg = nixio.open(cachefile, oflags) + mfile:writeall(jsonc.stringify(status)) + mfile:close() + end + end else - result = {code=200, status=status} + errors[#errors+1] = {app=meta.name, code=404, msg="entrysh of this package not found"} end end - else - result = {code=404, msg="entrysh of this package not found"} end + lock:lock("ulock") + lock:close() + luci.http.prepare_content("application/json") - luci.http.write_json(result) + luci.http.write_json({code=200, status=results, errors=errors}) end function docker_check_dir() diff --git a/openwrt-packages/luci-app-store/swagger.yaml b/openwrt-packages/luci-app-store/swagger.yaml index ac1f89d525..fcd475525e 100644 --- a/openwrt-packages/luci-app-store/swagger.yaml +++ b/openwrt-packages/luci-app-store/swagger.yaml @@ -246,18 +246,23 @@ paths: - in: "query" name: "package" type: string - required: true - description: "包名，例如aria2" + description: "包名，例如aria2。支持英文逗号分隔多个包名。如果未提供，则返回所有支持entrysh的包" - in: "query" name: "hostname" type: string required: true description: "主机名，不包含端口。前端应该使用location.hostname获取" + - in: "query" + name: "update" + type: integer + description: "如果为1则强制更新缓存" responses: "200": description: OK schema: $ref: "#/definitions/ResponseStoreEntrysh" + "400": + description: Bad Request。hostname不合法 /cgi-bin/luci/admin/store/docker_check_dir: get: tags: @@ -461,27 +466,45 @@ definitions: code: type: integer description: "为200时" - msg: - type: string - description: "code不为200时显示错误信息" status: - type: object - description: "状态和入口信息，不同插件可能有些不一样，仅列出常用公共参数" - properties: - app: - type: string - description: "插件名称，跟请求的包名一致" - docker: - type: boolean - description: "如果是docker插件" - running: - type: boolean - description: "是否运行中" - deployed: - type: boolean - description: "如果是docker插件且未运行，则是否已经部署" - web: - type: string - description: "web端跳转url" - + description: "处理成功的结果集" + type: array + items: + type: object + description: "状态和入口信息，不同插件可能有些不一样，仅列出常用公共参数" + properties: + app: + type: string + description: "插件名称" + docker: + type: boolean + description: "如果是docker插件" + running: + type: boolean + description: "是否运行中" + deployed: + type: boolean + description: "如果是docker插件且未运行，则是否已经部署" + web: + type: string + description: "url" + href: + type: string + description: "web端直接跳转url" + errors: + description: "处理失败的结果集" + type: array + items: + type: object + description: "失败信息" + properties: + app: + type: string + description: "插件名称" + code: + type: integer + description: "404或500" + msg: + type: string + description: "错误信息" diff --git a/sing-box/docs/changelog.md b/sing-box/docs/changelog.md index 762c8cb395..10c624c488 100644 --- a/sing-box/docs/changelog.md +++ b/sing-box/docs/changelog.md @@ -4,6 +4,8 @@ icon: material/alert-decagram #### 1.10.0-alpha.19 +* Add `rule-set decompile` command +* Add IP address support for `rule-set match` command * Fixes and improvements #### 1.10.0-alpha.18 diff --git a/sing-box/go.mod b/sing-box/go.mod index c45159fb23..3194287af5 100644 --- a/sing-box/go.mod +++ b/sing-box/go.mod @@ -82,7 +82,6 @@ require ( github.com/pmezard/go-difflib v1.0.0 // indirect github.com/quic-go/qpack v0.4.0 // indirect github.com/quic-go/qtls-go1-20 v0.4.1 // indirect - github.com/sagernet/fswatch v0.1.1 // indirect github.com/sagernet/netlink v0.0.0-20240612041022-b9a21c07ac6a // indirect github.com/sagernet/nftables v0.3.0-beta.4 // indirect github.com/spf13/pflag v1.0.5 // indirect diff --git a/small/v2ray-geodata/Makefile b/small/v2ray-geodata/Makefile index 5b35ae1acb..458b589fb3 100644 --- a/small/v2ray-geodata/Makefile +++ b/small/v2ray-geodata/Makefile @@ -12,13 +12,13 @@ PKG_MAINTAINER:=Tianling Shen include $(INCLUDE_DIR)/package.mk -GEOIP_VER:=202406270043 +GEOIP_VER:=202407040043 GEOIP_FILE:=geoip.dat.$(GEOIP_VER) define Download/geoip URL:=https://github.com/v2fly/geoip/releases/download/$(GEOIP_VER)/ URL_FILE:=geoip.dat FILE:=$(GEOIP_FILE) - HASH:=84ef45f035a4e44ced0be85e453d07850ae1ebeb9bf99a788ef4d924dedbb5a9 + HASH:=c55f7e9866acb963873b0d907404b395bd3b7447470b5407d79868c3d1c0cb04 endef GEOSITE_VER:=20240624143214 diff --git a/suyu/README.md b/suyu/README.md index 6fa5ed4d2e..c119a5849d 100644 --- a/suyu/README.md +++ b/suyu/README.md @@ -7,7 +7,7 @@ SPDX-License-Identifier: GPL-3.0-or-later **Note**: We do not support or condone piracy in any form. In order to use suyu, you'll need keys from your real Switch system, and games which you have legally obtained and paid for. We do not intend to make money or profit from this project. We're in need of developers. Please join our chat below if you want to contribute! -This repo was based on Yuzu EA 4176 but the code is being rewritten from the ground up for legal and performance reasons. +This repo was based on Yuzu EA 4176
diff --git a/xray-core/go.mod b/xray-core/go.mod index 3715ec599d..31b32a8d4e 100644 --- a/xray-core/go.mod +++ b/xray-core/go.mod @@ -27,7 +27,7 @@ require ( golang.org/x/sync v0.7.0 golang.org/x/sys v0.21.0 golang.zx2c4.com/wireguard v0.0.0-20231211153847-12269c276173 - google.golang.org/grpc v1.64.0 + google.golang.org/grpc v1.65.0 google.golang.org/protobuf v1.34.2 gvisor.dev/gvisor v0.0.0-20231202080848-1f7806d17489 h12.io/socks v1.0.3 diff --git a/xray-core/go.sum b/xray-core/go.sum index bc4dcd9c65..60e11526c4 100644 --- a/xray-core/go.sum +++ b/xray-core/go.sum @@ -273,8 +273,8 @@ google.golang.org/grpc v1.14.0/go.mod h1:yo6s7OP7yaDglbqo1J04qKzAhqBH6lvTonzMVmE google.golang.org/grpc v1.16.0/go.mod h1:0JHn/cJsOMiMfNA9+DeHDlAU7KAAB5GDlYFpa9MZMio= google.golang.org/grpc v1.17.0/go.mod h1:6QZJwpn2B+Zp71q/5VxRsJ6NXXVCE5NRUHRo+f3cWCs= google.golang.org/grpc v1.19.0/go.mod h1:mqu4LbDTu4XGKhr4mRzUsmM4RtVoemTSY81AxZiDr8c= -google.golang.org/grpc v1.64.0 h1:KH3VH9y/MgNQg1dE7b3XfVK0GsPSIzJwdF617gUSbvY= -google.golang.org/grpc v1.64.0/go.mod h1:oxjF8E3FBnjp+/gVFYdWacaLDx9na1aqy9oovLpxQYg= +google.golang.org/grpc v1.65.0 h1:bs/cUb4lp1G5iImFFd3u5ixQzweKizoZJAwBNLR42lc= +google.golang.org/grpc v1.65.0/go.mod h1:WgYC2ypjlB0EiQi6wdKixMqukr6lBc0Vo+oOgjrM5ZQ= google.golang.org/protobuf v1.34.2 h1:6xV6lTsCfpGD21XK49h7MhtcApnLqkfYgPcdHftf6hg= google.golang.org/protobuf v1.34.2/go.mod h1:qYOHts0dSfpeUzUFpOMr/WGzszTmLH+DiWniOlNbLDw= gopkg.in/check.v1 v0.0.0-20161208181325-20d25e280405 h1:yhCVgyC4o1eVCa2tZl7eS0r+SDo693bJlVdllGtEeKM= diff --git a/yass/.github/workflows/releases-rpm.yml b/yass/.github/workflows/releases-rpm.yml index 05913197e7..43faf17d2f 100644 --- a/yass/.github/workflows/releases-rpm.yml +++ b/yass/.github/workflows/releases-rpm.yml @@ -43,7 +43,6 @@ jobs: fail-fast: false matrix: container: - - 'centos7' - 'centos8' - 'centos9' - 'fedora39' @@ -84,12 +83,10 @@ jobs: fail-fast: false matrix: include: - - container: 'centos7' + - container: 'centos8' gui_variant: gtk3 - - container: 'centos7' + - container: 'centos8' gui_variant: qt5 - - container: 'centos9' - gui_variant: gtk4 # qt6 sits on epel repo, disabling # - container: 'centos9' # gui_variant: qt6 @@ -129,19 +126,10 @@ jobs: - name: Cache clang id: clang-cache uses: actions/cache@v4 - if: ${{ matrix.container != 'centos7' }} with: path: | third_party/llvm-build/Release+Asserts key: ${{ runner.os }}-toolchain-${{ hashFiles('CLANG_REVISION') }}-v${{ env.CACHE_EPOCH }} - - name: Cache clang (el7) - id: clang-cache-el7 - uses: actions/cache@v3 - if: ${{ matrix.container == 'centos7' }} - with: - path: | - third_party/llvm-build/Release+Asserts - key: ${{ runner.os }}-toolchain-el7-${{ hashFiles('CLANG_REVISION') }}-v${{ env.CACHE_EPOCH }} - name: Cache golang uses: actions/cache@v3 with: @@ -152,16 +140,10 @@ jobs: restore-keys: | ${{ runner.os }}-go-docker- - name: "Install dependency: prebuilt clang and clang-tidy binaries" - if: ${{ steps.clang-cache.outputs.cache-hit != 'true' && matrix.container != 'centos7' }} + if: ${{ steps.clang-cache.outputs.cache-hit != 'true' }} run: | ./scripts/download-clang-prebuilt-binaries.py rm -f third_party/llvm-build/Release+Asserts/*.tgz - - name: "Install dependency: prebuilt clang and clang-tidy binaries (el7 patch)" - if: ${{ steps.clang-cache-el7.outputs.cache-hit != 'true' && matrix.container == 'centos7' }} - run: | - ./scripts/download-clang-prebuilt-binaries.py - rm -f third_party/llvm-build/Release+Asserts/*.tgz - ./scripts/libstdc++-el7.sh - name: Set clang environment run: | # use custom compiler @@ -172,11 +154,6 @@ jobs: run: | # use custom libc++ echo "USE_LIBCXX=1" >> $GITHUB_ENV - - name: Set LLD environment - if: ${{ matrix.container == 'centos7' }} - run: | - # newer ld.lld doesn't work on glibc 2.17 - echo "DISABLE_LLD=1" >> $GITHUB_ENV - name: Set QT6 environment if: ${{ matrix.gui_variant == 'qt6' }} run: | diff --git a/yass/src/net/resolver.cpp b/yass/src/net/resolver.cpp index b3fce540e4..76527d9964 100644 --- a/yass/src/net/resolver.cpp +++ b/yass/src/net/resolver.cpp @@ -2,39 +2,139 @@ /* Copyright (c) 2024 Chilledheart */ #include "net/resolver.hpp" + #include "config/config_network.hpp" +#include "core/utils.hpp" +#include "net/doh_resolver.hpp" +#include "net/dot_resolver.hpp" + +#ifdef HAVE_C_ARES +#include "net/c-ares.hpp" +#endif namespace net { -Resolver::Resolver(asio::io_context& io_context) - : io_context_(io_context), - doh_resolver_(nullptr), - dot_resolver_(nullptr), +class Resolver::ResolverImpl { + public: + ResolverImpl(asio::io_context& io_context) + : io_context_(io_context), + doh_resolver_(nullptr), + dot_resolver_(nullptr), #ifdef HAVE_C_ARES - resolver_(nullptr) + resolver_(nullptr) #else - resolver_(io_context) + resolver_(io_context) #endif -{ + { + } + + int Init() { + doh_url_ = absl::GetFlag(FLAGS_doh_url); + if (!doh_url_.empty()) { + doh_resolver_ = DoHResolver::Create(io_context_); + return doh_resolver_->Init(doh_url_, 10000); + } + dot_host_ = absl::GetFlag(FLAGS_dot_host); + if (!dot_host_.empty()) { + dot_resolver_ = DoTResolver::Create(io_context_); + return dot_resolver_->Init(dot_host_, 10000); + } +#ifdef HAVE_C_ARES + resolver_ = CAresResolver::Create(io_context_); + return resolver_->Init(5000); +#else + return 0; +#endif + } + + void Cancel() { + if (!doh_url_.empty()) { + if (doh_resolver_) { + doh_resolver_->Cancel(); + } + return; + } + if (!dot_host_.empty()) { + if (dot_resolver_) { + dot_resolver_->Cancel(); + } + return; + } +#ifdef HAVE_C_ARES + if (resolver_) { + resolver_->Cancel(); + } +#else + resolver_.cancel(); +#endif + } + + void Reset() { + if (!doh_url_.empty()) { + doh_resolver_.reset(); + return; + } + if (!dot_host_.empty()) { + dot_resolver_.reset(); + return; + } +#ifdef HAVE_C_ARES + resolver_.reset(); +#endif + } + + void AsyncResolve(const std::string& host_name, int port, AsyncResolveCallback cb) { + if (!doh_url_.empty()) { + doh_resolver_->AsyncResolve(host_name, port, cb); + return; + } + if (!dot_host_.empty()) { + dot_resolver_->AsyncResolve(host_name, port, cb); + return; + } +#ifdef HAVE_C_ARES + resolver_->AsyncResolve(host_name, std::to_string(port), cb); +#else + resolver_.async_resolve(Net_ipv6works() ? asio::ip::tcp::unspec() : asio::ip::tcp::v4(), host_name, + std::to_string(port), cb); +#endif + } + + private: + asio::io_context& io_context_; + std::string doh_url_; + std::string dot_host_; + + scoped_refptr doh_resolver_; + scoped_refptr dot_resolver_; + +#ifdef HAVE_C_ARES + scoped_refptr resolver_; +#else + asio::ip::tcp::resolver resolver_; +#endif +}; + +Resolver::Resolver(asio::io_context& io_context) : impl_(new ResolverImpl(io_context)) {} + +Resolver::~Resolver() { + delete impl_; } int Resolver::Init() { - doh_url_ = absl::GetFlag(FLAGS_doh_url); - if (!doh_url_.empty()) { - doh_resolver_ = DoHResolver::Create(io_context_); - return doh_resolver_->Init(doh_url_, 10000); - } - dot_host_ = absl::GetFlag(FLAGS_dot_host); - if (!dot_host_.empty()) { - dot_resolver_ = DoTResolver::Create(io_context_); - return dot_resolver_->Init(dot_host_, 10000); - } -#ifdef HAVE_C_ARES - resolver_ = CAresResolver::Create(io_context_); - return resolver_->Init(5000); -#else - return 0; -#endif + return impl_->Init(); +} + +void Resolver::Cancel() { + impl_->Cancel(); +} + +void Resolver::Reset() { + impl_->Reset(); +} + +void Resolver::AsyncResolve(const std::string& host_name, int port, AsyncResolveCallback cb) { + impl_->AsyncResolve(host_name, port, cb); } } // namespace net diff --git a/yass/src/net/resolver.hpp b/yass/src/net/resolver.hpp index df028cc07a..00e95c1d26 100644 --- a/yass/src/net/resolver.hpp +++ b/yass/src/net/resolver.hpp @@ -4,89 +4,28 @@ #ifndef H_NET_RESOLVER_HPP #define H_NET_RESOLVER_HPP -#include "core/utils.hpp" -#include "net/asio.hpp" -#include "net/doh_resolver.hpp" -#include "net/dot_resolver.hpp" +#include -#ifdef HAVE_C_ARES -#include "net/c-ares.hpp" -#endif +#include "net/asio.hpp" namespace net { class Resolver { + class ResolverImpl; + public: Resolver(asio::io_context& io_context); + ~Resolver(); int Init(); - - void Cancel() { - if (!doh_url_.empty()) { - if (doh_resolver_) { - doh_resolver_->Cancel(); - } - return; - } - if (!dot_host_.empty()) { - if (dot_resolver_) { - dot_resolver_->Cancel(); - } - return; - } -#ifdef HAVE_C_ARES - if (resolver_) { - resolver_->Cancel(); - } -#else - resolver_.cancel(); -#endif - } - - void Reset() { - if (!doh_url_.empty()) { - doh_resolver_.reset(); - return; - } - if (!dot_host_.empty()) { - dot_resolver_.reset(); - return; - } -#ifdef HAVE_C_ARES - resolver_.reset(); -#endif - } + void Cancel(); + void Reset(); using AsyncResolveCallback = std::function; - void AsyncResolve(const std::string& host_name, int port, AsyncResolveCallback cb) { - if (!doh_url_.empty()) { - doh_resolver_->AsyncResolve(host_name, port, cb); - return; - } - if (!dot_host_.empty()) { - dot_resolver_->AsyncResolve(host_name, port, cb); - return; - } -#ifdef HAVE_C_ARES - resolver_->AsyncResolve(host_name, std::to_string(port), cb); -#else - resolver_.async_resolve(Net_ipv6works() ? asio::ip::tcp::unspec() : asio::ip::tcp::v4(), host_name, - std::to_string(port), cb); -#endif - } + void AsyncResolve(const std::string& host_name, int port, AsyncResolveCallback cb); private: - asio::io_context& io_context_; - std::string doh_url_; - std::string dot_host_; - scoped_refptr doh_resolver_; - scoped_refptr dot_resolver_; - -#ifdef HAVE_C_ARES - scoped_refptr resolver_; -#else - asio::ip::tcp::resolver resolver_; -#endif + ResolverImpl* impl_ = nullptr; }; } // namespace net diff --git a/yass/src/qt6/yass_window.cpp b/yass/src/qt6/yass_window.cpp index ed87f4b5ed..395e4e72a3 100644 --- a/yass/src/qt6/yass_window.cpp +++ b/yass/src/qt6/yass_window.cpp @@ -23,6 +23,7 @@ #include "cli/cli_connection_stats.hpp" #include "config/config.hpp" +#include "core/utils.hpp" #include "feature.h" #include "freedesktop/utils.hpp" #include "version.h" diff --git a/yt-dlp/yt_dlp/extractor/douyutv.py b/yt-dlp/yt_dlp/extractor/douyutv.py index fdf19c2520..e36eac9193 100644 --- a/yt-dlp/yt_dlp/extractor/douyutv.py +++ b/yt-dlp/yt_dlp/extractor/douyutv.py @@ -24,8 +24,9 @@ from ..utils import ( class DouyuBaseIE(InfoExtractor): def _download_cryptojs_md5(self, video_id): for url in [ + # XXX: Do NOT use cdn.bootcdn.net; ref: https://sansec.io/research/polyfill-supply-chain-attack 'https://cdnjs.cloudflare.com/ajax/libs/crypto-js/3.1.2/rollups/md5.js', - 'https://cdn.bootcdn.net/ajax/libs/crypto-js/3.1.2/rollups/md5.js', + 'https://unpkg.com/cryptojslib@3.1.2/rollups/md5.js', ]: js_code = self._download_webpage( url, video_id, note='Downloading signing dependency', fatal=False) @@ -35,7 +36,8 @@ class DouyuBaseIE(InfoExtractor): raise ExtractorError('Unable to download JS dependency (crypto-js/md5)') def _get_cryptojs_md5(self, video_id): - return self.cache.load('douyu', 'crypto-js-md5') or self._download_cryptojs_md5(video_id) + return self.cache.load( + 'douyu', 'crypto-js-md5', min_ver='2024.07.04') or self._download_cryptojs_md5(video_id) def _calc_sign(self, sign_func, video_id, a): b = uuid.uuid4().hex