diff --git a/.github/update.log b/.github/update.log index af88fe80e3..9d79dcc278 100644 --- a/.github/update.log +++ b/.github/update.log @@ -779,3 +779,4 @@ Update On Thu Sep 26 20:35:45 CEST 2024 Update On Fri Sep 27 20:34:20 CEST 2024 Update On Sat Sep 28 20:32:29 CEST 2024 Update On Sun Sep 29 20:35:08 CEST 2024 +Update On Mon Sep 30 20:38:12 CEST 2024 diff --git a/clash-meta-android/build.gradle.kts b/clash-meta-android/build.gradle.kts index d1bbaffee5..5467252cee 100644 --- a/clash-meta-android/build.gradle.kts +++ b/clash-meta-android/build.gradle.kts @@ -40,8 +40,8 @@ subprojects { minSdk = 21 targetSdk = 31 - versionName = "2.11.0" - versionCode = 211000 + versionName = "2.11.1" + versionCode = 211001 resValue("string", "release_name", "v$versionName") resValue("integer", "release_code", "$versionCode") diff --git a/clash-meta-android/core/src/foss/golang/clash/config/config.go b/clash-meta-android/core/src/foss/golang/clash/config/config.go index 9067d14ff9..3117853cbd 100644 --- a/clash-meta-android/core/src/foss/golang/clash/config/config.go +++ b/clash-meta-android/core/src/foss/golang/clash/config/config.go @@ -107,6 +107,12 @@ type Controller struct { ExternalUI string ExternalDohServer string Secret string + Cors Cors +} + +type Cors struct { + AllowOrigins []string + AllowPrivateNetwork bool } // Experimental config @@ -191,6 +197,11 @@ type Config struct { TLS *TLS } +type RawCors struct { + AllowOrigins []string `yaml:"allow-origins" json:"allow-origins"` + AllowPrivateNetwork bool `yaml:"allow-private-network" json:"allow-private-network"` +} + type RawDNS struct { Enable bool `yaml:"enable" json:"enable"` PreferH3 bool `yaml:"prefer-h3" json:"prefer-h3"` @@ -368,6 +379,7 @@ type RawConfig struct { ExternalControllerPipe string `yaml:"external-controller-pipe" json:"external-controller-pipe"` ExternalControllerUnix string `yaml:"external-controller-unix" json:"external-controller-unix"` ExternalControllerTLS string `yaml:"external-controller-tls" json:"external-controller-tls"` + ExternalControllerCors RawCors `yaml:"external-controller-cors" json:"external-controller-cors"` ExternalUI string `yaml:"external-ui" json:"external-ui"` ExternalUIURL string `yaml:"external-ui-url" json:"external-ui-url"` ExternalUIName string `yaml:"external-ui-name" json:"external-ui-name"` @@ -541,6 +553,10 @@ func DefaultRawConfig() *RawConfig { OverrideDest: true, }, ExternalUIURL: "https://github.com/MetaCubeX/metacubexd/archive/refs/heads/gh-pages.zip", + ExternalControllerCors: RawCors{ + AllowOrigins: []string{"*"}, + AllowPrivateNetwork: true, + }, } } @@ -775,6 +791,10 @@ func parseController(cfg *RawConfig) (*Controller, error) { ExternalControllerUnix: cfg.ExternalControllerUnix, ExternalControllerTLS: cfg.ExternalControllerTLS, ExternalDohServer: cfg.ExternalDohServer, + Cors: Cors{ + AllowOrigins: cfg.ExternalControllerCors.AllowOrigins, + AllowPrivateNetwork: cfg.ExternalControllerCors.AllowPrivateNetwork, + }, }, nil } diff --git a/clash-meta-android/core/src/foss/golang/clash/docs/config.yaml b/clash-meta-android/core/src/foss/golang/clash/docs/config.yaml index 9c480b3f2a..15bcf6076d 100644 --- a/clash-meta-android/core/src/foss/golang/clash/docs/config.yaml +++ b/clash-meta-android/core/src/foss/golang/clash/docs/config.yaml @@ -58,6 +58,12 @@ external-controller: 0.0.0.0:9093 # RESTful API 监听地址 external-controller-tls: 0.0.0.0:9443 # RESTful API HTTPS 监听地址，需要配置 tls 部分配置文件 # secret: "123456" # `Authorization:Bearer ${secret}` +# RESTful API CORS标头配置 +external-controller-cors: + allow-origins: + - * + allow-private-network: true + # RESTful API Unix socket 监听地址（ windows版本大于17063也可以使用，即大于等于1803/RS4版本即可使用 ） # ！！！注意： 从Unix socket访问api接口不会验证secret， 如果开启请自行保证安全问题 ！！！ # 测试方法： curl -v --unix-socket "mihomo.sock" http://localhost/ diff --git a/clash-meta-android/core/src/foss/golang/clash/go.mod b/clash-meta-android/core/src/foss/golang/clash/go.mod index b74cee92e1..4b066c9017 100644 --- a/clash-meta-android/core/src/foss/golang/clash/go.mod +++ b/clash-meta-android/core/src/foss/golang/clash/go.mod @@ -8,7 +8,6 @@ require ( github.com/coreos/go-iptables v0.7.0 github.com/dlclark/regexp2 v1.11.4 github.com/go-chi/chi/v5 v5.1.0 - github.com/go-chi/cors v1.2.1 github.com/go-chi/render v1.0.3 github.com/gobwas/ws v1.4.0 github.com/gofrs/uuid/v5 v5.3.0 @@ -37,6 +36,7 @@ require ( github.com/openacid/low v0.1.21 github.com/oschwald/maxminddb-golang v1.12.0 github.com/puzpuzpuz/xsync/v3 v3.4.0 + github.com/sagernet/cors v1.2.1 github.com/sagernet/fswatch v0.1.1 github.com/sagernet/netlink v0.0.0-20240612041022-b9a21c07ac6a github.com/sagernet/sing v0.5.0-alpha.13 diff --git a/clash-meta-android/core/src/foss/golang/clash/go.sum b/clash-meta-android/core/src/foss/golang/clash/go.sum index ba2d181951..60818034d1 100644 --- a/clash-meta-android/core/src/foss/golang/clash/go.sum +++ b/clash-meta-android/core/src/foss/golang/clash/go.sum @@ -42,8 +42,6 @@ github.com/gaukas/godicttls v0.0.4 h1:NlRaXb3J6hAnTmWdsEKb9bcSBD6BvcIjdGdeb0zfXb github.com/gaukas/godicttls v0.0.4/go.mod h1:l6EenT4TLWgTdwslVb4sEMOCf7Bv0JAK67deKr9/NCI= github.com/go-chi/chi/v5 v5.1.0 h1:acVI1TYaD+hhedDJ3r54HyA6sExp3HfXq7QWEEY/xMw= github.com/go-chi/chi/v5 v5.1.0/go.mod h1:DslCQbL2OYiznFReuXYUmQ2hGd1aDpCnlMNITLSKoi8= -github.com/go-chi/cors v1.2.1 h1:xEC8UT3Rlp2QuWNEr4Fs/c2EAGVKBwy/1vHx3bppil4= -github.com/go-chi/cors v1.2.1/go.mod h1:sSbTewc+6wYHBBCW7ytsFSn836hqM7JxpglAy2Vzc58= github.com/go-chi/render v1.0.3 h1:AsXqd2a1/INaIfUSKq3G5uA8weYx20FOsM7uSoCyyt4= github.com/go-chi/render v1.0.3/go.mod h1:/gr3hVkmYR0YlEy3LxCuVRFzEu9Ruok+gFqbIofjao0= github.com/go-logr/logr v1.2.4 h1:g01GSCwiDw2xSZfjJ2/T9M+S6pFdcNtFYsp+Y43HYDQ= @@ -160,6 +158,8 @@ github.com/quic-go/qpack v0.4.0 h1:Cr9BXA1sQS2SmDUWjSofMPNKmvF6IiIfDRmgU0w1ZCo= github.com/quic-go/qpack v0.4.0/go.mod h1:UZVnYIfi5GRk+zI9UMaCPsmZ2xKJP7XBUvVyT1Knj9A= github.com/quic-go/qtls-go1-20 v0.4.1 h1:D33340mCNDAIKBqXuAvexTNMUByrYmFYVfKfDN5nfFs= github.com/quic-go/qtls-go1-20 v0.4.1/go.mod h1:X9Nh97ZL80Z+bX/gUXMbipO6OxdiDi58b/fMC9mAL+k= +github.com/sagernet/cors v1.2.1 h1:Cv5Z8y9YSD6Gm+qSpNrL3LO4lD3eQVvbFYJSG7JCMHQ= +github.com/sagernet/cors v1.2.1/go.mod h1:O64VyOjjhrkLmQIjF4KGRrJO/5dVXFdpEmCW/eISRAI= github.com/sagernet/fswatch v0.1.1 h1:YqID+93B7VRfqIH3PArW/XpJv5H4OLEVWDfProGoRQs= github.com/sagernet/fswatch v0.1.1/go.mod h1:nz85laH0mkQqJfaOrqPpkwtU1znMFNVTpT/5oRsVz/o= github.com/sagernet/netlink v0.0.0-20240612041022-b9a21c07ac6a h1:ObwtHN2VpqE0ZNjr6sGeT00J8uU7JF4cNUdb44/Duis= diff --git a/clash-meta-android/core/src/foss/golang/clash/hub/hub.go b/clash-meta-android/core/src/foss/golang/clash/hub/hub.go index 73a44eee66..69f627ffa8 100644 --- a/clash-meta-android/core/src/foss/golang/clash/hub/hub.go +++ b/clash-meta-android/core/src/foss/golang/clash/hub/hub.go @@ -59,6 +59,10 @@ func applyRoute(cfg *config.Config) { PrivateKey: cfg.TLS.PrivateKey, DohServer: cfg.Controller.ExternalDohServer, IsDebug: cfg.General.LogLevel == log.DEBUG, + Cors: route.Cors{ + AllowOrigins: cfg.Controller.Cors.AllowOrigins, + AllowPrivateNetwork: cfg.Controller.Cors.AllowPrivateNetwork, + }, }) } diff --git a/clash-meta-android/core/src/foss/golang/clash/hub/route/configs.go b/clash-meta-android/core/src/foss/golang/clash/hub/route/configs.go index d4bda2bf4c..b23a35a52a 100644 --- a/clash-meta-android/core/src/foss/golang/clash/hub/route/configs.go +++ b/clash-meta-android/core/src/foss/golang/clash/hub/route/configs.go @@ -24,9 +24,11 @@ import ( func configRouter() http.Handler { r := chi.NewRouter() r.Get("/", getConfigs) - r.Put("/", updateConfigs) - r.Post("/geo", updateGeoDatabases) - r.Patch("/", patchConfigs) + if !embedMode { // disallow update/patch configs in embed mode + r.Put("/", updateConfigs) + r.Post("/geo", updateGeoDatabases) + r.Patch("/", patchConfigs) + } return r } diff --git a/clash-meta-android/core/src/foss/golang/clash/hub/route/groups.go b/clash-meta-android/core/src/foss/golang/clash/hub/route/groups.go index 68d1f3542b..873a94df51 100644 --- a/clash-meta-android/core/src/foss/golang/clash/hub/route/groups.go +++ b/clash-meta-android/core/src/foss/golang/clash/hub/route/groups.go @@ -16,7 +16,7 @@ import ( "github.com/metacubex/mihomo/tunnel" ) -func GroupRouter() http.Handler { +func groupRouter() http.Handler { r := chi.NewRouter() r.Get("/", getGroups) diff --git a/clash-meta-android/core/src/foss/golang/clash/hub/route/patch_android.go b/clash-meta-android/core/src/foss/golang/clash/hub/route/patch_android.go new file mode 100644 index 0000000000..5eba279646 --- /dev/null +++ b/clash-meta-android/core/src/foss/golang/clash/hub/route/patch_android.go @@ -0,0 +1,7 @@ +//go:build android && cmfa + +package route + +func init() { + SetEmbedMode(true) // set embed mode default +} diff --git a/clash-meta-android/core/src/foss/golang/clash/hub/route/server.go b/clash-meta-android/core/src/foss/golang/clash/hub/route/server.go index 4c22609cfc..21102cc38b 100644 --- a/clash-meta-android/core/src/foss/golang/clash/hub/route/server.go +++ b/clash-meta-android/core/src/foss/golang/clash/hub/route/server.go @@ -23,10 +23,10 @@ import ( "github.com/go-chi/chi/v5" "github.com/go-chi/chi/v5/middleware" - "github.com/go-chi/cors" "github.com/go-chi/render" "github.com/gobwas/ws" "github.com/gobwas/ws/wsutil" + "github.com/sagernet/cors" ) var ( @@ -36,8 +36,14 @@ var ( tlsServer *http.Server unixServer *http.Server pipeServer *http.Server + + embedMode = false ) +func SetEmbedMode(embed bool) { + embedMode = embed +} + type Traffic struct { Up int64 `json:"up"` Down int64 `json:"down"` @@ -58,6 +64,22 @@ type Config struct { PrivateKey string DohServer string IsDebug bool + Cors Cors +} + +type Cors struct { + AllowOrigins []string + AllowPrivateNetwork bool +} + +func (c Cors) Apply(r chi.Router) { + r.Use(cors.New(cors.Options{ + AllowedOrigins: c.AllowOrigins, + AllowedMethods: []string{"GET", "POST", "PUT", "PATCH", "DELETE"}, + AllowedHeaders: []string{"Content-Type", "Authorization"}, + AllowPrivateNetwork: c.AllowPrivateNetwork, + MaxAge: 300, + }).Handler) } func ReCreateServer(cfg *Config) { @@ -73,16 +95,9 @@ func SetUIPath(path string) { uiPath = C.Path.Resolve(path) } -func router(isDebug bool, secret string, dohServer string) *chi.Mux { +func router(isDebug bool, secret string, dohServer string, cors Cors) *chi.Mux { r := chi.NewRouter() - corsM := cors.New(cors.Options{ - AllowedOrigins: []string{"*"}, - AllowedMethods: []string{"GET", "POST", "PUT", "PATCH", "DELETE"}, - AllowedHeaders: []string{"Content-Type", "Authorization"}, - MaxAge: 300, - }) - r.Use(setPrivateNetworkAccess) - r.Use(corsM.Handler) + cors.Apply(r) if isDebug { r.Mount("/debug", func() http.Handler { r := chi.NewRouter() @@ -105,15 +120,17 @@ func router(isDebug bool, secret string, dohServer string) *chi.Mux { r.Get("/version", version) r.Mount("/configs", configRouter()) r.Mount("/proxies", proxyRouter()) - r.Mount("/group", GroupRouter()) + r.Mount("/group", groupRouter()) r.Mount("/rules", ruleRouter()) r.Mount("/connections", connectionRouter()) r.Mount("/providers/proxies", proxyProviderRouter()) r.Mount("/providers/rules", ruleProviderRouter()) r.Mount("/cache", cacheRouter()) r.Mount("/dns", dnsRouter()) - r.Mount("/restart", restartRouter()) - r.Mount("/upgrade", upgradeRouter()) + if !embedMode { // disallow restart and upgrade in embed mode + r.Mount("/restart", restartRouter()) + r.Mount("/upgrade", upgradeRouter()) + } addExternalRouters(r) }) @@ -151,7 +168,7 @@ func start(cfg *Config) { log.Infoln("RESTful API listening at: %s", l.Addr().String()) server := &http.Server{ - Handler: router(cfg.IsDebug, cfg.Secret, cfg.DohServer), + Handler: router(cfg.IsDebug, cfg.Secret, cfg.DohServer, cfg.Cors), } httpServer = server if err = server.Serve(l); err != nil { @@ -183,7 +200,7 @@ func startTLS(cfg *Config) { log.Infoln("RESTful API tls listening at: %s", l.Addr().String()) server := &http.Server{ - Handler: router(cfg.IsDebug, cfg.Secret, cfg.DohServer), + Handler: router(cfg.IsDebug, cfg.Secret, cfg.DohServer, cfg.Cors), TLSConfig: &tls.Config{ Certificates: []tls.Certificate{c}, }, @@ -228,10 +245,11 @@ func startUnix(cfg *Config) { log.Errorln("External controller unix listen error: %s", err) return } + _ = os.Chmod(addr, 0o666) log.Infoln("RESTful API unix listening at: %s", l.Addr().String()) server := &http.Server{ - Handler: router(cfg.IsDebug, "", cfg.DohServer), + Handler: router(cfg.IsDebug, "", cfg.DohServer, cfg.Cors), } unixServer = server if err = server.Serve(l); err != nil { @@ -262,7 +280,7 @@ func startPipe(cfg *Config) { log.Infoln("RESTful API pipe listening at: %s", l.Addr().String()) server := &http.Server{ - Handler: router(cfg.IsDebug, "", cfg.DohServer), + Handler: router(cfg.IsDebug, "", cfg.DohServer, cfg.Cors), } pipeServer = server if err = server.Serve(l); err != nil { @@ -271,15 +289,6 @@ func startPipe(cfg *Config) { } } -func setPrivateNetworkAccess(next http.Handler) http.Handler { - return http.HandlerFunc(func(w http.ResponseWriter, r *http.Request) { - if r.Method == http.MethodOptions && r.Header.Get("Access-Control-Request-Method") != "" { - w.Header().Add("Access-Control-Allow-Private-Network", "true") - } - next.ServeHTTP(w, r) - }) -} - func safeEuqal(a, b string) bool { aBuf := utils.ImmutableBytesFromString(a) bBuf := utils.ImmutableBytesFromString(b) diff --git a/clash-meta-android/core/src/foss/golang/go.mod b/clash-meta-android/core/src/foss/golang/go.mod index 57a73c9529..efe418e319 100644 --- a/clash-meta-android/core/src/foss/golang/go.mod +++ b/clash-meta-android/core/src/foss/golang/go.mod @@ -22,7 +22,6 @@ require ( github.com/fsnotify/fsnotify v1.7.0 // indirect github.com/gaukas/godicttls v0.0.4 // indirect github.com/go-chi/chi/v5 v5.1.0 // indirect - github.com/go-chi/cors v1.2.1 // indirect github.com/go-chi/render v1.0.3 // indirect github.com/go-ole/go-ole v1.3.0 // indirect github.com/go-task/slim-sprig v0.0.0-20230315185526-52ccab3ef572 // indirect @@ -71,6 +70,7 @@ require ( github.com/puzpuzpuz/xsync/v3 v3.4.0 // indirect github.com/quic-go/qpack v0.4.0 // indirect github.com/quic-go/qtls-go1-20 v0.4.1 // indirect + github.com/sagernet/cors v1.2.1 // indirect github.com/sagernet/fswatch v0.1.1 // indirect github.com/sagernet/netlink v0.0.0-20240612041022-b9a21c07ac6a // indirect github.com/sagernet/nftables v0.3.0-beta.4 // indirect diff --git a/clash-meta-android/core/src/foss/golang/go.sum b/clash-meta-android/core/src/foss/golang/go.sum index 1fda649591..3919bbde96 100644 --- a/clash-meta-android/core/src/foss/golang/go.sum +++ b/clash-meta-android/core/src/foss/golang/go.sum @@ -41,8 +41,6 @@ github.com/gaukas/godicttls v0.0.4 h1:NlRaXb3J6hAnTmWdsEKb9bcSBD6BvcIjdGdeb0zfXb github.com/gaukas/godicttls v0.0.4/go.mod h1:l6EenT4TLWgTdwslVb4sEMOCf7Bv0JAK67deKr9/NCI= github.com/go-chi/chi/v5 v5.1.0 h1:acVI1TYaD+hhedDJ3r54HyA6sExp3HfXq7QWEEY/xMw= github.com/go-chi/chi/v5 v5.1.0/go.mod h1:DslCQbL2OYiznFReuXYUmQ2hGd1aDpCnlMNITLSKoi8= -github.com/go-chi/cors v1.2.1 h1:xEC8UT3Rlp2QuWNEr4Fs/c2EAGVKBwy/1vHx3bppil4= -github.com/go-chi/cors v1.2.1/go.mod h1:sSbTewc+6wYHBBCW7ytsFSn836hqM7JxpglAy2Vzc58= github.com/go-chi/render v1.0.3 h1:AsXqd2a1/INaIfUSKq3G5uA8weYx20FOsM7uSoCyyt4= github.com/go-chi/render v1.0.3/go.mod h1:/gr3hVkmYR0YlEy3LxCuVRFzEu9Ruok+gFqbIofjao0= github.com/go-logr/logr v1.2.4 h1:g01GSCwiDw2xSZfjJ2/T9M+S6pFdcNtFYsp+Y43HYDQ= @@ -155,6 +153,8 @@ github.com/quic-go/qpack v0.4.0 h1:Cr9BXA1sQS2SmDUWjSofMPNKmvF6IiIfDRmgU0w1ZCo= github.com/quic-go/qpack v0.4.0/go.mod h1:UZVnYIfi5GRk+zI9UMaCPsmZ2xKJP7XBUvVyT1Knj9A= github.com/quic-go/qtls-go1-20 v0.4.1 h1:D33340mCNDAIKBqXuAvexTNMUByrYmFYVfKfDN5nfFs= github.com/quic-go/qtls-go1-20 v0.4.1/go.mod h1:X9Nh97ZL80Z+bX/gUXMbipO6OxdiDi58b/fMC9mAL+k= +github.com/sagernet/cors v1.2.1 h1:Cv5Z8y9YSD6Gm+qSpNrL3LO4lD3eQVvbFYJSG7JCMHQ= +github.com/sagernet/cors v1.2.1/go.mod h1:O64VyOjjhrkLmQIjF4KGRrJO/5dVXFdpEmCW/eISRAI= github.com/sagernet/fswatch v0.1.1 h1:YqID+93B7VRfqIH3PArW/XpJv5H4OLEVWDfProGoRQs= github.com/sagernet/fswatch v0.1.1/go.mod h1:nz85laH0mkQqJfaOrqPpkwtU1znMFNVTpT/5oRsVz/o= github.com/sagernet/netlink v0.0.0-20240612041022-b9a21c07ac6a h1:ObwtHN2VpqE0ZNjr6sGeT00J8uU7JF4cNUdb44/Duis= diff --git a/clash-meta-android/core/src/main/golang/go.mod b/clash-meta-android/core/src/main/golang/go.mod index e900bf5311..0ca3286a63 100644 --- a/clash-meta-android/core/src/main/golang/go.mod +++ b/clash-meta-android/core/src/main/golang/go.mod @@ -30,7 +30,6 @@ require ( github.com/fsnotify/fsnotify v1.7.0 // indirect github.com/gaukas/godicttls v0.0.4 // indirect github.com/go-chi/chi/v5 v5.1.0 // indirect - github.com/go-chi/cors v1.2.1 // indirect github.com/go-chi/render v1.0.3 // indirect github.com/go-ole/go-ole v1.3.0 // indirect github.com/go-task/slim-sprig v0.0.0-20230315185526-52ccab3ef572 // indirect @@ -78,6 +77,7 @@ require ( github.com/puzpuzpuz/xsync/v3 v3.4.0 // indirect github.com/quic-go/qpack v0.4.0 // indirect github.com/quic-go/qtls-go1-20 v0.4.1 // indirect + github.com/sagernet/cors v1.2.1 // indirect github.com/sagernet/fswatch v0.1.1 // indirect github.com/sagernet/netlink v0.0.0-20240612041022-b9a21c07ac6a // indirect github.com/sagernet/nftables v0.3.0-beta.4 // indirect diff --git a/clash-meta-android/core/src/main/golang/go.sum b/clash-meta-android/core/src/main/golang/go.sum index 1fda649591..3919bbde96 100644 --- a/clash-meta-android/core/src/main/golang/go.sum +++ b/clash-meta-android/core/src/main/golang/go.sum @@ -41,8 +41,6 @@ github.com/gaukas/godicttls v0.0.4 h1:NlRaXb3J6hAnTmWdsEKb9bcSBD6BvcIjdGdeb0zfXb github.com/gaukas/godicttls v0.0.4/go.mod h1:l6EenT4TLWgTdwslVb4sEMOCf7Bv0JAK67deKr9/NCI= github.com/go-chi/chi/v5 v5.1.0 h1:acVI1TYaD+hhedDJ3r54HyA6sExp3HfXq7QWEEY/xMw= github.com/go-chi/chi/v5 v5.1.0/go.mod h1:DslCQbL2OYiznFReuXYUmQ2hGd1aDpCnlMNITLSKoi8= -github.com/go-chi/cors v1.2.1 h1:xEC8UT3Rlp2QuWNEr4Fs/c2EAGVKBwy/1vHx3bppil4= -github.com/go-chi/cors v1.2.1/go.mod h1:sSbTewc+6wYHBBCW7ytsFSn836hqM7JxpglAy2Vzc58= github.com/go-chi/render v1.0.3 h1:AsXqd2a1/INaIfUSKq3G5uA8weYx20FOsM7uSoCyyt4= github.com/go-chi/render v1.0.3/go.mod h1:/gr3hVkmYR0YlEy3LxCuVRFzEu9Ruok+gFqbIofjao0= github.com/go-logr/logr v1.2.4 h1:g01GSCwiDw2xSZfjJ2/T9M+S6pFdcNtFYsp+Y43HYDQ= @@ -155,6 +153,8 @@ github.com/quic-go/qpack v0.4.0 h1:Cr9BXA1sQS2SmDUWjSofMPNKmvF6IiIfDRmgU0w1ZCo= github.com/quic-go/qpack v0.4.0/go.mod h1:UZVnYIfi5GRk+zI9UMaCPsmZ2xKJP7XBUvVyT1Knj9A= github.com/quic-go/qtls-go1-20 v0.4.1 h1:D33340mCNDAIKBqXuAvexTNMUByrYmFYVfKfDN5nfFs= github.com/quic-go/qtls-go1-20 v0.4.1/go.mod h1:X9Nh97ZL80Z+bX/gUXMbipO6OxdiDi58b/fMC9mAL+k= +github.com/sagernet/cors v1.2.1 h1:Cv5Z8y9YSD6Gm+qSpNrL3LO4lD3eQVvbFYJSG7JCMHQ= +github.com/sagernet/cors v1.2.1/go.mod h1:O64VyOjjhrkLmQIjF4KGRrJO/5dVXFdpEmCW/eISRAI= github.com/sagernet/fswatch v0.1.1 h1:YqID+93B7VRfqIH3PArW/XpJv5H4OLEVWDfProGoRQs= github.com/sagernet/fswatch v0.1.1/go.mod h1:nz85laH0mkQqJfaOrqPpkwtU1znMFNVTpT/5oRsVz/o= github.com/sagernet/netlink v0.0.0-20240612041022-b9a21c07ac6a h1:ObwtHN2VpqE0ZNjr6sGeT00J8uU7JF4cNUdb44/Duis= diff --git a/clash-meta-android/core/src/main/java/com/github/kr328/clash/core/model/ConfigurationOverride.kt b/clash-meta-android/core/src/main/java/com/github/kr328/clash/core/model/ConfigurationOverride.kt index bceef3f291..3587a1d87a 100644 --- a/clash-meta-android/core/src/main/java/com/github/kr328/clash/core/model/ConfigurationOverride.kt +++ b/clash-meta-android/core/src/main/java/com/github/kr328/clash/core/model/ConfigurationOverride.kt @@ -47,6 +47,9 @@ data class ConfigurationOverride( @SerialName("external-controller-tls") var externalControllerTLS: String? = null, + @SerialName("external-controller-cors") + var externalControllerCors: ExternalControllerCors = ExternalControllerCors(), + @SerialName("secret") var secret: String? = null, @@ -210,6 +213,15 @@ data class ConfigurationOverride( var geosite: String? = null, ) + @Serializable + data class ExternalControllerCors( + @SerialName("allow-origins") + var allowOrigins: List? = null, + + @SerialName("allow-private-network") + var allowPrivateNetwork: Boolean? = null, + ) + override fun writeToParcel(parcel: Parcel, flags: Int) { Parcelizer.encodeToParcel(serializer(), parcel, this) } diff --git a/clash-meta-android/design/src/main/java/com/github/kr328/clash/design/OverrideSettingsDesign.kt b/clash-meta-android/design/src/main/java/com/github/kr328/clash/design/OverrideSettingsDesign.kt index 1b91ce4aab..e35944ca45 100644 --- a/clash-meta-android/design/src/main/java/com/github/kr328/clash/design/OverrideSettingsDesign.kt +++ b/clash-meta-android/design/src/main/java/com/github/kr328/clash/design/OverrideSettingsDesign.kt @@ -157,6 +157,20 @@ class OverrideSettingsDesign( empty = R.string.default_ ) + editableTextList( + value = configuration.externalControllerCors::allowOrigins, + adapter = TextAdapter.String, + title = R.string.allow_origins, + placeholder = R.string.dont_modify, + ) + + selectableList( + value = configuration.externalControllerCors::allowPrivateNetwork, + values = booleanValues, + valuesText = booleanValuesText, + title = R.string.allow_private_network, + ) + editableText( value = configuration::secret, adapter = NullableTextAdapter.String, diff --git a/clash-meta-android/design/src/main/res/values/strings.xml b/clash-meta-android/design/src/main/res/values/strings.xml index 783d980f65..622adbb944 100644 --- a/clash-meta-android/design/src/main/res/values/strings.xml +++ b/clash-meta-android/design/src/main/res/values/strings.xml @@ -150,6 +150,8 @@ IPv6 External Controller External Controller TLS + External Controller Allow Origins + External Controller Allow Private Network Secret Hosts New diff --git a/clash-meta/hub/route/configs.go b/clash-meta/hub/route/configs.go index d4bda2bf4c..b23a35a52a 100644 --- a/clash-meta/hub/route/configs.go +++ b/clash-meta/hub/route/configs.go @@ -24,9 +24,11 @@ import ( func configRouter() http.Handler { r := chi.NewRouter() r.Get("/", getConfigs) - r.Put("/", updateConfigs) - r.Post("/geo", updateGeoDatabases) - r.Patch("/", patchConfigs) + if !embedMode { // disallow update/patch configs in embed mode + r.Put("/", updateConfigs) + r.Post("/geo", updateGeoDatabases) + r.Patch("/", patchConfigs) + } return r } diff --git a/clash-meta/hub/route/groups.go b/clash-meta/hub/route/groups.go index 68d1f3542b..873a94df51 100644 --- a/clash-meta/hub/route/groups.go +++ b/clash-meta/hub/route/groups.go @@ -16,7 +16,7 @@ import ( "github.com/metacubex/mihomo/tunnel" ) -func GroupRouter() http.Handler { +func groupRouter() http.Handler { r := chi.NewRouter() r.Get("/", getGroups) diff --git a/clash-meta/hub/route/patch_android.go b/clash-meta/hub/route/patch_android.go new file mode 100644 index 0000000000..5eba279646 --- /dev/null +++ b/clash-meta/hub/route/patch_android.go @@ -0,0 +1,7 @@ +//go:build android && cmfa + +package route + +func init() { + SetEmbedMode(true) // set embed mode default +} diff --git a/clash-meta/hub/route/server.go b/clash-meta/hub/route/server.go index e71347fcd6..21102cc38b 100644 --- a/clash-meta/hub/route/server.go +++ b/clash-meta/hub/route/server.go @@ -36,8 +36,14 @@ var ( tlsServer *http.Server unixServer *http.Server pipeServer *http.Server + + embedMode = false ) +func SetEmbedMode(embed bool) { + embedMode = embed +} + type Traffic struct { Up int64 `json:"up"` Down int64 `json:"down"` @@ -114,15 +120,17 @@ func router(isDebug bool, secret string, dohServer string, cors Cors) *chi.Mux { r.Get("/version", version) r.Mount("/configs", configRouter()) r.Mount("/proxies", proxyRouter()) - r.Mount("/group", GroupRouter()) + r.Mount("/group", groupRouter()) r.Mount("/rules", ruleRouter()) r.Mount("/connections", connectionRouter()) r.Mount("/providers/proxies", proxyProviderRouter()) r.Mount("/providers/rules", ruleProviderRouter()) r.Mount("/cache", cacheRouter()) r.Mount("/dns", dnsRouter()) - r.Mount("/restart", restartRouter()) - r.Mount("/upgrade", upgradeRouter()) + if !embedMode { // disallow restart and upgrade in embed mode + r.Mount("/restart", restartRouter()) + r.Mount("/upgrade", upgradeRouter()) + } addExternalRouters(r) }) diff --git a/clash-nyanpasu/backend/Cargo.lock b/clash-nyanpasu/backend/Cargo.lock index ead7db432e..7ee26ccd22 100644 --- a/clash-nyanpasu/backend/Cargo.lock +++ b/clash-nyanpasu/backend/Cargo.lock @@ -2954,8 +2954,8 @@ dependencies = [ "aho-corasick", "bstr", "log", - "regex-automata 0.4.7", - "regex-syntax 0.8.4", + "regex-automata 0.4.8", + "regex-syntax 0.8.5", ] [[package]] @@ -3493,7 +3493,7 @@ dependencies = [ "globset", "log", "memchr", - "regex-automata 0.4.7", + "regex-automata 0.4.8", "same-file", "walkdir", "winapi-util", @@ -4879,9 +4879,12 @@ dependencies = [ [[package]] name = "once_cell" -version = "1.19.0" +version = "1.20.1" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "3fdb12b2476b595f9358c5161aa467c2438859caa136dec86c26fdd2efe17b92" +checksum = "82881c4be219ab5faaf2ad5e5e5ecdff8c66bd7402ca3160975c93b24961afd1" +dependencies = [ + "portable-atomic", +] [[package]] name = "opaque-debug" @@ -6003,14 +6006,14 @@ dependencies = [ [[package]] name = "regex" -version = "1.10.6" +version = "1.11.0" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "4219d74c6b67a3654a9fbebc4b419e22126d13d2f3c4a07ee0cb61ff79a79619" +checksum = "38200e5ee88914975b69f657f0801b6f6dccafd44fd9326302a4aaeecfacb1d8" dependencies = [ "aho-corasick", "memchr", - "regex-automata 0.4.7", - "regex-syntax 0.8.4", + "regex-automata 0.4.8", + "regex-syntax 0.8.5", ] [[package]] @@ -6024,13 +6027,13 @@ dependencies = [ [[package]] name = "regex-automata" -version = "0.4.7" +version = "0.4.8" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "38caf58cc5ef2fed281f89292ef23f6365465ed9a41b7a7754eb4e26496c92df" +checksum = "368758f23274712b504848e9d5a6f010445cc8b87a7cdb4d7cbee666c1288da3" dependencies = [ "aho-corasick", "memchr", - "regex-syntax 0.8.4", + "regex-syntax 0.8.5", ] [[package]] @@ -6041,9 +6044,9 @@ checksum = "f162c6dd7b008981e4d40210aca20b4bd0f9b60ca9271061b07f78537722f2e1" [[package]] name = "regex-syntax" -version = "0.8.4" +version = "0.8.5" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "7a66a03ae7c801facd77a29370b4faec201768915ac14a721ba36f20bc9c209b" +checksum = "2b15c43186be67a4fd63bee50d0303afffcef381492ebe2c5d87f324e1b8815c" [[package]] name = "regress" diff --git a/clash-nyanpasu/frontend/nyanpasu/package.json b/clash-nyanpasu/frontend/nyanpasu/package.json index 5ccafa9a48..c4dd8dd600 100644 --- a/clash-nyanpasu/frontend/nyanpasu/package.json +++ b/clash-nyanpasu/frontend/nyanpasu/package.json @@ -39,7 +39,7 @@ "react-dom": "rc", "react-error-boundary": "4.0.13", "react-fast-marquee": "1.6.5", - "react-hook-form-mui": "7.2.0", + "react-hook-form-mui": "7.2.1", "react-i18next": "15.0.2", "react-markdown": "9.0.1", "react-router-dom": "6.26.2", @@ -69,8 +69,8 @@ "@types/react": "18.3.10", "@types/react-dom": "18.3.0", "@types/validator": "13.12.2", - "@vitejs/plugin-react": "4.3.1", - "@vitejs/plugin-react-swc": "3.7.0", + "@vitejs/plugin-react": "4.3.2", + "@vitejs/plugin-react-swc": "3.7.1", "clsx": "2.1.1", "meta-json-schema": "1.18.8", "monaco-yaml": "5.2.2", diff --git a/clash-nyanpasu/frontend/ui/package.json b/clash-nyanpasu/frontend/ui/package.json index c6890ca2bb..7201372d41 100644 --- a/clash-nyanpasu/frontend/ui/package.json +++ b/clash-nyanpasu/frontend/ui/package.json @@ -25,7 +25,7 @@ "@tauri-apps/api": "2.0.0-rc.6", "@types/d3": "7.4.3", "@types/react": "18.3.10", - "@vitejs/plugin-react": "4.3.1", + "@vitejs/plugin-react": "4.3.2", "ahooks": "3.8.1", "d3": "7.9.0", "framer-motion": "12.0.0-alpha.1", @@ -45,6 +45,6 @@ "sass": "1.79.4", "tailwind-merge": "2.5.2", "typescript-plugin-css-modules": "5.1.0", - "vite-plugin-dts": "4.2.2" + "vite-plugin-dts": "4.2.3" } } diff --git a/clash-nyanpasu/manifest/version.json b/clash-nyanpasu/manifest/version.json index 5c0add9702..9530811ae8 100644 --- a/clash-nyanpasu/manifest/version.json +++ b/clash-nyanpasu/manifest/version.json @@ -1,11 +1,11 @@ { "manifest_version": 1, "latest": { - "mihomo": "v1.18.8", - "mihomo_alpha": "alpha-2647135", - "clash_rs": "v0.4.0", + "mihomo": "v1.18.9", + "mihomo_alpha": "alpha-fc9d5cf", + "clash_rs": "v0.5.0", "clash_premium": "2023-09-05-gdcc8d87", - "clash_rs_alpha": "0.4.1-alpha+sha.9e31f42" + "clash_rs_alpha": "0.5.0-alpha+sha.0bf0abc" }, "arch_template": { "mihomo": { @@ -69,5 +69,5 @@ "linux-armv7hf": "clash-armv7-unknown-linux-gnueabihf" } }, - "updated_at": "2024-09-28T22:20:28.528Z" + "updated_at": "2024-09-29T22:20:21.364Z" } diff --git a/clash-nyanpasu/pnpm-lock.yaml b/clash-nyanpasu/pnpm-lock.yaml index 3d9f1a7ad0..a883d3dd6c 100644 --- a/clash-nyanpasu/pnpm-lock.yaml +++ b/clash-nyanpasu/pnpm-lock.yaml @@ -271,8 +271,8 @@ importers: specifier: 1.6.5 version: 1.6.5(react-dom@19.0.0-rc-3edc000d-20240926(react@19.0.0-rc-3edc000d-20240926))(react@19.0.0-rc-3edc000d-20240926) react-hook-form-mui: - specifier: 7.2.0 - version: 7.2.0(dh5u2o7zcjokm2q27utszgh7xi) + specifier: 7.2.1 + version: 7.2.1(dh5u2o7zcjokm2q27utszgh7xi) react-i18next: specifier: 15.0.2 version: 15.0.2(i18next@23.15.1)(react-dom@19.0.0-rc-3edc000d-20240926(react@19.0.0-rc-3edc000d-20240926))(react@19.0.0-rc-3edc000d-20240926) @@ -356,11 +356,11 @@ importers: specifier: 13.12.2 version: 13.12.2 '@vitejs/plugin-react': - specifier: 4.3.1 - version: 4.3.1(vite@5.4.8(@types/node@22.7.4)(less@4.2.0)(sass-embedded@1.78.0)(sass@1.79.4)(stylus@0.62.0)) + specifier: 4.3.2 + version: 4.3.2(vite@5.4.8(@types/node@22.7.4)(less@4.2.0)(sass-embedded@1.78.0)(sass@1.79.4)(stylus@0.62.0)) '@vitejs/plugin-react-swc': - specifier: 3.7.0 - version: 3.7.0(vite@5.4.8(@types/node@22.7.4)(less@4.2.0)(sass-embedded@1.78.0)(sass@1.79.4)(stylus@0.62.0)) + specifier: 3.7.1 + version: 3.7.1(vite@5.4.8(@types/node@22.7.4)(less@4.2.0)(sass-embedded@1.78.0)(sass@1.79.4)(stylus@0.62.0)) clsx: specifier: 2.1.1 version: 2.1.1 @@ -437,8 +437,8 @@ importers: specifier: npm:types-react@rc version: types-react@19.0.0-rc.1 '@vitejs/plugin-react': - specifier: 4.3.1 - version: 4.3.1(vite@5.4.8(@types/node@22.7.4)(less@4.2.0)(sass-embedded@1.78.0)(sass@1.79.4)(stylus@0.62.0)) + specifier: 4.3.2 + version: 4.3.2(vite@5.4.8(@types/node@22.7.4)(less@4.2.0)(sass-embedded@1.78.0)(sass@1.79.4)(stylus@0.62.0)) ahooks: specifier: 3.8.1 version: 3.8.1(react@19.0.0-rc-3edc000d-20240926) @@ -492,8 +492,8 @@ importers: specifier: 5.1.0 version: 5.1.0(typescript@5.6.2) vite-plugin-dts: - specifier: 4.2.2 - version: 4.2.2(@types/node@22.7.4)(rollup@4.21.0)(typescript@5.6.2)(vite@5.4.8(@types/node@22.7.4)(less@4.2.0)(sass-embedded@1.78.0)(sass@1.79.4)(stylus@0.62.0)) + specifier: 4.2.3 + version: 4.2.3(@types/node@22.7.4)(rollup@4.21.0)(typescript@5.6.2)(vite@5.4.8(@types/node@22.7.4)(less@4.2.0)(sass-embedded@1.78.0)(sass@1.79.4)(stylus@0.62.0)) scripts: dependencies: @@ -578,26 +578,14 @@ packages: '@antfu/utils@0.7.10': resolution: {integrity: sha512-+562v9k4aI80m1+VuMHehNJWLOFjBnXn3tdOitzD0il5b7smkSBal4+a3oKiQTbrwMmN/TBUMDvbdoWDehgOww==} - '@babel/code-frame@7.24.2': - resolution: {integrity: sha512-y5+tLQyV8pg3fsiln67BVLD1P13Eg4lh5RW9mF0zUuvLrv9uIQ4MCL+CRT+FTsBlBjcIan6PGsLcBN0m3ClUyQ==} - engines: {node: '>=6.9.0'} - '@babel/code-frame@7.24.7': resolution: {integrity: sha512-BcYH1CVJBO9tvyIZ2jVeXgSIMvGZ2FDRvDdOIVQyuklNKSsx+eppDEBq/g47Ayw+RqNFE+URvOShmf+f/qwAlA==} engines: {node: '>=6.9.0'} - '@babel/compat-data@7.24.4': - resolution: {integrity: sha512-vg8Gih2MLK+kOkHJp4gBEIkyaIi00jgWot2D9QOmmfLC8jINSOzmCLta6Bvz/JSBCqnegV0L80jhxkol5GWNfQ==} - engines: {node: '>=6.9.0'} - '@babel/compat-data@7.25.4': resolution: {integrity: sha512-+LGRog6RAsCJrrrg/IO6LGmpphNe5DiK30dGjCoxxeGv49B10/3XYGxPsAwrDlMFcFEvdAUavDT8r9k/hSyQqQ==} engines: {node: '>=6.9.0'} - '@babel/core@7.24.5': - resolution: {integrity: sha512-tVQRucExLQ02Boi4vdPp49svNGcfL2GhdTCT9aldhXgCJVAI21EtRfBettiuLUwce/7r6bFdgs6JFkcdTiFttA==} - engines: {node: '>=6.9.0'} - '@babel/core@7.25.2': resolution: {integrity: sha512-BBt3opiCOxUr9euZ5/ro/Xv8/V7yJ5bjYMqG/C1YAo8MIKAnumZalCN+msbci3Pigy4lIQfPUpfMM27HMGaYEA==} engines: {node: '>=6.9.0'} @@ -614,10 +602,6 @@ packages: resolution: {integrity: sha512-BaDeOonYvhdKw+JoMVkAixAAJzG2jVPIwWoKBPdYuY9b452e2rPuI9QPYh3KpofZ3pW2akOmwZLOiOsHMiqRAg==} engines: {node: '>=6.9.0'} - '@babel/helper-compilation-targets@7.23.6': - resolution: {integrity: sha512-9JB548GZoQVmzrFgp8o7KxdgkTGm6xs9DW0o/Pim72UDjzr5ObUQ6ZzYPqA+g9OTS2bBQoctLJrky0RDCAWRgQ==} - engines: {node: '>=6.9.0'} - '@babel/helper-compilation-targets@7.25.2': resolution: {integrity: sha512-U2U5LsSaZ7TAt3cfaymQ8WHh0pxvdHoEk6HVpaexxixjyEquMh0L0YNJNM6CTGKMXV1iksi0iZkGw4AcFkPaaw==} engines: {node: '>=6.9.0'} @@ -628,10 +612,6 @@ packages: peerDependencies: '@babel/core': ^7.0.0 - '@babel/helper-environment-visitor@7.22.20': - resolution: {integrity: sha512-zfedSIzFhat/gFhWfHtgWvlec0nqB9YEIVrpuwjruLlXfUSnA8cJB0miHKwqDnQ7d32aKo2xt88/xZptwxbfhA==} - engines: {node: '>=6.9.0'} - '@babel/helper-environment-visitor@7.24.7': resolution: {integrity: sha512-DoiN84+4Gnd0ncbBOM9AZENV4a5ZiL39HYMyZJGZ/AZEykHYdJw0wW3kdcsh9/Kn+BRXHLkkklZ51ecPKmI1CQ==} engines: {node: '>=6.9.0'} @@ -656,12 +636,6 @@ packages: resolution: {integrity: sha512-8AyH3C+74cgCVVXow/myrynrAGv+nTVg5vKu2nZph9x7RcRwzmh0VFallJuFTZ9mx6u4eSdXZfcOzSqTUm0HCA==} engines: {node: '>=6.9.0'} - '@babel/helper-module-transforms@7.24.5': - resolution: {integrity: sha512-9GxeY8c2d2mdQUP1Dye0ks3VDyIMS98kt/llQ2nUId8IsWqTF0l1LkSX0/uP7l7MCDrzXS009Hyhe2gzTiGW8A==} - engines: {node: '>=6.9.0'} - peerDependencies: - '@babel/core': ^7.0.0 - '@babel/helper-module-transforms@7.25.2': resolution: {integrity: sha512-BjyRAbix6j/wv83ftcVJmBt72QtHI56C7JXZoG2xATiLpmoC7dpd8WnkikExHDVPpi/3qCmO6WY1EaXOluiecQ==} engines: {node: '>=6.9.0'} @@ -672,10 +646,6 @@ packages: resolution: {integrity: sha512-jKiTsW2xmWwxT1ixIdfXUZp+P5yURx2suzLZr5Hi64rURpDYdMW0pv+Uf17EYk2Rd428Lx4tLsnjGJzYKDM/6A==} engines: {node: '>=6.9.0'} - '@babel/helper-plugin-utils@7.24.5': - resolution: {integrity: sha512-xjNLDopRzW2o6ba0gKbkZq5YWEBaK3PCyTOY1K2P/O07LGMhMqlMXPxwN4S5/RhWuCobT8z0jrlKGlYmeR1OhQ==} - engines: {node: '>=6.9.0'} - '@babel/helper-plugin-utils@7.24.8': resolution: {integrity: sha512-FFWx5142D8h2Mgr/iPVGH5G7w6jDn4jUSpZTyDnQO0Yn7Ks2Kuz6Pci8H6MPCoUJegd/UZQ3tAvfLCxQSnWWwg==} engines: {node: '>=6.9.0'} @@ -686,10 +656,6 @@ packages: peerDependencies: '@babel/core': ^7.0.0 - '@babel/helper-simple-access@7.24.5': - resolution: {integrity: sha512-uH3Hmf5q5n7n8mz7arjUlDOCbttY/DW4DYhE6FUsjKJ/oYC1kQQUvwEQWxRwUpX9qQKRXeqLwWxrqilMrf32sQ==} - engines: {node: '>=6.9.0'} - '@babel/helper-simple-access@7.24.7': resolution: {integrity: sha512-zBAIvbCMh5Ts+b86r/CjU+4XGYIs+R1j951gxI3KmmxBMhCg4oQMsv6ZXQ64XOm/cvzfU1FmoCyt6+owc5QMYg==} engines: {node: '>=6.9.0'} @@ -698,10 +664,6 @@ packages: resolution: {integrity: sha512-IO+DLT3LQUElMbpzlatRASEyQtfhSE0+m465v++3jyyXeBTBUjtVZg28/gHeV5mrTJqvEKhKroBGAvhW+qPHiQ==} engines: {node: '>=6.9.0'} - '@babel/helper-split-export-declaration@7.24.5': - resolution: {integrity: sha512-5CHncttXohrHk8GWOFCcCl4oRD9fKosWlIRgWm4ql9VYioKm52Mk2xsmoohvm7f3JoiLSM5ZgJuRaf5QZZYd3Q==} - engines: {node: '>=6.9.0'} - '@babel/helper-split-export-declaration@7.24.7': resolution: {integrity: sha512-oy5V7pD+UvfkEATUKvIjvIAH/xCzfsFVw7ygW2SI6NClZzquT+mwdTfgfdbUiceh6iQO0CHtCPsyze/MZ2YbAA==} engines: {node: '>=6.9.0'} @@ -714,26 +676,14 @@ packages: resolution: {integrity: sha512-rR+PBcQ1SMQDDyF6X0wxtG8QyLCgUB0eRAGguqRLfkCA87l7yAP7ehq8SNj96OOGTO8OBV70KhuFYcIkHXOg0w==} engines: {node: '>=6.9.0'} - '@babel/helper-validator-option@7.23.5': - resolution: {integrity: sha512-85ttAOMLsr53VgXkTbkx8oA6YTfT4q7/HzXSLEYmjcSTJPMPQtvq1BD79Byep5xMUYbGRzEpDsjUf3dyp54IKw==} - engines: {node: '>=6.9.0'} - '@babel/helper-validator-option@7.24.8': resolution: {integrity: sha512-xb8t9tD1MHLungh/AIoWYN+gVHaB9kwlu8gffXGSt3FFEIT7RjS+xWbc2vUD1UTZdIpKj/ab3rdqJ7ufngyi2Q==} engines: {node: '>=6.9.0'} - '@babel/helpers@7.24.5': - resolution: {integrity: sha512-CiQmBMMpMQHwM5m01YnrM6imUG1ebgYJ+fAIW4FZe6m4qHTPaRHti+R8cggAwkdz4oXhtO4/K9JWlh+8hIfR2Q==} - engines: {node: '>=6.9.0'} - '@babel/helpers@7.25.6': resolution: {integrity: sha512-Xg0tn4HcfTijTwfDwYlvVCl43V6h4KyVVX2aEm4qdO/PC6L2YvzLHFdmxhoeSA3eslcE6+ZVXHgWwopXYLNq4Q==} engines: {node: '>=6.9.0'} - '@babel/highlight@7.24.5': - resolution: {integrity: sha512-8lLmua6AVh/8SLJRRVD6V8p73Hir9w5mJrhE+IPpILG31KKlI9iz5zmBYKcWPS59qSfgP9RaSBQSHHE81WKuEw==} - engines: {node: '>=6.9.0'} - '@babel/highlight@7.24.7': resolution: {integrity: sha512-EStJpq4OuY8xYfhGVXngigBJRWxftKX9ksiGDnmlY3o7B/V7KIAc9X4oiK87uPJSc/vs5L869bem5fhZa8caZw==} engines: {node: '>=6.9.0'} @@ -762,14 +712,14 @@ packages: peerDependencies: '@babel/core': ^7.0.0-0 - '@babel/plugin-transform-react-jsx-self@7.24.5': - resolution: {integrity: sha512-RtCJoUO2oYrYwFPtR1/jkoBEcFuI1ae9a9IMxeyAVa3a1Ap4AnxmyIKG2b2FaJKqkidw/0cxRbWN+HOs6ZWd1w==} + '@babel/plugin-transform-react-jsx-self@7.24.7': + resolution: {integrity: sha512-fOPQYbGSgH0HUp4UJO4sMBFjY6DuWq+2i8rixyUMb3CdGixs/gccURvYOAhajBdKDoGajFr3mUq5rH3phtkGzw==} engines: {node: '>=6.9.0'} peerDependencies: '@babel/core': ^7.0.0-0 - '@babel/plugin-transform-react-jsx-source@7.24.1': - resolution: {integrity: sha512-1v202n7aUq4uXAieRTKcwPzNyphlCuqHHDcdSNc+vdhoTEZcFMh+L5yZuCmGaIO7bs1nJUNfHB89TZyoL48xNA==} + '@babel/plugin-transform-react-jsx-source@7.24.7': + resolution: {integrity: sha512-J2z+MWzZHVOemyLweMqngXrgGC42jQ//R0KdxqkIz/OrbVIIlhFI3WigZ5fO+nwFvBlncr4MGapd8vTyc7RPNQ==} engines: {node: '>=6.9.0'} peerDependencies: '@babel/core': ^7.0.0-0 @@ -2125,68 +2075,68 @@ packages: peerDependencies: '@svgr/core': '*' - '@swc/core-darwin-arm64@1.6.1': - resolution: {integrity: sha512-u6GdwOXsOEdNAdSI6nWq6G2BQw5HiSNIZVcBaH1iSvBnxZvWbnIKyDiZKaYnDwTLHLzig2GuUjjE2NaCJPy4jg==} + '@swc/core-darwin-arm64@1.7.26': + resolution: {integrity: sha512-FF3CRYTg6a7ZVW4yT9mesxoVVZTrcSWtmZhxKCYJX9brH4CS/7PRPjAKNk6kzWgWuRoglP7hkjQcd6EpMcZEAw==} engines: {node: '>=10'} cpu: [arm64] os: [darwin] - '@swc/core-darwin-x64@1.6.1': - resolution: {integrity: sha512-/tXwQibkDNLVbAtr7PUQI0iQjoB708fjhDDDfJ6WILSBVZ3+qs/LHjJ7jHwumEYxVq1XA7Fv2Q7SE/ZSQoWHcQ==} + '@swc/core-darwin-x64@1.7.26': + resolution: {integrity: sha512-az3cibZdsay2HNKmc4bjf62QVukuiMRh5sfM5kHR/JMTrLyS6vSw7Ihs3UTkZjUxkLTT8ro54LI6sV6sUQUbLQ==} engines: {node: '>=10'} cpu: [x64] os: [darwin] - '@swc/core-linux-arm-gnueabihf@1.6.1': - resolution: {integrity: sha512-aDgipxhJTms8iH78emHVutFR2c16LNhO+NTRCdYi+X4PyIn58/DyYTH6VDZ0AeEcS5f132ZFldU5AEgExwihXA==} + '@swc/core-linux-arm-gnueabihf@1.7.26': + resolution: {integrity: sha512-VYPFVJDO5zT5U3RpCdHE5v1gz4mmR8BfHecUZTmD2v1JeFY6fv9KArJUpjrHEEsjK/ucXkQFmJ0jaiWXmpOV9Q==} engines: {node: '>=10'} cpu: [arm] os: [linux] - '@swc/core-linux-arm64-gnu@1.6.1': - resolution: {integrity: sha512-XkJ+eO4zUKG5g458RyhmKPyBGxI0FwfWFgpfIj5eDybxYJ6s4HBT5MoxyBLorB5kMlZ0XoY/usUMobPVY3nL0g==} + '@swc/core-linux-arm64-gnu@1.7.26': + resolution: {integrity: sha512-YKevOV7abpjcAzXrhsl+W48Z9mZvgoVs2eP5nY+uoMAdP2b3GxC0Df1Co0I90o2lkzO4jYBpTMcZlmUXLdXn+Q==} engines: {node: '>=10'} cpu: [arm64] os: [linux] - '@swc/core-linux-arm64-musl@1.6.1': - resolution: {integrity: sha512-dr6YbLBg/SsNxs1hDqJhxdcrS8dGMlOXJwXIrUvACiA8jAd6S5BxYCaqsCefLYXtaOmu0bbx1FB/evfodqB70Q==} + '@swc/core-linux-arm64-musl@1.7.26': + resolution: {integrity: sha512-3w8iZICMkQQON0uIcvz7+Q1MPOW6hJ4O5ETjA0LSP/tuKqx30hIniCGOgPDnv3UTMruLUnQbtBwVCZTBKR3Rkg==} engines: {node: '>=10'} cpu: [arm64] os: [linux] - '@swc/core-linux-x64-gnu@1.6.1': - resolution: {integrity: sha512-A0b/3V+yFy4LXh3O9umIE7LXPC7NBWdjl6AQYqymSMcMu0EOb1/iygA6s6uWhz9y3e172Hpb9b/CGsuD8Px/bg==} + '@swc/core-linux-x64-gnu@1.7.26': + resolution: {integrity: sha512-c+pp9Zkk2lqb06bNGkR2Looxrs7FtGDMA4/aHjZcCqATgp348hOKH5WPvNLBl+yPrISuWjbKDVn3NgAvfvpH4w==} engines: {node: '>=10'} cpu: [x64] os: [linux] - '@swc/core-linux-x64-musl@1.6.1': - resolution: {integrity: sha512-5dJjlzZXhC87nZZZWbpiDP8kBIO0ibis893F/rtPIQBI5poH+iJuA32EU3wN4/WFHeK4et8z6SGSVghPtWyk4g==} + '@swc/core-linux-x64-musl@1.7.26': + resolution: {integrity: sha512-PgtyfHBF6xG87dUSSdTJHwZ3/8vWZfNIXQV2GlwEpslrOkGqy+WaiiyE7Of7z9AvDILfBBBcJvJ/r8u980wAfQ==} engines: {node: '>=10'} cpu: [x64] os: [linux] - '@swc/core-win32-arm64-msvc@1.6.1': - resolution: {integrity: sha512-HBi1ZlwvfcUibLtT3g/lP57FaDPC799AD6InolB2KSgkqyBbZJ9wAXM8/CcH67GLIP0tZ7FqblrJTzGXxetTJQ==} + '@swc/core-win32-arm64-msvc@1.7.26': + resolution: {integrity: sha512-9TNXPIJqFynlAOrRD6tUQjMq7KApSklK3R/tXgIxc7Qx+lWu8hlDQ/kVPLpU7PWvMMwC/3hKBW+p5f+Tms1hmA==} engines: {node: '>=10'} cpu: [arm64] os: [win32] - '@swc/core-win32-ia32-msvc@1.6.1': - resolution: {integrity: sha512-AKqHohlWERclexar5y6ux4sQ8yaMejEXNxeKXm7xPhXrp13/1p4/I3E5bPVX/jMnvpm4HpcKSP0ee2WsqmhhPw==} + '@swc/core-win32-ia32-msvc@1.7.26': + resolution: {integrity: sha512-9YngxNcG3177GYdsTum4V98Re+TlCeJEP4kEwEg9EagT5s3YejYdKwVAkAsJszzkXuyRDdnHUpYbTrPG6FiXrQ==} engines: {node: '>=10'} cpu: [ia32] os: [win32] - '@swc/core-win32-x64-msvc@1.6.1': - resolution: {integrity: sha512-0dLdTLd+ONve8kgC5T6VQ2Y5G+OZ7y0ujjapnK66wpvCBM6BKYGdT/OKhZKZydrC5gUKaxFN6Y5oOt9JOFUrOQ==} + '@swc/core-win32-x64-msvc@1.7.26': + resolution: {integrity: sha512-VR+hzg9XqucgLjXxA13MtV5O3C0bK0ywtLIBw/+a+O+Oc6mxFWHtdUeXDbIi5AiPbn0fjgVJMqYnyjGyyX8u0w==} engines: {node: '>=10'} cpu: [x64] os: [win32] - '@swc/core@1.6.1': - resolution: {integrity: sha512-Yz5uj5hNZpS5brLtBvKY0L4s2tBAbQ4TjmW8xF1EC3YLFxQRrUjMP49Zm1kp/KYyYvTkSaG48Ffj2YWLu9nChw==} + '@swc/core@1.7.26': + resolution: {integrity: sha512-f5uYFf+TmMQyYIoxkn/evWhNGuUzC730dFwAKGwBVHHVoPyak1/GvJUm6i1SKl+2Hrj9oN0i3WSoWWZ4pgI8lw==} engines: {node: '>=10'} peerDependencies: '@swc/helpers': '*' @@ -2197,8 +2147,8 @@ packages: '@swc/counter@0.1.3': resolution: {integrity: sha512-e2BR4lsJkkRlKZ/qCHPw9ZaSxc0MVUd7gtbtaB7aMvHeJVYe8sOB8DBZkP2DtISHGSku9sCK6T6cnY0CtXrOCQ==} - '@swc/types@0.1.8': - resolution: {integrity: sha512-RNFA3+7OJFNYY78x0FYwi1Ow+iF1eF5WvmfY1nXPOEH4R2p/D4Cr1vzje7dNAI2aLFqpv8Wyz4oKSWqIZArpQA==} + '@swc/types@0.1.12': + resolution: {integrity: sha512-wBJA+SdtkbFhHjTMYH+dEH1y4VpfGdAc2Kw/LK09i9bXd/K6j6PkDcFCEzb6iVfZMkPRrl/q0e3toqTAJdkIVA==} '@szmarczak/http-timer@4.0.6': resolution: {integrity: sha512-4BAffykYOgO+5nzBWYwE3W90sBgLJoUPRWWcL8wlyiM8IB8ipJz3UMJ9KXQd1RKQXpKp8Tutn80HZtWsu2u76w==} @@ -2673,13 +2623,13 @@ packages: '@ungap/structured-clone@1.2.0': resolution: {integrity: sha512-zuVdFrMJiuCDQUMCzQaD6KL28MjnqqN8XnAqiEq9PNm/hCPTSGfrXCOfwj1ow4LFb/tNymJPwsNbVePc1xFqrQ==} - '@vitejs/plugin-react-swc@3.7.0': - resolution: {integrity: sha512-yrknSb3Dci6svCd/qhHqhFPDSw0QtjumcqdKMoNNzmOl5lMXTTiqzjWtG4Qask2HdvvzaNgSunbQGet8/GrKdA==} + '@vitejs/plugin-react-swc@3.7.1': + resolution: {integrity: sha512-vgWOY0i1EROUK0Ctg1hwhtC3SdcDjZcdit4Ups4aPkDcB1jYhmo+RMYWY87cmXMhvtD5uf8lV89j2w16vkdSVg==} peerDependencies: vite: ^4 || ^5 - '@vitejs/plugin-react@4.3.1': - resolution: {integrity: sha512-m/V2syj5CuVnaxcUJOQRel/Wr31FFXRFlnOoq1TVtkCxsY5veGMTEmpWHndrhB2U8ScHtCQB1e+4hWYExQc6Lg==} + '@vitejs/plugin-react@4.3.2': + resolution: {integrity: sha512-hieu+o05v4glEBucTcKMK3dlES0OeJlD9YVOAPraVMOInBCwzumaIFiUjr4bHK7NPgnAHgiskUoceKercrN8vg==} engines: {node: ^14.18.0 || >=16.0.0} peerDependencies: vite: ^4.2.0 || ^5.0.0 @@ -5783,8 +5733,8 @@ packages: react: '>= 16.8.0 || ^18.0.0' react-dom: '>= 16.8.0 || ^18.0.0' - react-hook-form-mui@7.2.0: - resolution: {integrity: sha512-F7SAOQ7EGqOaFtiLaGZxDvwXHT4DerTLb6V+jBM3hVdI2/2zDWPA4tkJo1WZSaaUa1YZsTLA0hI3jubru1Aktg==} + react-hook-form-mui@7.2.1: + resolution: {integrity: sha512-aLMck3QAaAH6Va9geZa+IuQh5xsHwDkqS46M8sswPKDv++NNdEO417yjGsaPaSTDk4SG9TCNteKSEgpmxKzztw==} engines: {node: '>=14'} peerDependencies: '@mui/icons-material': '>= 5.x <7' @@ -6932,8 +6882,8 @@ packages: engines: {node: ^18.19.0 || >=20.6.0} hasBin: true - vite-plugin-dts@4.2.2: - resolution: {integrity: sha512-USwTMReZFf8yXV+cKkm4WOMqmFjbReAvkyxON5xzdnZzJEBnFgax6BBDZIGGr9WMJYvhHdpaIHLrOjXDcla4OA==} + vite-plugin-dts@4.2.3: + resolution: {integrity: sha512-O5NalzHANQRwVw1xj8KQun3Bv8OSDAlNJXrnqoAz10BOuW8FVvY5g4ygj+DlJZL5mtSPuMu9vd3OfrdW5d4k6w==} engines: {node: ^14.18.0 || >=16.0.0} peerDependencies: typescript: '*' @@ -7211,40 +7161,13 @@ snapshots: '@antfu/utils@0.7.10': {} - '@babel/code-frame@7.24.2': - dependencies: - '@babel/highlight': 7.24.5 - picocolors: 1.1.0 - '@babel/code-frame@7.24.7': dependencies: '@babel/highlight': 7.24.7 picocolors: 1.1.0 - '@babel/compat-data@7.24.4': {} - '@babel/compat-data@7.25.4': {} - '@babel/core@7.24.5': - dependencies: - '@ampproject/remapping': 2.3.0 - '@babel/code-frame': 7.24.2 - '@babel/generator': 7.25.6 - '@babel/helper-compilation-targets': 7.23.6 - '@babel/helper-module-transforms': 7.24.5(@babel/core@7.24.5) - '@babel/helpers': 7.24.5 - '@babel/parser': 7.25.6 - '@babel/template': 7.25.0 - '@babel/traverse': 7.25.6 - '@babel/types': 7.25.6 - convert-source-map: 2.0.0 - debug: 4.3.7 - gensync: 1.0.0-beta.2 - json5: 2.2.3 - semver: 6.3.1 - transitivePeerDependencies: - - supports-color - '@babel/core@7.25.2': dependencies: '@ampproject/remapping': 2.3.0 @@ -7283,14 +7206,6 @@ snapshots: dependencies: '@babel/types': 7.25.6 - '@babel/helper-compilation-targets@7.23.6': - dependencies: - '@babel/compat-data': 7.24.4 - '@babel/helper-validator-option': 7.23.5 - browserslist: 4.23.0 - lru-cache: 5.1.1 - semver: 6.3.1 - '@babel/helper-compilation-targets@7.25.2': dependencies: '@babel/compat-data': 7.25.4 @@ -7312,8 +7227,6 @@ snapshots: transitivePeerDependencies: - supports-color - '@babel/helper-environment-visitor@7.22.20': {} - '@babel/helper-environment-visitor@7.24.7': dependencies: '@babel/types': 7.25.6 @@ -7348,15 +7261,6 @@ snapshots: transitivePeerDependencies: - supports-color - '@babel/helper-module-transforms@7.24.5(@babel/core@7.24.5)': - dependencies: - '@babel/core': 7.24.5 - '@babel/helper-environment-visitor': 7.22.20 - '@babel/helper-module-imports': 7.24.3 - '@babel/helper-simple-access': 7.24.5 - '@babel/helper-split-export-declaration': 7.24.5 - '@babel/helper-validator-identifier': 7.24.7 - '@babel/helper-module-transforms@7.25.2(@babel/core@7.25.2)': dependencies: '@babel/core': 7.25.2 @@ -7371,8 +7275,6 @@ snapshots: dependencies: '@babel/types': 7.25.6 - '@babel/helper-plugin-utils@7.24.5': {} - '@babel/helper-plugin-utils@7.24.8': {} '@babel/helper-replace-supers@7.25.0(@babel/core@7.25.2)': @@ -7384,10 +7286,6 @@ snapshots: transitivePeerDependencies: - supports-color - '@babel/helper-simple-access@7.24.5': - dependencies: - '@babel/types': 7.25.6 - '@babel/helper-simple-access@7.24.7': dependencies: '@babel/traverse': 7.25.6 @@ -7402,10 +7300,6 @@ snapshots: transitivePeerDependencies: - supports-color - '@babel/helper-split-export-declaration@7.24.5': - dependencies: - '@babel/types': 7.25.6 - '@babel/helper-split-export-declaration@7.24.7': dependencies: '@babel/types': 7.25.6 @@ -7415,30 +7309,13 @@ snapshots: '@babel/helper-validator-identifier@7.24.7': {} - '@babel/helper-validator-option@7.23.5': {} - '@babel/helper-validator-option@7.24.8': {} - '@babel/helpers@7.24.5': - dependencies: - '@babel/template': 7.25.0 - '@babel/traverse': 7.25.6 - '@babel/types': 7.25.6 - transitivePeerDependencies: - - supports-color - '@babel/helpers@7.25.6': dependencies: '@babel/template': 7.25.0 '@babel/types': 7.25.6 - '@babel/highlight@7.24.5': - dependencies: - '@babel/helper-validator-identifier': 7.24.7 - chalk: 2.4.2 - js-tokens: 4.0.0 - picocolors: 1.1.0 - '@babel/highlight@7.24.7': dependencies: '@babel/helper-validator-identifier': 7.24.7 @@ -7468,15 +7345,15 @@ snapshots: '@babel/core': 7.25.2 '@babel/helper-plugin-utils': 7.24.8 - '@babel/plugin-transform-react-jsx-self@7.24.5(@babel/core@7.24.5)': + '@babel/plugin-transform-react-jsx-self@7.24.7(@babel/core@7.25.2)': dependencies: - '@babel/core': 7.24.5 - '@babel/helper-plugin-utils': 7.24.5 + '@babel/core': 7.25.2 + '@babel/helper-plugin-utils': 7.24.8 - '@babel/plugin-transform-react-jsx-source@7.24.1(@babel/core@7.24.5)': + '@babel/plugin-transform-react-jsx-source@7.24.7(@babel/core@7.25.2)': dependencies: - '@babel/core': 7.24.5 - '@babel/helper-plugin-utils': 7.24.5 + '@babel/core': 7.25.2 + '@babel/helper-plugin-utils': 7.24.8 '@babel/runtime@7.24.5': dependencies: @@ -8812,55 +8689,55 @@ snapshots: transitivePeerDependencies: - supports-color - '@swc/core-darwin-arm64@1.6.1': + '@swc/core-darwin-arm64@1.7.26': optional: true - '@swc/core-darwin-x64@1.6.1': + '@swc/core-darwin-x64@1.7.26': optional: true - '@swc/core-linux-arm-gnueabihf@1.6.1': + '@swc/core-linux-arm-gnueabihf@1.7.26': optional: true - '@swc/core-linux-arm64-gnu@1.6.1': + '@swc/core-linux-arm64-gnu@1.7.26': optional: true - '@swc/core-linux-arm64-musl@1.6.1': + '@swc/core-linux-arm64-musl@1.7.26': optional: true - '@swc/core-linux-x64-gnu@1.6.1': + '@swc/core-linux-x64-gnu@1.7.26': optional: true - '@swc/core-linux-x64-musl@1.6.1': + '@swc/core-linux-x64-musl@1.7.26': optional: true - '@swc/core-win32-arm64-msvc@1.6.1': + '@swc/core-win32-arm64-msvc@1.7.26': optional: true - '@swc/core-win32-ia32-msvc@1.6.1': + '@swc/core-win32-ia32-msvc@1.7.26': optional: true - '@swc/core-win32-x64-msvc@1.6.1': + '@swc/core-win32-x64-msvc@1.7.26': optional: true - '@swc/core@1.6.1': + '@swc/core@1.7.26': dependencies: '@swc/counter': 0.1.3 - '@swc/types': 0.1.8 + '@swc/types': 0.1.12 optionalDependencies: - '@swc/core-darwin-arm64': 1.6.1 - '@swc/core-darwin-x64': 1.6.1 - '@swc/core-linux-arm-gnueabihf': 1.6.1 - '@swc/core-linux-arm64-gnu': 1.6.1 - '@swc/core-linux-arm64-musl': 1.6.1 - '@swc/core-linux-x64-gnu': 1.6.1 - '@swc/core-linux-x64-musl': 1.6.1 - '@swc/core-win32-arm64-msvc': 1.6.1 - '@swc/core-win32-ia32-msvc': 1.6.1 - '@swc/core-win32-x64-msvc': 1.6.1 + '@swc/core-darwin-arm64': 1.7.26 + '@swc/core-darwin-x64': 1.7.26 + '@swc/core-linux-arm-gnueabihf': 1.7.26 + '@swc/core-linux-arm64-gnu': 1.7.26 + '@swc/core-linux-arm64-musl': 1.7.26 + '@swc/core-linux-x64-gnu': 1.7.26 + '@swc/core-linux-x64-musl': 1.7.26 + '@swc/core-win32-arm64-msvc': 1.7.26 + '@swc/core-win32-ia32-msvc': 1.7.26 + '@swc/core-win32-x64-msvc': 1.7.26 '@swc/counter@0.1.3': {} - '@swc/types@0.1.8': + '@swc/types@0.1.12': dependencies: '@swc/counter': 0.1.3 @@ -9392,18 +9269,18 @@ snapshots: '@ungap/structured-clone@1.2.0': {} - '@vitejs/plugin-react-swc@3.7.0(vite@5.4.8(@types/node@22.7.4)(less@4.2.0)(sass-embedded@1.78.0)(sass@1.79.4)(stylus@0.62.0))': + '@vitejs/plugin-react-swc@3.7.1(vite@5.4.8(@types/node@22.7.4)(less@4.2.0)(sass-embedded@1.78.0)(sass@1.79.4)(stylus@0.62.0))': dependencies: - '@swc/core': 1.6.1 + '@swc/core': 1.7.26 vite: 5.4.8(@types/node@22.7.4)(less@4.2.0)(sass-embedded@1.78.0)(sass@1.79.4)(stylus@0.62.0) transitivePeerDependencies: - '@swc/helpers' - '@vitejs/plugin-react@4.3.1(vite@5.4.8(@types/node@22.7.4)(less@4.2.0)(sass-embedded@1.78.0)(sass@1.79.4)(stylus@0.62.0))': + '@vitejs/plugin-react@4.3.2(vite@5.4.8(@types/node@22.7.4)(less@4.2.0)(sass-embedded@1.78.0)(sass@1.79.4)(stylus@0.62.0))': dependencies: - '@babel/core': 7.24.5 - '@babel/plugin-transform-react-jsx-self': 7.24.5(@babel/core@7.24.5) - '@babel/plugin-transform-react-jsx-source': 7.24.1(@babel/core@7.24.5) + '@babel/core': 7.25.2 + '@babel/plugin-transform-react-jsx-self': 7.24.7(@babel/core@7.25.2) + '@babel/plugin-transform-react-jsx-source': 7.24.7(@babel/core@7.25.2) '@types/babel__core': 7.20.5 react-refresh: 0.14.2 vite: 5.4.8(@types/node@22.7.4)(less@4.2.0)(sass-embedded@1.78.0)(sass@1.79.4)(stylus@0.62.0) @@ -12812,7 +12689,7 @@ snapshots: react: 19.0.0-rc-3edc000d-20240926 react-dom: 19.0.0-rc-3edc000d-20240926(react@19.0.0-rc-3edc000d-20240926) - react-hook-form-mui@7.2.0(dh5u2o7zcjokm2q27utszgh7xi): + react-hook-form-mui@7.2.1(dh5u2o7zcjokm2q27utszgh7xi): dependencies: '@mui/material': 6.1.1(@emotion/react@11.13.3(react@19.0.0-rc-3edc000d-20240926)(types-react@19.0.0-rc.1))(@emotion/styled@11.13.0(@emotion/react@11.13.3(react@19.0.0-rc-3edc000d-20240926)(types-react@19.0.0-rc.1))(react@19.0.0-rc-3edc000d-20240926)(types-react@19.0.0-rc.1))(react-dom@19.0.0-rc-3edc000d-20240926(react@19.0.0-rc-3edc000d-20240926))(react@19.0.0-rc-3edc000d-20240926)(types-react@19.0.0-rc.1) react: 19.0.0-rc-3edc000d-20240926 @@ -14101,7 +13978,7 @@ snapshots: - rollup - supports-color - vite-plugin-dts@4.2.2(@types/node@22.7.4)(rollup@4.21.0)(typescript@5.6.2)(vite@5.4.8(@types/node@22.7.4)(less@4.2.0)(sass-embedded@1.78.0)(sass@1.79.4)(stylus@0.62.0)): + vite-plugin-dts@4.2.3(@types/node@22.7.4)(rollup@4.21.0)(typescript@5.6.2)(vite@5.4.8(@types/node@22.7.4)(less@4.2.0)(sass-embedded@1.78.0)(sass@1.79.4)(stylus@0.62.0)): dependencies: '@microsoft/api-extractor': 7.47.7(@types/node@22.7.4) '@rollup/pluginutils': 5.1.0(rollup@4.21.0) diff --git a/filebrowser/.github/workflows/stale.yml b/filebrowser/.github/workflows/stale.yml index 60c6ae5ea3..45a7e9e50d 100644 --- a/filebrowser/.github/workflows/stale.yml +++ b/filebrowser/.github/workflows/stale.yml @@ -11,7 +11,7 @@ jobs: stale: runs-on: ubuntu-latest steps: - - uses: actions/stale@v5 + - uses: actions/stale@v9 with: stale-pr-message: 'This PR is stale because it has been open 30 days with no activity. Remove stale label or comment or this will be closed in 5 days.' close-pr-message: 'This PR was closed because it has been stalled for 5 days with no activity.' diff --git a/filebrowser/frontend/package-lock.json b/filebrowser/frontend/package-lock.json index 624f94eb82..5dc0c1e573 100644 --- a/filebrowser/frontend/package-lock.json +++ b/filebrowser/frontend/package-lock.json @@ -2558,9 +2558,9 @@ } }, "node_modules/@rollup/rollup-android-arm-eabi": { - "version": "4.21.3", - "resolved": "https://registry.npmjs.org/@rollup/rollup-android-arm-eabi/-/rollup-android-arm-eabi-4.21.3.tgz", - "integrity": "sha512-MmKSfaB9GX+zXl6E8z4koOr/xU63AMVleLEa64v7R0QF/ZloMs5vcD1sHgM64GXXS1csaJutG+ddtzcueI/BLg==", + "version": "4.22.4", + "resolved": "https://registry.npmjs.org/@rollup/rollup-android-arm-eabi/-/rollup-android-arm-eabi-4.22.4.tgz", + "integrity": "sha512-Fxamp4aEZnfPOcGA8KSNEohV8hX7zVHOemC8jVBoBUHu5zpJK/Eu3uJwt6BMgy9fkvzxDaurgj96F/NiLukF2w==", "cpu": [ "arm" ], @@ -2571,9 +2571,9 @@ ] }, "node_modules/@rollup/rollup-android-arm64": { - "version": "4.21.3", - "resolved": "https://registry.npmjs.org/@rollup/rollup-android-arm64/-/rollup-android-arm64-4.21.3.tgz", - "integrity": "sha512-zrt8ecH07PE3sB4jPOggweBjJMzI1JG5xI2DIsUbkA+7K+Gkjys6eV7i9pOenNSDJH3eOr/jLb/PzqtmdwDq5g==", + "version": "4.22.4", + "resolved": "https://registry.npmjs.org/@rollup/rollup-android-arm64/-/rollup-android-arm64-4.22.4.tgz", + "integrity": "sha512-VXoK5UMrgECLYaMuGuVTOx5kcuap1Jm8g/M83RnCHBKOqvPPmROFJGQaZhGccnsFtfXQ3XYa4/jMCJvZnbJBdA==", "cpu": [ "arm64" ], @@ -2584,9 +2584,9 @@ ] }, "node_modules/@rollup/rollup-darwin-arm64": { - "version": "4.21.3", - "resolved": "https://registry.npmjs.org/@rollup/rollup-darwin-arm64/-/rollup-darwin-arm64-4.21.3.tgz", - "integrity": "sha512-P0UxIOrKNBFTQaXTxOH4RxuEBVCgEA5UTNV6Yz7z9QHnUJ7eLX9reOd/NYMO3+XZO2cco19mXTxDMXxit4R/eQ==", + "version": "4.22.4", + "resolved": "https://registry.npmjs.org/@rollup/rollup-darwin-arm64/-/rollup-darwin-arm64-4.22.4.tgz", + "integrity": "sha512-xMM9ORBqu81jyMKCDP+SZDhnX2QEVQzTcC6G18KlTQEzWK8r/oNZtKuZaCcHhnsa6fEeOBionoyl5JsAbE/36Q==", "cpu": [ "arm64" ], @@ -2597,9 +2597,9 @@ ] }, "node_modules/@rollup/rollup-darwin-x64": { - "version": "4.21.3", - "resolved": "https://registry.npmjs.org/@rollup/rollup-darwin-x64/-/rollup-darwin-x64-4.21.3.tgz", - "integrity": "sha512-L1M0vKGO5ASKntqtsFEjTq/fD91vAqnzeaF6sfNAy55aD+Hi2pBI5DKwCO+UNDQHWsDViJLqshxOahXyLSh3EA==", + "version": "4.22.4", + "resolved": "https://registry.npmjs.org/@rollup/rollup-darwin-x64/-/rollup-darwin-x64-4.22.4.tgz", + "integrity": "sha512-aJJyYKQwbHuhTUrjWjxEvGnNNBCnmpHDvrb8JFDbeSH3m2XdHcxDd3jthAzvmoI8w/kSjd2y0udT+4okADsZIw==", "cpu": [ "x64" ], @@ -2610,9 +2610,9 @@ ] }, "node_modules/@rollup/rollup-linux-arm-gnueabihf": { - "version": "4.21.3", - "resolved": "https://registry.npmjs.org/@rollup/rollup-linux-arm-gnueabihf/-/rollup-linux-arm-gnueabihf-4.21.3.tgz", - "integrity": "sha512-btVgIsCjuYFKUjopPoWiDqmoUXQDiW2A4C3Mtmp5vACm7/GnyuprqIDPNczeyR5W8rTXEbkmrJux7cJmD99D2g==", + "version": "4.22.4", + "resolved": "https://registry.npmjs.org/@rollup/rollup-linux-arm-gnueabihf/-/rollup-linux-arm-gnueabihf-4.22.4.tgz", + "integrity": "sha512-j63YtCIRAzbO+gC2L9dWXRh5BFetsv0j0va0Wi9epXDgU/XUi5dJKo4USTttVyK7fGw2nPWK0PbAvyliz50SCQ==", "cpu": [ "arm" ], @@ -2623,9 +2623,9 @@ ] }, "node_modules/@rollup/rollup-linux-arm-musleabihf": { - "version": "4.21.3", - "resolved": "https://registry.npmjs.org/@rollup/rollup-linux-arm-musleabihf/-/rollup-linux-arm-musleabihf-4.21.3.tgz", - "integrity": "sha512-zmjbSphplZlau6ZTkxd3+NMtE4UKVy7U4aVFMmHcgO5CUbw17ZP6QCgyxhzGaU/wFFdTfiojjbLG3/0p9HhAqA==", + "version": "4.22.4", + "resolved": "https://registry.npmjs.org/@rollup/rollup-linux-arm-musleabihf/-/rollup-linux-arm-musleabihf-4.22.4.tgz", + "integrity": "sha512-dJnWUgwWBX1YBRsuKKMOlXCzh2Wu1mlHzv20TpqEsfdZLb3WoJW2kIEsGwLkroYf24IrPAvOT/ZQ2OYMV6vlrg==", "cpu": [ "arm" ], @@ -2636,9 +2636,9 @@ ] }, "node_modules/@rollup/rollup-linux-arm64-gnu": { - "version": "4.21.3", - "resolved": "https://registry.npmjs.org/@rollup/rollup-linux-arm64-gnu/-/rollup-linux-arm64-gnu-4.21.3.tgz", - "integrity": "sha512-nSZfcZtAnQPRZmUkUQwZq2OjQciR6tEoJaZVFvLHsj0MF6QhNMg0fQ6mUOsiCUpTqxTx0/O6gX0V/nYc7LrgPw==", + "version": "4.22.4", + "resolved": "https://registry.npmjs.org/@rollup/rollup-linux-arm64-gnu/-/rollup-linux-arm64-gnu-4.22.4.tgz", + "integrity": "sha512-AdPRoNi3NKVLolCN/Sp4F4N1d98c4SBnHMKoLuiG6RXgoZ4sllseuGioszumnPGmPM2O7qaAX/IJdeDU8f26Aw==", "cpu": [ "arm64" ], @@ -2649,9 +2649,9 @@ ] }, "node_modules/@rollup/rollup-linux-arm64-musl": { - "version": "4.21.3", - "resolved": "https://registry.npmjs.org/@rollup/rollup-linux-arm64-musl/-/rollup-linux-arm64-musl-4.21.3.tgz", - "integrity": "sha512-MnvSPGO8KJXIMGlQDYfvYS3IosFN2rKsvxRpPO2l2cum+Z3exiExLwVU+GExL96pn8IP+GdH8Tz70EpBhO0sIQ==", + "version": "4.22.4", + "resolved": "https://registry.npmjs.org/@rollup/rollup-linux-arm64-musl/-/rollup-linux-arm64-musl-4.22.4.tgz", + "integrity": "sha512-Gl0AxBtDg8uoAn5CCqQDMqAx22Wx22pjDOjBdmG0VIWX3qUBHzYmOKh8KXHL4UpogfJ14G4wk16EQogF+v8hmA==", "cpu": [ "arm64" ], @@ -2662,9 +2662,9 @@ ] }, "node_modules/@rollup/rollup-linux-powerpc64le-gnu": { - "version": "4.21.3", - "resolved": "https://registry.npmjs.org/@rollup/rollup-linux-powerpc64le-gnu/-/rollup-linux-powerpc64le-gnu-4.21.3.tgz", - "integrity": "sha512-+W+p/9QNDr2vE2AXU0qIy0qQE75E8RTwTwgqS2G5CRQ11vzq0tbnfBd6brWhS9bCRjAjepJe2fvvkvS3dno+iw==", + "version": "4.22.4", + "resolved": "https://registry.npmjs.org/@rollup/rollup-linux-powerpc64le-gnu/-/rollup-linux-powerpc64le-gnu-4.22.4.tgz", + "integrity": "sha512-3aVCK9xfWW1oGQpTsYJJPF6bfpWfhbRnhdlyhak2ZiyFLDaayz0EP5j9V1RVLAAxlmWKTDfS9wyRyY3hvhPoOg==", "cpu": [ "ppc64" ], @@ -2675,9 +2675,9 @@ ] }, "node_modules/@rollup/rollup-linux-riscv64-gnu": { - "version": "4.21.3", - "resolved": "https://registry.npmjs.org/@rollup/rollup-linux-riscv64-gnu/-/rollup-linux-riscv64-gnu-4.21.3.tgz", - "integrity": "sha512-yXH6K6KfqGXaxHrtr+Uoy+JpNlUlI46BKVyonGiaD74ravdnF9BUNC+vV+SIuB96hUMGShhKV693rF9QDfO6nQ==", + "version": "4.22.4", + "resolved": "https://registry.npmjs.org/@rollup/rollup-linux-riscv64-gnu/-/rollup-linux-riscv64-gnu-4.22.4.tgz", + "integrity": "sha512-ePYIir6VYnhgv2C5Xe9u+ico4t8sZWXschR6fMgoPUK31yQu7hTEJb7bCqivHECwIClJfKgE7zYsh1qTP3WHUA==", "cpu": [ "riscv64" ], @@ -2688,9 +2688,9 @@ ] }, "node_modules/@rollup/rollup-linux-s390x-gnu": { - "version": "4.21.3", - "resolved": "https://registry.npmjs.org/@rollup/rollup-linux-s390x-gnu/-/rollup-linux-s390x-gnu-4.21.3.tgz", - "integrity": "sha512-R8cwY9wcnApN/KDYWTH4gV/ypvy9yZUHlbJvfaiXSB48JO3KpwSpjOGqO4jnGkLDSk1hgjYkTbTt6Q7uvPf8eg==", + "version": "4.22.4", + "resolved": "https://registry.npmjs.org/@rollup/rollup-linux-s390x-gnu/-/rollup-linux-s390x-gnu-4.22.4.tgz", + "integrity": "sha512-GqFJ9wLlbB9daxhVlrTe61vJtEY99/xB3C8e4ULVsVfflcpmR6c8UZXjtkMA6FhNONhj2eA5Tk9uAVw5orEs4Q==", "cpu": [ "s390x" ], @@ -2701,9 +2701,9 @@ ] }, "node_modules/@rollup/rollup-linux-x64-gnu": { - "version": "4.21.3", - "resolved": "https://registry.npmjs.org/@rollup/rollup-linux-x64-gnu/-/rollup-linux-x64-gnu-4.21.3.tgz", - "integrity": "sha512-kZPbX/NOPh0vhS5sI+dR8L1bU2cSO9FgxwM8r7wHzGydzfSjLRCFAT87GR5U9scj2rhzN3JPYVC7NoBbl4FZ0g==", + "version": "4.22.4", + "resolved": "https://registry.npmjs.org/@rollup/rollup-linux-x64-gnu/-/rollup-linux-x64-gnu-4.22.4.tgz", + "integrity": "sha512-87v0ol2sH9GE3cLQLNEy0K/R0pz1nvg76o8M5nhMR0+Q+BBGLnb35P0fVz4CQxHYXaAOhE8HhlkaZfsdUOlHwg==", "cpu": [ "x64" ], @@ -2714,9 +2714,9 @@ ] }, "node_modules/@rollup/rollup-linux-x64-musl": { - "version": "4.21.3", - "resolved": "https://registry.npmjs.org/@rollup/rollup-linux-x64-musl/-/rollup-linux-x64-musl-4.21.3.tgz", - "integrity": "sha512-S0Yq+xA1VEH66uiMNhijsWAafffydd2X5b77eLHfRmfLsRSpbiAWiRHV6DEpz6aOToPsgid7TI9rGd6zB1rhbg==", + "version": "4.22.4", + "resolved": "https://registry.npmjs.org/@rollup/rollup-linux-x64-musl/-/rollup-linux-x64-musl-4.22.4.tgz", + "integrity": "sha512-UV6FZMUgePDZrFjrNGIWzDo/vABebuXBhJEqrHxrGiU6HikPy0Z3LfdtciIttEUQfuDdCn8fqh7wiFJjCNwO+g==", "cpu": [ "x64" ], @@ -2727,9 +2727,9 @@ ] }, "node_modules/@rollup/rollup-win32-arm64-msvc": { - "version": "4.21.3", - "resolved": "https://registry.npmjs.org/@rollup/rollup-win32-arm64-msvc/-/rollup-win32-arm64-msvc-4.21.3.tgz", - "integrity": "sha512-9isNzeL34yquCPyerog+IMCNxKR8XYmGd0tHSV+OVx0TmE0aJOo9uw4fZfUuk2qxobP5sug6vNdZR6u7Mw7Q+Q==", + "version": "4.22.4", + "resolved": "https://registry.npmjs.org/@rollup/rollup-win32-arm64-msvc/-/rollup-win32-arm64-msvc-4.22.4.tgz", + "integrity": "sha512-BjI+NVVEGAXjGWYHz/vv0pBqfGoUH0IGZ0cICTn7kB9PyjrATSkX+8WkguNjWoj2qSr1im/+tTGRaY+4/PdcQw==", "cpu": [ "arm64" ], @@ -2740,9 +2740,9 @@ ] }, "node_modules/@rollup/rollup-win32-ia32-msvc": { - "version": "4.21.3", - "resolved": "https://registry.npmjs.org/@rollup/rollup-win32-ia32-msvc/-/rollup-win32-ia32-msvc-4.21.3.tgz", - "integrity": "sha512-nMIdKnfZfzn1Vsk+RuOvl43ONTZXoAPUUxgcU0tXooqg4YrAqzfKzVenqqk2g5efWh46/D28cKFrOzDSW28gTA==", + "version": "4.22.4", + "resolved": "https://registry.npmjs.org/@rollup/rollup-win32-ia32-msvc/-/rollup-win32-ia32-msvc-4.22.4.tgz", + "integrity": "sha512-SiWG/1TuUdPvYmzmYnmd3IEifzR61Tragkbx9D3+R8mzQqDBz8v+BvZNDlkiTtI9T15KYZhP0ehn3Dld4n9J5g==", "cpu": [ "ia32" ], @@ -2753,9 +2753,9 @@ ] }, "node_modules/@rollup/rollup-win32-x64-msvc": { - "version": "4.21.3", - "resolved": "https://registry.npmjs.org/@rollup/rollup-win32-x64-msvc/-/rollup-win32-x64-msvc-4.21.3.tgz", - "integrity": "sha512-fOvu7PCQjAj4eWDEuD8Xz5gpzFqXzGlxHZozHP4b9Jxv9APtdxL6STqztDzMLuRXEc4UpXGGhx029Xgm91QBeA==", + "version": "4.22.4", + "resolved": "https://registry.npmjs.org/@rollup/rollup-win32-x64-msvc/-/rollup-win32-x64-msvc-4.22.4.tgz", + "integrity": "sha512-j8pPKp53/lq9lMXN57S8cFz0MynJk8OWNuUnXct/9KCpKU7DgU3bYMJhwWmcqC0UU29p8Lr0/7KEVcaM6bf47Q==", "cpu": [ "x64" ], @@ -6691,9 +6691,9 @@ } }, "node_modules/rollup": { - "version": "4.21.3", - "resolved": "https://registry.npmjs.org/rollup/-/rollup-4.21.3.tgz", - "integrity": "sha512-7sqRtBNnEbcBtMeRVc6VRsJMmpI+JU1z9VTvW8D4gXIYQFz0aLcsE6rRkyghZkLfEgUZgVvOG7A5CVz/VW5GIA==", + "version": "4.22.4", + "resolved": "https://registry.npmjs.org/rollup/-/rollup-4.22.4.tgz", + "integrity": "sha512-vD8HJ5raRcWOyymsR6Z3o6+RzfEPCnVLMFJ6vRslO1jt4LO6dUo5Qnpg7y4RkZFM2DMe3WUirkI5c16onjrc6A==", "dev": true, "dependencies": { "@types/estree": "1.0.5" @@ -6706,22 +6706,22 @@ "npm": ">=8.0.0" }, "optionalDependencies": { - "@rollup/rollup-android-arm-eabi": "4.21.3", - "@rollup/rollup-android-arm64": "4.21.3", - "@rollup/rollup-darwin-arm64": "4.21.3", - "@rollup/rollup-darwin-x64": "4.21.3", - "@rollup/rollup-linux-arm-gnueabihf": "4.21.3", - "@rollup/rollup-linux-arm-musleabihf": "4.21.3", - "@rollup/rollup-linux-arm64-gnu": "4.21.3", - "@rollup/rollup-linux-arm64-musl": "4.21.3", - "@rollup/rollup-linux-powerpc64le-gnu": "4.21.3", - "@rollup/rollup-linux-riscv64-gnu": "4.21.3", - "@rollup/rollup-linux-s390x-gnu": "4.21.3", - "@rollup/rollup-linux-x64-gnu": "4.21.3", - "@rollup/rollup-linux-x64-musl": "4.21.3", - "@rollup/rollup-win32-arm64-msvc": "4.21.3", - "@rollup/rollup-win32-ia32-msvc": "4.21.3", - "@rollup/rollup-win32-x64-msvc": "4.21.3", + "@rollup/rollup-android-arm-eabi": "4.22.4", + "@rollup/rollup-android-arm64": "4.22.4", + "@rollup/rollup-darwin-arm64": "4.22.4", + "@rollup/rollup-darwin-x64": "4.22.4", + "@rollup/rollup-linux-arm-gnueabihf": "4.22.4", + "@rollup/rollup-linux-arm-musleabihf": "4.22.4", + "@rollup/rollup-linux-arm64-gnu": "4.22.4", + "@rollup/rollup-linux-arm64-musl": "4.22.4", + "@rollup/rollup-linux-powerpc64le-gnu": "4.22.4", + "@rollup/rollup-linux-riscv64-gnu": "4.22.4", + "@rollup/rollup-linux-s390x-gnu": "4.22.4", + "@rollup/rollup-linux-x64-gnu": "4.22.4", + "@rollup/rollup-linux-x64-musl": "4.22.4", + "@rollup/rollup-win32-arm64-msvc": "4.22.4", + "@rollup/rollup-win32-ia32-msvc": "4.22.4", + "@rollup/rollup-win32-x64-msvc": "4.22.4", "fsevents": "~2.3.2" } }, diff --git a/filebrowser/frontend/src/components/Sidebar.vue b/filebrowser/frontend/src/components/Sidebar.vue index 13329c6119..d88d2d2f9d 100644 --- a/filebrowser/frontend/src/components/Sidebar.vue +++ b/filebrowser/frontend/src/components/Sidebar.vue @@ -101,7 +101,7 @@ href="https://github.com/filebrowser/filebrowser" >File Browser - {{ version }} + {{ ' ' }} {{ version }} {{ $t("sidebar.help") }} diff --git a/filebrowser/frontend/src/css/listing.css b/filebrowser/frontend/src/css/listing.css index d1423e4701..fa1c01a801 100644 --- a/filebrowser/frontend/src/css/listing.css +++ b/filebrowser/frontend/src/css/listing.css @@ -195,6 +195,10 @@ html[dir="rtl"] #listing { align-items: center; } +#listing.list .item p.name:not(#listing.list .item.header .name) { + margin-right: -3em; +} + #listing.list .item .name { width: 50%; } @@ -227,10 +231,6 @@ html[dir="rtl"] #listing { width: 0; } -#listing.list .item.header .name { - margin-right: 3em; -} - #listing.list .header a { color: inherit; } @@ -246,10 +246,6 @@ html[dir="rtl"] #listing { white-space: pre-wrap; } -#listing.list .item.header .name { - margin-right: 3em; -} - #listing.list .header span { vertical-align: middle; } diff --git a/lede/target/linux/rockchip/files-5.15/arch/arm64/boot/dts/rockchip/rk3588-base-pinctrl.dtsi b/lede/target/linux/rockchip/files-5.15/arch/arm64/boot/dts/rockchip/rk3588-base-pinctrl.dtsi deleted file mode 100644 index d136841850..0000000000 --- a/lede/target/linux/rockchip/files-5.15/arch/arm64/boot/dts/rockchip/rk3588-base-pinctrl.dtsi +++ /dev/null @@ -1,3447 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2021 Rockchip Electronics Co., Ltd. - */ - -#include -#include "rockchip-pinconf.dtsi" - -/* - * This file is auto generated by pin2dts tool, please keep these code - * by adding changes at end of this file. - */ -&pinctrl { - auddsm { - /omit-if-no-ref/ - auddsm_pins: auddsm-pins { - rockchip,pins = - /* auddsm_ln */ - <3 RK_PA1 4 &pcfg_pull_none>, - /* auddsm_lp */ - <3 RK_PA2 4 &pcfg_pull_none>, - /* auddsm_rn */ - <3 RK_PA3 4 &pcfg_pull_none>, - /* auddsm_rp */ - <3 RK_PA4 4 &pcfg_pull_none>; - }; - }; - - bt1120 { - /omit-if-no-ref/ - bt1120_pins: bt1120-pins { - rockchip,pins = - /* bt1120_clkout */ - <4 RK_PB0 2 &pcfg_pull_none>, - /* bt1120_d0 */ - <4 RK_PA0 2 &pcfg_pull_none>, - /* bt1120_d1 */ - <4 RK_PA1 2 &pcfg_pull_none>, - /* bt1120_d2 */ - <4 RK_PA2 2 &pcfg_pull_none>, - /* bt1120_d3 */ - <4 RK_PA3 2 &pcfg_pull_none>, - /* bt1120_d4 */ - <4 RK_PA4 2 &pcfg_pull_none>, - /* bt1120_d5 */ - <4 RK_PA5 2 &pcfg_pull_none>, - /* bt1120_d6 */ - <4 RK_PA6 2 &pcfg_pull_none>, - /* bt1120_d7 */ - <4 RK_PA7 2 &pcfg_pull_none>, - /* bt1120_d8 */ - <4 RK_PB2 2 &pcfg_pull_none>, - /* bt1120_d9 */ - <4 RK_PB3 2 &pcfg_pull_none>, - /* bt1120_d10 */ - <4 RK_PB4 2 &pcfg_pull_none>, - /* bt1120_d11 */ - <4 RK_PB5 2 &pcfg_pull_none>, - /* bt1120_d12 */ - <4 RK_PB6 2 &pcfg_pull_none>, - /* bt1120_d13 */ - <4 RK_PB7 2 &pcfg_pull_none>, - /* bt1120_d14 */ - <4 RK_PC0 2 &pcfg_pull_none>, - /* bt1120_d15 */ - <4 RK_PC1 2 &pcfg_pull_none>; - }; - }; - - can0 { - /omit-if-no-ref/ - can0m0_pins: can0m0-pins { - rockchip,pins = - /* can0_rx_m0 */ - <0 RK_PC0 11 &pcfg_pull_none>, - /* can0_tx_m0 */ - <0 RK_PB7 11 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - can0m1_pins: can0m1-pins { - rockchip,pins = - /* can0_rx_m1 */ - <4 RK_PD5 9 &pcfg_pull_none>, - /* can0_tx_m1 */ - <4 RK_PD4 9 &pcfg_pull_none>; - }; - }; - - can1 { - /omit-if-no-ref/ - can1m0_pins: can1m0-pins { - rockchip,pins = - /* can1_rx_m0 */ - <3 RK_PB5 9 &pcfg_pull_none>, - /* can1_tx_m0 */ - <3 RK_PB6 9 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - can1m1_pins: can1m1-pins { - rockchip,pins = - /* can1_rx_m1 */ - <4 RK_PB2 12 &pcfg_pull_none>, - /* can1_tx_m1 */ - <4 RK_PB3 12 &pcfg_pull_none>; - }; - }; - - can2 { - /omit-if-no-ref/ - can2m0_pins: can2m0-pins { - rockchip,pins = - /* can2_rx_m0 */ - <3 RK_PC4 9 &pcfg_pull_none>, - /* can2_tx_m0 */ - <3 RK_PC5 9 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - can2m1_pins: can2m1-pins { - rockchip,pins = - /* can2_rx_m1 */ - <0 RK_PD4 10 &pcfg_pull_none>, - /* can2_tx_m1 */ - <0 RK_PD5 10 &pcfg_pull_none>; - }; - }; - - cif { - /omit-if-no-ref/ - cif_clk: cif-clk { - rockchip,pins = - /* cif_clkout */ - <4 RK_PB4 1 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - cif_dvp_clk: cif-dvp-clk { - rockchip,pins = - /* cif_clkin */ - <4 RK_PB0 1 &pcfg_pull_none>, - /* cif_href */ - <4 RK_PB2 1 &pcfg_pull_none>, - /* cif_vsync */ - <4 RK_PB3 1 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - cif_dvp_bus16: cif-dvp-bus16 { - rockchip,pins = - /* cif_d8 */ - <3 RK_PC4 1 &pcfg_pull_none>, - /* cif_d9 */ - <3 RK_PC5 1 &pcfg_pull_none>, - /* cif_d10 */ - <3 RK_PC6 1 &pcfg_pull_none>, - /* cif_d11 */ - <3 RK_PC7 1 &pcfg_pull_none>, - /* cif_d12 */ - <3 RK_PD0 1 &pcfg_pull_none>, - /* cif_d13 */ - <3 RK_PD1 1 &pcfg_pull_none>, - /* cif_d14 */ - <3 RK_PD2 1 &pcfg_pull_none>, - /* cif_d15 */ - <3 RK_PD3 1 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - cif_dvp_bus8: cif-dvp-bus8 { - rockchip,pins = - /* cif_d0 */ - <4 RK_PA0 1 &pcfg_pull_none>, - /* cif_d1 */ - <4 RK_PA1 1 &pcfg_pull_none>, - /* cif_d2 */ - <4 RK_PA2 1 &pcfg_pull_none>, - /* cif_d3 */ - <4 RK_PA3 1 &pcfg_pull_none>, - /* cif_d4 */ - <4 RK_PA4 1 &pcfg_pull_none>, - /* cif_d5 */ - <4 RK_PA5 1 &pcfg_pull_none>, - /* cif_d6 */ - <4 RK_PA6 1 &pcfg_pull_none>, - /* cif_d7 */ - <4 RK_PA7 1 &pcfg_pull_none>; - }; - }; - - clk32k { - /omit-if-no-ref/ - clk32k_in: clk32k-in { - rockchip,pins = - /* clk32k_in */ - <0 RK_PB2 1 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - clk32k_out0: clk32k-out0 { - rockchip,pins = - /* clk32k_out0 */ - <0 RK_PB2 2 &pcfg_pull_none>; - }; - }; - - cpu { - /omit-if-no-ref/ - cpu_pins: cpu-pins { - rockchip,pins = - /* cpu_big0_avs */ - <0 RK_PD1 2 &pcfg_pull_none>, - /* cpu_big1_avs */ - <0 RK_PD5 2 &pcfg_pull_none>; - }; - }; - - ddrphych0 { - /omit-if-no-ref/ - ddrphych0_pins: ddrphych0-pins { - rockchip,pins = - /* ddrphych0_dtb0 */ - <4 RK_PA0 7 &pcfg_pull_none>, - /* ddrphych0_dtb1 */ - <4 RK_PA1 7 &pcfg_pull_none>, - /* ddrphych0_dtb2 */ - <4 RK_PA2 7 &pcfg_pull_none>, - /* ddrphych0_dtb3 */ - <4 RK_PA3 7 &pcfg_pull_none>; - }; - }; - - ddrphych1 { - /omit-if-no-ref/ - ddrphych1_pins: ddrphych1-pins { - rockchip,pins = - /* ddrphych1_dtb0 */ - <4 RK_PA4 7 &pcfg_pull_none>, - /* ddrphych1_dtb1 */ - <4 RK_PA5 7 &pcfg_pull_none>, - /* ddrphych1_dtb2 */ - <4 RK_PA6 7 &pcfg_pull_none>, - /* ddrphych1_dtb3 */ - <4 RK_PA7 7 &pcfg_pull_none>; - }; - }; - - ddrphych2 { - /omit-if-no-ref/ - ddrphych2_pins: ddrphych2-pins { - rockchip,pins = - /* ddrphych2_dtb0 */ - <4 RK_PB0 7 &pcfg_pull_none>, - /* ddrphych2_dtb1 */ - <4 RK_PB1 7 &pcfg_pull_none>, - /* ddrphych2_dtb2 */ - <4 RK_PB2 7 &pcfg_pull_none>, - /* ddrphych2_dtb3 */ - <4 RK_PB3 7 &pcfg_pull_none>; - }; - }; - - ddrphych3 { - /omit-if-no-ref/ - ddrphych3_pins: ddrphych3-pins { - rockchip,pins = - /* ddrphych3_dtb0 */ - <4 RK_PB4 7 &pcfg_pull_none>, - /* ddrphych3_dtb1 */ - <4 RK_PB5 7 &pcfg_pull_none>, - /* ddrphych3_dtb2 */ - <4 RK_PB6 7 &pcfg_pull_none>, - /* ddrphych3_dtb3 */ - <4 RK_PB7 7 &pcfg_pull_none>; - }; - }; - - dp0 { - /omit-if-no-ref/ - dp0m0_pins: dp0m0-pins { - rockchip,pins = - /* dp0_hpdin_m0 */ - <4 RK_PB4 5 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - dp0m1_pins: dp0m1-pins { - rockchip,pins = - /* dp0_hpdin_m1 */ - <0 RK_PC4 10 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - dp0m2_pins: dp0m2-pins { - rockchip,pins = - /* dp0_hpdin_m2 */ - <1 RK_PA0 5 &pcfg_pull_none>; - }; - }; - - dp1 { - /omit-if-no-ref/ - dp1m0_pins: dp1m0-pins { - rockchip,pins = - /* dp1_hpdin_m0 */ - <3 RK_PD5 5 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - dp1m1_pins: dp1m1-pins { - rockchip,pins = - /* dp1_hpdin_m1 */ - <0 RK_PC5 10 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - dp1m2_pins: dp1m2-pins { - rockchip,pins = - /* dp1_hpdin_m2 */ - <1 RK_PA1 5 &pcfg_pull_none>; - }; - }; - - emmc { - /omit-if-no-ref/ - emmc_rstnout: emmc-rstnout { - rockchip,pins = - /* emmc_rstn */ - <2 RK_PA3 1 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - emmc_bus8: emmc-bus8 { - rockchip,pins = - /* emmc_d0 */ - <2 RK_PD0 1 &pcfg_pull_up_drv_level_2>, - /* emmc_d1 */ - <2 RK_PD1 1 &pcfg_pull_up_drv_level_2>, - /* emmc_d2 */ - <2 RK_PD2 1 &pcfg_pull_up_drv_level_2>, - /* emmc_d3 */ - <2 RK_PD3 1 &pcfg_pull_up_drv_level_2>, - /* emmc_d4 */ - <2 RK_PD4 1 &pcfg_pull_up_drv_level_2>, - /* emmc_d5 */ - <2 RK_PD5 1 &pcfg_pull_up_drv_level_2>, - /* emmc_d6 */ - <2 RK_PD6 1 &pcfg_pull_up_drv_level_2>, - /* emmc_d7 */ - <2 RK_PD7 1 &pcfg_pull_up_drv_level_2>; - }; - - /omit-if-no-ref/ - emmc_clk: emmc-clk { - rockchip,pins = - /* emmc_clkout */ - <2 RK_PA1 1 &pcfg_pull_up_drv_level_2>; - }; - - /omit-if-no-ref/ - emmc_cmd: emmc-cmd { - rockchip,pins = - /* emmc_cmd */ - <2 RK_PA0 1 &pcfg_pull_up_drv_level_2>; - }; - - /omit-if-no-ref/ - emmc_data_strobe: emmc-data-strobe { - rockchip,pins = - /* emmc_data_strobe */ - <2 RK_PA2 1 &pcfg_pull_down>; - }; - }; - - eth1 { - /omit-if-no-ref/ - eth1_pins: eth1-pins { - rockchip,pins = - /* eth1_refclko_25m */ - <3 RK_PA6 1 &pcfg_pull_none>; - }; - }; - - fspi { - /omit-if-no-ref/ - fspim0_pins: fspim0-pins { - rockchip,pins = - /* fspi_clk_m0 */ - <2 RK_PA0 2 &pcfg_pull_up_drv_level_2>, - /* fspi_cs0n_m0 */ - <2 RK_PD6 2 &pcfg_pull_up_drv_level_2>, - /* fspi_d0_m0 */ - <2 RK_PD0 2 &pcfg_pull_up_drv_level_2>, - /* fspi_d1_m0 */ - <2 RK_PD1 2 &pcfg_pull_up_drv_level_2>, - /* fspi_d2_m0 */ - <2 RK_PD2 2 &pcfg_pull_up_drv_level_2>, - /* fspi_d3_m0 */ - <2 RK_PD3 2 &pcfg_pull_up_drv_level_2>; - }; - - /omit-if-no-ref/ - fspim0_cs1: fspim0-cs1 { - rockchip,pins = - /* fspi_cs1n_m0 */ - <2 RK_PD7 2 &pcfg_pull_up_drv_level_2>; - }; - - /omit-if-no-ref/ - fspim2_pins: fspim2-pins { - rockchip,pins = - /* fspi_clk_m2 */ - <3 RK_PA5 5 &pcfg_pull_up_drv_level_2>, - /* fspi_cs0n_m2 */ - <3 RK_PC4 2 &pcfg_pull_up_drv_level_2>, - /* fspi_d0_m2 */ - <3 RK_PA0 5 &pcfg_pull_up_drv_level_2>, - /* fspi_d1_m2 */ - <3 RK_PA1 5 &pcfg_pull_up_drv_level_2>, - /* fspi_d2_m2 */ - <3 RK_PA2 5 &pcfg_pull_up_drv_level_2>, - /* fspi_d3_m2 */ - <3 RK_PA3 5 &pcfg_pull_up_drv_level_2>; - }; - - /omit-if-no-ref/ - fspim2_cs1: fspim2-cs1 { - rockchip,pins = - /* fspi_cs1n_m2 */ - <3 RK_PC5 2 &pcfg_pull_up_drv_level_2>; - }; - }; - - gmac1 { - /omit-if-no-ref/ - gmac1_miim: gmac1-miim { - rockchip,pins = - /* gmac1_mdc */ - <3 RK_PC2 1 &pcfg_pull_none>, - /* gmac1_mdio */ - <3 RK_PC3 1 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - gmac1_clkinout: gmac1-clkinout { - rockchip,pins = - /* gmac1_mclkinout */ - <3 RK_PB6 1 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - gmac1_rx_bus2: gmac1-rx-bus2 { - rockchip,pins = - /* gmac1_rxd0 */ - <3 RK_PA7 1 &pcfg_pull_none>, - /* gmac1_rxd1 */ - <3 RK_PB0 1 &pcfg_pull_none>, - /* gmac1_rxdv_crs */ - <3 RK_PB1 1 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - gmac1_tx_bus2: gmac1-tx-bus2 { - rockchip,pins = - /* gmac1_txd0 */ - <3 RK_PB3 1 &pcfg_pull_none>, - /* gmac1_txd1 */ - <3 RK_PB4 1 &pcfg_pull_none>, - /* gmac1_txen */ - <3 RK_PB5 1 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - gmac1_rgmii_clk: gmac1-rgmii-clk { - rockchip,pins = - /* gmac1_rxclk */ - <3 RK_PA5 1 &pcfg_pull_none>, - /* gmac1_txclk */ - <3 RK_PA4 1 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - gmac1_rgmii_bus: gmac1-rgmii-bus { - rockchip,pins = - /* gmac1_rxd2 */ - <3 RK_PA2 1 &pcfg_pull_none>, - /* gmac1_rxd3 */ - <3 RK_PA3 1 &pcfg_pull_none>, - /* gmac1_txd2 */ - <3 RK_PA0 1 &pcfg_pull_none>, - /* gmac1_txd3 */ - <3 RK_PA1 1 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - gmac1_ppsclk: gmac1-ppsclk { - rockchip,pins = - /* gmac1_ppsclk */ - <3 RK_PC1 1 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - gmac1_ppstrig: gmac1-ppstrig { - rockchip,pins = - /* gmac1_ppstrig */ - <3 RK_PC0 1 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - gmac1_ptp_ref_clk: gmac1-ptp-ref-clk { - rockchip,pins = - /* gmac1_ptp_ref_clk */ - <3 RK_PB7 1 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - gmac1_txer: gmac1-txer { - rockchip,pins = - /* gmac1_txer */ - <3 RK_PB2 1 &pcfg_pull_none>; - }; - }; - - gpu { - /omit-if-no-ref/ - gpu_pins: gpu-pins { - rockchip,pins = - /* gpu_avs */ - <0 RK_PC5 2 &pcfg_pull_none>; - }; - }; - - hdmi { - /omit-if-no-ref/ - hdmim0_rx_cec: hdmim0-rx-cec { - rockchip,pins = - /* hdmim0_rx_cec */ - <4 RK_PB5 5 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - hdmim0_rx_hpdin: hdmim0-rx-hpdin { - rockchip,pins = - /* hdmim0_rx_hpdin */ - <4 RK_PB6 5 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - hdmim0_rx_scl: hdmim0-rx-scl { - rockchip,pins = - /* hdmim0_rx_scl */ - <0 RK_PD2 11 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - hdmim0_rx_sda: hdmim0-rx-sda { - rockchip,pins = - /* hdmim0_rx_sda */ - <0 RK_PD1 11 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - hdmim0_tx0_cec: hdmim0-tx0-cec { - rockchip,pins = - /* hdmim0_tx0_cec */ - <4 RK_PC1 5 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - hdmim0_tx0_hpd: hdmim0-tx0-hpd { - rockchip,pins = - /* hdmim0_tx0_hpd */ - <1 RK_PA5 5 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - hdmim0_tx0_scl: hdmim0-tx0-scl { - rockchip,pins = - /* hdmim0_tx0_scl */ - <4 RK_PB7 5 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - hdmim0_tx0_sda: hdmim0-tx0-sda { - rockchip,pins = - /* hdmim0_tx0_sda */ - <4 RK_PC0 5 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - hdmim0_tx1_hpd: hdmim0-tx1-hpd { - rockchip,pins = - /* hdmim0_tx1_hpd */ - <1 RK_PA6 5 &pcfg_pull_none>; - }; - /omit-if-no-ref/ - hdmim1_rx_cec: hdmim1-rx-cec { - rockchip,pins = - /* hdmim1_rx_cec */ - <3 RK_PD1 5 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - hdmim1_rx_hpdin: hdmim1-rx-hpdin { - rockchip,pins = - /* hdmim1_rx_hpdin */ - <3 RK_PD4 5 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - hdmim1_rx_scl: hdmim1-rx-scl { - rockchip,pins = - /* hdmim1_rx_scl */ - <3 RK_PD2 5 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - hdmim1_rx_sda: hdmim1-rx-sda { - rockchip,pins = - /* hdmim1_rx_sda */ - <3 RK_PD3 5 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - hdmim1_tx0_cec: hdmim1-tx0-cec { - rockchip,pins = - /* hdmim1_tx0_cec */ - <0 RK_PD1 13 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - hdmim1_tx0_hpd: hdmim1-tx0-hpd { - rockchip,pins = - /* hdmim1_tx0_hpd */ - <3 RK_PD4 3 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - hdmim1_tx0_scl: hdmim1-tx0-scl { - rockchip,pins = - /* hdmim1_tx0_scl */ - <0 RK_PD5 11 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - hdmim1_tx0_sda: hdmim1-tx0-sda { - rockchip,pins = - /* hdmim1_tx0_sda */ - <0 RK_PD4 11 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - hdmim1_tx1_cec: hdmim1-tx1-cec { - rockchip,pins = - /* hdmim1_tx1_cec */ - <0 RK_PD2 13 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - hdmim1_tx1_hpd: hdmim1-tx1-hpd { - rockchip,pins = - /* hdmim1_tx1_hpd */ - <3 RK_PB7 5 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - hdmim1_tx1_scl: hdmim1-tx1-scl { - rockchip,pins = - /* hdmim1_tx1_scl */ - <3 RK_PC6 5 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - hdmim1_tx1_sda: hdmim1-tx1-sda { - rockchip,pins = - /* hdmim1_tx1_sda */ - <3 RK_PC5 5 &pcfg_pull_none>; - }; - /omit-if-no-ref/ - hdmim2_rx_cec: hdmim2-rx-cec { - rockchip,pins = - /* hdmim2_rx_cec */ - <1 RK_PB7 5 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - hdmim2_rx_hpdin: hdmim2-rx-hpdin { - rockchip,pins = - /* hdmim2_rx_hpdin */ - <1 RK_PB6 5 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - hdmim2_rx_scl: hdmim2-rx-scl { - rockchip,pins = - /* hdmim2_rx_scl */ - <1 RK_PD6 5 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - hdmim2_rx_sda: hdmim2-rx-sda { - rockchip,pins = - /* hdmim2_rx_sda */ - <1 RK_PD7 5 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - hdmim2_tx0_scl: hdmim2-tx0-scl { - rockchip,pins = - /* hdmim2_tx0_scl */ - <3 RK_PC7 5 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - hdmim2_tx0_sda: hdmim2-tx0-sda { - rockchip,pins = - /* hdmim2_tx0_sda */ - <3 RK_PD0 5 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - hdmim2_tx1_cec: hdmim2-tx1-cec { - rockchip,pins = - /* hdmim2_tx1_cec */ - <3 RK_PC4 5 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - hdmim2_tx1_scl: hdmim2-tx1-scl { - rockchip,pins = - /* hdmim2_tx1_scl */ - <1 RK_PA4 5 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - hdmim2_tx1_sda: hdmim2-tx1-sda { - rockchip,pins = - /* hdmim2_tx1_sda */ - <1 RK_PA3 5 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - hdmi_debug0: hdmi-debug0 { - rockchip,pins = - /* hdmi_debug0 */ - <1 RK_PA7 7 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - hdmi_debug1: hdmi-debug1 { - rockchip,pins = - /* hdmi_debug1 */ - <1 RK_PB0 7 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - hdmi_debug2: hdmi-debug2 { - rockchip,pins = - /* hdmi_debug2 */ - <1 RK_PB1 7 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - hdmi_debug3: hdmi-debug3 { - rockchip,pins = - /* hdmi_debug3 */ - <1 RK_PB2 7 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - hdmi_debug4: hdmi-debug4 { - rockchip,pins = - /* hdmi_debug4 */ - <1 RK_PB3 7 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - hdmi_debug5: hdmi-debug5 { - rockchip,pins = - /* hdmi_debug5 */ - <1 RK_PB4 7 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - hdmi_debug6: hdmi-debug6 { - rockchip,pins = - /* hdmi_debug6 */ - <1 RK_PA0 7 &pcfg_pull_none>; - }; - }; - - i2c0 { - /omit-if-no-ref/ - i2c0m0_xfer: i2c0m0-xfer { - rockchip,pins = - /* i2c0_scl_m0 */ - <0 RK_PB3 2 &pcfg_pull_none_smt>, - /* i2c0_sda_m0 */ - <0 RK_PA6 2 &pcfg_pull_none_smt>; - }; - - /omit-if-no-ref/ - i2c0m2_xfer: i2c0m2-xfer { - rockchip,pins = - /* i2c0_scl_m2 */ - <0 RK_PD1 3 &pcfg_pull_none_smt>, - /* i2c0_sda_m2 */ - <0 RK_PD2 3 &pcfg_pull_none_smt>; - }; - }; - - i2c1 { - /omit-if-no-ref/ - i2c1m0_xfer: i2c1m0-xfer { - rockchip,pins = - /* i2c1_scl_m0 */ - <0 RK_PB5 9 &pcfg_pull_none_smt>, - /* i2c1_sda_m0 */ - <0 RK_PB6 9 &pcfg_pull_none_smt>; - }; - - /omit-if-no-ref/ - i2c1m1_xfer: i2c1m1-xfer { - rockchip,pins = - /* i2c1_scl_m1 */ - <0 RK_PB0 2 &pcfg_pull_none_smt>, - /* i2c1_sda_m1 */ - <0 RK_PB1 2 &pcfg_pull_none_smt>; - }; - - /omit-if-no-ref/ - i2c1m2_xfer: i2c1m2-xfer { - rockchip,pins = - /* i2c1_scl_m2 */ - <0 RK_PD4 9 &pcfg_pull_none_smt>, - /* i2c1_sda_m2 */ - <0 RK_PD5 9 &pcfg_pull_none_smt>; - }; - - /omit-if-no-ref/ - i2c1m3_xfer: i2c1m3-xfer { - rockchip,pins = - /* i2c1_scl_m3 */ - <2 RK_PD4 9 &pcfg_pull_none_smt>, - /* i2c1_sda_m3 */ - <2 RK_PD5 9 &pcfg_pull_none_smt>; - }; - - /omit-if-no-ref/ - i2c1m4_xfer: i2c1m4-xfer { - rockchip,pins = - /* i2c1_scl_m4 */ - <1 RK_PD2 9 &pcfg_pull_none_smt>, - /* i2c1_sda_m4 */ - <1 RK_PD3 9 &pcfg_pull_none_smt>; - }; - }; - - i2c2 { - /omit-if-no-ref/ - i2c2m0_xfer: i2c2m0-xfer { - rockchip,pins = - /* i2c2_scl_m0 */ - <0 RK_PB7 9 &pcfg_pull_none_smt>, - /* i2c2_sda_m0 */ - <0 RK_PC0 9 &pcfg_pull_none_smt>; - }; - - /omit-if-no-ref/ - i2c2m2_xfer: i2c2m2-xfer { - rockchip,pins = - /* i2c2_scl_m2 */ - <2 RK_PA3 9 &pcfg_pull_none_smt>, - /* i2c2_sda_m2 */ - <2 RK_PA2 9 &pcfg_pull_none_smt>; - }; - - /omit-if-no-ref/ - i2c2m3_xfer: i2c2m3-xfer { - rockchip,pins = - /* i2c2_scl_m3 */ - <1 RK_PC5 9 &pcfg_pull_none_smt>, - /* i2c2_sda_m3 */ - <1 RK_PC4 9 &pcfg_pull_none_smt>; - }; - - /omit-if-no-ref/ - i2c2m4_xfer: i2c2m4-xfer { - rockchip,pins = - /* i2c2_scl_m4 */ - <1 RK_PA1 9 &pcfg_pull_none_smt>, - /* i2c2_sda_m4 */ - <1 RK_PA0 9 &pcfg_pull_none_smt>; - }; - }; - - i2c3 { - /omit-if-no-ref/ - i2c3m0_xfer: i2c3m0-xfer { - rockchip,pins = - /* i2c3_scl_m0 */ - <1 RK_PC1 9 &pcfg_pull_none_smt>, - /* i2c3_sda_m0 */ - <1 RK_PC0 9 &pcfg_pull_none_smt>; - }; - - /omit-if-no-ref/ - i2c3m1_xfer: i2c3m1-xfer { - rockchip,pins = - /* i2c3_scl_m1 */ - <3 RK_PB7 9 &pcfg_pull_none_smt>, - /* i2c3_sda_m1 */ - <3 RK_PC0 9 &pcfg_pull_none_smt>; - }; - - /omit-if-no-ref/ - i2c3m2_xfer: i2c3m2-xfer { - rockchip,pins = - /* i2c3_scl_m2 */ - <4 RK_PA4 9 &pcfg_pull_none_smt>, - /* i2c3_sda_m2 */ - <4 RK_PA5 9 &pcfg_pull_none_smt>; - }; - - /omit-if-no-ref/ - i2c3m4_xfer: i2c3m4-xfer { - rockchip,pins = - /* i2c3_scl_m4 */ - <4 RK_PD0 9 &pcfg_pull_none_smt>, - /* i2c3_sda_m4 */ - <4 RK_PD1 9 &pcfg_pull_none_smt>; - }; - }; - - i2c4 { - /omit-if-no-ref/ - i2c4m0_xfer: i2c4m0-xfer { - rockchip,pins = - /* i2c4_scl_m0 */ - <3 RK_PA6 9 &pcfg_pull_none_smt>, - /* i2c4_sda_m0 */ - <3 RK_PA5 9 &pcfg_pull_none_smt>; - }; - - /omit-if-no-ref/ - i2c4m2_xfer: i2c4m2-xfer { - rockchip,pins = - /* i2c4_scl_m2 */ - <0 RK_PC5 9 &pcfg_pull_none_smt>, - /* i2c4_sda_m2 */ - <0 RK_PC4 9 &pcfg_pull_none_smt>; - }; - - /omit-if-no-ref/ - i2c4m3_xfer: i2c4m3-xfer { - rockchip,pins = - /* i2c4_scl_m3 */ - <1 RK_PA3 9 &pcfg_pull_none_smt>, - /* i2c4_sda_m3 */ - <1 RK_PA2 9 &pcfg_pull_none_smt>; - }; - - /omit-if-no-ref/ - i2c4m4_xfer: i2c4m4-xfer { - rockchip,pins = - /* i2c4_scl_m4 */ - <1 RK_PC7 9 &pcfg_pull_none_smt>, - /* i2c4_sda_m4 */ - <1 RK_PC6 9 &pcfg_pull_none_smt>; - }; - }; - - i2c5 { - /omit-if-no-ref/ - i2c5m0_xfer: i2c5m0-xfer { - rockchip,pins = - /* i2c5_scl_m0 */ - <3 RK_PC7 9 &pcfg_pull_none_smt>, - /* i2c5_sda_m0 */ - <3 RK_PD0 9 &pcfg_pull_none_smt>; - }; - - /omit-if-no-ref/ - i2c5m1_xfer: i2c5m1-xfer { - rockchip,pins = - /* i2c5_scl_m1 */ - <4 RK_PB6 9 &pcfg_pull_none_smt>, - /* i2c5_sda_m1 */ - <4 RK_PB7 9 &pcfg_pull_none_smt>; - }; - - /omit-if-no-ref/ - i2c5m2_xfer: i2c5m2-xfer { - rockchip,pins = - /* i2c5_scl_m2 */ - <4 RK_PA6 9 &pcfg_pull_none_smt>, - /* i2c5_sda_m2 */ - <4 RK_PA7 9 &pcfg_pull_none_smt>; - }; - - /omit-if-no-ref/ - i2c5m3_xfer: i2c5m3-xfer { - rockchip,pins = - /* i2c5_scl_m3 */ - <1 RK_PB6 9 &pcfg_pull_none_smt>, - /* i2c5_sda_m3 */ - <1 RK_PB7 9 &pcfg_pull_none_smt>; - }; - }; - - i2c6 { - /omit-if-no-ref/ - i2c6m0_xfer: i2c6m0-xfer { - rockchip,pins = - /* i2c6_scl_m0 */ - <0 RK_PD0 9 &pcfg_pull_none_smt>, - /* i2c6_sda_m0 */ - <0 RK_PC7 9 &pcfg_pull_none_smt>; - }; - - /omit-if-no-ref/ - i2c6m1_xfer: i2c6m1-xfer { - rockchip,pins = - /* i2c6_scl_m1 */ - <1 RK_PC3 9 &pcfg_pull_none_smt>, - /* i2c6_sda_m1 */ - <1 RK_PC2 9 &pcfg_pull_none_smt>; - }; - - /omit-if-no-ref/ - i2c6m3_xfer: i2c6m3-xfer { - rockchip,pins = - /* i2c6_scl_m3 */ - <4 RK_PB1 9 &pcfg_pull_none_smt>, - /* i2c6_sda_m3 */ - <4 RK_PB0 9 &pcfg_pull_none_smt>; - }; - - /omit-if-no-ref/ - i2c6m4_xfer: i2c6m4-xfer { - rockchip,pins = - /* i2c6_scl_m4 */ - <3 RK_PA1 9 &pcfg_pull_none_smt>, - /* i2c6_sda_m4 */ - <3 RK_PA0 9 &pcfg_pull_none_smt>; - }; - }; - - i2c7 { - /omit-if-no-ref/ - i2c7m0_xfer: i2c7m0-xfer { - rockchip,pins = - /* i2c7_scl_m0 */ - <1 RK_PD0 9 &pcfg_pull_none_smt>, - /* i2c7_sda_m0 */ - <1 RK_PD1 9 &pcfg_pull_none_smt>; - }; - - /omit-if-no-ref/ - i2c7m2_xfer: i2c7m2-xfer { - rockchip,pins = - /* i2c7_scl_m2 */ - <3 RK_PD2 9 &pcfg_pull_none_smt>, - /* i2c7_sda_m2 */ - <3 RK_PD3 9 &pcfg_pull_none_smt>; - }; - - /omit-if-no-ref/ - i2c7m3_xfer: i2c7m3-xfer { - rockchip,pins = - /* i2c7_scl_m3 */ - <4 RK_PB2 9 &pcfg_pull_none_smt>, - /* i2c7_sda_m3 */ - <4 RK_PB3 9 &pcfg_pull_none_smt>; - }; - }; - - i2c8 { - /omit-if-no-ref/ - i2c8m0_xfer: i2c8m0-xfer { - rockchip,pins = - /* i2c8_scl_m0 */ - <4 RK_PD2 9 &pcfg_pull_none_smt>, - /* i2c8_sda_m0 */ - <4 RK_PD3 9 &pcfg_pull_none_smt>; - }; - - /omit-if-no-ref/ - i2c8m2_xfer: i2c8m2-xfer { - rockchip,pins = - /* i2c8_scl_m2 */ - <1 RK_PD6 9 &pcfg_pull_none_smt>, - /* i2c8_sda_m2 */ - <1 RK_PD7 9 &pcfg_pull_none_smt>; - }; - - /omit-if-no-ref/ - i2c8m3_xfer: i2c8m3-xfer { - rockchip,pins = - /* i2c8_scl_m3 */ - <4 RK_PC0 9 &pcfg_pull_none_smt>, - /* i2c8_sda_m3 */ - <4 RK_PC1 9 &pcfg_pull_none_smt>; - }; - - /omit-if-no-ref/ - i2c8m4_xfer: i2c8m4-xfer { - rockchip,pins = - /* i2c8_scl_m4 */ - <3 RK_PC2 9 &pcfg_pull_none_smt>, - /* i2c8_sda_m4 */ - <3 RK_PC3 9 &pcfg_pull_none_smt>; - }; - }; - - i2s0 { - /omit-if-no-ref/ - i2s0_lrck: i2s0-lrck { - rockchip,pins = - /* i2s0_lrck */ - <1 RK_PC5 1 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - i2s0_mclk: i2s0-mclk { - rockchip,pins = - /* i2s0_mclk */ - <1 RK_PC2 1 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - i2s0_sclk: i2s0-sclk { - rockchip,pins = - /* i2s0_sclk */ - <1 RK_PC3 1 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - i2s0_sdi0: i2s0-sdi0 { - rockchip,pins = - /* i2s0_sdi0 */ - <1 RK_PD4 2 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - i2s0_sdi1: i2s0-sdi1 { - rockchip,pins = - /* i2s0_sdi1 */ - <1 RK_PD3 2 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - i2s0_sdi2: i2s0-sdi2 { - rockchip,pins = - /* i2s0_sdi2 */ - <1 RK_PD2 2 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - i2s0_sdi3: i2s0-sdi3 { - rockchip,pins = - /* i2s0_sdi3 */ - <1 RK_PD1 2 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - i2s0_sdo0: i2s0-sdo0 { - rockchip,pins = - /* i2s0_sdo0 */ - <1 RK_PC7 1 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - i2s0_sdo1: i2s0-sdo1 { - rockchip,pins = - /* i2s0_sdo1 */ - <1 RK_PD0 1 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - i2s0_sdo2: i2s0-sdo2 { - rockchip,pins = - /* i2s0_sdo2 */ - <1 RK_PD1 1 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - i2s0_sdo3: i2s0-sdo3 { - rockchip,pins = - /* i2s0_sdo3 */ - <1 RK_PD2 1 &pcfg_pull_none>; - }; - }; - - i2s1 { - /omit-if-no-ref/ - i2s1m0_lrck: i2s1m0-lrck { - rockchip,pins = - /* i2s1m0_lrck */ - <4 RK_PA2 3 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - i2s1m0_mclk: i2s1m0-mclk { - rockchip,pins = - /* i2s1m0_mclk */ - <4 RK_PA0 3 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - i2s1m0_sclk: i2s1m0-sclk { - rockchip,pins = - /* i2s1m0_sclk */ - <4 RK_PA1 3 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - i2s1m0_sdi0: i2s1m0-sdi0 { - rockchip,pins = - /* i2s1m0_sdi0 */ - <4 RK_PA5 3 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - i2s1m0_sdi1: i2s1m0-sdi1 { - rockchip,pins = - /* i2s1m0_sdi1 */ - <4 RK_PA6 3 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - i2s1m0_sdi2: i2s1m0-sdi2 { - rockchip,pins = - /* i2s1m0_sdi2 */ - <4 RK_PA7 3 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - i2s1m0_sdi3: i2s1m0-sdi3 { - rockchip,pins = - /* i2s1m0_sdi3 */ - <4 RK_PB0 3 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - i2s1m0_sdo0: i2s1m0-sdo0 { - rockchip,pins = - /* i2s1m0_sdo0 */ - <4 RK_PB1 3 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - i2s1m0_sdo1: i2s1m0-sdo1 { - rockchip,pins = - /* i2s1m0_sdo1 */ - <4 RK_PB2 3 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - i2s1m0_sdo2: i2s1m0-sdo2 { - rockchip,pins = - /* i2s1m0_sdo2 */ - <4 RK_PB3 3 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - i2s1m0_sdo3: i2s1m0-sdo3 { - rockchip,pins = - /* i2s1m0_sdo3 */ - <4 RK_PB4 3 &pcfg_pull_none>; - }; - /omit-if-no-ref/ - i2s1m1_lrck: i2s1m1-lrck { - rockchip,pins = - /* i2s1m1_lrck */ - <0 RK_PB7 1 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - i2s1m1_mclk: i2s1m1-mclk { - rockchip,pins = - /* i2s1m1_mclk */ - <0 RK_PB5 1 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - i2s1m1_sclk: i2s1m1-sclk { - rockchip,pins = - /* i2s1m1_sclk */ - <0 RK_PB6 1 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - i2s1m1_sdi0: i2s1m1-sdi0 { - rockchip,pins = - /* i2s1m1_sdi0 */ - <0 RK_PC5 1 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - i2s1m1_sdi1: i2s1m1-sdi1 { - rockchip,pins = - /* i2s1m1_sdi1 */ - <0 RK_PC6 1 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - i2s1m1_sdi2: i2s1m1-sdi2 { - rockchip,pins = - /* i2s1m1_sdi2 */ - <0 RK_PC7 1 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - i2s1m1_sdi3: i2s1m1-sdi3 { - rockchip,pins = - /* i2s1m1_sdi3 */ - <0 RK_PD0 1 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - i2s1m1_sdo0: i2s1m1-sdo0 { - rockchip,pins = - /* i2s1m1_sdo0 */ - <0 RK_PD1 1 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - i2s1m1_sdo1: i2s1m1-sdo1 { - rockchip,pins = - /* i2s1m1_sdo1 */ - <0 RK_PD2 1 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - i2s1m1_sdo2: i2s1m1-sdo2 { - rockchip,pins = - /* i2s1m1_sdo2 */ - <0 RK_PD4 1 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - i2s1m1_sdo3: i2s1m1-sdo3 { - rockchip,pins = - /* i2s1m1_sdo3 */ - <0 RK_PD5 1 &pcfg_pull_none>; - }; - }; - - i2s2 { - /omit-if-no-ref/ - i2s2m0_lrck: i2s2m0-lrck { - rockchip,pins = - /* i2s2m0_lrck */ - <2 RK_PC0 2 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - i2s2m0_mclk: i2s2m0-mclk { - rockchip,pins = - /* i2s2m0_mclk */ - <2 RK_PB6 2 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - i2s2m0_sclk: i2s2m0-sclk { - rockchip,pins = - /* i2s2m0_sclk */ - <2 RK_PB7 2 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - i2s2m0_sdi: i2s2m0-sdi { - rockchip,pins = - /* i2s2m0_sdi */ - <2 RK_PC3 2 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - i2s2m0_sdo: i2s2m0-sdo { - rockchip,pins = - /* i2s2m0_sdo */ - <4 RK_PC3 2 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - i2s2m1_lrck: i2s2m1-lrck { - rockchip,pins = - /* i2s2m1_lrck */ - <3 RK_PB6 3 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - i2s2m1_mclk: i2s2m1-mclk { - rockchip,pins = - /* i2s2m1_mclk */ - <3 RK_PB4 3 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - i2s2m1_sclk: i2s2m1-sclk { - rockchip,pins = - /* i2s2m1_sclk */ - <3 RK_PB5 3 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - i2s2m1_sdi: i2s2m1-sdi { - rockchip,pins = - /* i2s2m1_sdi */ - <3 RK_PB2 3 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - i2s2m1_sdo: i2s2m1-sdo { - rockchip,pins = - /* i2s2m1_sdo */ - <3 RK_PB3 3 &pcfg_pull_none>; - }; - }; - - i2s3 { - /omit-if-no-ref/ - i2s3_lrck: i2s3-lrck { - rockchip,pins = - /* i2s3_lrck */ - <3 RK_PA2 3 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - i2s3_mclk: i2s3-mclk { - rockchip,pins = - /* i2s3_mclk */ - <3 RK_PA0 3 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - i2s3_sclk: i2s3-sclk { - rockchip,pins = - /* i2s3_sclk */ - <3 RK_PA1 3 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - i2s3_sdi: i2s3-sdi { - rockchip,pins = - /* i2s3_sdi */ - <3 RK_PA4 3 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - i2s3_sdo: i2s3-sdo { - rockchip,pins = - /* i2s3_sdo */ - <3 RK_PA3 3 &pcfg_pull_none>; - }; - }; - - jtag { - /omit-if-no-ref/ - jtagm0_pins: jtagm0-pins { - rockchip,pins = - /* jtag_tck_m0 */ - <4 RK_PD2 5 &pcfg_pull_none>, - /* jtag_tms_m0 */ - <4 RK_PD3 5 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - jtagm1_pins: jtagm1-pins { - rockchip,pins = - /* jtag_tck_m1 */ - <4 RK_PD0 5 &pcfg_pull_none>, - /* jtag_tms_m1 */ - <4 RK_PD1 5 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - jtagm2_pins: jtagm2-pins { - rockchip,pins = - /* jtag_tck_m2 */ - <0 RK_PB5 2 &pcfg_pull_none>, - /* jtag_tms_m2 */ - <0 RK_PB6 2 &pcfg_pull_none>; - }; - }; - - litcpu { - /omit-if-no-ref/ - litcpu_pins: litcpu-pins { - rockchip,pins = - /* litcpu_avs */ - <0 RK_PD3 1 &pcfg_pull_none>; - }; - }; - - mcu { - /omit-if-no-ref/ - mcum0_pins: mcum0-pins { - rockchip,pins = - /* mcu_jtag_tck_m0 */ - <4 RK_PD4 5 &pcfg_pull_none>, - /* mcu_jtag_tms_m0 */ - <4 RK_PD5 5 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - mcum1_pins: mcum1-pins { - rockchip,pins = - /* mcu_jtag_tck_m1 */ - <3 RK_PD4 6 &pcfg_pull_none>, - /* mcu_jtag_tms_m1 */ - <3 RK_PD5 6 &pcfg_pull_none>; - }; - }; - - mipi { - /omit-if-no-ref/ - mipim0_camera0_clk: mipim0-camera0-clk { - rockchip,pins = - /* mipim0_camera0_clk */ - <4 RK_PB1 1 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - mipim0_camera1_clk: mipim0-camera1-clk { - rockchip,pins = - /* mipim0_camera1_clk */ - <1 RK_PB6 2 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - mipim0_camera2_clk: mipim0-camera2-clk { - rockchip,pins = - /* mipim0_camera2_clk */ - <1 RK_PB7 2 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - mipim0_camera3_clk: mipim0-camera3-clk { - rockchip,pins = - /* mipim0_camera3_clk */ - <1 RK_PD6 2 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - mipim0_camera4_clk: mipim0-camera4-clk { - rockchip,pins = - /* mipim0_camera4_clk */ - <1 RK_PD7 2 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - mipim1_camera0_clk: mipim1-camera0-clk { - rockchip,pins = - /* mipim1_camera0_clk */ - <3 RK_PA5 4 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - mipim1_camera1_clk: mipim1-camera1-clk { - rockchip,pins = - /* mipim1_camera1_clk */ - <3 RK_PA6 4 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - mipim1_camera2_clk: mipim1-camera2-clk { - rockchip,pins = - /* mipim1_camera2_clk */ - <3 RK_PA7 4 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - mipim1_camera3_clk: mipim1-camera3-clk { - rockchip,pins = - /* mipim1_camera3_clk */ - <3 RK_PB0 4 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - mipim1_camera4_clk: mipim1-camera4-clk { - rockchip,pins = - /* mipim1_camera4_clk */ - <3 RK_PB1 4 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - mipi_te0: mipi-te0 { - rockchip,pins = - /* mipi_te0 */ - <3 RK_PC2 2 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - mipi_te1: mipi-te1 { - rockchip,pins = - /* mipi_te1 */ - <3 RK_PC3 2 &pcfg_pull_none>; - }; - }; - - npu { - /omit-if-no-ref/ - npu_pins: npu-pins { - rockchip,pins = - /* npu_avs */ - <0 RK_PC6 2 &pcfg_pull_none>; - }; - }; - - pcie20x1 { - /omit-if-no-ref/ - pcie20x1m0_pins: pcie20x1m0-pins { - rockchip,pins = - /* pcie20x1_2_clkreqn_m0 */ - <3 RK_PC7 4 &pcfg_pull_none>, - /* pcie20x1_2_perstn_m0 */ - <3 RK_PD1 4 &pcfg_pull_none>, - /* pcie20x1_2_waken_m0 */ - <3 RK_PD0 4 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - pcie20x1m1_pins: pcie20x1m1-pins { - rockchip,pins = - /* pcie20x1_2_clkreqn_m1 */ - <4 RK_PB7 4 &pcfg_pull_none>, - /* pcie20x1_2_perstn_m1 */ - <4 RK_PC1 4 &pcfg_pull_none>, - /* pcie20x1_2_waken_m1 */ - <4 RK_PC0 4 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - pcie20x1_2_button_rstn: pcie20x1-2-button-rstn { - rockchip,pins = - /* pcie20x1_2_button_rstn */ - <4 RK_PB3 4 &pcfg_pull_none>; - }; - }; - - pcie30phy { - /omit-if-no-ref/ - pcie30phy_pins: pcie30phy-pins { - rockchip,pins = - /* pcie30phy_dtb0 */ - <1 RK_PC4 4 &pcfg_pull_none>, - /* pcie30phy_dtb1 */ - <1 RK_PD1 4 &pcfg_pull_none>; - }; - }; - - pcie30x1 { - /omit-if-no-ref/ - pcie30x1m0_pins: pcie30x1m0-pins { - rockchip,pins = - /* pcie30x1_0_clkreqn_m0 */ - <0 RK_PC0 12 &pcfg_pull_none>, - /* pcie30x1_0_perstn_m0 */ - <0 RK_PC5 12 &pcfg_pull_none>, - /* pcie30x1_0_waken_m0 */ - <0 RK_PC4 12 &pcfg_pull_none>, - /* pcie30x1_1_clkreqn_m0 */ - <0 RK_PB5 12 &pcfg_pull_none>, - /* pcie30x1_1_perstn_m0 */ - <0 RK_PB7 12 &pcfg_pull_none>, - /* pcie30x1_1_waken_m0 */ - <0 RK_PB6 12 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - pcie30x1m1_pins: pcie30x1m1-pins { - rockchip,pins = - /* pcie30x1_0_clkreqn_m1 */ - <4 RK_PA3 4 &pcfg_pull_none>, - /* pcie30x1_0_perstn_m1 */ - <4 RK_PA5 4 &pcfg_pull_none>, - /* pcie30x1_0_waken_m1 */ - <4 RK_PA4 4 &pcfg_pull_none>, - /* pcie30x1_1_clkreqn_m1 */ - <4 RK_PA0 4 &pcfg_pull_none>, - /* pcie30x1_1_perstn_m1 */ - <4 RK_PA2 4 &pcfg_pull_none>, - /* pcie30x1_1_waken_m1 */ - <4 RK_PA1 4 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - pcie30x1m2_pins: pcie30x1m2-pins { - rockchip,pins = - /* pcie30x1_0_clkreqn_m2 */ - <1 RK_PB5 4 &pcfg_pull_none>, - /* pcie30x1_0_perstn_m2 */ - <1 RK_PB4 4 &pcfg_pull_none>, - /* pcie30x1_0_waken_m2 */ - <1 RK_PB3 4 &pcfg_pull_none>, - /* pcie30x1_1_clkreqn_m2 */ - <1 RK_PA0 4 &pcfg_pull_none>, - /* pcie30x1_1_perstn_m2 */ - <1 RK_PA7 4 &pcfg_pull_none>, - /* pcie30x1_1_waken_m2 */ - <1 RK_PA1 4 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - pcie30x1_0_button_rstn: pcie30x1-0-button-rstn { - rockchip,pins = - /* pcie30x1_0_button_rstn */ - <4 RK_PB1 4 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - pcie30x1_1_button_rstn: pcie30x1-1-button-rstn { - rockchip,pins = - /* pcie30x1_1_button_rstn */ - <4 RK_PB2 4 &pcfg_pull_none>; - }; - }; - - pcie30x2 { - /omit-if-no-ref/ - pcie30x2m0_pins: pcie30x2m0-pins { - rockchip,pins = - /* pcie30x2_clkreqn_m0 */ - <0 RK_PD1 12 &pcfg_pull_none>, - /* pcie30x2_perstn_m0 */ - <0 RK_PD4 12 &pcfg_pull_none>, - /* pcie30x2_waken_m0 */ - <0 RK_PD2 12 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - pcie30x2m1_pins: pcie30x2m1-pins { - rockchip,pins = - /* pcie30x2_clkreqn_m1 */ - <4 RK_PA6 4 &pcfg_pull_none>, - /* pcie30x2_perstn_m1 */ - <4 RK_PB0 4 &pcfg_pull_none>, - /* pcie30x2_waken_m1 */ - <4 RK_PA7 4 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - pcie30x2m2_pins: pcie30x2m2-pins { - rockchip,pins = - /* pcie30x2_clkreqn_m2 */ - <3 RK_PD2 4 &pcfg_pull_none>, - /* pcie30x2_perstn_m2 */ - <3 RK_PD4 4 &pcfg_pull_none>, - /* pcie30x2_waken_m2 */ - <3 RK_PD3 4 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - pcie30x2m3_pins: pcie30x2m3-pins { - rockchip,pins = - /* pcie30x2_clkreqn_m3 */ - <1 RK_PD7 4 &pcfg_pull_none>, - /* pcie30x2_perstn_m3 */ - <1 RK_PB7 4 &pcfg_pull_none>, - /* pcie30x2_waken_m3 */ - <1 RK_PB6 4 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - pcie30x2_button_rstn: pcie30x2-button-rstn { - rockchip,pins = - /* pcie30x2_button_rstn */ - <3 RK_PC1 4 &pcfg_pull_none>; - }; - }; - - pcie30x4 { - /omit-if-no-ref/ - pcie30x4m0_pins: pcie30x4m0-pins { - rockchip,pins = - /* pcie30x4_clkreqn_m0 */ - <0 RK_PC6 12 &pcfg_pull_none>, - /* pcie30x4_perstn_m0 */ - <0 RK_PD0 12 &pcfg_pull_none>, - /* pcie30x4_waken_m0 */ - <0 RK_PC7 12 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - pcie30x4m1_pins: pcie30x4m1-pins { - rockchip,pins = - /* pcie30x4_clkreqn_m1 */ - <4 RK_PB4 4 &pcfg_pull_none>, - /* pcie30x4_perstn_m1 */ - <4 RK_PB6 4 &pcfg_pull_none>, - /* pcie30x4_waken_m1 */ - <4 RK_PB5 4 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - pcie30x4m2_pins: pcie30x4m2-pins { - rockchip,pins = - /* pcie30x4_clkreqn_m2 */ - <3 RK_PC4 4 &pcfg_pull_none>, - /* pcie30x4_perstn_m2 */ - <3 RK_PC6 4 &pcfg_pull_none>, - /* pcie30x4_waken_m2 */ - <3 RK_PC5 4 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - pcie30x4m3_pins: pcie30x4m3-pins { - rockchip,pins = - /* pcie30x4_clkreqn_m3 */ - <1 RK_PB0 4 &pcfg_pull_none>, - /* pcie30x4_perstn_m3 */ - <1 RK_PB2 4 &pcfg_pull_none>, - /* pcie30x4_waken_m3 */ - <1 RK_PB1 4 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - pcie30x4_button_rstn: pcie30x4-button-rstn { - rockchip,pins = - /* pcie30x4_button_rstn */ - <3 RK_PD5 4 &pcfg_pull_none>; - }; - }; - - pdm0 { - /omit-if-no-ref/ - pdm0m0_clk: pdm0m0-clk { - rockchip,pins = - /* pdm0_clk0_m0 */ - <1 RK_PC6 3 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - pdm0m0_clk1: pdm0m0-clk1 { - rockchip,pins = - /* pdm0m0_clk1 */ - <1 RK_PC4 3 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - pdm0m0_sdi0: pdm0m0-sdi0 { - rockchip,pins = - /* pdm0m0_sdi0 */ - <1 RK_PD5 3 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - pdm0m0_sdi1: pdm0m0-sdi1 { - rockchip,pins = - /* pdm0m0_sdi1 */ - <1 RK_PD1 3 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - pdm0m0_sdi2: pdm0m0-sdi2 { - rockchip,pins = - /* pdm0m0_sdi2 */ - <1 RK_PD2 3 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - pdm0m0_sdi3: pdm0m0-sdi3 { - rockchip,pins = - /* pdm0m0_sdi3 */ - <1 RK_PD3 3 &pcfg_pull_none>; - }; - /omit-if-no-ref/ - pdm0m1_clk: pdm0m1-clk { - rockchip,pins = - /* pdm0_clk0_m1 */ - <0 RK_PC0 2 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - pdm0m1_clk1: pdm0m1-clk1 { - rockchip,pins = - /* pdm0m1_clk1 */ - <0 RK_PC4 2 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - pdm0m1_sdi0: pdm0m1-sdi0 { - rockchip,pins = - /* pdm0m1_sdi0 */ - <0 RK_PC7 2 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - pdm0m1_sdi1: pdm0m1-sdi1 { - rockchip,pins = - /* pdm0m1_sdi1 */ - <0 RK_PD0 2 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - pdm0m1_sdi2: pdm0m1-sdi2 { - rockchip,pins = - /* pdm0m1_sdi2 */ - <0 RK_PD4 2 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - pdm0m1_sdi3: pdm0m1-sdi3 { - rockchip,pins = - /* pdm0m1_sdi3 */ - <0 RK_PD6 2 &pcfg_pull_none>; - }; - }; - - pdm1 { - /omit-if-no-ref/ - pdm1m0_clk: pdm1m0-clk { - rockchip,pins = - /* pdm1_clk0_m0 */ - <4 RK_PD5 2 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - pdm1m0_clk1: pdm1m0-clk1 { - rockchip,pins = - /* pdm1m0_clk1 */ - <4 RK_PD4 2 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - pdm1m0_sdi0: pdm1m0-sdi0 { - rockchip,pins = - /* pdm1m0_sdi0 */ - <4 RK_PD3 2 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - pdm1m0_sdi1: pdm1m0-sdi1 { - rockchip,pins = - /* pdm1m0_sdi1 */ - <4 RK_PD2 2 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - pdm1m0_sdi2: pdm1m0-sdi2 { - rockchip,pins = - /* pdm1m0_sdi2 */ - <4 RK_PD1 2 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - pdm1m0_sdi3: pdm1m0-sdi3 { - rockchip,pins = - /* pdm1m0_sdi3 */ - <4 RK_PD0 2 &pcfg_pull_none>; - }; - /omit-if-no-ref/ - pdm1m1_clk: pdm1m1-clk { - rockchip,pins = - /* pdm1_clk0_m1 */ - <1 RK_PB4 2 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - pdm1m1_clk1: pdm1m1-clk1 { - rockchip,pins = - /* pdm1m1_clk1 */ - <1 RK_PB3 2 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - pdm1m1_sdi0: pdm1m1-sdi0 { - rockchip,pins = - /* pdm1m1_sdi0 */ - <1 RK_PA7 2 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - pdm1m1_sdi1: pdm1m1-sdi1 { - rockchip,pins = - /* pdm1m1_sdi1 */ - <1 RK_PB0 2 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - pdm1m1_sdi2: pdm1m1-sdi2 { - rockchip,pins = - /* pdm1m1_sdi2 */ - <1 RK_PB1 2 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - pdm1m1_sdi3: pdm1m1-sdi3 { - rockchip,pins = - /* pdm1m1_sdi3 */ - <1 RK_PB2 2 &pcfg_pull_none>; - }; - }; - - pmic { - /omit-if-no-ref/ - pmic_pins: pmic-pins { - rockchip,pins = - /* pmic_int_l */ - <0 RK_PA7 0 &pcfg_pull_up>, - /* pmic_sleep1 */ - <0 RK_PA2 1 &pcfg_pull_none>, - /* pmic_sleep2 */ - <0 RK_PA3 1 &pcfg_pull_none>, - /* pmic_sleep3 */ - <0 RK_PC1 1 &pcfg_pull_none>, - /* pmic_sleep4 */ - <0 RK_PC2 1 &pcfg_pull_none>, - /* pmic_sleep5 */ - <0 RK_PC3 1 &pcfg_pull_none>, - /* pmic_sleep6 */ - <0 RK_PD6 1 &pcfg_pull_none>; - }; - }; - - pmu { - /omit-if-no-ref/ - pmu_pins: pmu-pins { - rockchip,pins = - /* pmu_debug */ - <0 RK_PA5 3 &pcfg_pull_none>; - }; - }; - - pwm0 { - /omit-if-no-ref/ - pwm0m0_pins: pwm0m0-pins { - rockchip,pins = - /* pwm0_m0 */ - <0 RK_PB7 3 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - pwm0m1_pins: pwm0m1-pins { - rockchip,pins = - /* pwm0_m1 */ - <1 RK_PD2 11 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - pwm0m2_pins: pwm0m2-pins { - rockchip,pins = - /* pwm0_m2 */ - <1 RK_PA2 11 &pcfg_pull_none>; - }; - }; - - pwm1 { - /omit-if-no-ref/ - pwm1m0_pins: pwm1m0-pins { - rockchip,pins = - /* pwm1_m0 */ - <0 RK_PC0 3 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - pwm1m1_pins: pwm1m1-pins { - rockchip,pins = - /* pwm1_m1 */ - <1 RK_PD3 11 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - pwm1m2_pins: pwm1m2-pins { - rockchip,pins = - /* pwm1_m2 */ - <1 RK_PA3 11 &pcfg_pull_none>; - }; - }; - - pwm2 { - /omit-if-no-ref/ - pwm2m0_pins: pwm2m0-pins { - rockchip,pins = - /* pwm2_m0 */ - <0 RK_PC4 3 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - pwm2m1_pins: pwm2m1-pins { - rockchip,pins = - /* pwm2_m1 */ - <3 RK_PB1 11 &pcfg_pull_none>; - }; - }; - - pwm3 { - /omit-if-no-ref/ - pwm3m0_pins: pwm3m0-pins { - rockchip,pins = - /* pwm3_ir_m0 */ - <0 RK_PD4 3 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - pwm3m1_pins: pwm3m1-pins { - rockchip,pins = - /* pwm3_ir_m1 */ - <3 RK_PB2 11 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - pwm3m2_pins: pwm3m2-pins { - rockchip,pins = - /* pwm3_ir_m2 */ - <1 RK_PC2 11 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - pwm3m3_pins: pwm3m3-pins { - rockchip,pins = - /* pwm3_ir_m3 */ - <1 RK_PA7 11 &pcfg_pull_none>; - }; - }; - - pwm4 { - /omit-if-no-ref/ - pwm4m0_pins: pwm4m0-pins { - rockchip,pins = - /* pwm4_m0 */ - <0 RK_PC5 11 &pcfg_pull_none>; - }; - }; - - pwm5 { - /omit-if-no-ref/ - pwm5m0_pins: pwm5m0-pins { - rockchip,pins = - /* pwm5_m0 */ - <0 RK_PB1 3 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - pwm5m1_pins: pwm5m1-pins { - rockchip,pins = - /* pwm5_m1 */ - <0 RK_PC6 11 &pcfg_pull_none>; - }; - }; - - pwm6 { - /omit-if-no-ref/ - pwm6m0_pins: pwm6m0-pins { - rockchip,pins = - /* pwm6_m0 */ - <0 RK_PC7 11 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - pwm6m1_pins: pwm6m1-pins { - rockchip,pins = - /* pwm6_m1 */ - <4 RK_PC1 11 &pcfg_pull_none>; - }; - }; - - pwm7 { - /omit-if-no-ref/ - pwm7m0_pins: pwm7m0-pins { - rockchip,pins = - /* pwm7_ir_m0 */ - <0 RK_PD0 11 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - pwm7m1_pins: pwm7m1-pins { - rockchip,pins = - /* pwm7_ir_m1 */ - <4 RK_PD4 11 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - pwm7m2_pins: pwm7m2-pins { - rockchip,pins = - /* pwm7_ir_m2 */ - <1 RK_PC3 11 &pcfg_pull_none>; - }; - }; - - pwm8 { - /omit-if-no-ref/ - pwm8m0_pins: pwm8m0-pins { - rockchip,pins = - /* pwm8_m0 */ - <3 RK_PA7 11 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - pwm8m1_pins: pwm8m1-pins { - rockchip,pins = - /* pwm8_m1 */ - <4 RK_PD0 11 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - pwm8m2_pins: pwm8m2-pins { - rockchip,pins = - /* pwm8_m2 */ - <3 RK_PD0 11 &pcfg_pull_none>; - }; - }; - - pwm9 { - /omit-if-no-ref/ - pwm9m0_pins: pwm9m0-pins { - rockchip,pins = - /* pwm9_m0 */ - <3 RK_PB0 11 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - pwm9m1_pins: pwm9m1-pins { - rockchip,pins = - /* pwm9_m1 */ - <4 RK_PD1 11 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - pwm9m2_pins: pwm9m2-pins { - rockchip,pins = - /* pwm9_m2 */ - <3 RK_PD1 11 &pcfg_pull_none>; - }; - }; - - pwm10 { - /omit-if-no-ref/ - pwm10m0_pins: pwm10m0-pins { - rockchip,pins = - /* pwm10_m0 */ - <3 RK_PA0 11 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - pwm10m1_pins: pwm10m1-pins { - rockchip,pins = - /* pwm10_m1 */ - <4 RK_PD3 11 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - pwm10m2_pins: pwm10m2-pins { - rockchip,pins = - /* pwm10_m2 */ - <3 RK_PD3 11 &pcfg_pull_none>; - }; - }; - - pwm11 { - /omit-if-no-ref/ - pwm11m0_pins: pwm11m0-pins { - rockchip,pins = - /* pwm11_ir_m0 */ - <3 RK_PA1 11 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - pwm11m1_pins: pwm11m1-pins { - rockchip,pins = - /* pwm11_ir_m1 */ - <4 RK_PB4 11 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - pwm11m2_pins: pwm11m2-pins { - rockchip,pins = - /* pwm11_ir_m2 */ - <1 RK_PC4 11 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - pwm11m3_pins: pwm11m3-pins { - rockchip,pins = - /* pwm11_ir_m3 */ - <3 RK_PD5 11 &pcfg_pull_none>; - }; - }; - - pwm12 { - /omit-if-no-ref/ - pwm12m0_pins: pwm12m0-pins { - rockchip,pins = - /* pwm12_m0 */ - <3 RK_PB5 11 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - pwm12m1_pins: pwm12m1-pins { - rockchip,pins = - /* pwm12_m1 */ - <4 RK_PB5 11 &pcfg_pull_none>; - }; - }; - - pwm13 { - /omit-if-no-ref/ - pwm13m0_pins: pwm13m0-pins { - rockchip,pins = - /* pwm13_m0 */ - <3 RK_PB6 11 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - pwm13m1_pins: pwm13m1-pins { - rockchip,pins = - /* pwm13_m1 */ - <4 RK_PB6 11 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - pwm13m2_pins: pwm13m2-pins { - rockchip,pins = - /* pwm13_m2 */ - <1 RK_PB7 11 &pcfg_pull_none>; - }; - }; - - pwm14 { - /omit-if-no-ref/ - pwm14m0_pins: pwm14m0-pins { - rockchip,pins = - /* pwm14_m0 */ - <3 RK_PC2 11 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - pwm14m1_pins: pwm14m1-pins { - rockchip,pins = - /* pwm14_m1 */ - <4 RK_PB2 11 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - pwm14m2_pins: pwm14m2-pins { - rockchip,pins = - /* pwm14_m2 */ - <1 RK_PD6 11 &pcfg_pull_none>; - }; - }; - - pwm15 { - /omit-if-no-ref/ - pwm15m0_pins: pwm15m0-pins { - rockchip,pins = - /* pwm15_ir_m0 */ - <3 RK_PC3 11 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - pwm15m1_pins: pwm15m1-pins { - rockchip,pins = - /* pwm15_ir_m1 */ - <4 RK_PB3 11 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - pwm15m2_pins: pwm15m2-pins { - rockchip,pins = - /* pwm15_ir_m2 */ - <1 RK_PC6 11 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - pwm15m3_pins: pwm15m3-pins { - rockchip,pins = - /* pwm15_ir_m3 */ - <1 RK_PD7 11 &pcfg_pull_none>; - }; - }; - - refclk { - /omit-if-no-ref/ - refclk_pins: refclk-pins { - rockchip,pins = - /* refclk_out */ - <0 RK_PA0 1 &pcfg_pull_none>; - }; - }; - - sata { - /omit-if-no-ref/ - sata_pins: sata-pins { - rockchip,pins = - /* sata_cp_pod */ - <0 RK_PC6 13 &pcfg_pull_none>, - /* sata_cpdet */ - <0 RK_PD4 13 &pcfg_pull_none>, - /* sata_mp_switch */ - <0 RK_PD5 13 &pcfg_pull_none>; - }; - }; - - sata0 { - /omit-if-no-ref/ - sata0m0_pins: sata0m0-pins { - rockchip,pins = - /* sata0_act_led_m0 */ - <4 RK_PB6 6 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - sata0m1_pins: sata0m1-pins { - rockchip,pins = - /* sata0_act_led_m1 */ - <1 RK_PB3 6 &pcfg_pull_none>; - }; - }; - - sata1 { - /omit-if-no-ref/ - sata1m0_pins: sata1m0-pins { - rockchip,pins = - /* sata1_act_led_m0 */ - <4 RK_PB5 6 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - sata1m1_pins: sata1m1-pins { - rockchip,pins = - /* sata1_act_led_m1 */ - <1 RK_PA1 6 &pcfg_pull_none>; - }; - }; - - sata2 { - /omit-if-no-ref/ - sata2m0_pins: sata2m0-pins { - rockchip,pins = - /* sata2_act_led_m0 */ - <4 RK_PB1 6 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - sata2m1_pins: sata2m1-pins { - rockchip,pins = - /* sata2_act_led_m1 */ - <1 RK_PB7 6 &pcfg_pull_none>; - }; - }; - - sdio { - /omit-if-no-ref/ - sdiom1_pins: sdiom1-pins { - rockchip,pins = - /* sdio_clk_m1 */ - <3 RK_PA5 2 &pcfg_pull_none>, - /* sdio_cmd_m1 */ - <3 RK_PA4 2 &pcfg_pull_up>, - /* sdio_d0_m1 */ - <3 RK_PA0 2 &pcfg_pull_up>, - /* sdio_d1_m1 */ - <3 RK_PA1 2 &pcfg_pull_up>, - /* sdio_d2_m1 */ - <3 RK_PA2 2 &pcfg_pull_up>, - /* sdio_d3_m1 */ - <3 RK_PA3 2 &pcfg_pull_up>; - }; - }; - - sdmmc { - /omit-if-no-ref/ - sdmmc_bus4: sdmmc-bus4 { - rockchip,pins = - /* sdmmc_d0 */ - <4 RK_PD0 1 &pcfg_pull_up_drv_level_2>, - /* sdmmc_d1 */ - <4 RK_PD1 1 &pcfg_pull_up_drv_level_2>, - /* sdmmc_d2 */ - <4 RK_PD2 1 &pcfg_pull_up_drv_level_2>, - /* sdmmc_d3 */ - <4 RK_PD3 1 &pcfg_pull_up_drv_level_2>; - }; - - /omit-if-no-ref/ - sdmmc_clk: sdmmc-clk { - rockchip,pins = - /* sdmmc_clk */ - <4 RK_PD5 1 &pcfg_pull_up_drv_level_2>; - }; - - /omit-if-no-ref/ - sdmmc_cmd: sdmmc-cmd { - rockchip,pins = - /* sdmmc_cmd */ - <4 RK_PD4 1 &pcfg_pull_up_drv_level_2>; - }; - - /omit-if-no-ref/ - sdmmc_det: sdmmc-det { - rockchip,pins = - /* sdmmc_det */ - <0 RK_PA4 1 &pcfg_pull_up>; - }; - - /omit-if-no-ref/ - sdmmc_pwren: sdmmc-pwren { - rockchip,pins = - /* sdmmc_pwren */ - <0 RK_PA5 2 &pcfg_pull_none>; - }; - }; - - spdif0 { - /omit-if-no-ref/ - spdif0m0_tx: spdif0m0-tx { - rockchip,pins = - /* spdif0m0_tx */ - <1 RK_PB6 3 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - spdif0m1_tx: spdif0m1-tx { - rockchip,pins = - /* spdif0m1_tx */ - <4 RK_PB4 6 &pcfg_pull_none>; - }; - }; - - spdif1 { - /omit-if-no-ref/ - spdif1m0_tx: spdif1m0-tx { - rockchip,pins = - /* spdif1m0_tx */ - <1 RK_PB7 3 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - spdif1m1_tx: spdif1m1-tx { - rockchip,pins = - /* spdif1m1_tx */ - <4 RK_PB1 2 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - spdif1m2_tx: spdif1m2-tx { - rockchip,pins = - /* spdif1m2_tx */ - <4 RK_PC1 3 &pcfg_pull_none>; - }; - }; - - spi0 { - /omit-if-no-ref/ - spi0m0_pins: spi0m0-pins { - rockchip,pins = - /* spi0_clk_m0 */ - <0 RK_PC6 8 &pcfg_pull_up_drv_level_1>, - /* spi0_miso_m0 */ - <0 RK_PC7 8 &pcfg_pull_up_drv_level_1>, - /* spi0_mosi_m0 */ - <0 RK_PC0 8 &pcfg_pull_up_drv_level_1>; - }; - - /omit-if-no-ref/ - spi0m0_cs0: spi0m0-cs0 { - rockchip,pins = - /* spi0_cs0_m0 */ - <0 RK_PD1 8 &pcfg_pull_up_drv_level_1>; - }; - - /omit-if-no-ref/ - spi0m0_cs1: spi0m0-cs1 { - rockchip,pins = - /* spi0_cs1_m0 */ - <0 RK_PB7 8 &pcfg_pull_up_drv_level_1>; - }; - /omit-if-no-ref/ - spi0m1_pins: spi0m1-pins { - rockchip,pins = - /* spi0_clk_m1 */ - <4 RK_PA2 8 &pcfg_pull_up_drv_level_1>, - /* spi0_miso_m1 */ - <4 RK_PA0 8 &pcfg_pull_up_drv_level_1>, - /* spi0_mosi_m1 */ - <4 RK_PA1 8 &pcfg_pull_up_drv_level_1>; - }; - - /omit-if-no-ref/ - spi0m1_cs0: spi0m1-cs0 { - rockchip,pins = - /* spi0_cs0_m1 */ - <4 RK_PB2 8 &pcfg_pull_up_drv_level_1>; - }; - - /omit-if-no-ref/ - spi0m1_cs1: spi0m1-cs1 { - rockchip,pins = - /* spi0_cs1_m1 */ - <4 RK_PB1 8 &pcfg_pull_up_drv_level_1>; - }; - /omit-if-no-ref/ - spi0m2_pins: spi0m2-pins { - rockchip,pins = - /* spi0_clk_m2 */ - <1 RK_PB3 8 &pcfg_pull_up_drv_level_1>, - /* spi0_miso_m2 */ - <1 RK_PB1 8 &pcfg_pull_up_drv_level_1>, - /* spi0_mosi_m2 */ - <1 RK_PB2 8 &pcfg_pull_up_drv_level_1>; - }; - - /omit-if-no-ref/ - spi0m2_cs0: spi0m2-cs0 { - rockchip,pins = - /* spi0_cs0_m2 */ - <1 RK_PB4 8 &pcfg_pull_up_drv_level_1>; - }; - - /omit-if-no-ref/ - spi0m2_cs1: spi0m2-cs1 { - rockchip,pins = - /* spi0_cs1_m2 */ - <1 RK_PB5 8 &pcfg_pull_up_drv_level_1>; - }; - /omit-if-no-ref/ - spi0m3_pins: spi0m3-pins { - rockchip,pins = - /* spi0_clk_m3 */ - <3 RK_PD3 8 &pcfg_pull_up_drv_level_1>, - /* spi0_miso_m3 */ - <3 RK_PD1 8 &pcfg_pull_up_drv_level_1>, - /* spi0_mosi_m3 */ - <3 RK_PD2 8 &pcfg_pull_up_drv_level_1>; - }; - - /omit-if-no-ref/ - spi0m3_cs0: spi0m3-cs0 { - rockchip,pins = - /* spi0_cs0_m3 */ - <3 RK_PD4 8 &pcfg_pull_up_drv_level_1>; - }; - - /omit-if-no-ref/ - spi0m3_cs1: spi0m3-cs1 { - rockchip,pins = - /* spi0_cs1_m3 */ - <3 RK_PD5 8 &pcfg_pull_up_drv_level_1>; - }; - }; - - spi1 { - /omit-if-no-ref/ - spi1m1_pins: spi1m1-pins { - rockchip,pins = - /* spi1_clk_m1 */ - <3 RK_PC1 8 &pcfg_pull_up_drv_level_1>, - /* spi1_miso_m1 */ - <3 RK_PC0 8 &pcfg_pull_up_drv_level_1>, - /* spi1_mosi_m1 */ - <3 RK_PB7 8 &pcfg_pull_up_drv_level_1>; - }; - - /omit-if-no-ref/ - spi1m1_cs0: spi1m1-cs0 { - rockchip,pins = - /* spi1_cs0_m1 */ - <3 RK_PC2 8 &pcfg_pull_up_drv_level_1>; - }; - - /omit-if-no-ref/ - spi1m1_cs1: spi1m1-cs1 { - rockchip,pins = - /* spi1_cs1_m1 */ - <3 RK_PC3 8 &pcfg_pull_up_drv_level_1>; - }; - - /omit-if-no-ref/ - spi1m2_pins: spi1m2-pins { - rockchip,pins = - /* spi1_clk_m2 */ - <1 RK_PD2 8 &pcfg_pull_up_drv_level_1>, - /* spi1_miso_m2 */ - <1 RK_PD0 8 &pcfg_pull_up_drv_level_1>, - /* spi1_mosi_m2 */ - <1 RK_PD1 8 &pcfg_pull_up_drv_level_1>; - }; - - /omit-if-no-ref/ - spi1m2_cs0: spi1m2-cs0 { - rockchip,pins = - /* spi1_cs0_m2 */ - <1 RK_PD3 8 &pcfg_pull_up_drv_level_1>; - }; - - /omit-if-no-ref/ - spi1m2_cs1: spi1m2-cs1 { - rockchip,pins = - /* spi1_cs1_m2 */ - <1 RK_PD5 8 &pcfg_pull_up_drv_level_1>; - }; - }; - - spi2 { - /omit-if-no-ref/ - spi2m0_pins: spi2m0-pins { - rockchip,pins = - /* spi2_clk_m0 */ - <1 RK_PA6 8 &pcfg_pull_up_drv_level_1>, - /* spi2_miso_m0 */ - <1 RK_PA4 8 &pcfg_pull_up_drv_level_1>, - /* spi2_mosi_m0 */ - <1 RK_PA5 8 &pcfg_pull_up_drv_level_1>; - }; - - /omit-if-no-ref/ - spi2m0_cs0: spi2m0-cs0 { - rockchip,pins = - /* spi2_cs0_m0 */ - <1 RK_PA7 8 &pcfg_pull_up_drv_level_1>; - }; - - /omit-if-no-ref/ - spi2m0_cs1: spi2m0-cs1 { - rockchip,pins = - /* spi2_cs1_m0 */ - <1 RK_PB0 8 &pcfg_pull_up_drv_level_1>; - }; - - /omit-if-no-ref/ - spi2m1_pins: spi2m1-pins { - rockchip,pins = - /* spi2_clk_m1 */ - <4 RK_PA6 8 &pcfg_pull_up_drv_level_1>, - /* spi2_miso_m1 */ - <4 RK_PA4 8 &pcfg_pull_up_drv_level_1>, - /* spi2_mosi_m1 */ - <4 RK_PA5 8 &pcfg_pull_up_drv_level_1>; - }; - - /omit-if-no-ref/ - spi2m1_cs0: spi2m1-cs0 { - rockchip,pins = - /* spi2_cs0_m1 */ - <4 RK_PA7 8 &pcfg_pull_up_drv_level_1>; - }; - - /omit-if-no-ref/ - spi2m1_cs1: spi2m1-cs1 { - rockchip,pins = - /* spi2_cs1_m1 */ - <4 RK_PB0 8 &pcfg_pull_up_drv_level_1>; - }; - - /omit-if-no-ref/ - spi2m2_pins: spi2m2-pins { - rockchip,pins = - /* spi2_clk_m2 */ - <0 RK_PA5 1 &pcfg_pull_up_drv_level_1>, - /* spi2_miso_m2 */ - <0 RK_PB3 1 &pcfg_pull_up_drv_level_1>, - /* spi2_mosi_m2 */ - <0 RK_PA6 1 &pcfg_pull_up_drv_level_1>; - }; - - /omit-if-no-ref/ - spi2m2_cs0: spi2m2-cs0 { - rockchip,pins = - /* spi2_cs0_m2 */ - <0 RK_PB1 1 &pcfg_pull_up_drv_level_1>; - }; - - /omit-if-no-ref/ - spi2m2_cs1: spi2m2-cs1 { - rockchip,pins = - /* spi2_cs1_m2 */ - <0 RK_PB0 1 &pcfg_pull_up_drv_level_1>; - }; - }; - - spi3 { - /omit-if-no-ref/ - spi3m1_pins: spi3m1-pins { - rockchip,pins = - /* spi3_clk_m1 */ - <4 RK_PB7 8 &pcfg_pull_up_drv_level_1>, - /* spi3_miso_m1 */ - <4 RK_PB5 8 &pcfg_pull_up_drv_level_1>, - /* spi3_mosi_m1 */ - <4 RK_PB6 8 &pcfg_pull_up_drv_level_1>; - }; - - /omit-if-no-ref/ - spi3m1_cs0: spi3m1-cs0 { - rockchip,pins = - /* spi3_cs0_m1 */ - <4 RK_PC0 8 &pcfg_pull_up_drv_level_1>; - }; - - /omit-if-no-ref/ - spi3m1_cs1: spi3m1-cs1 { - rockchip,pins = - /* spi3_cs1_m1 */ - <4 RK_PC1 8 &pcfg_pull_up_drv_level_1>; - }; - - /omit-if-no-ref/ - spi3m2_pins: spi3m2-pins { - rockchip,pins = - /* spi3_clk_m2 */ - <0 RK_PD3 8 &pcfg_pull_up_drv_level_1>, - /* spi3_miso_m2 */ - <0 RK_PD0 8 &pcfg_pull_up_drv_level_1>, - /* spi3_mosi_m2 */ - <0 RK_PD2 8 &pcfg_pull_up_drv_level_1>; - }; - - /omit-if-no-ref/ - spi3m2_cs0: spi3m2-cs0 { - rockchip,pins = - /* spi3_cs0_m2 */ - <0 RK_PD4 8 &pcfg_pull_up_drv_level_1>; - }; - - /omit-if-no-ref/ - spi3m2_cs1: spi3m2-cs1 { - rockchip,pins = - /* spi3_cs1_m2 */ - <0 RK_PD5 8 &pcfg_pull_up_drv_level_1>; - }; - - /omit-if-no-ref/ - spi3m3_pins: spi3m3-pins { - rockchip,pins = - /* spi3_clk_m3 */ - <3 RK_PD0 8 &pcfg_pull_up_drv_level_1>, - /* spi3_miso_m3 */ - <3 RK_PC6 8 &pcfg_pull_up_drv_level_1>, - /* spi3_mosi_m3 */ - <3 RK_PC7 8 &pcfg_pull_up_drv_level_1>; - }; - - /omit-if-no-ref/ - spi3m3_cs0: spi3m3-cs0 { - rockchip,pins = - /* spi3_cs0_m3 */ - <3 RK_PC4 8 &pcfg_pull_up_drv_level_1>; - }; - - /omit-if-no-ref/ - spi3m3_cs1: spi3m3-cs1 { - rockchip,pins = - /* spi3_cs1_m3 */ - <3 RK_PC5 8 &pcfg_pull_up_drv_level_1>; - }; - }; - - spi4 { - /omit-if-no-ref/ - spi4m0_pins: spi4m0-pins { - rockchip,pins = - /* spi4_clk_m0 */ - <1 RK_PC2 8 &pcfg_pull_up_drv_level_1>, - /* spi4_miso_m0 */ - <1 RK_PC0 8 &pcfg_pull_up_drv_level_1>, - /* spi4_mosi_m0 */ - <1 RK_PC1 8 &pcfg_pull_up_drv_level_1>; - }; - - /omit-if-no-ref/ - spi4m0_cs0: spi4m0-cs0 { - rockchip,pins = - /* spi4_cs0_m0 */ - <1 RK_PC3 8 &pcfg_pull_up_drv_level_1>; - }; - - /omit-if-no-ref/ - spi4m0_cs1: spi4m0-cs1 { - rockchip,pins = - /* spi4_cs1_m0 */ - <1 RK_PC4 8 &pcfg_pull_up_drv_level_1>; - }; - - /omit-if-no-ref/ - spi4m1_pins: spi4m1-pins { - rockchip,pins = - /* spi4_clk_m1 */ - <3 RK_PA2 8 &pcfg_pull_up_drv_level_1>, - /* spi4_miso_m1 */ - <3 RK_PA0 8 &pcfg_pull_up_drv_level_1>, - /* spi4_mosi_m1 */ - <3 RK_PA1 8 &pcfg_pull_up_drv_level_1>; - }; - - /omit-if-no-ref/ - spi4m1_cs0: spi4m1-cs0 { - rockchip,pins = - /* spi4_cs0_m1 */ - <3 RK_PA3 8 &pcfg_pull_up_drv_level_1>; - }; - - /omit-if-no-ref/ - spi4m1_cs1: spi4m1-cs1 { - rockchip,pins = - /* spi4_cs1_m1 */ - <3 RK_PA4 8 &pcfg_pull_up_drv_level_1>; - }; - - /omit-if-no-ref/ - spi4m2_pins: spi4m2-pins { - rockchip,pins = - /* spi4_clk_m2 */ - <1 RK_PA2 8 &pcfg_pull_up_drv_level_1>, - /* spi4_miso_m2 */ - <1 RK_PA0 8 &pcfg_pull_up_drv_level_1>, - /* spi4_mosi_m2 */ - <1 RK_PA1 8 &pcfg_pull_up_drv_level_1>; - }; - - /omit-if-no-ref/ - spi4m2_cs0: spi4m2-cs0 { - rockchip,pins = - /* spi4_cs0_m2 */ - <1 RK_PA3 8 &pcfg_pull_up_drv_level_1>; - }; - }; - - tsadc { - /omit-if-no-ref/ - tsadcm1_shut: tsadcm1-shut { - rockchip,pins = - /* tsadcm1_shut */ - <0 RK_PA2 2 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - tsadc_shut: tsadc-shut { - rockchip,pins = - /* tsadc_shut */ - <0 RK_PA1 2 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - tsadc_shut_org: tsadc-shut-org { - rockchip,pins = - /* tsadc_shut_org */ - <0 RK_PA1 1 &pcfg_pull_none>; - }; - }; - - uart0 { - /omit-if-no-ref/ - uart0m0_xfer: uart0m0-xfer { - rockchip,pins = - /* uart0_rx_m0 */ - <0 RK_PC4 4 &pcfg_pull_up>, - /* uart0_tx_m0 */ - <0 RK_PC5 4 &pcfg_pull_up>; - }; - - /omit-if-no-ref/ - uart0m1_xfer: uart0m1-xfer { - rockchip,pins = - /* uart0_rx_m1 */ - <0 RK_PB0 4 &pcfg_pull_up>, - /* uart0_tx_m1 */ - <0 RK_PB1 4 &pcfg_pull_up>; - }; - - /omit-if-no-ref/ - uart0m2_xfer: uart0m2-xfer { - rockchip,pins = - /* uart0_rx_m2 */ - <4 RK_PA4 10 &pcfg_pull_up>, - /* uart0_tx_m2 */ - <4 RK_PA3 10 &pcfg_pull_up>; - }; - - /omit-if-no-ref/ - uart0_ctsn: uart0-ctsn { - rockchip,pins = - /* uart0_ctsn */ - <0 RK_PD1 4 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - uart0_rtsn: uart0-rtsn { - rockchip,pins = - /* uart0_rtsn */ - <0 RK_PC6 4 &pcfg_pull_none>; - }; - }; - - uart1 { - /omit-if-no-ref/ - uart1m1_xfer: uart1m1-xfer { - rockchip,pins = - /* uart1_rx_m1 */ - <1 RK_PB7 10 &pcfg_pull_up>, - /* uart1_tx_m1 */ - <1 RK_PB6 10 &pcfg_pull_up>; - }; - - /omit-if-no-ref/ - uart1m1_ctsn: uart1m1-ctsn { - rockchip,pins = - /* uart1m1_ctsn */ - <1 RK_PD7 10 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - uart1m1_rtsn: uart1m1-rtsn { - rockchip,pins = - /* uart1m1_rtsn */ - <1 RK_PD6 10 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - uart1m2_xfer: uart1m2-xfer { - rockchip,pins = - /* uart1_rx_m2 */ - <0 RK_PD2 10 &pcfg_pull_up>, - /* uart1_tx_m2 */ - <0 RK_PD1 10 &pcfg_pull_up>; - }; - - /omit-if-no-ref/ - uart1m2_ctsn: uart1m2-ctsn { - rockchip,pins = - /* uart1m2_ctsn */ - <0 RK_PD0 10 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - uart1m2_rtsn: uart1m2-rtsn { - rockchip,pins = - /* uart1m2_rtsn */ - <0 RK_PC7 10 &pcfg_pull_none>; - }; - }; - - uart2 { - /omit-if-no-ref/ - uart2m0_xfer: uart2m0-xfer { - rockchip,pins = - /* uart2_rx_m0 */ - <0 RK_PB6 10 &pcfg_pull_up>, - /* uart2_tx_m0 */ - <0 RK_PB5 10 &pcfg_pull_up>; - }; - - /omit-if-no-ref/ - uart2m1_xfer: uart2m1-xfer { - rockchip,pins = - /* uart2_rx_m1 */ - <4 RK_PD1 10 &pcfg_pull_up>, - /* uart2_tx_m1 */ - <4 RK_PD0 10 &pcfg_pull_up>; - }; - - /omit-if-no-ref/ - uart2m2_xfer: uart2m2-xfer { - rockchip,pins = - /* uart2_rx_m2 */ - <3 RK_PB2 10 &pcfg_pull_up>, - /* uart2_tx_m2 */ - <3 RK_PB1 10 &pcfg_pull_up>; - }; - - /omit-if-no-ref/ - uart2_ctsn: uart2-ctsn { - rockchip,pins = - /* uart2_ctsn */ - <3 RK_PB4 10 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - uart2_rtsn: uart2-rtsn { - rockchip,pins = - /* uart2_rtsn */ - <3 RK_PB3 10 &pcfg_pull_none>; - }; - }; - - uart3 { - /omit-if-no-ref/ - uart3m0_xfer: uart3m0-xfer { - rockchip,pins = - /* uart3_rx_m0 */ - <1 RK_PC0 10 &pcfg_pull_up>, - /* uart3_tx_m0 */ - <1 RK_PC1 10 &pcfg_pull_up>; - }; - - /omit-if-no-ref/ - uart3m1_xfer: uart3m1-xfer { - rockchip,pins = - /* uart3_rx_m1 */ - <3 RK_PB6 10 &pcfg_pull_up>, - /* uart3_tx_m1 */ - <3 RK_PB5 10 &pcfg_pull_up>; - }; - - /omit-if-no-ref/ - uart3m2_xfer: uart3m2-xfer { - rockchip,pins = - /* uart3_rx_m2 */ - <4 RK_PA6 10 &pcfg_pull_up>, - /* uart3_tx_m2 */ - <4 RK_PA5 10 &pcfg_pull_up>; - }; - - /omit-if-no-ref/ - uart3_ctsn: uart3-ctsn { - rockchip,pins = - /* uart3_ctsn */ - <1 RK_PC3 10 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - uart3_rtsn: uart3-rtsn { - rockchip,pins = - /* uart3_rtsn */ - <1 RK_PC2 10 &pcfg_pull_none>; - }; - }; - - uart4 { - /omit-if-no-ref/ - uart4m0_xfer: uart4m0-xfer { - rockchip,pins = - /* uart4_rx_m0 */ - <1 RK_PD3 10 &pcfg_pull_up>, - /* uart4_tx_m0 */ - <1 RK_PD2 10 &pcfg_pull_up>; - }; - - /omit-if-no-ref/ - uart4m1_xfer: uart4m1-xfer { - rockchip,pins = - /* uart4_rx_m1 */ - <3 RK_PD0 10 &pcfg_pull_up>, - /* uart4_tx_m1 */ - <3 RK_PD1 10 &pcfg_pull_up>; - }; - - /omit-if-no-ref/ - uart4m2_xfer: uart4m2-xfer { - rockchip,pins = - /* uart4_rx_m2 */ - <1 RK_PB2 10 &pcfg_pull_up>, - /* uart4_tx_m2 */ - <1 RK_PB3 10 &pcfg_pull_up>; - }; - - /omit-if-no-ref/ - uart4_ctsn: uart4-ctsn { - rockchip,pins = - /* uart4_ctsn */ - <1 RK_PC7 10 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - uart4_rtsn: uart4-rtsn { - rockchip,pins = - /* uart4_rtsn */ - <1 RK_PC5 10 &pcfg_pull_none>; - }; - }; - - uart5 { - /omit-if-no-ref/ - uart5m0_xfer: uart5m0-xfer { - rockchip,pins = - /* uart5_rx_m0 */ - <4 RK_PD4 10 &pcfg_pull_up>, - /* uart5_tx_m0 */ - <4 RK_PD5 10 &pcfg_pull_up>; - }; - - /omit-if-no-ref/ - uart5m0_ctsn: uart5m0-ctsn { - rockchip,pins = - /* uart5m0_ctsn */ - <4 RK_PD2 10 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - uart5m0_rtsn: uart5m0-rtsn { - rockchip,pins = - /* uart5m0_rtsn */ - <4 RK_PD3 10 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - uart5m1_xfer: uart5m1-xfer { - rockchip,pins = - /* uart5_rx_m1 */ - <3 RK_PC5 10 &pcfg_pull_up>, - /* uart5_tx_m1 */ - <3 RK_PC4 10 &pcfg_pull_up>; - }; - - /omit-if-no-ref/ - uart5m1_ctsn: uart5m1-ctsn { - rockchip,pins = - /* uart5m1_ctsn */ - <2 RK_PA2 10 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - uart5m1_rtsn: uart5m1-rtsn { - rockchip,pins = - /* uart5m1_rtsn */ - <2 RK_PA3 10 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - uart5m2_xfer: uart5m2-xfer { - rockchip,pins = - /* uart5_rx_m2 */ - <2 RK_PD4 10 &pcfg_pull_up>, - /* uart5_tx_m2 */ - <2 RK_PD5 10 &pcfg_pull_up>; - }; - }; - - uart6 { - /omit-if-no-ref/ - uart6m1_xfer: uart6m1-xfer { - rockchip,pins = - /* uart6_rx_m1 */ - <1 RK_PA0 10 &pcfg_pull_up>, - /* uart6_tx_m1 */ - <1 RK_PA1 10 &pcfg_pull_up>; - }; - - /omit-if-no-ref/ - uart6m1_ctsn: uart6m1-ctsn { - rockchip,pins = - /* uart6m1_ctsn */ - <1 RK_PA3 10 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - uart6m1_rtsn: uart6m1-rtsn { - rockchip,pins = - /* uart6m1_rtsn */ - <1 RK_PA2 10 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - uart6m2_xfer: uart6m2-xfer { - rockchip,pins = - /* uart6_rx_m2 */ - <1 RK_PD1 10 &pcfg_pull_up>, - /* uart6_tx_m2 */ - <1 RK_PD0 10 &pcfg_pull_up>; - }; - }; - - uart7 { - /omit-if-no-ref/ - uart7m1_xfer: uart7m1-xfer { - rockchip,pins = - /* uart7_rx_m1 */ - <3 RK_PC1 10 &pcfg_pull_up>, - /* uart7_tx_m1 */ - <3 RK_PC0 10 &pcfg_pull_up>; - }; - - /omit-if-no-ref/ - uart7m1_ctsn: uart7m1-ctsn { - rockchip,pins = - /* uart7m1_ctsn */ - <3 RK_PC3 10 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - uart7m1_rtsn: uart7m1-rtsn { - rockchip,pins = - /* uart7m1_rtsn */ - <3 RK_PC2 10 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - uart7m2_xfer: uart7m2-xfer { - rockchip,pins = - /* uart7_rx_m2 */ - <1 RK_PB4 10 &pcfg_pull_up>, - /* uart7_tx_m2 */ - <1 RK_PB5 10 &pcfg_pull_up>; - }; - }; - - uart8 { - /omit-if-no-ref/ - uart8m0_xfer: uart8m0-xfer { - rockchip,pins = - /* uart8_rx_m0 */ - <4 RK_PB1 10 &pcfg_pull_up>, - /* uart8_tx_m0 */ - <4 RK_PB0 10 &pcfg_pull_up>; - }; - - /omit-if-no-ref/ - uart8m0_ctsn: uart8m0-ctsn { - rockchip,pins = - /* uart8m0_ctsn */ - <4 RK_PB3 10 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - uart8m0_rtsn: uart8m0-rtsn { - rockchip,pins = - /* uart8m0_rtsn */ - <4 RK_PB2 10 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - uart8m1_xfer: uart8m1-xfer { - rockchip,pins = - /* uart8_rx_m1 */ - <3 RK_PA3 10 &pcfg_pull_up>, - /* uart8_tx_m1 */ - <3 RK_PA2 10 &pcfg_pull_up>; - }; - - /omit-if-no-ref/ - uart8m1_ctsn: uart8m1-ctsn { - rockchip,pins = - /* uart8m1_ctsn */ - <3 RK_PA5 10 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - uart8m1_rtsn: uart8m1-rtsn { - rockchip,pins = - /* uart8m1_rtsn */ - <3 RK_PA4 10 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - uart8_xfer: uart8-xfer { - rockchip,pins = - /* uart8_rx_ */ - <4 RK_PB1 10 &pcfg_pull_up>; - }; - }; - - uart9 { - /omit-if-no-ref/ - uart9m0_xfer: uart9m0-xfer { - rockchip,pins = - /* uart9_rx_m0 */ - <2 RK_PC4 10 &pcfg_pull_up>, - /* uart9_tx_m0 */ - <2 RK_PC2 10 &pcfg_pull_up>; - }; - - /omit-if-no-ref/ - uart9m1_xfer: uart9m1-xfer { - rockchip,pins = - /* uart9_rx_m1 */ - <4 RK_PB5 10 &pcfg_pull_up>, - /* uart9_tx_m1 */ - <4 RK_PB4 10 &pcfg_pull_up>; - }; - - /omit-if-no-ref/ - uart9m1_ctsn: uart9m1-ctsn { - rockchip,pins = - /* uart9m1_ctsn */ - <4 RK_PA1 10 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - uart9m1_rtsn: uart9m1-rtsn { - rockchip,pins = - /* uart9m1_rtsn */ - <4 RK_PA0 10 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - uart9m2_xfer: uart9m2-xfer { - rockchip,pins = - /* uart9_rx_m2 */ - <3 RK_PD4 10 &pcfg_pull_up>, - /* uart9_tx_m2 */ - <3 RK_PD5 10 &pcfg_pull_up>; - }; - - /omit-if-no-ref/ - uart9m2_ctsn: uart9m2-ctsn { - rockchip,pins = - /* uart9m2_ctsn */ - <3 RK_PD3 10 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - uart9m2_rtsn: uart9m2-rtsn { - rockchip,pins = - /* uart9m2_rtsn */ - <3 RK_PD2 10 &pcfg_pull_none>; - }; - }; - - vop { - /omit-if-no-ref/ - vop_pins: vop-pins { - rockchip,pins = - /* vop_post_empty */ - <1 RK_PA2 1 &pcfg_pull_none>; - }; - }; -}; - -/* - * This part is edited handly. - */ -&pinctrl { - bt656 { - /omit-if-no-ref/ - bt656_pins: bt656-pins { - rockchip,pins = - /* bt1120_clkout */ - <4 RK_PB0 2 &pcfg_pull_none_drv_level_2>, - /* bt1120_d0 */ - <4 RK_PA0 2 &pcfg_pull_none_drv_level_2>, - /* bt1120_d1 */ - <4 RK_PA1 2 &pcfg_pull_none_drv_level_2>, - /* bt1120_d2 */ - <4 RK_PA2 2 &pcfg_pull_none_drv_level_2>, - /* bt1120_d3 */ - <4 RK_PA3 2 &pcfg_pull_none_drv_level_2>, - /* bt1120_d4 */ - <4 RK_PA4 2 &pcfg_pull_none_drv_level_2>, - /* bt1120_d5 */ - <4 RK_PA5 2 &pcfg_pull_none_drv_level_2>, - /* bt1120_d6 */ - <4 RK_PA6 2 &pcfg_pull_none_drv_level_2>, - /* bt1120_d7 */ - <4 RK_PA7 2 &pcfg_pull_none_drv_level_2>; - }; - }; - - gpio-func { - /omit-if-no-ref/ - tsadc_gpio_func: tsadc-gpio-func { - rockchip,pins = - <0 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; -}; diff --git a/lede/target/linux/rockchip/files-5.15/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi b/lede/target/linux/rockchip/files-5.15/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi deleted file mode 100644 index d97d84b888..0000000000 --- a/lede/target/linux/rockchip/files-5.15/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi +++ /dev/null @@ -1,2911 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2021 Rockchip Electronics Co., Ltd. - */ - -#include -#include -#include -#include -#include -#include -#include -#include - -/ { - compatible = "rockchip,rk3588"; - - interrupt-parent = <&gic>; - #address-cells = <2>; - #size-cells = <2>; - - aliases { - gpio0 = &gpio0; - gpio1 = &gpio1; - gpio2 = &gpio2; - gpio3 = &gpio3; - gpio4 = &gpio4; - i2c0 = &i2c0; - i2c1 = &i2c1; - i2c2 = &i2c2; - i2c3 = &i2c3; - i2c4 = &i2c4; - i2c5 = &i2c5; - i2c6 = &i2c6; - i2c7 = &i2c7; - i2c8 = &i2c8; - serial0 = &uart0; - serial1 = &uart1; - serial2 = &uart2; - serial3 = &uart3; - serial4 = &uart4; - serial5 = &uart5; - serial6 = &uart6; - serial7 = &uart7; - serial8 = &uart8; - serial9 = &uart9; - spi0 = &spi0; - spi1 = &spi1; - spi2 = &spi2; - spi3 = &spi3; - spi4 = &spi4; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu-map { - cluster0 { - core0 { - cpu = <&cpu_l0>; - }; - core1 { - cpu = <&cpu_l1>; - }; - core2 { - cpu = <&cpu_l2>; - }; - core3 { - cpu = <&cpu_l3>; - }; - }; - cluster1 { - core0 { - cpu = <&cpu_b0>; - }; - core1 { - cpu = <&cpu_b1>; - }; - }; - cluster2 { - core0 { - cpu = <&cpu_b2>; - }; - core1 { - cpu = <&cpu_b3>; - }; - }; - }; - - cpu_l0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a55"; - reg = <0x0>; - enable-method = "psci"; - capacity-dmips-mhz = <530>; - clocks = <&scmi_clk SCMI_CLK_CPUL>; - assigned-clocks = <&scmi_clk SCMI_CLK_CPUL>; - assigned-clock-rates = <816000000>; - cpu-idle-states = <&CPU_SLEEP>; - i-cache-size = <32768>; - i-cache-line-size = <64>; - i-cache-sets = <128>; - d-cache-size = <32768>; - d-cache-line-size = <64>; - d-cache-sets = <128>; - next-level-cache = <&l2_cache_l0>; - dynamic-power-coefficient = <228>; - #cooling-cells = <2>; - }; - - cpu_l1: cpu@100 { - device_type = "cpu"; - compatible = "arm,cortex-a55"; - reg = <0x100>; - enable-method = "psci"; - capacity-dmips-mhz = <530>; - clocks = <&scmi_clk SCMI_CLK_CPUL>; - cpu-idle-states = <&CPU_SLEEP>; - i-cache-size = <32768>; - i-cache-line-size = <64>; - i-cache-sets = <128>; - d-cache-size = <32768>; - d-cache-line-size = <64>; - d-cache-sets = <128>; - next-level-cache = <&l2_cache_l1>; - dynamic-power-coefficient = <228>; - #cooling-cells = <2>; - }; - - cpu_l2: cpu@200 { - device_type = "cpu"; - compatible = "arm,cortex-a55"; - reg = <0x200>; - enable-method = "psci"; - capacity-dmips-mhz = <530>; - clocks = <&scmi_clk SCMI_CLK_CPUL>; - cpu-idle-states = <&CPU_SLEEP>; - i-cache-size = <32768>; - i-cache-line-size = <64>; - i-cache-sets = <128>; - d-cache-size = <32768>; - d-cache-line-size = <64>; - d-cache-sets = <128>; - next-level-cache = <&l2_cache_l2>; - dynamic-power-coefficient = <228>; - #cooling-cells = <2>; - }; - - cpu_l3: cpu@300 { - device_type = "cpu"; - compatible = "arm,cortex-a55"; - reg = <0x300>; - enable-method = "psci"; - capacity-dmips-mhz = <530>; - clocks = <&scmi_clk SCMI_CLK_CPUL>; - cpu-idle-states = <&CPU_SLEEP>; - i-cache-size = <32768>; - i-cache-line-size = <64>; - i-cache-sets = <128>; - d-cache-size = <32768>; - d-cache-line-size = <64>; - d-cache-sets = <128>; - next-level-cache = <&l2_cache_l3>; - dynamic-power-coefficient = <228>; - #cooling-cells = <2>; - }; - - cpu_b0: cpu@400 { - device_type = "cpu"; - compatible = "arm,cortex-a76"; - reg = <0x400>; - enable-method = "psci"; - capacity-dmips-mhz = <1024>; - clocks = <&scmi_clk SCMI_CLK_CPUB01>; - assigned-clocks = <&scmi_clk SCMI_CLK_CPUB01>; - assigned-clock-rates = <816000000>; - cpu-idle-states = <&CPU_SLEEP>; - i-cache-size = <65536>; - i-cache-line-size = <64>; - i-cache-sets = <256>; - d-cache-size = <65536>; - d-cache-line-size = <64>; - d-cache-sets = <256>; - next-level-cache = <&l2_cache_b0>; - dynamic-power-coefficient = <416>; - #cooling-cells = <2>; - }; - - cpu_b1: cpu@500 { - device_type = "cpu"; - compatible = "arm,cortex-a76"; - reg = <0x500>; - enable-method = "psci"; - capacity-dmips-mhz = <1024>; - clocks = <&scmi_clk SCMI_CLK_CPUB01>; - cpu-idle-states = <&CPU_SLEEP>; - i-cache-size = <65536>; - i-cache-line-size = <64>; - i-cache-sets = <256>; - d-cache-size = <65536>; - d-cache-line-size = <64>; - d-cache-sets = <256>; - next-level-cache = <&l2_cache_b1>; - dynamic-power-coefficient = <416>; - #cooling-cells = <2>; - }; - - cpu_b2: cpu@600 { - device_type = "cpu"; - compatible = "arm,cortex-a76"; - reg = <0x600>; - enable-method = "psci"; - capacity-dmips-mhz = <1024>; - clocks = <&scmi_clk SCMI_CLK_CPUB23>; - assigned-clocks = <&scmi_clk SCMI_CLK_CPUB23>; - assigned-clock-rates = <816000000>; - cpu-idle-states = <&CPU_SLEEP>; - i-cache-size = <65536>; - i-cache-line-size = <64>; - i-cache-sets = <256>; - d-cache-size = <65536>; - d-cache-line-size = <64>; - d-cache-sets = <256>; - next-level-cache = <&l2_cache_b2>; - dynamic-power-coefficient = <416>; - #cooling-cells = <2>; - }; - - cpu_b3: cpu@700 { - device_type = "cpu"; - compatible = "arm,cortex-a76"; - reg = <0x700>; - enable-method = "psci"; - capacity-dmips-mhz = <1024>; - clocks = <&scmi_clk SCMI_CLK_CPUB23>; - cpu-idle-states = <&CPU_SLEEP>; - i-cache-size = <65536>; - i-cache-line-size = <64>; - i-cache-sets = <256>; - d-cache-size = <65536>; - d-cache-line-size = <64>; - d-cache-sets = <256>; - next-level-cache = <&l2_cache_b3>; - dynamic-power-coefficient = <416>; - #cooling-cells = <2>; - }; - - idle-states { - entry-method = "psci"; - CPU_SLEEP: cpu-sleep { - compatible = "arm,idle-state"; - local-timer-stop; - arm,psci-suspend-param = <0x0010000>; - entry-latency-us = <100>; - exit-latency-us = <120>; - min-residency-us = <1000>; - }; - }; - - l2_cache_l0: l2-cache-l0 { - compatible = "cache"; - cache-size = <131072>; - cache-line-size = <64>; - cache-sets = <512>; - cache-level = <2>; - cache-unified; - next-level-cache = <&l3_cache>; - }; - - l2_cache_l1: l2-cache-l1 { - compatible = "cache"; - cache-size = <131072>; - cache-line-size = <64>; - cache-sets = <512>; - cache-level = <2>; - cache-unified; - next-level-cache = <&l3_cache>; - }; - - l2_cache_l2: l2-cache-l2 { - compatible = "cache"; - cache-size = <131072>; - cache-line-size = <64>; - cache-sets = <512>; - cache-level = <2>; - cache-unified; - next-level-cache = <&l3_cache>; - }; - - l2_cache_l3: l2-cache-l3 { - compatible = "cache"; - cache-size = <131072>; - cache-line-size = <64>; - cache-sets = <512>; - cache-level = <2>; - cache-unified; - next-level-cache = <&l3_cache>; - }; - - l2_cache_b0: l2-cache-b0 { - compatible = "cache"; - cache-size = <524288>; - cache-line-size = <64>; - cache-sets = <1024>; - cache-level = <2>; - cache-unified; - next-level-cache = <&l3_cache>; - }; - - l2_cache_b1: l2-cache-b1 { - compatible = "cache"; - cache-size = <524288>; - cache-line-size = <64>; - cache-sets = <1024>; - cache-level = <2>; - cache-unified; - next-level-cache = <&l3_cache>; - }; - - l2_cache_b2: l2-cache-b2 { - compatible = "cache"; - cache-size = <524288>; - cache-line-size = <64>; - cache-sets = <1024>; - cache-level = <2>; - cache-unified; - next-level-cache = <&l3_cache>; - }; - - l2_cache_b3: l2-cache-b3 { - compatible = "cache"; - cache-size = <524288>; - cache-line-size = <64>; - cache-sets = <1024>; - cache-level = <2>; - cache-unified; - next-level-cache = <&l3_cache>; - }; - - l3_cache: l3-cache { - compatible = "cache"; - cache-size = <3145728>; - cache-line-size = <64>; - cache-sets = <4096>; - cache-level = <3>; - cache-unified; - }; - }; - - display_subsystem: display-subsystem { - compatible = "rockchip,display-subsystem"; - ports = <&vop_out>; - }; - - firmware { - optee: optee { - compatible = "linaro,optee-tz"; - method = "smc"; - }; - - scmi: scmi { - compatible = "arm,scmi-smc"; - arm,smc-id = <0x82000010>; - shmem = <&scmi_shmem>; - #address-cells = <1>; - #size-cells = <0>; - - scmi_clk: protocol@14 { - reg = <0x14>; - #clock-cells = <1>; - }; - - scmi_reset: protocol@16 { - reg = <0x16>; - #reset-cells = <1>; - }; - }; - }; - - pmu-a55 { - compatible = "arm,cortex-a55-pmu"; - interrupts = ; - }; - - pmu-a76 { - compatible = "arm,cortex-a76-pmu"; - interrupts = ; - }; - - psci { - compatible = "arm,psci-1.0"; - method = "smc"; - }; - - spll: clock-0 { - compatible = "fixed-clock"; - clock-frequency = <702000000>; - clock-output-names = "spll"; - #clock-cells = <0>; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupts = , - , - , - , - ; - interrupt-names = "sec-phys", "phys", "virt", "hyp-phys", "hyp-virt"; - }; - - xin24m: clock-1 { - compatible = "fixed-clock"; - clock-frequency = <24000000>; - clock-output-names = "xin24m"; - #clock-cells = <0>; - }; - - xin32k: clock-2 { - compatible = "fixed-clock"; - clock-frequency = <32768>; - clock-output-names = "xin32k"; - #clock-cells = <0>; - }; - - pmu_sram: sram@10f000 { - compatible = "mmio-sram"; - reg = <0x0 0x0010f000 0x0 0x100>; - ranges = <0 0x0 0x0010f000 0x100>; - #address-cells = <1>; - #size-cells = <1>; - - scmi_shmem: sram@0 { - compatible = "arm,scmi-shmem"; - reg = <0x0 0x100>; - }; - }; - - gpu: gpu@fb000000 { - compatible = "rockchip,rk3588-mali", "arm,mali-valhall-csf"; - reg = <0x0 0xfb000000 0x0 0x200000>; - #cooling-cells = <2>; - assigned-clocks = <&scmi_clk SCMI_CLK_GPU>; - assigned-clock-rates = <200000000>; - clocks = <&cru CLK_GPU>, <&cru CLK_GPU_COREGROUP>, - <&cru CLK_GPU_STACKS>; - clock-names = "core", "coregroup", "stacks"; - dynamic-power-coefficient = <2982>; - interrupts = , - , - ; - interrupt-names = "job", "mmu", "gpu"; - power-domains = <&power RK3588_PD_GPU>; - status = "disabled"; - }; - - usb_host0_xhci: usb@fc000000 { - compatible = "rockchip,rk3588-dwc3", "snps,dwc3"; - reg = <0x0 0xfc000000 0x0 0x400000>; - interrupts = ; - clocks = <&cru REF_CLK_USB3OTG0>, <&cru SUSPEND_CLK_USB3OTG0>, - <&cru ACLK_USB3OTG0>; - clock-names = "ref_clk", "suspend_clk", "bus_clk"; - dr_mode = "otg"; - phys = <&u2phy0_otg>, <&usbdp_phy0 PHY_TYPE_USB3>; - phy-names = "usb2-phy", "usb3-phy"; - phy_type = "utmi_wide"; - power-domains = <&power RK3588_PD_USB>; - resets = <&cru SRST_A_USB3OTG0>; - snps,dis_enblslpm_quirk; - snps,dis-u1-entry-quirk; - snps,dis-u2-entry-quirk; - snps,dis-u2-freeclk-exists-quirk; - snps,dis-del-phy-power-chg-quirk; - snps,dis-tx-ipgap-linecheck-quirk; - status = "disabled"; - }; - - usb_host0_ehci: usb@fc800000 { - compatible = "rockchip,rk3588-ehci", "generic-ehci"; - reg = <0x0 0xfc800000 0x0 0x40000>; - interrupts = ; - clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST_ARB0>, <&cru ACLK_USB>, <&u2phy2>; - phys = <&u2phy2_host>; - phy-names = "usb"; - power-domains = <&power RK3588_PD_USB>; - status = "disabled"; - }; - - usb_host0_ohci: usb@fc840000 { - compatible = "rockchip,rk3588-ohci", "generic-ohci"; - reg = <0x0 0xfc840000 0x0 0x40000>; - interrupts = ; - clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST_ARB0>, <&cru ACLK_USB>, <&u2phy2>; - phys = <&u2phy2_host>; - phy-names = "usb"; - power-domains = <&power RK3588_PD_USB>; - status = "disabled"; - }; - - usb_host1_ehci: usb@fc880000 { - compatible = "rockchip,rk3588-ehci", "generic-ehci"; - reg = <0x0 0xfc880000 0x0 0x40000>; - interrupts = ; - clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST_ARB1>, <&cru ACLK_USB>, <&u2phy3>; - phys = <&u2phy3_host>; - phy-names = "usb"; - power-domains = <&power RK3588_PD_USB>; - status = "disabled"; - }; - - usb_host1_ohci: usb@fc8c0000 { - compatible = "rockchip,rk3588-ohci", "generic-ohci"; - reg = <0x0 0xfc8c0000 0x0 0x40000>; - interrupts = ; - clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST_ARB1>, <&cru ACLK_USB>, <&u2phy3>; - phys = <&u2phy3_host>; - phy-names = "usb"; - power-domains = <&power RK3588_PD_USB>; - status = "disabled"; - }; - - usb_host2_xhci: usb@fcd00000 { - compatible = "rockchip,rk3588-dwc3", "snps,dwc3"; - reg = <0x0 0xfcd00000 0x0 0x400000>; - interrupts = ; - clocks = <&cru REF_CLK_USB3OTG2>, <&cru SUSPEND_CLK_USB3OTG2>, - <&cru ACLK_USB3OTG2>, <&cru CLK_UTMI_OTG2>, - <&cru CLK_PIPEPHY2_PIPE_U3_G>; - clock-names = "ref_clk", "suspend_clk", "bus_clk", "utmi", "pipe"; - dr_mode = "host"; - phys = <&combphy2_psu PHY_TYPE_USB3>; - phy-names = "usb3-phy"; - phy_type = "utmi_wide"; - resets = <&cru SRST_A_USB3OTG2>; - snps,dis_enblslpm_quirk; - snps,dis-u2-freeclk-exists-quirk; - snps,dis-del-phy-power-chg-quirk; - snps,dis-tx-ipgap-linecheck-quirk; - snps,dis_rxdet_inp3_quirk; - status = "disabled"; - }; - - mmu600_pcie: iommu@fc900000 { - compatible = "arm,smmu-v3"; - reg = <0x0 0xfc900000 0x0 0x200000>; - interrupts = , - , - , - ; - interrupt-names = "eventq", "gerror", "priq", "cmdq-sync"; - #iommu-cells = <1>; - status = "disabled"; - }; - - mmu600_php: iommu@fcb00000 { - compatible = "arm,smmu-v3"; - reg = <0x0 0xfcb00000 0x0 0x200000>; - interrupts = , - , - , - ; - interrupt-names = "eventq", "gerror", "priq", "cmdq-sync"; - #iommu-cells = <1>; - status = "disabled"; - }; - - pmu1grf: syscon@fd58a000 { - compatible = "rockchip,rk3588-pmugrf", "syscon", "simple-mfd"; - reg = <0x0 0xfd58a000 0x0 0x10000>; - }; - - sys_grf: syscon@fd58c000 { - compatible = "rockchip,rk3588-sys-grf", "syscon"; - reg = <0x0 0xfd58c000 0x0 0x1000>; - }; - - vop_grf: syscon@fd5a4000 { - compatible = "rockchip,rk3588-vop-grf", "syscon"; - reg = <0x0 0xfd5a4000 0x0 0x2000>; - }; - - vo0_grf: syscon@fd5a6000 { - compatible = "rockchip,rk3588-vo0-grf", "syscon"; - reg = <0x0 0xfd5a6000 0x0 0x2000>; - clocks = <&cru PCLK_VO0GRF>; - }; - - vo1_grf: syscon@fd5a8000 { - compatible = "rockchip,rk3588-vo1-grf", "syscon"; - reg = <0x0 0xfd5a8000 0x0 0x4000>; - clocks = <&cru PCLK_VO1GRF>; - }; - - usb_grf: syscon@fd5ac000 { - compatible = "rockchip,rk3588-usb-grf", "syscon"; - reg = <0x0 0xfd5ac000 0x0 0x4000>; - }; - - php_grf: syscon@fd5b0000 { - compatible = "rockchip,rk3588-php-grf", "syscon"; - reg = <0x0 0xfd5b0000 0x0 0x1000>; - }; - - pipe_phy0_grf: syscon@fd5bc000 { - compatible = "rockchip,rk3588-pipe-phy-grf", "syscon"; - reg = <0x0 0xfd5bc000 0x0 0x100>; - }; - - pipe_phy2_grf: syscon@fd5c4000 { - compatible = "rockchip,rk3588-pipe-phy-grf", "syscon"; - reg = <0x0 0xfd5c4000 0x0 0x100>; - }; - - usbdpphy0_grf: syscon@fd5c8000 { - compatible = "rockchip,rk3588-usbdpphy-grf", "syscon"; - reg = <0x0 0xfd5c8000 0x0 0x4000>; - }; - - usb2phy0_grf: syscon@fd5d0000 { - compatible = "rockchip,rk3588-usb2phy-grf", "syscon", "simple-mfd"; - reg = <0x0 0xfd5d0000 0x0 0x4000>; - #address-cells = <1>; - #size-cells = <1>; - - u2phy0: usb2phy@0 { - compatible = "rockchip,rk3588-usb2phy"; - reg = <0x0 0x10>; - #clock-cells = <0>; - clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>; - clock-names = "phyclk"; - clock-output-names = "usb480m_phy0"; - interrupts = ; - resets = <&cru SRST_OTGPHY_U3_0>, <&cru SRST_P_USB2PHY_U3_0_GRF0>; - reset-names = "phy", "apb"; - status = "disabled"; - - u2phy0_otg: otg-port { - #phy-cells = <0>; - status = "disabled"; - }; - }; - }; - - usb2phy2_grf: syscon@fd5d8000 { - compatible = "rockchip,rk3588-usb2phy-grf", "syscon", "simple-mfd"; - reg = <0x0 0xfd5d8000 0x0 0x4000>; - #address-cells = <1>; - #size-cells = <1>; - - u2phy2: usb2phy@8000 { - compatible = "rockchip,rk3588-usb2phy"; - reg = <0x8000 0x10>; - #clock-cells = <0>; - clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>; - clock-names = "phyclk"; - clock-output-names = "usb480m_phy2"; - interrupts = ; - resets = <&cru SRST_OTGPHY_U2_0>, <&cru SRST_P_USB2PHY_U2_0_GRF0>; - reset-names = "phy", "apb"; - status = "disabled"; - - u2phy2_host: host-port { - #phy-cells = <0>; - status = "disabled"; - }; - }; - }; - - usb2phy3_grf: syscon@fd5dc000 { - compatible = "rockchip,rk3588-usb2phy-grf", "syscon", "simple-mfd"; - reg = <0x0 0xfd5dc000 0x0 0x4000>; - #address-cells = <1>; - #size-cells = <1>; - - u2phy3: usb2phy@c000 { - compatible = "rockchip,rk3588-usb2phy"; - reg = <0xc000 0x10>; - #clock-cells = <0>; - clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>; - clock-names = "phyclk"; - clock-output-names = "usb480m_phy3"; - interrupts = ; - resets = <&cru SRST_OTGPHY_U2_1>, <&cru SRST_P_USB2PHY_U2_1_GRF0>; - reset-names = "phy", "apb"; - status = "disabled"; - - u2phy3_host: host-port { - #phy-cells = <0>; - status = "disabled"; - }; - }; - }; - - hdptxphy0_grf: syscon@fd5e0000 { - compatible = "rockchip,rk3588-hdptxphy-grf", "syscon"; - reg = <0x0 0xfd5e0000 0x0 0x100>; - }; - - ioc: syscon@fd5f0000 { - compatible = "rockchip,rk3588-ioc", "syscon"; - reg = <0x0 0xfd5f0000 0x0 0x10000>; - }; - - system_sram1: sram@fd600000 { - compatible = "mmio-sram"; - reg = <0x0 0xfd600000 0x0 0x100000>; - ranges = <0x0 0x0 0xfd600000 0x100000>; - #address-cells = <1>; - #size-cells = <1>; - }; - - cru: clock-controller@fd7c0000 { - compatible = "rockchip,rk3588-cru"; - reg = <0x0 0xfd7c0000 0x0 0x5c000>; - assigned-clocks = - <&cru PLL_PPLL>, <&cru PLL_AUPLL>, - <&cru PLL_NPLL>, <&cru PLL_GPLL>, - <&cru ACLK_CENTER_ROOT>, - <&cru HCLK_CENTER_ROOT>, <&cru ACLK_CENTER_LOW_ROOT>, - <&cru ACLK_TOP_ROOT>, <&cru PCLK_TOP_ROOT>, - <&cru ACLK_LOW_TOP_ROOT>, <&cru PCLK_PMU0_ROOT>, - <&cru HCLK_PMU_CM0_ROOT>, <&cru ACLK_VOP>, - <&cru ACLK_BUS_ROOT>, <&cru CLK_150M_SRC>, - <&cru CLK_GPU>; - assigned-clock-rates = - <1100000000>, <786432000>, - <850000000>, <1188000000>, - <702000000>, - <400000000>, <500000000>, - <800000000>, <100000000>, - <400000000>, <100000000>, - <200000000>, <500000000>, - <375000000>, <150000000>, - <200000000>; - rockchip,grf = <&php_grf>; - #clock-cells = <1>; - #reset-cells = <1>; - }; - - i2c0: i2c@fd880000 { - compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; - reg = <0x0 0xfd880000 0x0 0x1000>; - interrupts = ; - clocks = <&cru CLK_I2C0>, <&cru PCLK_I2C0>; - clock-names = "i2c", "pclk"; - pinctrl-0 = <&i2c0m0_xfer>; - pinctrl-names = "default"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - uart0: serial@fd890000 { - compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; - reg = <0x0 0xfd890000 0x0 0x100>; - interrupts = ; - clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; - clock-names = "baudclk", "apb_pclk"; - dmas = <&dmac0 6>, <&dmac0 7>; - dma-names = "tx", "rx"; - pinctrl-0 = <&uart0m1_xfer>; - pinctrl-names = "default"; - reg-shift = <2>; - reg-io-width = <4>; - status = "disabled"; - }; - - pwm0: pwm@fd8b0000 { - compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; - reg = <0x0 0xfd8b0000 0x0 0x10>; - clocks = <&cru CLK_PMU1PWM>, <&cru PCLK_PMU1PWM>; - clock-names = "pwm", "pclk"; - pinctrl-0 = <&pwm0m0_pins>; - pinctrl-names = "default"; - #pwm-cells = <3>; - status = "disabled"; - }; - - pwm1: pwm@fd8b0010 { - compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; - reg = <0x0 0xfd8b0010 0x0 0x10>; - clocks = <&cru CLK_PMU1PWM>, <&cru PCLK_PMU1PWM>; - clock-names = "pwm", "pclk"; - pinctrl-0 = <&pwm1m0_pins>; - pinctrl-names = "default"; - #pwm-cells = <3>; - status = "disabled"; - }; - - pwm2: pwm@fd8b0020 { - compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; - reg = <0x0 0xfd8b0020 0x0 0x10>; - clocks = <&cru CLK_PMU1PWM>, <&cru PCLK_PMU1PWM>; - clock-names = "pwm", "pclk"; - pinctrl-0 = <&pwm2m0_pins>; - pinctrl-names = "default"; - #pwm-cells = <3>; - status = "disabled"; - }; - - pwm3: pwm@fd8b0030 { - compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; - reg = <0x0 0xfd8b0030 0x0 0x10>; - clocks = <&cru CLK_PMU1PWM>, <&cru PCLK_PMU1PWM>; - clock-names = "pwm", "pclk"; - pinctrl-0 = <&pwm3m0_pins>; - pinctrl-names = "default"; - #pwm-cells = <3>; - status = "disabled"; - }; - - pmu: power-management@fd8d8000 { - compatible = "rockchip,rk3588-pmu", "syscon", "simple-mfd"; - reg = <0x0 0xfd8d8000 0x0 0x400>; - - power: power-controller { - compatible = "rockchip,rk3588-power-controller"; - #address-cells = <1>; - #power-domain-cells = <1>; - #size-cells = <0>; - status = "okay"; - - /* These power domains are grouped by VD_NPU */ - power-domain@RK3588_PD_NPU { - reg = ; - #power-domain-cells = <0>; - #address-cells = <1>; - #size-cells = <0>; - - power-domain@RK3588_PD_NPUTOP { - reg = ; - clocks = <&cru HCLK_NPU_ROOT>, - <&cru PCLK_NPU_ROOT>, - <&cru CLK_NPU_DSU0>, - <&cru HCLK_NPU_CM0_ROOT>; - pm_qos = <&qos_npu0_mwr>, - <&qos_npu0_mro>, - <&qos_mcu_npu>; - #power-domain-cells = <0>; - #address-cells = <1>; - #size-cells = <0>; - - power-domain@RK3588_PD_NPU1 { - reg = ; - clocks = <&cru HCLK_NPU_ROOT>, - <&cru PCLK_NPU_ROOT>, - <&cru CLK_NPU_DSU0>; - pm_qos = <&qos_npu1>; - #power-domain-cells = <0>; - }; - power-domain@RK3588_PD_NPU2 { - reg = ; - clocks = <&cru HCLK_NPU_ROOT>, - <&cru PCLK_NPU_ROOT>, - <&cru CLK_NPU_DSU0>; - pm_qos = <&qos_npu2>; - #power-domain-cells = <0>; - }; - }; - }; - /* These power domains are grouped by VD_GPU */ - power-domain@RK3588_PD_GPU { - reg = ; - clocks = <&cru CLK_GPU>, - <&cru CLK_GPU_COREGROUP>, - <&cru CLK_GPU_STACKS>; - pm_qos = <&qos_gpu_m0>, - <&qos_gpu_m1>, - <&qos_gpu_m2>, - <&qos_gpu_m3>; - #power-domain-cells = <0>; - }; - /* These power domains are grouped by VD_VCODEC */ - power-domain@RK3588_PD_VCODEC { - reg = ; - #address-cells = <1>; - #size-cells = <0>; - #power-domain-cells = <0>; - - power-domain@RK3588_PD_RKVDEC0 { - reg = ; - clocks = <&cru HCLK_RKVDEC0>, - <&cru HCLK_VDPU_ROOT>, - <&cru ACLK_VDPU_ROOT>, - <&cru ACLK_RKVDEC0>, - <&cru ACLK_RKVDEC_CCU>; - pm_qos = <&qos_rkvdec0>; - #power-domain-cells = <0>; - }; - power-domain@RK3588_PD_RKVDEC1 { - reg = ; - clocks = <&cru HCLK_RKVDEC1>, - <&cru HCLK_VDPU_ROOT>, - <&cru ACLK_VDPU_ROOT>, - <&cru ACLK_RKVDEC1>; - pm_qos = <&qos_rkvdec1>; - #power-domain-cells = <0>; - }; - power-domain@RK3588_PD_VENC0 { - reg = ; - clocks = <&cru HCLK_RKVENC0>, - <&cru ACLK_RKVENC0>; - pm_qos = <&qos_rkvenc0_m0ro>, - <&qos_rkvenc0_m1ro>, - <&qos_rkvenc0_m2wo>; - #address-cells = <1>; - #size-cells = <0>; - #power-domain-cells = <0>; - - power-domain@RK3588_PD_VENC1 { - reg = ; - clocks = <&cru HCLK_RKVENC1>, - <&cru HCLK_RKVENC0>, - <&cru ACLK_RKVENC0>, - <&cru ACLK_RKVENC1>; - pm_qos = <&qos_rkvenc1_m0ro>, - <&qos_rkvenc1_m1ro>, - <&qos_rkvenc1_m2wo>; - #power-domain-cells = <0>; - }; - }; - }; - /* These power domains are grouped by VD_LOGIC */ - power-domain@RK3588_PD_VDPU { - reg = ; - clocks = <&cru HCLK_VDPU_ROOT>, - <&cru ACLK_VDPU_LOW_ROOT>, - <&cru ACLK_VDPU_ROOT>, - <&cru ACLK_JPEG_DECODER_ROOT>, - <&cru ACLK_IEP2P0>, - <&cru HCLK_IEP2P0>, - <&cru ACLK_JPEG_ENCODER0>, - <&cru HCLK_JPEG_ENCODER0>, - <&cru ACLK_JPEG_ENCODER1>, - <&cru HCLK_JPEG_ENCODER1>, - <&cru ACLK_JPEG_ENCODER2>, - <&cru HCLK_JPEG_ENCODER2>, - <&cru ACLK_JPEG_ENCODER3>, - <&cru HCLK_JPEG_ENCODER3>, - <&cru ACLK_JPEG_DECODER>, - <&cru HCLK_JPEG_DECODER>, - <&cru ACLK_RGA2>, - <&cru HCLK_RGA2>; - pm_qos = <&qos_iep>, - <&qos_jpeg_dec>, - <&qos_jpeg_enc0>, - <&qos_jpeg_enc1>, - <&qos_jpeg_enc2>, - <&qos_jpeg_enc3>, - <&qos_rga2_mro>, - <&qos_rga2_mwo>; - #address-cells = <1>; - #size-cells = <0>; - #power-domain-cells = <0>; - - - power-domain@RK3588_PD_AV1 { - reg = ; - clocks = <&cru PCLK_AV1>, - <&cru ACLK_AV1>, - <&cru HCLK_VDPU_ROOT>; - pm_qos = <&qos_av1>; - #power-domain-cells = <0>; - }; - power-domain@RK3588_PD_RKVDEC0 { - reg = ; - clocks = <&cru HCLK_RKVDEC0>, - <&cru HCLK_VDPU_ROOT>, - <&cru ACLK_VDPU_ROOT>, - <&cru ACLK_RKVDEC0>; - pm_qos = <&qos_rkvdec0>; - #power-domain-cells = <0>; - }; - power-domain@RK3588_PD_RKVDEC1 { - reg = ; - clocks = <&cru HCLK_RKVDEC1>, - <&cru HCLK_VDPU_ROOT>, - <&cru ACLK_VDPU_ROOT>; - pm_qos = <&qos_rkvdec1>; - #power-domain-cells = <0>; - }; - power-domain@RK3588_PD_RGA30 { - reg = ; - clocks = <&cru ACLK_RGA3_0>, - <&cru HCLK_RGA3_0>; - pm_qos = <&qos_rga3_0>; - #power-domain-cells = <0>; - }; - }; - power-domain@RK3588_PD_VOP { - reg = ; - clocks = <&cru PCLK_VOP_ROOT>, - <&cru HCLK_VOP_ROOT>, - <&cru ACLK_VOP>; - pm_qos = <&qos_vop_m0>, - <&qos_vop_m1>; - #address-cells = <1>; - #size-cells = <0>; - #power-domain-cells = <0>; - - power-domain@RK3588_PD_VO0 { - reg = ; - clocks = <&cru PCLK_VO0_ROOT>, - <&cru PCLK_VO0_S_ROOT>, - <&cru HCLK_VO0_S_ROOT>, - <&cru ACLK_VO0_ROOT>, - <&cru HCLK_HDCP0>, - <&cru ACLK_HDCP0>, - <&cru HCLK_VOP_ROOT>; - pm_qos = <&qos_hdcp0>; - #power-domain-cells = <0>; - }; - }; - power-domain@RK3588_PD_VO1 { - reg = ; - clocks = <&cru PCLK_VO1_ROOT>, - <&cru PCLK_VO1_S_ROOT>, - <&cru HCLK_VO1_S_ROOT>, - <&cru HCLK_HDCP1>, - <&cru ACLK_HDCP1>, - <&cru ACLK_HDMIRX_ROOT>, - <&cru HCLK_VO1USB_TOP_ROOT>; - pm_qos = <&qos_hdcp1>, - <&qos_hdmirx>; - #power-domain-cells = <0>; - }; - power-domain@RK3588_PD_VI { - reg = ; - clocks = <&cru HCLK_VI_ROOT>, - <&cru PCLK_VI_ROOT>, - <&cru HCLK_ISP0>, - <&cru ACLK_ISP0>, - <&cru HCLK_VICAP>, - <&cru ACLK_VICAP>; - pm_qos = <&qos_isp0_mro>, - <&qos_isp0_mwo>, - <&qos_vicap_m0>, - <&qos_vicap_m1>; - #address-cells = <1>; - #size-cells = <0>; - #power-domain-cells = <0>; - - power-domain@RK3588_PD_ISP1 { - reg = ; - clocks = <&cru HCLK_ISP1>, - <&cru ACLK_ISP1>, - <&cru HCLK_VI_ROOT>, - <&cru PCLK_VI_ROOT>; - pm_qos = <&qos_isp1_mwo>, - <&qos_isp1_mro>; - #power-domain-cells = <0>; - }; - power-domain@RK3588_PD_FEC { - reg = ; - clocks = <&cru HCLK_FISHEYE0>, - <&cru ACLK_FISHEYE0>, - <&cru HCLK_FISHEYE1>, - <&cru ACLK_FISHEYE1>, - <&cru PCLK_VI_ROOT>; - pm_qos = <&qos_fisheye0>, - <&qos_fisheye1>; - #power-domain-cells = <0>; - }; - }; - power-domain@RK3588_PD_RGA31 { - reg = ; - clocks = <&cru HCLK_RGA3_1>, - <&cru ACLK_RGA3_1>; - pm_qos = <&qos_rga3_1>; - #power-domain-cells = <0>; - }; - power-domain@RK3588_PD_USB { - reg = ; - clocks = <&cru PCLK_PHP_ROOT>, - <&cru ACLK_USB_ROOT>, - <&cru ACLK_USB>, - <&cru HCLK_USB_ROOT>, - <&cru HCLK_HOST0>, - <&cru HCLK_HOST_ARB0>, - <&cru HCLK_HOST1>, - <&cru HCLK_HOST_ARB1>; - pm_qos = <&qos_usb3_0>, - <&qos_usb3_1>, - <&qos_usb2host_0>, - <&qos_usb2host_1>; - #power-domain-cells = <0>; - }; - power-domain@RK3588_PD_GMAC { - reg = ; - clocks = <&cru PCLK_PHP_ROOT>, - <&cru ACLK_PCIE_ROOT>, - <&cru ACLK_PHP_ROOT>; - #power-domain-cells = <0>; - }; - power-domain@RK3588_PD_PCIE { - reg = ; - clocks = <&cru PCLK_PHP_ROOT>, - <&cru ACLK_PCIE_ROOT>, - <&cru ACLK_PHP_ROOT>; - #power-domain-cells = <0>; - }; - power-domain@RK3588_PD_SDIO { - reg = ; - clocks = <&cru HCLK_SDIO>, - <&cru HCLK_NVM_ROOT>; - pm_qos = <&qos_sdio>; - #power-domain-cells = <0>; - }; - power-domain@RK3588_PD_AUDIO { - reg = ; - clocks = <&cru HCLK_AUDIO_ROOT>, - <&cru PCLK_AUDIO_ROOT>; - #power-domain-cells = <0>; - }; - power-domain@RK3588_PD_SDMMC { - reg = ; - pm_qos = <&qos_sdmmc>; - #power-domain-cells = <0>; - }; - }; - }; - - vpu121: video-codec@fdb50000 { - compatible = "rockchip,rk3588-vpu121", "rockchip,rk3568-vpu"; - reg = <0x0 0xfdb50000 0x0 0x800>; - interrupts = ; - interrupt-names = "vdpu"; - clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>; - clock-names = "aclk", "hclk"; - iommus = <&vpu121_mmu>; - power-domains = <&power RK3588_PD_VDPU>; - }; - - vpu121_mmu: iommu@fdb50800 { - compatible = "rockchip,rk3588-iommu", "rockchip,rk3568-iommu"; - reg = <0x0 0xfdb50800 0x0 0x40>; - interrupts = ; - clock-names = "aclk", "iface"; - clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>; - power-domains = <&power RK3588_PD_VDPU>; - #iommu-cells = <0>; - }; - - rga: rga@fdb80000 { - compatible = "rockchip,rk3588-rga", "rockchip,rk3288-rga"; - reg = <0x0 0xfdb80000 0x0 0x180>; - interrupts = ; - clocks = <&cru ACLK_RGA2>, <&cru HCLK_RGA2>, <&cru CLK_RGA2_CORE>; - clock-names = "aclk", "hclk", "sclk"; - resets = <&cru SRST_RGA2_CORE>, <&cru SRST_A_RGA2>, <&cru SRST_H_RGA2>; - reset-names = "core", "axi", "ahb"; - power-domains = <&power RK3588_PD_VDPU>; - }; - - vepu121_0: video-codec@fdba0000 { - compatible = "rockchip,rk3588-vepu121"; - reg = <0x0 0xfdba0000 0x0 0x800>; - interrupts = ; - clocks = <&cru ACLK_JPEG_ENCODER0>, <&cru HCLK_JPEG_ENCODER0>; - clock-names = "aclk", "hclk"; - iommus = <&vepu121_0_mmu>; - power-domains = <&power RK3588_PD_VDPU>; - }; - - vepu121_0_mmu: iommu@fdba0800 { - compatible = "rockchip,rk3588-iommu", "rockchip,rk3568-iommu"; - reg = <0x0 0xfdba0800 0x0 0x40>; - interrupts = ; - clocks = <&cru ACLK_JPEG_ENCODER0>, <&cru HCLK_JPEG_ENCODER0>; - clock-names = "aclk", "iface"; - power-domains = <&power RK3588_PD_VDPU>; - #iommu-cells = <0>; - }; - - vepu121_1: video-codec@fdba4000 { - compatible = "rockchip,rk3588-vepu121"; - reg = <0x0 0xfdba4000 0x0 0x800>; - interrupts = ; - clocks = <&cru ACLK_JPEG_ENCODER1>, <&cru HCLK_JPEG_ENCODER1>; - clock-names = "aclk", "hclk"; - iommus = <&vepu121_1_mmu>; - power-domains = <&power RK3588_PD_VDPU>; - }; - - vepu121_1_mmu: iommu@fdba4800 { - compatible = "rockchip,rk3588-iommu", "rockchip,rk3568-iommu"; - reg = <0x0 0xfdba4800 0x0 0x40>; - interrupts = ; - clocks = <&cru ACLK_JPEG_ENCODER1>, <&cru HCLK_JPEG_ENCODER1>; - clock-names = "aclk", "iface"; - power-domains = <&power RK3588_PD_VDPU>; - #iommu-cells = <0>; - }; - - vepu121_2: video-codec@fdba8000 { - compatible = "rockchip,rk3588-vepu121"; - reg = <0x0 0xfdba8000 0x0 0x800>; - interrupts = ; - clocks = <&cru ACLK_JPEG_ENCODER2>, <&cru HCLK_JPEG_ENCODER2>; - clock-names = "aclk", "hclk"; - iommus = <&vepu121_2_mmu>; - power-domains = <&power RK3588_PD_VDPU>; - }; - - vepu121_2_mmu: iommu@fdba8800 { - compatible = "rockchip,rk3588-iommu", "rockchip,rk3568-iommu"; - reg = <0x0 0xfdba8800 0x0 0x40>; - interrupts = ; - clocks = <&cru ACLK_JPEG_ENCODER2>, <&cru HCLK_JPEG_ENCODER2>; - clock-names = "aclk", "iface"; - power-domains = <&power RK3588_PD_VDPU>; - #iommu-cells = <0>; - }; - - vepu121_3: video-codec@fdbac000 { - compatible = "rockchip,rk3588-vepu121"; - reg = <0x0 0xfdbac000 0x0 0x800>; - interrupts = ; - clocks = <&cru ACLK_JPEG_ENCODER3>, <&cru HCLK_JPEG_ENCODER3>; - clock-names = "aclk", "hclk"; - iommus = <&vepu121_3_mmu>; - power-domains = <&power RK3588_PD_VDPU>; - }; - - vepu121_3_mmu: iommu@fdbac800 { - compatible = "rockchip,rk3588-iommu", "rockchip,rk3568-iommu"; - reg = <0x0 0xfdbac800 0x0 0x40>; - interrupts = ; - clocks = <&cru ACLK_JPEG_ENCODER3>, <&cru HCLK_JPEG_ENCODER3>; - clock-names = "aclk", "iface"; - power-domains = <&power RK3588_PD_VDPU>; - #iommu-cells = <0>; - }; - - av1d: video-codec@fdc70000 { - compatible = "rockchip,rk3588-av1-vpu"; - reg = <0x0 0xfdc70000 0x0 0x800>; - interrupts = ; - interrupt-names = "vdpu"; - assigned-clocks = <&cru ACLK_AV1>, <&cru PCLK_AV1>; - assigned-clock-rates = <400000000>, <400000000>; - clocks = <&cru ACLK_AV1>, <&cru PCLK_AV1>; - clock-names = "aclk", "hclk"; - power-domains = <&power RK3588_PD_AV1>; - resets = <&cru SRST_A_AV1>, <&cru SRST_P_AV1>, <&cru SRST_A_AV1_BIU>, <&cru SRST_P_AV1_BIU>; - }; - - vop: vop@fdd90000 { - compatible = "rockchip,rk3588-vop"; - reg = <0x0 0xfdd90000 0x0 0x4200>, <0x0 0xfdd95000 0x0 0x1000>; - reg-names = "vop", "gamma-lut"; - interrupts = ; - clocks = <&cru ACLK_VOP>, - <&cru HCLK_VOP>, - <&cru DCLK_VOP0>, - <&cru DCLK_VOP1>, - <&cru DCLK_VOP2>, - <&cru DCLK_VOP3>, - <&cru PCLK_VOP_ROOT>; - clock-names = "aclk", - "hclk", - "dclk_vp0", - "dclk_vp1", - "dclk_vp2", - "dclk_vp3", - "pclk_vop"; - iommus = <&vop_mmu>; - power-domains = <&power RK3588_PD_VOP>; - rockchip,grf = <&sys_grf>; - rockchip,vop-grf = <&vop_grf>; - rockchip,vo1-grf = <&vo1_grf>; - rockchip,pmu = <&pmu>; - status = "disabled"; - - vop_out: ports { - #address-cells = <1>; - #size-cells = <0>; - - vp0: port@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - }; - - vp1: port@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - }; - - vp2: port@2 { - #address-cells = <1>; - #size-cells = <0>; - reg = <2>; - }; - - vp3: port@3 { - #address-cells = <1>; - #size-cells = <0>; - reg = <3>; - }; - }; - }; - - vop_mmu: iommu@fdd97e00 { - compatible = "rockchip,rk3588-iommu", "rockchip,rk3568-iommu"; - reg = <0x0 0xfdd97e00 0x0 0x100>, <0x0 0xfdd97f00 0x0 0x100>; - interrupts = ; - clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>; - clock-names = "aclk", "iface"; - #iommu-cells = <0>; - power-domains = <&power RK3588_PD_VOP>; - status = "disabled"; - }; - - i2s4_8ch: i2s@fddc0000 { - compatible = "rockchip,rk3588-i2s-tdm"; - reg = <0x0 0xfddc0000 0x0 0x1000>; - interrupts = ; - clocks = <&cru MCLK_I2S4_8CH_TX>, <&cru MCLK_I2S4_8CH_TX>, <&cru HCLK_I2S4_8CH>; - clock-names = "mclk_tx", "mclk_rx", "hclk"; - assigned-clocks = <&cru CLK_I2S4_8CH_TX_SRC>; - assigned-clock-parents = <&cru PLL_AUPLL>; - dmas = <&dmac2 0>; - dma-names = "tx"; - power-domains = <&power RK3588_PD_VO0>; - resets = <&cru SRST_M_I2S4_8CH_TX>; - reset-names = "tx-m"; - #sound-dai-cells = <0>; - status = "disabled"; - }; - - i2s5_8ch: i2s@fddf0000 { - compatible = "rockchip,rk3588-i2s-tdm"; - reg = <0x0 0xfddf0000 0x0 0x1000>; - interrupts = ; - clocks = <&cru MCLK_I2S5_8CH_TX>, <&cru MCLK_I2S5_8CH_TX>, <&cru HCLK_I2S5_8CH>; - clock-names = "mclk_tx", "mclk_rx", "hclk"; - assigned-clocks = <&cru CLK_I2S5_8CH_TX_SRC>; - assigned-clock-parents = <&cru PLL_AUPLL>; - dmas = <&dmac2 2>; - dma-names = "tx"; - power-domains = <&power RK3588_PD_VO1>; - resets = <&cru SRST_M_I2S5_8CH_TX>; - reset-names = "tx-m"; - #sound-dai-cells = <0>; - status = "disabled"; - }; - - i2s9_8ch: i2s@fddfc000 { - compatible = "rockchip,rk3588-i2s-tdm"; - reg = <0x0 0xfddfc000 0x0 0x1000>; - interrupts = ; - clocks = <&cru MCLK_I2S9_8CH_RX>, <&cru MCLK_I2S9_8CH_RX>, <&cru HCLK_I2S9_8CH>; - clock-names = "mclk_tx", "mclk_rx", "hclk"; - assigned-clocks = <&cru CLK_I2S9_8CH_RX_SRC>; - assigned-clock-parents = <&cru PLL_AUPLL>; - dmas = <&dmac2 23>; - dma-names = "rx"; - power-domains = <&power RK3588_PD_VO1>; - resets = <&cru SRST_M_I2S9_8CH_RX>; - reset-names = "rx-m"; - #sound-dai-cells = <0>; - status = "disabled"; - }; - - qos_gpu_m0: qos@fdf35000 { - compatible = "rockchip,rk3588-qos", "syscon"; - reg = <0x0 0xfdf35000 0x0 0x20>; - }; - - qos_gpu_m1: qos@fdf35200 { - compatible = "rockchip,rk3588-qos", "syscon"; - reg = <0x0 0xfdf35200 0x0 0x20>; - }; - - qos_gpu_m2: qos@fdf35400 { - compatible = "rockchip,rk3588-qos", "syscon"; - reg = <0x0 0xfdf35400 0x0 0x20>; - }; - - qos_gpu_m3: qos@fdf35600 { - compatible = "rockchip,rk3588-qos", "syscon"; - reg = <0x0 0xfdf35600 0x0 0x20>; - }; - - qos_rga3_1: qos@fdf36000 { - compatible = "rockchip,rk3588-qos", "syscon"; - reg = <0x0 0xfdf36000 0x0 0x20>; - }; - - qos_sdio: qos@fdf39000 { - compatible = "rockchip,rk3588-qos", "syscon"; - reg = <0x0 0xfdf39000 0x0 0x20>; - }; - - qos_sdmmc: qos@fdf3d800 { - compatible = "rockchip,rk3588-qos", "syscon"; - reg = <0x0 0xfdf3d800 0x0 0x20>; - }; - - qos_usb3_1: qos@fdf3e000 { - compatible = "rockchip,rk3588-qos", "syscon"; - reg = <0x0 0xfdf3e000 0x0 0x20>; - }; - - qos_usb3_0: qos@fdf3e200 { - compatible = "rockchip,rk3588-qos", "syscon"; - reg = <0x0 0xfdf3e200 0x0 0x20>; - }; - - qos_usb2host_0: qos@fdf3e400 { - compatible = "rockchip,rk3588-qos", "syscon"; - reg = <0x0 0xfdf3e400 0x0 0x20>; - }; - - qos_usb2host_1: qos@fdf3e600 { - compatible = "rockchip,rk3588-qos", "syscon"; - reg = <0x0 0xfdf3e600 0x0 0x20>; - }; - - qos_fisheye0: qos@fdf40000 { - compatible = "rockchip,rk3588-qos", "syscon"; - reg = <0x0 0xfdf40000 0x0 0x20>; - }; - - qos_fisheye1: qos@fdf40200 { - compatible = "rockchip,rk3588-qos", "syscon"; - reg = <0x0 0xfdf40200 0x0 0x20>; - }; - - qos_isp0_mro: qos@fdf40400 { - compatible = "rockchip,rk3588-qos", "syscon"; - reg = <0x0 0xfdf40400 0x0 0x20>; - }; - - qos_isp0_mwo: qos@fdf40500 { - compatible = "rockchip,rk3588-qos", "syscon"; - reg = <0x0 0xfdf40500 0x0 0x20>; - }; - - qos_vicap_m0: qos@fdf40600 { - compatible = "rockchip,rk3588-qos", "syscon"; - reg = <0x0 0xfdf40600 0x0 0x20>; - }; - - qos_vicap_m1: qos@fdf40800 { - compatible = "rockchip,rk3588-qos", "syscon"; - reg = <0x0 0xfdf40800 0x0 0x20>; - }; - - qos_isp1_mwo: qos@fdf41000 { - compatible = "rockchip,rk3588-qos", "syscon"; - reg = <0x0 0xfdf41000 0x0 0x20>; - }; - - qos_isp1_mro: qos@fdf41100 { - compatible = "rockchip,rk3588-qos", "syscon"; - reg = <0x0 0xfdf41100 0x0 0x20>; - }; - - qos_rkvenc0_m0ro: qos@fdf60000 { - compatible = "rockchip,rk3588-qos", "syscon"; - reg = <0x0 0xfdf60000 0x0 0x20>; - }; - - qos_rkvenc0_m1ro: qos@fdf60200 { - compatible = "rockchip,rk3588-qos", "syscon"; - reg = <0x0 0xfdf60200 0x0 0x20>; - }; - - qos_rkvenc0_m2wo: qos@fdf60400 { - compatible = "rockchip,rk3588-qos", "syscon"; - reg = <0x0 0xfdf60400 0x0 0x20>; - }; - - qos_rkvenc1_m0ro: qos@fdf61000 { - compatible = "rockchip,rk3588-qos", "syscon"; - reg = <0x0 0xfdf61000 0x0 0x20>; - }; - - qos_rkvenc1_m1ro: qos@fdf61200 { - compatible = "rockchip,rk3588-qos", "syscon"; - reg = <0x0 0xfdf61200 0x0 0x20>; - }; - - qos_rkvenc1_m2wo: qos@fdf61400 { - compatible = "rockchip,rk3588-qos", "syscon"; - reg = <0x0 0xfdf61400 0x0 0x20>; - }; - - qos_rkvdec0: qos@fdf62000 { - compatible = "rockchip,rk3588-qos", "syscon"; - reg = <0x0 0xfdf62000 0x0 0x20>; - }; - - qos_rkvdec1: qos@fdf63000 { - compatible = "rockchip,rk3588-qos", "syscon"; - reg = <0x0 0xfdf63000 0x0 0x20>; - }; - - qos_av1: qos@fdf64000 { - compatible = "rockchip,rk3588-qos", "syscon"; - reg = <0x0 0xfdf64000 0x0 0x20>; - }; - - qos_iep: qos@fdf66000 { - compatible = "rockchip,rk3588-qos", "syscon"; - reg = <0x0 0xfdf66000 0x0 0x20>; - }; - - qos_jpeg_dec: qos@fdf66200 { - compatible = "rockchip,rk3588-qos", "syscon"; - reg = <0x0 0xfdf66200 0x0 0x20>; - }; - - qos_jpeg_enc0: qos@fdf66400 { - compatible = "rockchip,rk3588-qos", "syscon"; - reg = <0x0 0xfdf66400 0x0 0x20>; - }; - - qos_jpeg_enc1: qos@fdf66600 { - compatible = "rockchip,rk3588-qos", "syscon"; - reg = <0x0 0xfdf66600 0x0 0x20>; - }; - - qos_jpeg_enc2: qos@fdf66800 { - compatible = "rockchip,rk3588-qos", "syscon"; - reg = <0x0 0xfdf66800 0x0 0x20>; - }; - - qos_jpeg_enc3: qos@fdf66a00 { - compatible = "rockchip,rk3588-qos", "syscon"; - reg = <0x0 0xfdf66a00 0x0 0x20>; - }; - - qos_rga2_mro: qos@fdf66c00 { - compatible = "rockchip,rk3588-qos", "syscon"; - reg = <0x0 0xfdf66c00 0x0 0x20>; - }; - - qos_rga2_mwo: qos@fdf66e00 { - compatible = "rockchip,rk3588-qos", "syscon"; - reg = <0x0 0xfdf66e00 0x0 0x20>; - }; - - qos_rga3_0: qos@fdf67000 { - compatible = "rockchip,rk3588-qos", "syscon"; - reg = <0x0 0xfdf67000 0x0 0x20>; - }; - - qos_vdpu: qos@fdf67200 { - compatible = "rockchip,rk3588-qos", "syscon"; - reg = <0x0 0xfdf67200 0x0 0x20>; - }; - - qos_npu1: qos@fdf70000 { - compatible = "rockchip,rk3588-qos", "syscon"; - reg = <0x0 0xfdf70000 0x0 0x20>; - }; - - qos_npu2: qos@fdf71000 { - compatible = "rockchip,rk3588-qos", "syscon"; - reg = <0x0 0xfdf71000 0x0 0x20>; - }; - - qos_npu0_mwr: qos@fdf72000 { - compatible = "rockchip,rk3588-qos", "syscon"; - reg = <0x0 0xfdf72000 0x0 0x20>; - }; - - qos_npu0_mro: qos@fdf72200 { - compatible = "rockchip,rk3588-qos", "syscon"; - reg = <0x0 0xfdf72200 0x0 0x20>; - }; - - qos_mcu_npu: qos@fdf72400 { - compatible = "rockchip,rk3588-qos", "syscon"; - reg = <0x0 0xfdf72400 0x0 0x20>; - }; - - qos_hdcp0: qos@fdf80000 { - compatible = "rockchip,rk3588-qos", "syscon"; - reg = <0x0 0xfdf80000 0x0 0x20>; - }; - - qos_hdcp1: qos@fdf81000 { - compatible = "rockchip,rk3588-qos", "syscon"; - reg = <0x0 0xfdf81000 0x0 0x20>; - }; - - qos_hdmirx: qos@fdf81200 { - compatible = "rockchip,rk3588-qos", "syscon"; - reg = <0x0 0xfdf81200 0x0 0x20>; - }; - - qos_vop_m0: qos@fdf82000 { - compatible = "rockchip,rk3588-qos", "syscon"; - reg = <0x0 0xfdf82000 0x0 0x20>; - }; - - qos_vop_m1: qos@fdf82200 { - compatible = "rockchip,rk3588-qos", "syscon"; - reg = <0x0 0xfdf82200 0x0 0x20>; - }; - - dfi: dfi@fe060000 { - reg = <0x00 0xfe060000 0x00 0x10000>; - compatible = "rockchip,rk3588-dfi"; - interrupts = , - , - , - ; - rockchip,pmu = <&pmu1grf>; - }; - - pcie2x1l1: pcie@fe180000 { - compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie"; - bus-range = <0x30 0x3f>; - clocks = <&cru ACLK_PCIE_1L1_MSTR>, <&cru ACLK_PCIE_1L1_SLV>, - <&cru ACLK_PCIE_1L1_DBI>, <&cru PCLK_PCIE_1L1>, - <&cru CLK_PCIE_AUX3>, <&cru CLK_PCIE1L1_PIPE>; - clock-names = "aclk_mst", "aclk_slv", - "aclk_dbi", "pclk", - "aux", "pipe"; - device_type = "pci"; - interrupts = , - , - , - , - ; - interrupt-names = "sys", "pmc", "msg", "legacy", "err"; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 7>; - interrupt-map = <0 0 0 1 &pcie2x1l1_intc 0>, - <0 0 0 2 &pcie2x1l1_intc 1>, - <0 0 0 3 &pcie2x1l1_intc 2>, - <0 0 0 4 &pcie2x1l1_intc 3>; - linux,pci-domain = <3>; - max-link-speed = <2>; - msi-map = <0x3000 &its0 0x3000 0x1000>; - num-lanes = <1>; - phys = <&combphy2_psu PHY_TYPE_PCIE>; - phy-names = "pcie-phy"; - power-domains = <&power RK3588_PD_PCIE>; - ranges = <0x01000000 0x0 0xf3100000 0x0 0xf3100000 0x0 0x00100000>, - <0x02000000 0x0 0xf3200000 0x0 0xf3200000 0x0 0x00e00000>, - <0x03000000 0x0 0x40000000 0x9 0xc0000000 0x0 0x40000000>; - reg = <0xa 0x40c00000 0x0 0x00400000>, - <0x0 0xfe180000 0x0 0x00010000>, - <0x0 0xf3000000 0x0 0x00100000>; - reg-names = "dbi", "apb", "config"; - resets = <&cru SRST_PCIE3_POWER_UP>, <&cru SRST_P_PCIE3>; - reset-names = "pwr", "pipe"; - #address-cells = <3>; - #size-cells = <2>; - status = "disabled"; - - pcie2x1l1_intc: legacy-interrupt-controller { - interrupt-controller; - #address-cells = <0>; - #interrupt-cells = <1>; - interrupt-parent = <&gic>; - interrupts = ; - }; - }; - - pcie2x1l2: pcie@fe190000 { - compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie"; - bus-range = <0x40 0x4f>; - clocks = <&cru ACLK_PCIE_1L2_MSTR>, <&cru ACLK_PCIE_1L2_SLV>, - <&cru ACLK_PCIE_1L2_DBI>, <&cru PCLK_PCIE_1L2>, - <&cru CLK_PCIE_AUX4>, <&cru CLK_PCIE1L2_PIPE>; - clock-names = "aclk_mst", "aclk_slv", - "aclk_dbi", "pclk", - "aux", "pipe"; - device_type = "pci"; - interrupts = , - , - , - , - ; - interrupt-names = "sys", "pmc", "msg", "legacy", "err"; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 7>; - interrupt-map = <0 0 0 1 &pcie2x1l2_intc 0>, - <0 0 0 2 &pcie2x1l2_intc 1>, - <0 0 0 3 &pcie2x1l2_intc 2>, - <0 0 0 4 &pcie2x1l2_intc 3>; - linux,pci-domain = <4>; - max-link-speed = <2>; - msi-map = <0x4000 &its0 0x4000 0x1000>; - num-lanes = <1>; - phys = <&combphy0_ps PHY_TYPE_PCIE>; - phy-names = "pcie-phy"; - power-domains = <&power RK3588_PD_PCIE>; - ranges = <0x01000000 0x0 0xf4100000 0x0 0xf4100000 0x0 0x00100000>, - <0x02000000 0x0 0xf4200000 0x0 0xf4200000 0x0 0x00e00000>, - <0x03000000 0x0 0x40000000 0xa 0x00000000 0x0 0x40000000>; - reg = <0xa 0x41000000 0x0 0x00400000>, - <0x0 0xfe190000 0x0 0x00010000>, - <0x0 0xf4000000 0x0 0x00100000>; - reg-names = "dbi", "apb", "config"; - resets = <&cru SRST_PCIE4_POWER_UP>, <&cru SRST_P_PCIE4>; - reset-names = "pwr", "pipe"; - #address-cells = <3>; - #size-cells = <2>; - status = "disabled"; - - pcie2x1l2_intc: legacy-interrupt-controller { - interrupt-controller; - #address-cells = <0>; - #interrupt-cells = <1>; - interrupt-parent = <&gic>; - interrupts = ; - }; - }; - - gmac1: ethernet@fe1c0000 { - compatible = "rockchip,rk3588-gmac", "snps,dwmac-4.20a"; - reg = <0x0 0xfe1c0000 0x0 0x10000>; - interrupts = , - ; - interrupt-names = "macirq", "eth_wake_irq"; - clocks = <&cru CLK_GMAC_125M>, <&cru CLK_GMAC_50M>, - <&cru PCLK_GMAC1>, <&cru ACLK_GMAC1>, - <&cru CLK_GMAC1_PTP_REF>; - clock-names = "stmmaceth", "clk_mac_ref", - "pclk_mac", "aclk_mac", - "ptp_ref"; - power-domains = <&power RK3588_PD_GMAC>; - resets = <&cru SRST_A_GMAC1>; - reset-names = "stmmaceth"; - rockchip,grf = <&sys_grf>; - rockchip,php-grf = <&php_grf>; - snps,axi-config = <&gmac1_stmmac_axi_setup>; - snps,mixed-burst; - snps,mtl-rx-config = <&gmac1_mtl_rx_setup>; - snps,mtl-tx-config = <&gmac1_mtl_tx_setup>; - snps,tso; - status = "disabled"; - - mdio1: mdio { - compatible = "snps,dwmac-mdio"; - #address-cells = <0x1>; - #size-cells = <0x0>; - }; - - gmac1_stmmac_axi_setup: stmmac-axi-config { - snps,blen = <0 0 0 0 16 8 4>; - snps,wr_osr_lmt = <4>; - snps,rd_osr_lmt = <8>; - }; - - gmac1_mtl_rx_setup: rx-queues-config { - snps,rx-queues-to-use = <2>; - queue0 {}; - queue1 {}; - }; - - gmac1_mtl_tx_setup: tx-queues-config { - snps,tx-queues-to-use = <2>; - queue0 {}; - queue1 {}; - }; - }; - - sata0: sata@fe210000 { - compatible = "rockchip,rk3588-dwc-ahci", "snps,dwc-ahci"; - reg = <0 0xfe210000 0 0x1000>; - interrupts = ; - clocks = <&cru ACLK_SATA0>, <&cru CLK_PMALIVE0>, - <&cru CLK_RXOOB0>, <&cru CLK_PIPEPHY0_REF>, - <&cru CLK_PIPEPHY0_PIPE_ASIC_G>; - clock-names = "sata", "pmalive", "rxoob", "ref", "asic"; - ports-implemented = <0x1>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - - sata-port@0 { - reg = <0>; - hba-port-cap = ; - phys = <&combphy0_ps PHY_TYPE_SATA>; - phy-names = "sata-phy"; - snps,rx-ts-max = <32>; - snps,tx-ts-max = <32>; - }; - }; - - sata2: sata@fe230000 { - compatible = "rockchip,rk3588-dwc-ahci", "snps,dwc-ahci"; - reg = <0 0xfe230000 0 0x1000>; - interrupts = ; - clocks = <&cru ACLK_SATA2>, <&cru CLK_PMALIVE2>, - <&cru CLK_RXOOB2>, <&cru CLK_PIPEPHY2_REF>, - <&cru CLK_PIPEPHY2_PIPE_ASIC_G>; - clock-names = "sata", "pmalive", "rxoob", "ref", "asic"; - ports-implemented = <0x1>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - - sata-port@0 { - reg = <0>; - hba-port-cap = ; - phys = <&combphy2_psu PHY_TYPE_SATA>; - phy-names = "sata-phy"; - snps,rx-ts-max = <32>; - snps,tx-ts-max = <32>; - }; - }; - - sfc: spi@fe2b0000 { - compatible = "rockchip,sfc"; - reg = <0x0 0xfe2b0000 0x0 0x4000>; - interrupts = ; - clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>; - clock-names = "clk_sfc", "hclk_sfc"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - sdmmc: mmc@fe2c0000 { - compatible = "rockchip,rk3588-dw-mshc", "rockchip,rk3288-dw-mshc"; - reg = <0x0 0xfe2c0000 0x0 0x4000>; - interrupts = ; - clocks = <&scmi_clk SCMI_HCLK_SD>, <&scmi_clk SCMI_CCLK_SD>, - <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; - clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; - fifo-depth = <0x100>; - max-frequency = <200000000>; - pinctrl-names = "default"; - pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_det &sdmmc_bus4>; - power-domains = <&power RK3588_PD_SDMMC>; - status = "disabled"; - }; - - sdio: mmc@fe2d0000 { - compatible = "rockchip,rk3588-dw-mshc", "rockchip,rk3288-dw-mshc"; - reg = <0x00 0xfe2d0000 0x00 0x4000>; - interrupts = ; - clocks = <&cru HCLK_SDIO>, <&cru CCLK_SRC_SDIO>, - <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>; - clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; - fifo-depth = <0x100>; - max-frequency = <200000000>; - pinctrl-names = "default"; - pinctrl-0 = <&sdiom1_pins>; - power-domains = <&power RK3588_PD_SDIO>; - status = "disabled"; - }; - - sdhci: mmc@fe2e0000 { - compatible = "rockchip,rk3588-dwcmshc"; - reg = <0x0 0xfe2e0000 0x0 0x10000>; - interrupts = ; - assigned-clocks = <&cru BCLK_EMMC>, <&cru TMCLK_EMMC>, <&cru CCLK_EMMC>; - assigned-clock-rates = <200000000>, <24000000>, <200000000>; - clocks = <&cru CCLK_EMMC>, <&cru HCLK_EMMC>, - <&cru ACLK_EMMC>, <&cru BCLK_EMMC>, - <&cru TMCLK_EMMC>; - clock-names = "core", "bus", "axi", "block", "timer"; - max-frequency = <200000000>; - pinctrl-0 = <&emmc_rstnout>, <&emmc_bus8>, <&emmc_clk>, - <&emmc_cmd>, <&emmc_data_strobe>; - pinctrl-names = "default"; - resets = <&cru SRST_C_EMMC>, <&cru SRST_H_EMMC>, - <&cru SRST_A_EMMC>, <&cru SRST_B_EMMC>, - <&cru SRST_T_EMMC>; - reset-names = "core", "bus", "axi", "block", "timer"; - status = "disabled"; - }; - - i2s0_8ch: i2s@fe470000 { - compatible = "rockchip,rk3588-i2s-tdm"; - reg = <0x0 0xfe470000 0x0 0x1000>; - interrupts = ; - clocks = <&cru MCLK_I2S0_8CH_TX>, <&cru MCLK_I2S0_8CH_RX>, <&cru HCLK_I2S0_8CH>; - clock-names = "mclk_tx", "mclk_rx", "hclk"; - assigned-clocks = <&cru CLK_I2S0_8CH_TX_SRC>, <&cru CLK_I2S0_8CH_RX_SRC>; - assigned-clock-parents = <&cru PLL_AUPLL>, <&cru PLL_AUPLL>; - dmas = <&dmac0 0>, <&dmac0 1>; - dma-names = "tx", "rx"; - power-domains = <&power RK3588_PD_AUDIO>; - resets = <&cru SRST_M_I2S0_8CH_TX>, <&cru SRST_M_I2S0_8CH_RX>; - reset-names = "tx-m", "rx-m"; - rockchip,trcm-sync-tx-only; - pinctrl-names = "default"; - pinctrl-0 = <&i2s0_lrck - &i2s0_sclk - &i2s0_sdi0 - &i2s0_sdi1 - &i2s0_sdi2 - &i2s0_sdi3 - &i2s0_sdo0 - &i2s0_sdo1 - &i2s0_sdo2 - &i2s0_sdo3>; - #sound-dai-cells = <0>; - status = "disabled"; - }; - - i2s1_8ch: i2s@fe480000 { - compatible = "rockchip,rk3588-i2s-tdm"; - reg = <0x0 0xfe480000 0x0 0x1000>; - interrupts = ; - clocks = <&cru MCLK_I2S1_8CH_TX>, <&cru MCLK_I2S1_8CH_RX>, <&cru HCLK_I2S1_8CH>; - clock-names = "mclk_tx", "mclk_rx", "hclk"; - dmas = <&dmac0 2>, <&dmac0 3>; - dma-names = "tx", "rx"; - resets = <&cru SRST_M_I2S1_8CH_TX>, <&cru SRST_M_I2S1_8CH_RX>; - reset-names = "tx-m", "rx-m"; - rockchip,trcm-sync-tx-only; - pinctrl-names = "default"; - pinctrl-0 = <&i2s1m0_lrck - &i2s1m0_sclk - &i2s1m0_sdi0 - &i2s1m0_sdi1 - &i2s1m0_sdi2 - &i2s1m0_sdi3 - &i2s1m0_sdo0 - &i2s1m0_sdo1 - &i2s1m0_sdo2 - &i2s1m0_sdo3>; - #sound-dai-cells = <0>; - status = "disabled"; - }; - - i2s2_2ch: i2s@fe490000 { - compatible = "rockchip,rk3588-i2s", "rockchip,rk3066-i2s"; - reg = <0x0 0xfe490000 0x0 0x1000>; - interrupts = ; - clocks = <&cru MCLK_I2S2_2CH>, <&cru HCLK_I2S2_2CH>; - clock-names = "i2s_clk", "i2s_hclk"; - assigned-clocks = <&cru CLK_I2S2_2CH_SRC>; - assigned-clock-parents = <&cru PLL_AUPLL>; - dmas = <&dmac1 0>, <&dmac1 1>; - dma-names = "tx", "rx"; - power-domains = <&power RK3588_PD_AUDIO>; - pinctrl-names = "default"; - pinctrl-0 = <&i2s2m1_lrck - &i2s2m1_sclk - &i2s2m1_sdi - &i2s2m1_sdo>; - #sound-dai-cells = <0>; - status = "disabled"; - }; - - i2s3_2ch: i2s@fe4a0000 { - compatible = "rockchip,rk3588-i2s", "rockchip,rk3066-i2s"; - reg = <0x0 0xfe4a0000 0x0 0x1000>; - interrupts = ; - clocks = <&cru MCLK_I2S3_2CH>, <&cru HCLK_I2S3_2CH>; - clock-names = "i2s_clk", "i2s_hclk"; - assigned-clocks = <&cru CLK_I2S3_2CH_SRC>; - assigned-clock-parents = <&cru PLL_AUPLL>; - dmas = <&dmac1 2>, <&dmac1 3>; - dma-names = "tx", "rx"; - power-domains = <&power RK3588_PD_AUDIO>; - pinctrl-names = "default"; - pinctrl-0 = <&i2s3_lrck - &i2s3_sclk - &i2s3_sdi - &i2s3_sdo>; - #sound-dai-cells = <0>; - status = "disabled"; - }; - - gic: interrupt-controller@fe600000 { - compatible = "arm,gic-v3"; - reg = <0x0 0xfe600000 0 0x10000>, /* GICD */ - <0x0 0xfe680000 0 0x100000>; /* GICR */ - interrupts = ; - interrupt-controller; - mbi-alias = <0x0 0xfe610000>; - mbi-ranges = <424 56>; - msi-controller; - ranges; - #address-cells = <2>; - #interrupt-cells = <4>; - #size-cells = <2>; - - its0: msi-controller@fe640000 { - compatible = "arm,gic-v3-its"; - reg = <0x0 0xfe640000 0x0 0x20000>; - msi-controller; - #msi-cells = <1>; - }; - - its1: msi-controller@fe660000 { - compatible = "arm,gic-v3-its"; - reg = <0x0 0xfe660000 0x0 0x20000>; - msi-controller; - #msi-cells = <1>; - }; - - ppi-partitions { - ppi_partition0: interrupt-partition-0 { - affinity = <&cpu_l0 &cpu_l1 &cpu_l2 &cpu_l3>; - }; - - ppi_partition1: interrupt-partition-1 { - affinity = <&cpu_b0 &cpu_b1 &cpu_b2 &cpu_b3>; - }; - }; - }; - - dmac0: dma-controller@fea10000 { - compatible = "arm,pl330", "arm,primecell"; - reg = <0x0 0xfea10000 0x0 0x4000>; - interrupts = , - ; - arm,pl330-periph-burst; - clocks = <&cru ACLK_DMAC0>; - clock-names = "apb_pclk"; - #dma-cells = <1>; - }; - - dmac1: dma-controller@fea30000 { - compatible = "arm,pl330", "arm,primecell"; - reg = <0x0 0xfea30000 0x0 0x4000>; - interrupts = , - ; - arm,pl330-periph-burst; - clocks = <&cru ACLK_DMAC1>; - clock-names = "apb_pclk"; - #dma-cells = <1>; - }; - - i2c1: i2c@fea90000 { - compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; - reg = <0x0 0xfea90000 0x0 0x1000>; - clocks = <&cru CLK_I2C1>, <&cru PCLK_I2C1>; - clock-names = "i2c", "pclk"; - interrupts = ; - pinctrl-0 = <&i2c1m0_xfer>; - pinctrl-names = "default"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c2: i2c@feaa0000 { - compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; - reg = <0x0 0xfeaa0000 0x0 0x1000>; - clocks = <&cru CLK_I2C2>, <&cru PCLK_I2C2>; - clock-names = "i2c", "pclk"; - interrupts = ; - pinctrl-0 = <&i2c2m0_xfer>; - pinctrl-names = "default"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c3: i2c@feab0000 { - compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; - reg = <0x0 0xfeab0000 0x0 0x1000>; - clocks = <&cru CLK_I2C3>, <&cru PCLK_I2C3>; - clock-names = "i2c", "pclk"; - interrupts = ; - pinctrl-0 = <&i2c3m0_xfer>; - pinctrl-names = "default"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c4: i2c@feac0000 { - compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; - reg = <0x0 0xfeac0000 0x0 0x1000>; - clocks = <&cru CLK_I2C4>, <&cru PCLK_I2C4>; - clock-names = "i2c", "pclk"; - interrupts = ; - pinctrl-0 = <&i2c4m0_xfer>; - pinctrl-names = "default"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c5: i2c@fead0000 { - compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; - reg = <0x0 0xfead0000 0x0 0x1000>; - clocks = <&cru CLK_I2C5>, <&cru PCLK_I2C5>; - clock-names = "i2c", "pclk"; - interrupts = ; - pinctrl-0 = <&i2c5m0_xfer>; - pinctrl-names = "default"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - timer0: timer@feae0000 { - compatible = "rockchip,rk3588-timer", "rockchip,rk3288-timer"; - reg = <0x0 0xfeae0000 0x0 0x20>; - interrupts = ; - clocks = <&cru PCLK_BUSTIMER0>, <&cru CLK_BUSTIMER0>; - clock-names = "pclk", "timer"; - }; - - wdt: watchdog@feaf0000 { - compatible = "rockchip,rk3588-wdt", "snps,dw-wdt"; - reg = <0x0 0xfeaf0000 0x0 0x100>; - clocks = <&cru TCLK_WDT0>, <&cru PCLK_WDT0>; - clock-names = "tclk", "pclk"; - interrupts = ; - }; - - spi0: spi@feb00000 { - compatible = "rockchip,rk3588-spi", "rockchip,rk3066-spi"; - reg = <0x0 0xfeb00000 0x0 0x1000>; - interrupts = ; - clocks = <&cru CLK_SPI0>, <&cru PCLK_SPI0>; - clock-names = "spiclk", "apb_pclk"; - dmas = <&dmac0 14>, <&dmac0 15>; - dma-names = "tx", "rx"; - num-cs = <2>; - pinctrl-0 = <&spi0m0_cs0 &spi0m0_cs1 &spi0m0_pins>; - pinctrl-names = "default"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi1: spi@feb10000 { - compatible = "rockchip,rk3588-spi", "rockchip,rk3066-spi"; - reg = <0x0 0xfeb10000 0x0 0x1000>; - interrupts = ; - clocks = <&cru CLK_SPI1>, <&cru PCLK_SPI1>; - clock-names = "spiclk", "apb_pclk"; - dmas = <&dmac0 16>, <&dmac0 17>; - dma-names = "tx", "rx"; - num-cs = <2>; - pinctrl-0 = <&spi1m1_cs0 &spi1m1_cs1 &spi1m1_pins>; - pinctrl-names = "default"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi2: spi@feb20000 { - compatible = "rockchip,rk3588-spi", "rockchip,rk3066-spi"; - reg = <0x0 0xfeb20000 0x0 0x1000>; - interrupts = ; - clocks = <&cru CLK_SPI2>, <&cru PCLK_SPI2>; - clock-names = "spiclk", "apb_pclk"; - dmas = <&dmac1 15>, <&dmac1 16>; - dma-names = "tx", "rx"; - num-cs = <2>; - pinctrl-0 = <&spi2m2_cs0 &spi2m2_cs1 &spi2m2_pins>; - pinctrl-names = "default"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi3: spi@feb30000 { - compatible = "rockchip,rk3588-spi", "rockchip,rk3066-spi"; - reg = <0x0 0xfeb30000 0x0 0x1000>; - interrupts = ; - clocks = <&cru CLK_SPI3>, <&cru PCLK_SPI3>; - clock-names = "spiclk", "apb_pclk"; - dmas = <&dmac1 17>, <&dmac1 18>; - dma-names = "tx", "rx"; - num-cs = <2>; - pinctrl-0 = <&spi3m1_cs0 &spi3m1_cs1 &spi3m1_pins>; - pinctrl-names = "default"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - uart1: serial@feb40000 { - compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; - reg = <0x0 0xfeb40000 0x0 0x100>; - interrupts = ; - clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; - clock-names = "baudclk", "apb_pclk"; - dmas = <&dmac0 8>, <&dmac0 9>; - dma-names = "tx", "rx"; - pinctrl-0 = <&uart1m1_xfer>; - pinctrl-names = "default"; - reg-io-width = <4>; - reg-shift = <2>; - status = "disabled"; - }; - - uart2: serial@feb50000 { - compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; - reg = <0x0 0xfeb50000 0x0 0x100>; - interrupts = ; - clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; - clock-names = "baudclk", "apb_pclk"; - dmas = <&dmac0 10>, <&dmac0 11>; - dma-names = "tx", "rx"; - pinctrl-0 = <&uart2m1_xfer>; - pinctrl-names = "default"; - reg-io-width = <4>; - reg-shift = <2>; - status = "disabled"; - }; - - uart3: serial@feb60000 { - compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; - reg = <0x0 0xfeb60000 0x0 0x100>; - interrupts = ; - clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; - clock-names = "baudclk", "apb_pclk"; - dmas = <&dmac0 12>, <&dmac0 13>; - dma-names = "tx", "rx"; - pinctrl-0 = <&uart3m1_xfer>; - pinctrl-names = "default"; - reg-io-width = <4>; - reg-shift = <2>; - status = "disabled"; - }; - - uart4: serial@feb70000 { - compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; - reg = <0x0 0xfeb70000 0x0 0x100>; - interrupts = ; - clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>; - clock-names = "baudclk", "apb_pclk"; - dmas = <&dmac1 9>, <&dmac1 10>; - dma-names = "tx", "rx"; - pinctrl-0 = <&uart4m1_xfer>; - pinctrl-names = "default"; - reg-io-width = <4>; - reg-shift = <2>; - status = "disabled"; - }; - - uart5: serial@feb80000 { - compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; - reg = <0x0 0xfeb80000 0x0 0x100>; - interrupts = ; - clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>; - clock-names = "baudclk", "apb_pclk"; - dmas = <&dmac1 11>, <&dmac1 12>; - dma-names = "tx", "rx"; - pinctrl-0 = <&uart5m1_xfer>; - pinctrl-names = "default"; - reg-io-width = <4>; - reg-shift = <2>; - status = "disabled"; - }; - - uart6: serial@feb90000 { - compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; - reg = <0x0 0xfeb90000 0x0 0x100>; - interrupts = ; - clocks = <&cru SCLK_UART6>, <&cru PCLK_UART6>; - clock-names = "baudclk", "apb_pclk"; - dmas = <&dmac1 13>, <&dmac1 14>; - dma-names = "tx", "rx"; - pinctrl-0 = <&uart6m1_xfer>; - pinctrl-names = "default"; - reg-io-width = <4>; - reg-shift = <2>; - status = "disabled"; - }; - - uart7: serial@feba0000 { - compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; - reg = <0x0 0xfeba0000 0x0 0x100>; - interrupts = ; - clocks = <&cru SCLK_UART7>, <&cru PCLK_UART7>; - clock-names = "baudclk", "apb_pclk"; - dmas = <&dmac2 7>, <&dmac2 8>; - dma-names = "tx", "rx"; - pinctrl-0 = <&uart7m1_xfer>; - pinctrl-names = "default"; - reg-io-width = <4>; - reg-shift = <2>; - status = "disabled"; - }; - - uart8: serial@febb0000 { - compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; - reg = <0x0 0xfebb0000 0x0 0x100>; - interrupts = ; - clocks = <&cru SCLK_UART8>, <&cru PCLK_UART8>; - clock-names = "baudclk", "apb_pclk"; - dmas = <&dmac2 9>, <&dmac2 10>; - dma-names = "tx", "rx"; - pinctrl-0 = <&uart8m1_xfer>; - pinctrl-names = "default"; - reg-io-width = <4>; - reg-shift = <2>; - status = "disabled"; - }; - - uart9: serial@febc0000 { - compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; - reg = <0x0 0xfebc0000 0x0 0x100>; - interrupts = ; - clocks = <&cru SCLK_UART9>, <&cru PCLK_UART9>; - clock-names = "baudclk", "apb_pclk"; - dmas = <&dmac2 11>, <&dmac2 12>; - dma-names = "tx", "rx"; - pinctrl-0 = <&uart9m1_xfer>; - pinctrl-names = "default"; - reg-io-width = <4>; - reg-shift = <2>; - status = "disabled"; - }; - - pwm4: pwm@febd0000 { - compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; - reg = <0x0 0xfebd0000 0x0 0x10>; - clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; - clock-names = "pwm", "pclk"; - pinctrl-0 = <&pwm4m0_pins>; - pinctrl-names = "default"; - #pwm-cells = <3>; - status = "disabled"; - }; - - pwm5: pwm@febd0010 { - compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; - reg = <0x0 0xfebd0010 0x0 0x10>; - clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; - clock-names = "pwm", "pclk"; - pinctrl-0 = <&pwm5m0_pins>; - pinctrl-names = "default"; - #pwm-cells = <3>; - status = "disabled"; - }; - - pwm6: pwm@febd0020 { - compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; - reg = <0x0 0xfebd0020 0x0 0x10>; - clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; - clock-names = "pwm", "pclk"; - pinctrl-0 = <&pwm6m0_pins>; - pinctrl-names = "default"; - #pwm-cells = <3>; - status = "disabled"; - }; - - pwm7: pwm@febd0030 { - compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; - reg = <0x0 0xfebd0030 0x0 0x10>; - clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; - clock-names = "pwm", "pclk"; - pinctrl-0 = <&pwm7m0_pins>; - pinctrl-names = "default"; - #pwm-cells = <3>; - status = "disabled"; - }; - - pwm8: pwm@febe0000 { - compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; - reg = <0x0 0xfebe0000 0x0 0x10>; - clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; - clock-names = "pwm", "pclk"; - pinctrl-0 = <&pwm8m0_pins>; - pinctrl-names = "default"; - #pwm-cells = <3>; - status = "disabled"; - }; - - pwm9: pwm@febe0010 { - compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; - reg = <0x0 0xfebe0010 0x0 0x10>; - clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; - clock-names = "pwm", "pclk"; - pinctrl-0 = <&pwm9m0_pins>; - pinctrl-names = "default"; - #pwm-cells = <3>; - status = "disabled"; - }; - - pwm10: pwm@febe0020 { - compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; - reg = <0x0 0xfebe0020 0x0 0x10>; - clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; - clock-names = "pwm", "pclk"; - pinctrl-0 = <&pwm10m0_pins>; - pinctrl-names = "default"; - #pwm-cells = <3>; - status = "disabled"; - }; - - pwm11: pwm@febe0030 { - compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; - reg = <0x0 0xfebe0030 0x0 0x10>; - clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; - clock-names = "pwm", "pclk"; - pinctrl-0 = <&pwm11m0_pins>; - pinctrl-names = "default"; - #pwm-cells = <3>; - status = "disabled"; - }; - - pwm12: pwm@febf0000 { - compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; - reg = <0x0 0xfebf0000 0x0 0x10>; - clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>; - clock-names = "pwm", "pclk"; - pinctrl-0 = <&pwm12m0_pins>; - pinctrl-names = "default"; - #pwm-cells = <3>; - status = "disabled"; - }; - - pwm13: pwm@febf0010 { - compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; - reg = <0x0 0xfebf0010 0x0 0x10>; - clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>; - clock-names = "pwm", "pclk"; - pinctrl-0 = <&pwm13m0_pins>; - pinctrl-names = "default"; - #pwm-cells = <3>; - status = "disabled"; - }; - - pwm14: pwm@febf0020 { - compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; - reg = <0x0 0xfebf0020 0x0 0x10>; - clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>; - clock-names = "pwm", "pclk"; - pinctrl-0 = <&pwm14m0_pins>; - pinctrl-names = "default"; - #pwm-cells = <3>; - status = "disabled"; - }; - - pwm15: pwm@febf0030 { - compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; - reg = <0x0 0xfebf0030 0x0 0x10>; - clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>; - clock-names = "pwm", "pclk"; - pinctrl-0 = <&pwm15m0_pins>; - pinctrl-names = "default"; - #pwm-cells = <3>; - status = "disabled"; - }; - - thermal_zones: thermal-zones { - /* sensor near the center of the SoC */ - package_thermal: package-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsadc 0>; - - trips { - package_crit: package-crit { - temperature = <115000>; - hysteresis = <0>; - type = "critical"; - }; - }; - }; - - /* sensor between A76 cores 0 and 1 */ - bigcore0_thermal: bigcore0-thermal { - polling-delay-passive = <100>; - polling-delay = <0>; - thermal-sensors = <&tsadc 1>; - - trips { - bigcore0_alert: bigcore0-alert { - temperature = <85000>; - hysteresis = <2000>; - type = "passive"; - }; - - bigcore0_crit: bigcore0-crit { - temperature = <115000>; - hysteresis = <0>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&bigcore0_alert>; - cooling-device = - <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu_b1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - - /* sensor between A76 cores 2 and 3 */ - bigcore2_thermal: bigcore2-thermal { - polling-delay-passive = <100>; - polling-delay = <0>; - thermal-sensors = <&tsadc 2>; - - trips { - bigcore2_alert: bigcore2-alert { - temperature = <85000>; - hysteresis = <2000>; - type = "passive"; - }; - - bigcore2_crit: bigcore2-crit { - temperature = <115000>; - hysteresis = <0>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&bigcore2_alert>; - cooling-device = - <&cpu_b2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu_b3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - - /* sensor between the four A55 cores */ - little_core_thermal: littlecore-thermal { - polling-delay-passive = <100>; - polling-delay = <0>; - thermal-sensors = <&tsadc 3>; - - trips { - littlecore_alert: littlecore-alert { - temperature = <85000>; - hysteresis = <2000>; - type = "passive"; - }; - - littlecore_crit: littlecore-crit { - temperature = <115000>; - hysteresis = <0>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&littlecore_alert>; - cooling-device = - <&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu_l1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu_l2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu_l3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - - /* sensor near the PD_CENTER power domain */ - center_thermal: center-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsadc 4>; - - trips { - center_crit: center-crit { - temperature = <115000>; - hysteresis = <0>; - type = "critical"; - }; - }; - }; - - gpu_thermal: gpu-thermal { - polling-delay-passive = <100>; - polling-delay = <0>; - thermal-sensors = <&tsadc 5>; - - trips { - gpu_alert: gpu-alert { - temperature = <85000>; - hysteresis = <2000>; - type = "passive"; - }; - - gpu_crit: gpu-crit { - temperature = <115000>; - hysteresis = <0>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&gpu_alert>; - cooling-device = - <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - - npu_thermal: npu-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsadc 6>; - - trips { - npu_crit: npu-crit { - temperature = <115000>; - hysteresis = <0>; - type = "critical"; - }; - }; - }; - }; - - tsadc: tsadc@fec00000 { - compatible = "rockchip,rk3588-tsadc"; - reg = <0x0 0xfec00000 0x0 0x400>; - interrupts = ; - clocks = <&cru CLK_TSADC>, <&cru PCLK_TSADC>; - clock-names = "tsadc", "apb_pclk"; - assigned-clocks = <&cru CLK_TSADC>; - assigned-clock-rates = <2000000>; - resets = <&cru SRST_P_TSADC>, <&cru SRST_TSADC>; - reset-names = "tsadc-apb", "tsadc"; - rockchip,hw-tshut-temp = <120000>; - rockchip,hw-tshut-mode = <0>; /* tshut mode 0:CRU 1:GPIO */ - rockchip,hw-tshut-polarity = <0>; /* tshut polarity 0:LOW 1:HIGH */ - pinctrl-0 = <&tsadc_gpio_func>; - pinctrl-1 = <&tsadc_shut>; - pinctrl-names = "gpio", "otpout"; - #thermal-sensor-cells = <1>; - status = "disabled"; - }; - - saradc: adc@fec10000 { - compatible = "rockchip,rk3588-saradc"; - reg = <0x0 0xfec10000 0x0 0x10000>; - interrupts = ; - #io-channel-cells = <1>; - clocks = <&cru CLK_SARADC>, <&cru PCLK_SARADC>; - clock-names = "saradc", "apb_pclk"; - resets = <&cru SRST_P_SARADC>; - reset-names = "saradc-apb"; - status = "disabled"; - }; - - i2c6: i2c@fec80000 { - compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; - reg = <0x0 0xfec80000 0x0 0x1000>; - clocks = <&cru CLK_I2C6>, <&cru PCLK_I2C6>; - clock-names = "i2c", "pclk"; - interrupts = ; - pinctrl-0 = <&i2c6m0_xfer>; - pinctrl-names = "default"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c7: i2c@fec90000 { - compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; - reg = <0x0 0xfec90000 0x0 0x1000>; - clocks = <&cru CLK_I2C7>, <&cru PCLK_I2C7>; - clock-names = "i2c", "pclk"; - interrupts = ; - pinctrl-0 = <&i2c7m0_xfer>; - pinctrl-names = "default"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c8: i2c@feca0000 { - compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; - reg = <0x0 0xfeca0000 0x0 0x1000>; - clocks = <&cru CLK_I2C8>, <&cru PCLK_I2C8>; - clock-names = "i2c", "pclk"; - interrupts = ; - pinctrl-0 = <&i2c8m0_xfer>; - pinctrl-names = "default"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi4: spi@fecb0000 { - compatible = "rockchip,rk3588-spi", "rockchip,rk3066-spi"; - reg = <0x0 0xfecb0000 0x0 0x1000>; - interrupts = ; - clocks = <&cru CLK_SPI4>, <&cru PCLK_SPI4>; - clock-names = "spiclk", "apb_pclk"; - dmas = <&dmac2 13>, <&dmac2 14>; - dma-names = "tx", "rx"; - num-cs = <2>; - pinctrl-0 = <&spi4m0_cs0 &spi4m0_cs1 &spi4m0_pins>; - pinctrl-names = "default"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - otp: efuse@fecc0000 { - compatible = "rockchip,rk3588-otp"; - reg = <0x0 0xfecc0000 0x0 0x400>; - clocks = <&cru CLK_OTPC_NS>, <&cru PCLK_OTPC_NS>, - <&cru CLK_OTP_PHY_G>, <&cru CLK_OTPC_ARB>; - clock-names = "otp", "apb_pclk", "phy", "arb"; - resets = <&cru SRST_OTPC_NS>, <&cru SRST_P_OTPC_NS>, - <&cru SRST_OTPC_ARB>; - reset-names = "otp", "apb", "arb"; - #address-cells = <1>; - #size-cells = <1>; - - cpu_code: cpu-code@2 { - reg = <0x02 0x2>; - }; - - otp_id: id@7 { - reg = <0x07 0x10>; - }; - - cpub0_leakage: cpu-leakage@17 { - reg = <0x17 0x1>; - }; - - cpub1_leakage: cpu-leakage@18 { - reg = <0x18 0x1>; - }; - - cpul_leakage: cpu-leakage@19 { - reg = <0x19 0x1>; - }; - - log_leakage: log-leakage@1a { - reg = <0x1a 0x1>; - }; - - gpu_leakage: gpu-leakage@1b { - reg = <0x1b 0x1>; - }; - - otp_cpu_version: cpu-version@1c { - reg = <0x1c 0x1>; - bits = <3 3>; - }; - - npu_leakage: npu-leakage@28 { - reg = <0x28 0x1>; - }; - - codec_leakage: codec-leakage@29 { - reg = <0x29 0x1>; - }; - }; - - dmac2: dma-controller@fed10000 { - compatible = "arm,pl330", "arm,primecell"; - reg = <0x0 0xfed10000 0x0 0x4000>; - interrupts = , - ; - arm,pl330-periph-burst; - clocks = <&cru ACLK_DMAC2>; - clock-names = "apb_pclk"; - #dma-cells = <1>; - }; - - hdptxphy_hdmi0: phy@fed60000 { - compatible = "rockchip,rk3588-hdptx-phy"; - reg = <0x0 0xfed60000 0x0 0x2000>; - clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>, <&cru PCLK_HDPTX0>; - clock-names = "ref", "apb"; - #phy-cells = <0>; - resets = <&cru SRST_HDPTX0>, <&cru SRST_P_HDPTX0>, - <&cru SRST_HDPTX0_INIT>, <&cru SRST_HDPTX0_CMN>, - <&cru SRST_HDPTX0_LANE>, <&cru SRST_HDPTX0_ROPLL>, - <&cru SRST_HDPTX0_LCPLL>; - reset-names = "phy", "apb", "init", "cmn", "lane", "ropll", - "lcpll"; - rockchip,grf = <&hdptxphy0_grf>; - status = "disabled"; - }; - - usbdp_phy0: phy@fed80000 { - compatible = "rockchip,rk3588-usbdp-phy"; - reg = <0x0 0xfed80000 0x0 0x10000>; - #phy-cells = <1>; - clocks = <&cru CLK_USBDPPHY_MIPIDCPPHY_REF>, - <&cru CLK_USBDP_PHY0_IMMORTAL>, - <&cru PCLK_USBDPPHY0>, - <&u2phy0>; - clock-names = "refclk", "immortal", "pclk", "utmi"; - resets = <&cru SRST_USBDP_COMBO_PHY0_INIT>, - <&cru SRST_USBDP_COMBO_PHY0_CMN>, - <&cru SRST_USBDP_COMBO_PHY0_LANE>, - <&cru SRST_USBDP_COMBO_PHY0_PCS>, - <&cru SRST_P_USBDPPHY0>; - reset-names = "init", "cmn", "lane", "pcs_apb", "pma_apb"; - rockchip,u2phy-grf = <&usb2phy0_grf>; - rockchip,usb-grf = <&usb_grf>; - rockchip,usbdpphy-grf = <&usbdpphy0_grf>; - rockchip,vo-grf = <&vo0_grf>; - status = "disabled"; - }; - - combphy0_ps: phy@fee00000 { - compatible = "rockchip,rk3588-naneng-combphy"; - reg = <0x0 0xfee00000 0x0 0x100>; - clocks = <&cru CLK_REF_PIPE_PHY0>, <&cru PCLK_PCIE_COMBO_PIPE_PHY0>, - <&cru PCLK_PHP_ROOT>; - clock-names = "ref", "apb", "pipe"; - assigned-clocks = <&cru CLK_REF_PIPE_PHY0>; - assigned-clock-rates = <100000000>; - #phy-cells = <1>; - resets = <&cru SRST_REF_PIPE_PHY0>, <&cru SRST_P_PCIE2_PHY0>; - reset-names = "phy", "apb"; - rockchip,pipe-grf = <&php_grf>; - rockchip,pipe-phy-grf = <&pipe_phy0_grf>; - status = "disabled"; - }; - - combphy2_psu: phy@fee20000 { - compatible = "rockchip,rk3588-naneng-combphy"; - reg = <0x0 0xfee20000 0x0 0x100>; - clocks = <&cru CLK_REF_PIPE_PHY2>, <&cru PCLK_PCIE_COMBO_PIPE_PHY2>, - <&cru PCLK_PHP_ROOT>; - clock-names = "ref", "apb", "pipe"; - assigned-clocks = <&cru CLK_REF_PIPE_PHY2>; - assigned-clock-rates = <100000000>; - #phy-cells = <1>; - resets = <&cru SRST_REF_PIPE_PHY2>, <&cru SRST_P_PCIE2_PHY2>; - reset-names = "phy", "apb"; - rockchip,pipe-grf = <&php_grf>; - rockchip,pipe-phy-grf = <&pipe_phy2_grf>; - status = "disabled"; - }; - - system_sram2: sram@ff001000 { - compatible = "mmio-sram"; - reg = <0x0 0xff001000 0x0 0xef000>; - ranges = <0x0 0x0 0xff001000 0xef000>; - #address-cells = <1>; - #size-cells = <1>; - }; - - pinctrl: pinctrl { - compatible = "rockchip,rk3588-pinctrl"; - ranges; - rockchip,grf = <&ioc>; - #address-cells = <2>; - #size-cells = <2>; - - gpio0: gpio@fd8a0000 { - compatible = "rockchip,gpio-bank"; - reg = <0x0 0xfd8a0000 0x0 0x100>; - interrupts = ; - clocks = <&cru PCLK_GPIO0>, <&cru DBCLK_GPIO0>; - gpio-controller; - gpio-ranges = <&pinctrl 0 0 32>; - interrupt-controller; - #gpio-cells = <2>; - #interrupt-cells = <2>; - }; - - gpio1: gpio@fec20000 { - compatible = "rockchip,gpio-bank"; - reg = <0x0 0xfec20000 0x0 0x100>; - interrupts = ; - clocks = <&cru PCLK_GPIO1>, <&cru DBCLK_GPIO1>; - gpio-controller; - gpio-ranges = <&pinctrl 0 32 32>; - interrupt-controller; - #gpio-cells = <2>; - #interrupt-cells = <2>; - }; - - gpio2: gpio@fec30000 { - compatible = "rockchip,gpio-bank"; - reg = <0x0 0xfec30000 0x0 0x100>; - interrupts = ; - clocks = <&cru PCLK_GPIO2>, <&cru DBCLK_GPIO2>; - gpio-controller; - gpio-ranges = <&pinctrl 0 64 32>; - interrupt-controller; - #gpio-cells = <2>; - #interrupt-cells = <2>; - }; - - gpio3: gpio@fec40000 { - compatible = "rockchip,gpio-bank"; - reg = <0x0 0xfec40000 0x0 0x100>; - interrupts = ; - clocks = <&cru PCLK_GPIO3>, <&cru DBCLK_GPIO3>; - gpio-controller; - gpio-ranges = <&pinctrl 0 96 32>; - interrupt-controller; - #gpio-cells = <2>; - #interrupt-cells = <2>; - }; - - gpio4: gpio@fec50000 { - compatible = "rockchip,gpio-bank"; - reg = <0x0 0xfec50000 0x0 0x100>; - interrupts = ; - clocks = <&cru PCLK_GPIO4>, <&cru DBCLK_GPIO4>; - gpio-controller; - gpio-ranges = <&pinctrl 0 128 32>; - interrupt-controller; - #gpio-cells = <2>; - #interrupt-cells = <2>; - }; - }; -}; - -#include "rk3588-base-pinctrl.dtsi" diff --git a/lede/target/linux/rockchip/files-5.15/arch/arm64/boot/dts/rockchip/rk3588-extra-pinctrl.dtsi b/lede/target/linux/rockchip/files-5.15/arch/arm64/boot/dts/rockchip/rk3588-extra-pinctrl.dtsi deleted file mode 100644 index 244c66faa1..0000000000 --- a/lede/target/linux/rockchip/files-5.15/arch/arm64/boot/dts/rockchip/rk3588-extra-pinctrl.dtsi +++ /dev/null @@ -1,516 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2021 Rockchip Electronics Co., Ltd. - */ - -#include -#include "rockchip-pinconf.dtsi" - -/* - * This file is auto generated by pin2dts tool, please keep these code - * by adding changes at end of this file. - */ -&pinctrl { - clk32k { - /omit-if-no-ref/ - clk32k_out1: clk32k-out1 { - rockchip,pins = - /* clk32k_out1 */ - <2 RK_PC5 1 &pcfg_pull_none>; - }; - - }; - - eth0 { - /omit-if-no-ref/ - eth0_pins: eth0-pins { - rockchip,pins = - /* eth0_refclko_25m */ - <2 RK_PC3 1 &pcfg_pull_none>; - }; - - }; - - fspi { - /omit-if-no-ref/ - fspim1_pins: fspim1-pins { - rockchip,pins = - /* fspi_clk_m1 */ - <2 RK_PB3 3 &pcfg_pull_up_drv_level_2>, - /* fspi_cs0n_m1 */ - <2 RK_PB4 3 &pcfg_pull_up_drv_level_2>, - /* fspi_d0_m1 */ - <2 RK_PA6 3 &pcfg_pull_up_drv_level_2>, - /* fspi_d1_m1 */ - <2 RK_PA7 3 &pcfg_pull_up_drv_level_2>, - /* fspi_d2_m1 */ - <2 RK_PB0 3 &pcfg_pull_up_drv_level_2>, - /* fspi_d3_m1 */ - <2 RK_PB1 3 &pcfg_pull_up_drv_level_2>; - }; - - /omit-if-no-ref/ - fspim1_cs1: fspim1-cs1 { - rockchip,pins = - /* fspi_cs1n_m1 */ - <2 RK_PB5 3 &pcfg_pull_up_drv_level_2>; - }; - }; - - gmac0 { - /omit-if-no-ref/ - gmac0_miim: gmac0-miim { - rockchip,pins = - /* gmac0_mdc */ - <4 RK_PC4 1 &pcfg_pull_none>, - /* gmac0_mdio */ - <4 RK_PC5 1 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - gmac0_clkinout: gmac0-clkinout { - rockchip,pins = - /* gmac0_mclkinout */ - <4 RK_PC3 1 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - gmac0_rx_bus2: gmac0-rx-bus2 { - rockchip,pins = - /* gmac0_rxd0 */ - <2 RK_PC1 1 &pcfg_pull_none>, - /* gmac0_rxd1 */ - <2 RK_PC2 1 &pcfg_pull_none>, - /* gmac0_rxdv_crs */ - <4 RK_PC2 1 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - gmac0_tx_bus2: gmac0-tx-bus2 { - rockchip,pins = - /* gmac0_txd0 */ - <2 RK_PB6 1 &pcfg_pull_none>, - /* gmac0_txd1 */ - <2 RK_PB7 1 &pcfg_pull_none>, - /* gmac0_txen */ - <2 RK_PC0 1 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - gmac0_rgmii_clk: gmac0-rgmii-clk { - rockchip,pins = - /* gmac0_rxclk */ - <2 RK_PB0 1 &pcfg_pull_none>, - /* gmac0_txclk */ - <2 RK_PB3 1 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - gmac0_rgmii_bus: gmac0-rgmii-bus { - rockchip,pins = - /* gmac0_rxd2 */ - <2 RK_PA6 1 &pcfg_pull_none>, - /* gmac0_rxd3 */ - <2 RK_PA7 1 &pcfg_pull_none>, - /* gmac0_txd2 */ - <2 RK_PB1 1 &pcfg_pull_none>, - /* gmac0_txd3 */ - <2 RK_PB2 1 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - gmac0_ppsclk: gmac0-ppsclk { - rockchip,pins = - /* gmac0_ppsclk */ - <2 RK_PC4 1 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - gmac0_ppstring: gmac0-ppstring { - rockchip,pins = - /* gmac0_ppstring */ - <2 RK_PB5 1 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - gmac0_ptp_refclk: gmac0-ptp-refclk { - rockchip,pins = - /* gmac0_ptp_refclk */ - <2 RK_PB4 1 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - gmac0_txer: gmac0-txer { - rockchip,pins = - /* gmac0_txer */ - <4 RK_PC6 1 &pcfg_pull_none>; - }; - - }; - - hdmi { - /omit-if-no-ref/ - hdmim0_tx1_cec: hdmim0-tx1-cec { - rockchip,pins = - /* hdmim0_tx1_cec */ - <2 RK_PC4 4 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - hdmim0_tx1_scl: hdmim0-tx1-scl { - rockchip,pins = - /* hdmim0_tx1_scl */ - <2 RK_PB5 4 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - hdmim0_tx1_sda: hdmim0-tx1-sda { - rockchip,pins = - /* hdmim0_tx1_sda */ - <2 RK_PB4 4 &pcfg_pull_none>; - }; - }; - - i2c0 { - /omit-if-no-ref/ - i2c0m1_xfer: i2c0m1-xfer { - rockchip,pins = - /* i2c0_scl_m1 */ - <4 RK_PC5 9 &pcfg_pull_none_smt>, - /* i2c0_sda_m1 */ - <4 RK_PC6 9 &pcfg_pull_none_smt>; - }; - }; - - i2c2 { - /omit-if-no-ref/ - i2c2m1_xfer: i2c2m1-xfer { - rockchip,pins = - /* i2c2_scl_m1 */ - <2 RK_PC1 9 &pcfg_pull_none_smt>, - /* i2c2_sda_m1 */ - <2 RK_PC0 9 &pcfg_pull_none_smt>; - }; - }; - - i2c3 { - /omit-if-no-ref/ - i2c3m3_xfer: i2c3m3-xfer { - rockchip,pins = - /* i2c3_scl_m3 */ - <2 RK_PB2 9 &pcfg_pull_none_smt>, - /* i2c3_sda_m3 */ - <2 RK_PB3 9 &pcfg_pull_none_smt>; - }; - }; - - i2c4 { - /omit-if-no-ref/ - i2c4m1_xfer: i2c4m1-xfer { - rockchip,pins = - /* i2c4_scl_m1 */ - <2 RK_PB5 9 &pcfg_pull_none_smt>, - /* i2c4_sda_m1 */ - <2 RK_PB4 9 &pcfg_pull_none_smt>; - }; - }; - - i2c5 { - /omit-if-no-ref/ - i2c5m4_xfer: i2c5m4-xfer { - rockchip,pins = - /* i2c5_scl_m4 */ - <2 RK_PB6 9 &pcfg_pull_none_smt>, - /* i2c5_sda_m4 */ - <2 RK_PB7 9 &pcfg_pull_none_smt>; - }; - }; - - i2c6 { - /omit-if-no-ref/ - i2c6m2_xfer: i2c6m2-xfer { - rockchip,pins = - /* i2c6_scl_m2 */ - <2 RK_PC3 9 &pcfg_pull_none_smt>, - /* i2c6_sda_m2 */ - <2 RK_PC2 9 &pcfg_pull_none_smt>; - }; - }; - - i2c7 { - /omit-if-no-ref/ - i2c7m1_xfer: i2c7m1-xfer { - rockchip,pins = - /* i2c7_scl_m1 */ - <4 RK_PC3 9 &pcfg_pull_none_smt>, - /* i2c7_sda_m1 */ - <4 RK_PC4 9 &pcfg_pull_none_smt>; - }; - }; - - i2c8 { - /omit-if-no-ref/ - i2c8m1_xfer: i2c8m1-xfer { - rockchip,pins = - /* i2c8_scl_m1 */ - <2 RK_PB0 9 &pcfg_pull_none_smt>, - /* i2c8_sda_m1 */ - <2 RK_PB1 9 &pcfg_pull_none_smt>; - }; - }; - - i2s2 { - /omit-if-no-ref/ - i2s2m0_lrck: i2s2m0-lrck { - rockchip,pins = - /* i2s2m0_lrck */ - <2 RK_PC0 2 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - i2s2m0_mclk: i2s2m0-mclk { - rockchip,pins = - /* i2s2m0_mclk */ - <2 RK_PB6 2 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - i2s2m0_sclk: i2s2m0-sclk { - rockchip,pins = - /* i2s2m0_sclk */ - <2 RK_PB7 2 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - i2s2m0_sdi: i2s2m0-sdi { - rockchip,pins = - /* i2s2m0_sdi */ - <2 RK_PC3 2 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - i2s2m0_sdo: i2s2m0-sdo { - rockchip,pins = - /* i2s2m0_sdo */ - <4 RK_PC3 2 &pcfg_pull_none>; - }; - }; - - pwm2 { - /omit-if-no-ref/ - pwm2m2_pins: pwm2m2-pins { - rockchip,pins = - /* pwm2_m2 */ - <4 RK_PC2 11 &pcfg_pull_none>; - }; - }; - - pwm4 { - /omit-if-no-ref/ - pwm4m1_pins: pwm4m1-pins { - rockchip,pins = - /* pwm4_m1 */ - <4 RK_PC3 11 &pcfg_pull_none>; - }; - }; - - pwm5 { - /omit-if-no-ref/ - pwm5m2_pins: pwm5m2-pins { - rockchip,pins = - /* pwm5_m2 */ - <4 RK_PC4 11 &pcfg_pull_none>; - }; - }; - - pwm6 { - /omit-if-no-ref/ - pwm6m2_pins: pwm6m2-pins { - rockchip,pins = - /* pwm6_m2 */ - <4 RK_PC5 11 &pcfg_pull_none>; - }; - }; - - pwm7 { - /omit-if-no-ref/ - pwm7m3_pins: pwm7m3-pins { - rockchip,pins = - /* pwm7_ir_m3 */ - <4 RK_PC6 11 &pcfg_pull_none>; - }; - }; - - sdio { - /omit-if-no-ref/ - sdiom0_pins: sdiom0-pins { - rockchip,pins = - /* sdio_clk_m0 */ - <2 RK_PB3 2 &pcfg_pull_none>, - /* sdio_cmd_m0 */ - <2 RK_PB2 2 &pcfg_pull_none>, - /* sdio_d0_m0 */ - <2 RK_PA6 2 &pcfg_pull_none>, - /* sdio_d1_m0 */ - <2 RK_PA7 2 &pcfg_pull_none>, - /* sdio_d2_m0 */ - <2 RK_PB0 2 &pcfg_pull_none>, - /* sdio_d3_m0 */ - <2 RK_PB1 2 &pcfg_pull_none>; - }; - }; - - spi1 { - /omit-if-no-ref/ - spi1m0_pins: spi1m0-pins { - rockchip,pins = - /* spi1_clk_m0 */ - <2 RK_PC0 8 &pcfg_pull_up_drv_level_1>, - /* spi1_miso_m0 */ - <2 RK_PC1 8 &pcfg_pull_up_drv_level_1>, - /* spi1_mosi_m0 */ - <2 RK_PC2 8 &pcfg_pull_up_drv_level_1>; - }; - - /omit-if-no-ref/ - spi1m0_cs0: spi1m0-cs0 { - rockchip,pins = - /* spi1_cs0_m0 */ - <2 RK_PC3 8 &pcfg_pull_up_drv_level_1>; - }; - - /omit-if-no-ref/ - spi1m0_cs1: spi1m0-cs1 { - rockchip,pins = - /* spi1_cs1_m0 */ - <2 RK_PC4 8 &pcfg_pull_up_drv_level_1>; - }; - }; - - spi3 { - /omit-if-no-ref/ - spi3m0_pins: spi3m0-pins { - rockchip,pins = - /* spi3_clk_m0 */ - <4 RK_PC6 8 &pcfg_pull_up_drv_level_1>, - /* spi3_miso_m0 */ - <4 RK_PC4 8 &pcfg_pull_up_drv_level_1>, - /* spi3_mosi_m0 */ - <4 RK_PC5 8 &pcfg_pull_up_drv_level_1>; - }; - - /omit-if-no-ref/ - spi3m0_cs0: spi3m0-cs0 { - rockchip,pins = - /* spi3_cs0_m0 */ - <4 RK_PC2 8 &pcfg_pull_up_drv_level_1>; - }; - - /omit-if-no-ref/ - spi3m0_cs1: spi3m0-cs1 { - rockchip,pins = - /* spi3_cs1_m0 */ - <4 RK_PC3 8 &pcfg_pull_up_drv_level_1>; - }; - }; - - uart1 { - /omit-if-no-ref/ - uart1m0_xfer: uart1m0-xfer { - rockchip,pins = - /* uart1_rx_m0 */ - <2 RK_PB6 10 &pcfg_pull_up>, - /* uart1_tx_m0 */ - <2 RK_PB7 10 &pcfg_pull_up>; - }; - - /omit-if-no-ref/ - uart1m0_ctsn: uart1m0-ctsn { - rockchip,pins = - /* uart1m0_ctsn */ - <2 RK_PC1 10 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - uart1m0_rtsn: uart1m0-rtsn { - rockchip,pins = - /* uart1m0_rtsn */ - <2 RK_PC0 10 &pcfg_pull_none>; - }; - }; - - uart6 { - /omit-if-no-ref/ - uart6m0_xfer: uart6m0-xfer { - rockchip,pins = - /* uart6_rx_m0 */ - <2 RK_PA6 10 &pcfg_pull_up>, - /* uart6_tx_m0 */ - <2 RK_PA7 10 &pcfg_pull_up>; - }; - - /omit-if-no-ref/ - uart6m0_ctsn: uart6m0-ctsn { - rockchip,pins = - /* uart6m0_ctsn */ - <2 RK_PB1 10 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - uart6m0_rtsn: uart6m0-rtsn { - rockchip,pins = - /* uart6m0_rtsn */ - <2 RK_PB0 10 &pcfg_pull_none>; - }; - }; - - uart7 { - /omit-if-no-ref/ - uart7m0_xfer: uart7m0-xfer { - rockchip,pins = - /* uart7_rx_m0 */ - <2 RK_PB4 10 &pcfg_pull_up>, - /* uart7_tx_m0 */ - <2 RK_PB5 10 &pcfg_pull_up>; - }; - - /omit-if-no-ref/ - uart7m0_ctsn: uart7m0-ctsn { - rockchip,pins = - /* uart7m0_ctsn */ - <4 RK_PC6 10 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - uart7m0_rtsn: uart7m0-rtsn { - rockchip,pins = - /* uart7m0_rtsn */ - <4 RK_PC2 10 &pcfg_pull_none>; - }; - }; - - uart9 { - /omit-if-no-ref/ - uart9m0_xfer: uart9m0-xfer { - rockchip,pins = - /* uart9_rx_m0 */ - <2 RK_PC4 10 &pcfg_pull_up>, - /* uart9_tx_m0 */ - <2 RK_PC2 10 &pcfg_pull_up>; - }; - - /omit-if-no-ref/ - uart9m0_ctsn: uart9m0-ctsn { - rockchip,pins = - /* uart9m0_ctsn */ - <4 RK_PC5 10 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - uart9m0_rtsn: uart9m0-rtsn { - rockchip,pins = - /* uart9m0_rtsn */ - <4 RK_PC4 10 &pcfg_pull_none>; - }; - }; -}; diff --git a/lede/target/linux/rockchip/files-5.15/arch/arm64/boot/dts/rockchip/rk3588-extra.dtsi b/lede/target/linux/rockchip/files-5.15/arch/arm64/boot/dts/rockchip/rk3588-extra.dtsi deleted file mode 100644 index 0ce0934ec6..0000000000 --- a/lede/target/linux/rockchip/files-5.15/arch/arm64/boot/dts/rockchip/rk3588-extra.dtsi +++ /dev/null @@ -1,448 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2021 Rockchip Electronics Co., Ltd. - */ - -#include "rk3588-base.dtsi" -#include "rk3588-extra-pinctrl.dtsi" - -/ { - usb_host1_xhci: usb@fc400000 { - compatible = "rockchip,rk3588-dwc3", "snps,dwc3"; - reg = <0x0 0xfc400000 0x0 0x400000>; - interrupts = ; - clocks = <&cru REF_CLK_USB3OTG1>, <&cru SUSPEND_CLK_USB3OTG1>, - <&cru ACLK_USB3OTG1>; - clock-names = "ref_clk", "suspend_clk", "bus_clk"; - dr_mode = "otg"; - phys = <&u2phy1_otg>, <&usbdp_phy1 PHY_TYPE_USB3>; - phy-names = "usb2-phy", "usb3-phy"; - phy_type = "utmi_wide"; - power-domains = <&power RK3588_PD_USB>; - resets = <&cru SRST_A_USB3OTG1>; - snps,dis_enblslpm_quirk; - snps,dis-u2-freeclk-exists-quirk; - snps,dis-del-phy-power-chg-quirk; - snps,dis-tx-ipgap-linecheck-quirk; - status = "disabled"; - }; - - pcie30_phy_grf: syscon@fd5b8000 { - compatible = "rockchip,rk3588-pcie3-phy-grf", "syscon"; - reg = <0x0 0xfd5b8000 0x0 0x10000>; - }; - - pipe_phy1_grf: syscon@fd5c0000 { - compatible = "rockchip,rk3588-pipe-phy-grf", "syscon"; - reg = <0x0 0xfd5c0000 0x0 0x100>; - }; - - usbdpphy1_grf: syscon@fd5cc000 { - compatible = "rockchip,rk3588-usbdpphy-grf", "syscon"; - reg = <0x0 0xfd5cc000 0x0 0x4000>; - }; - - usb2phy1_grf: syscon@fd5d4000 { - compatible = "rockchip,rk3588-usb2phy-grf", "syscon", "simple-mfd"; - reg = <0x0 0xfd5d4000 0x0 0x4000>; - #address-cells = <1>; - #size-cells = <1>; - - u2phy1: usb2phy@4000 { - compatible = "rockchip,rk3588-usb2phy"; - reg = <0x4000 0x10>; - #clock-cells = <0>; - clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>; - clock-names = "phyclk"; - clock-output-names = "usb480m_phy1"; - interrupts = ; - resets = <&cru SRST_OTGPHY_U3_1>, <&cru SRST_P_USB2PHY_U3_1_GRF0>; - reset-names = "phy", "apb"; - status = "disabled"; - - u2phy1_otg: otg-port { - #phy-cells = <0>; - status = "disabled"; - }; - }; - }; - - i2s8_8ch: i2s@fddc8000 { - compatible = "rockchip,rk3588-i2s-tdm"; - reg = <0x0 0xfddc8000 0x0 0x1000>; - interrupts = ; - clocks = <&cru MCLK_I2S8_8CH_TX>, <&cru MCLK_I2S8_8CH_TX>, <&cru HCLK_I2S8_8CH>; - clock-names = "mclk_tx", "mclk_rx", "hclk"; - assigned-clocks = <&cru CLK_I2S8_8CH_TX_SRC>; - assigned-clock-parents = <&cru PLL_AUPLL>; - dmas = <&dmac2 22>; - dma-names = "tx"; - power-domains = <&power RK3588_PD_VO0>; - resets = <&cru SRST_M_I2S8_8CH_TX>; - reset-names = "tx-m"; - #sound-dai-cells = <0>; - status = "disabled"; - }; - - i2s6_8ch: i2s@fddf4000 { - compatible = "rockchip,rk3588-i2s-tdm"; - reg = <0x0 0xfddf4000 0x0 0x1000>; - interrupts = ; - clocks = <&cru MCLK_I2S6_8CH_TX>, <&cru MCLK_I2S6_8CH_TX>, <&cru HCLK_I2S6_8CH>; - clock-names = "mclk_tx", "mclk_rx", "hclk"; - assigned-clocks = <&cru CLK_I2S6_8CH_TX_SRC>; - assigned-clock-parents = <&cru PLL_AUPLL>; - dmas = <&dmac2 4>; - dma-names = "tx"; - power-domains = <&power RK3588_PD_VO1>; - resets = <&cru SRST_M_I2S6_8CH_TX>; - reset-names = "tx-m"; - #sound-dai-cells = <0>; - status = "disabled"; - }; - - i2s7_8ch: i2s@fddf8000 { - compatible = "rockchip,rk3588-i2s-tdm"; - reg = <0x0 0xfddf8000 0x0 0x1000>; - interrupts = ; - clocks = <&cru MCLK_I2S7_8CH_RX>, <&cru MCLK_I2S7_8CH_RX>, <&cru HCLK_I2S7_8CH>; - clock-names = "mclk_tx", "mclk_rx", "hclk"; - assigned-clocks = <&cru CLK_I2S7_8CH_RX_SRC>; - assigned-clock-parents = <&cru PLL_AUPLL>; - dmas = <&dmac2 21>; - dma-names = "rx"; - power-domains = <&power RK3588_PD_VO1>; - resets = <&cru SRST_M_I2S7_8CH_RX>; - reset-names = "rx-m"; - #sound-dai-cells = <0>; - status = "disabled"; - }; - - i2s10_8ch: i2s@fde00000 { - compatible = "rockchip,rk3588-i2s-tdm"; - reg = <0x0 0xfde00000 0x0 0x1000>; - interrupts = ; - clocks = <&cru MCLK_I2S10_8CH_RX>, <&cru MCLK_I2S10_8CH_RX>, <&cru HCLK_I2S10_8CH>; - clock-names = "mclk_tx", "mclk_rx", "hclk"; - assigned-clocks = <&cru CLK_I2S10_8CH_RX_SRC>; - assigned-clock-parents = <&cru PLL_AUPLL>; - dmas = <&dmac2 24>; - dma-names = "rx"; - power-domains = <&power RK3588_PD_VO1>; - resets = <&cru SRST_M_I2S10_8CH_RX>; - reset-names = "rx-m"; - #sound-dai-cells = <0>; - status = "disabled"; - }; - - pcie3x4: pcie@fe150000 { - compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie"; - #address-cells = <3>; - #size-cells = <2>; - bus-range = <0x00 0x0f>; - clocks = <&cru ACLK_PCIE_4L_MSTR>, <&cru ACLK_PCIE_4L_SLV>, - <&cru ACLK_PCIE_4L_DBI>, <&cru PCLK_PCIE_4L>, - <&cru CLK_PCIE_AUX0>, <&cru CLK_PCIE4L_PIPE>; - clock-names = "aclk_mst", "aclk_slv", - "aclk_dbi", "pclk", - "aux", "pipe"; - device_type = "pci"; - interrupts = , - , - , - , - ; - interrupt-names = "sys", "pmc", "msg", "legacy", "err"; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 7>; - interrupt-map = <0 0 0 1 &pcie3x4_intc 0>, - <0 0 0 2 &pcie3x4_intc 1>, - <0 0 0 3 &pcie3x4_intc 2>, - <0 0 0 4 &pcie3x4_intc 3>; - linux,pci-domain = <0>; - max-link-speed = <3>; - msi-map = <0x0000 &its1 0x0000 0x1000>; - num-lanes = <4>; - phys = <&pcie30phy>; - phy-names = "pcie-phy"; - power-domains = <&power RK3588_PD_PCIE>; - ranges = <0x01000000 0x0 0xf0100000 0x0 0xf0100000 0x0 0x00100000>, - <0x02000000 0x0 0xf0200000 0x0 0xf0200000 0x0 0x00e00000>, - <0x03000000 0x0 0x40000000 0x9 0x00000000 0x0 0x40000000>; - reg = <0xa 0x40000000 0x0 0x00400000>, - <0x0 0xfe150000 0x0 0x00010000>, - <0x0 0xf0000000 0x0 0x00100000>; - reg-names = "dbi", "apb", "config"; - resets = <&cru SRST_PCIE0_POWER_UP>, <&cru SRST_P_PCIE0>; - reset-names = "pwr", "pipe"; - status = "disabled"; - - pcie3x4_intc: legacy-interrupt-controller { - interrupt-controller; - #address-cells = <0>; - #interrupt-cells = <1>; - interrupt-parent = <&gic>; - interrupts = ; - }; - }; - - pcie3x4_ep: pcie-ep@fe150000 { - compatible = "rockchip,rk3588-pcie-ep"; - reg = <0xa 0x40000000 0x0 0x00100000>, - <0xa 0x40100000 0x0 0x00100000>, - <0x0 0xfe150000 0x0 0x00010000>, - <0x9 0x00000000 0x0 0x40000000>, - <0xa 0x40300000 0x0 0x00100000>; - reg-names = "dbi", "dbi2", "apb", "addr_space", "atu"; - clocks = <&cru ACLK_PCIE_4L_MSTR>, <&cru ACLK_PCIE_4L_SLV>, - <&cru ACLK_PCIE_4L_DBI>, <&cru PCLK_PCIE_4L>, - <&cru CLK_PCIE_AUX0>, <&cru CLK_PCIE4L_PIPE>; - clock-names = "aclk_mst", "aclk_slv", - "aclk_dbi", "pclk", - "aux", "pipe"; - interrupts = , - , - , - , - , - , - , - , - ; - interrupt-names = "sys", "pmc", "msg", "legacy", "err", - "dma0", "dma1", "dma2", "dma3"; - max-link-speed = <3>; - num-lanes = <4>; - phys = <&pcie30phy>; - phy-names = "pcie-phy"; - power-domains = <&power RK3588_PD_PCIE>; - resets = <&cru SRST_PCIE0_POWER_UP>, <&cru SRST_P_PCIE0>; - reset-names = "pwr", "pipe"; - status = "disabled"; - }; - - pcie3x2: pcie@fe160000 { - compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie"; - #address-cells = <3>; - #size-cells = <2>; - bus-range = <0x10 0x1f>; - clocks = <&cru ACLK_PCIE_2L_MSTR>, <&cru ACLK_PCIE_2L_SLV>, - <&cru ACLK_PCIE_2L_DBI>, <&cru PCLK_PCIE_2L>, - <&cru CLK_PCIE_AUX1>, <&cru CLK_PCIE2L_PIPE>; - clock-names = "aclk_mst", "aclk_slv", - "aclk_dbi", "pclk", - "aux", "pipe"; - device_type = "pci"; - interrupts = , - , - , - , - ; - interrupt-names = "sys", "pmc", "msg", "legacy", "err"; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 7>; - interrupt-map = <0 0 0 1 &pcie3x2_intc 0>, - <0 0 0 2 &pcie3x2_intc 1>, - <0 0 0 3 &pcie3x2_intc 2>, - <0 0 0 4 &pcie3x2_intc 3>; - linux,pci-domain = <1>; - max-link-speed = <3>; - msi-map = <0x1000 &its1 0x1000 0x1000>; - num-lanes = <2>; - phys = <&pcie30phy>; - phy-names = "pcie-phy"; - power-domains = <&power RK3588_PD_PCIE>; - ranges = <0x01000000 0x0 0xf1100000 0x0 0xf1100000 0x0 0x00100000>, - <0x02000000 0x0 0xf1200000 0x0 0xf1200000 0x0 0x00e00000>, - <0x03000000 0x0 0x40000000 0x9 0x40000000 0x0 0x40000000>; - reg = <0xa 0x40400000 0x0 0x00400000>, - <0x0 0xfe160000 0x0 0x00010000>, - <0x0 0xf1000000 0x0 0x00100000>; - reg-names = "dbi", "apb", "config"; - resets = <&cru SRST_PCIE1_POWER_UP>, <&cru SRST_P_PCIE1>; - reset-names = "pwr", "pipe"; - status = "disabled"; - - pcie3x2_intc: legacy-interrupt-controller { - interrupt-controller; - #address-cells = <0>; - #interrupt-cells = <1>; - interrupt-parent = <&gic>; - interrupts = ; - }; - }; - - pcie2x1l0: pcie@fe170000 { - compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie"; - bus-range = <0x20 0x2f>; - clocks = <&cru ACLK_PCIE_1L0_MSTR>, <&cru ACLK_PCIE_1L0_SLV>, - <&cru ACLK_PCIE_1L0_DBI>, <&cru PCLK_PCIE_1L0>, - <&cru CLK_PCIE_AUX2>, <&cru CLK_PCIE1L0_PIPE>; - clock-names = "aclk_mst", "aclk_slv", - "aclk_dbi", "pclk", - "aux", "pipe"; - device_type = "pci"; - interrupts = , - , - , - , - ; - interrupt-names = "sys", "pmc", "msg", "legacy", "err"; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 7>; - interrupt-map = <0 0 0 1 &pcie2x1l0_intc 0>, - <0 0 0 2 &pcie2x1l0_intc 1>, - <0 0 0 3 &pcie2x1l0_intc 2>, - <0 0 0 4 &pcie2x1l0_intc 3>; - linux,pci-domain = <2>; - max-link-speed = <2>; - msi-map = <0x2000 &its0 0x2000 0x1000>; - num-lanes = <1>; - phys = <&combphy1_ps PHY_TYPE_PCIE>; - phy-names = "pcie-phy"; - power-domains = <&power RK3588_PD_PCIE>; - ranges = <0x01000000 0x0 0xf2100000 0x0 0xf2100000 0x0 0x00100000>, - <0x02000000 0x0 0xf2200000 0x0 0xf2200000 0x0 0x00e00000>, - <0x03000000 0x0 0x40000000 0x9 0x80000000 0x0 0x40000000>; - reg = <0xa 0x40800000 0x0 0x00400000>, - <0x0 0xfe170000 0x0 0x00010000>, - <0x0 0xf2000000 0x0 0x00100000>; - reg-names = "dbi", "apb", "config"; - resets = <&cru SRST_PCIE2_POWER_UP>, <&cru SRST_P_PCIE2>; - reset-names = "pwr", "pipe"; - #address-cells = <3>; - #size-cells = <2>; - status = "disabled"; - - pcie2x1l0_intc: legacy-interrupt-controller { - interrupt-controller; - #address-cells = <0>; - #interrupt-cells = <1>; - interrupt-parent = <&gic>; - interrupts = ; - }; - }; - - gmac0: ethernet@fe1b0000 { - compatible = "rockchip,rk3588-gmac", "snps,dwmac-4.20a"; - reg = <0x0 0xfe1b0000 0x0 0x10000>; - interrupts = , - ; - interrupt-names = "macirq", "eth_wake_irq"; - clocks = <&cru CLK_GMAC_125M>, <&cru CLK_GMAC_50M>, - <&cru PCLK_GMAC0>, <&cru ACLK_GMAC0>, - <&cru CLK_GMAC0_PTP_REF>; - clock-names = "stmmaceth", "clk_mac_ref", - "pclk_mac", "aclk_mac", - "ptp_ref"; - power-domains = <&power RK3588_PD_GMAC>; - resets = <&cru SRST_A_GMAC0>; - reset-names = "stmmaceth"; - rockchip,grf = <&sys_grf>; - rockchip,php-grf = <&php_grf>; - snps,axi-config = <&gmac0_stmmac_axi_setup>; - snps,mixed-burst; - snps,mtl-rx-config = <&gmac0_mtl_rx_setup>; - snps,mtl-tx-config = <&gmac0_mtl_tx_setup>; - snps,tso; - status = "disabled"; - - mdio0: mdio { - compatible = "snps,dwmac-mdio"; - #address-cells = <0x1>; - #size-cells = <0x0>; - }; - - gmac0_stmmac_axi_setup: stmmac-axi-config { - snps,blen = <0 0 0 0 16 8 4>; - snps,wr_osr_lmt = <4>; - snps,rd_osr_lmt = <8>; - }; - - gmac0_mtl_rx_setup: rx-queues-config { - snps,rx-queues-to-use = <2>; - queue0 {}; - queue1 {}; - }; - - gmac0_mtl_tx_setup: tx-queues-config { - snps,tx-queues-to-use = <2>; - queue0 {}; - queue1 {}; - }; - }; - - sata1: sata@fe220000 { - compatible = "rockchip,rk3588-dwc-ahci", "snps,dwc-ahci"; - reg = <0 0xfe220000 0 0x1000>; - interrupts = ; - clocks = <&cru ACLK_SATA1>, <&cru CLK_PMALIVE1>, - <&cru CLK_RXOOB1>, <&cru CLK_PIPEPHY1_REF>, - <&cru CLK_PIPEPHY1_PIPE_ASIC_G>; - clock-names = "sata", "pmalive", "rxoob", "ref", "asic"; - ports-implemented = <0x1>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - - sata-port@0 { - reg = <0>; - hba-port-cap = ; - phys = <&combphy1_ps PHY_TYPE_SATA>; - phy-names = "sata-phy"; - snps,rx-ts-max = <32>; - snps,tx-ts-max = <32>; - }; - }; - - usbdp_phy1: phy@fed90000 { - compatible = "rockchip,rk3588-usbdp-phy"; - reg = <0x0 0xfed90000 0x0 0x10000>; - #phy-cells = <1>; - clocks = <&cru CLK_USBDPPHY_MIPIDCPPHY_REF>, - <&cru CLK_USBDP_PHY1_IMMORTAL>, - <&cru PCLK_USBDPPHY1>, - <&u2phy1>; - clock-names = "refclk", "immortal", "pclk", "utmi"; - resets = <&cru SRST_USBDP_COMBO_PHY1_INIT>, - <&cru SRST_USBDP_COMBO_PHY1_CMN>, - <&cru SRST_USBDP_COMBO_PHY1_LANE>, - <&cru SRST_USBDP_COMBO_PHY1_PCS>, - <&cru SRST_P_USBDPPHY1>; - reset-names = "init", "cmn", "lane", "pcs_apb", "pma_apb"; - rockchip,u2phy-grf = <&usb2phy1_grf>; - rockchip,usb-grf = <&usb_grf>; - rockchip,usbdpphy-grf = <&usbdpphy1_grf>; - rockchip,vo-grf = <&vo0_grf>; - status = "disabled"; - }; - - combphy1_ps: phy@fee10000 { - compatible = "rockchip,rk3588-naneng-combphy"; - reg = <0x0 0xfee10000 0x0 0x100>; - clocks = <&cru CLK_REF_PIPE_PHY1>, <&cru PCLK_PCIE_COMBO_PIPE_PHY1>, - <&cru PCLK_PHP_ROOT>; - clock-names = "ref", "apb", "pipe"; - assigned-clocks = <&cru CLK_REF_PIPE_PHY1>; - assigned-clock-rates = <100000000>; - #phy-cells = <1>; - resets = <&cru SRST_REF_PIPE_PHY1>, <&cru SRST_P_PCIE2_PHY1>; - reset-names = "phy", "apb"; - rockchip,pipe-grf = <&php_grf>; - rockchip,pipe-phy-grf = <&pipe_phy1_grf>; - status = "disabled"; - }; - - pcie30phy: phy@fee80000 { - compatible = "rockchip,rk3588-pcie3-phy"; - reg = <0x0 0xfee80000 0x0 0x20000>; - #phy-cells = <0>; - clocks = <&cru PCLK_PCIE_COMBO_PIPE_PHY>; - clock-names = "pclk"; - resets = <&cru SRST_PCIE30_PHY>; - reset-names = "phy"; - rockchip,pipe-grf = <&php_grf>; - rockchip,phy-grf = <&pcie30_phy_grf>; - status = "disabled"; - }; -}; diff --git a/lede/target/linux/rockchip/files-5.15/arch/arm64/boot/dts/rockchip/rk3588-opp.dtsi b/lede/target/linux/rockchip/files-5.15/arch/arm64/boot/dts/rockchip/rk3588-opp.dtsi deleted file mode 100644 index 0f1a776973..0000000000 --- a/lede/target/linux/rockchip/files-5.15/arch/arm64/boot/dts/rockchip/rk3588-opp.dtsi +++ /dev/null @@ -1,190 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) - -/ { - cluster0_opp_table: opp-table-cluster0 { - compatible = "operating-points-v2"; - opp-shared; - - opp-1008000000 { - opp-hz = /bits/ 64 <1008000000>; - opp-microvolt = <675000 675000 950000>; - clock-latency-ns = <40000>; - }; - opp-1200000000 { - opp-hz = /bits/ 64 <1200000000>; - opp-microvolt = <712500 712500 950000>; - clock-latency-ns = <40000>; - }; - opp-1416000000 { - opp-hz = /bits/ 64 <1416000000>; - opp-microvolt = <762500 762500 950000>; - clock-latency-ns = <40000>; - opp-suspend; - }; - opp-1608000000 { - opp-hz = /bits/ 64 <1608000000>; - opp-microvolt = <850000 850000 950000>; - clock-latency-ns = <40000>; - }; - opp-1800000000 { - opp-hz = /bits/ 64 <1800000000>; - opp-microvolt = <950000 950000 950000>; - clock-latency-ns = <40000>; - }; - }; - - cluster1_opp_table: opp-table-cluster1 { - compatible = "operating-points-v2"; - opp-shared; - - opp-1200000000 { - opp-hz = /bits/ 64 <1200000000>; - opp-microvolt = <675000 675000 1000000>; - clock-latency-ns = <40000>; - }; - opp-1416000000 { - opp-hz = /bits/ 64 <1416000000>; - opp-microvolt = <725000 725000 1000000>; - clock-latency-ns = <40000>; - }; - opp-1608000000 { - opp-hz = /bits/ 64 <1608000000>; - opp-microvolt = <762500 762500 1000000>; - clock-latency-ns = <40000>; - }; - opp-1800000000 { - opp-hz = /bits/ 64 <1800000000>; - opp-microvolt = <850000 850000 1000000>; - clock-latency-ns = <40000>; - }; - opp-2016000000 { - opp-hz = /bits/ 64 <2016000000>; - opp-microvolt = <925000 925000 1000000>; - clock-latency-ns = <40000>; - }; - opp-2208000000 { - opp-hz = /bits/ 64 <2208000000>; - opp-microvolt = <987500 987500 1000000>; - clock-latency-ns = <40000>; - }; - opp-2400000000 { - opp-hz = /bits/ 64 <2400000000>; - opp-microvolt = <1000000 1000000 1000000>; - clock-latency-ns = <40000>; - }; - }; - - cluster2_opp_table: opp-table-cluster2 { - compatible = "operating-points-v2"; - opp-shared; - - opp-1200000000 { - opp-hz = /bits/ 64 <1200000000>; - opp-microvolt = <675000 675000 1000000>; - clock-latency-ns = <40000>; - }; - opp-1416000000 { - opp-hz = /bits/ 64 <1416000000>; - opp-microvolt = <725000 725000 1000000>; - clock-latency-ns = <40000>; - }; - opp-1608000000 { - opp-hz = /bits/ 64 <1608000000>; - opp-microvolt = <762500 762500 1000000>; - clock-latency-ns = <40000>; - }; - opp-1800000000 { - opp-hz = /bits/ 64 <1800000000>; - opp-microvolt = <850000 850000 1000000>; - clock-latency-ns = <40000>; - }; - opp-2016000000 { - opp-hz = /bits/ 64 <2016000000>; - opp-microvolt = <925000 925000 1000000>; - clock-latency-ns = <40000>; - }; - opp-2208000000 { - opp-hz = /bits/ 64 <2208000000>; - opp-microvolt = <987500 987500 1000000>; - clock-latency-ns = <40000>; - }; - opp-2400000000 { - opp-hz = /bits/ 64 <2400000000>; - opp-microvolt = <1000000 1000000 1000000>; - clock-latency-ns = <40000>; - }; - }; - - gpu_opp_table: opp-table { - compatible = "operating-points-v2"; - - opp-300000000 { - opp-hz = /bits/ 64 <300000000>; - opp-microvolt = <675000 675000 850000>; - }; - opp-400000000 { - opp-hz = /bits/ 64 <400000000>; - opp-microvolt = <675000 675000 850000>; - }; - opp-500000000 { - opp-hz = /bits/ 64 <500000000>; - opp-microvolt = <675000 675000 850000>; - }; - opp-600000000 { - opp-hz = /bits/ 64 <600000000>; - opp-microvolt = <675000 675000 850000>; - }; - opp-700000000 { - opp-hz = /bits/ 64 <700000000>; - opp-microvolt = <700000 700000 850000>; - }; - opp-800000000 { - opp-hz = /bits/ 64 <800000000>; - opp-microvolt = <750000 750000 850000>; - }; - opp-900000000 { - opp-hz = /bits/ 64 <900000000>; - opp-microvolt = <800000 800000 850000>; - }; - opp-1000000000 { - opp-hz = /bits/ 64 <1000000000>; - opp-microvolt = <850000 850000 850000>; - }; - }; -}; - -&cpu_b0 { - operating-points-v2 = <&cluster1_opp_table>; -}; - -&cpu_b1 { - operating-points-v2 = <&cluster1_opp_table>; -}; - -&cpu_b2 { - operating-points-v2 = <&cluster2_opp_table>; -}; - -&cpu_b3 { - operating-points-v2 = <&cluster2_opp_table>; -}; - -&cpu_l0 { - operating-points-v2 = <&cluster0_opp_table>; -}; - -&cpu_l1 { - operating-points-v2 = <&cluster0_opp_table>; -}; - -&cpu_l2 { - operating-points-v2 = <&cluster0_opp_table>; -}; - -&cpu_l3 { - operating-points-v2 = <&cluster0_opp_table>; -}; - -&gpu { - operating-points-v2 = <&gpu_opp_table>; -}; diff --git a/lede/target/linux/rockchip/files-5.15/arch/arm64/boot/dts/rockchip/rk3588.dtsi b/lede/target/linux/rockchip/files-5.15/arch/arm64/boot/dts/rockchip/rk3588.dtsi deleted file mode 100644 index 7462cc1e10..0000000000 --- a/lede/target/linux/rockchip/files-5.15/arch/arm64/boot/dts/rockchip/rk3588.dtsi +++ /dev/null @@ -1,8 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2022 Rockchip Electronics Co., Ltd. - * - */ - -#include "rk3588-extra.dtsi" -#include "rk3588-opp.dtsi" diff --git a/lede/target/linux/rockchip/files-5.15/include/dt-bindings/ata/ahci.h b/lede/target/linux/rockchip/files-5.15/include/dt-bindings/ata/ahci.h deleted file mode 100644 index b3f3b7cf9a..0000000000 --- a/lede/target/linux/rockchip/files-5.15/include/dt-bindings/ata/ahci.h +++ /dev/null @@ -1,20 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */ -/* - * This header provides constants for most AHCI bindings. - */ - -#ifndef _DT_BINDINGS_ATA_AHCI_H -#define _DT_BINDINGS_ATA_AHCI_H - -/* Host Bus Adapter generic platform capabilities */ -#define HBA_SSS (1 << 27) -#define HBA_SMPS (1 << 28) - -/* Host Bus Adapter port-specific platform capabilities */ -#define HBA_PORT_HPCP (1 << 18) -#define HBA_PORT_MPSP (1 << 19) -#define HBA_PORT_CPD (1 << 20) -#define HBA_PORT_ESP (1 << 21) -#define HBA_PORT_FBSCP (1 << 22) - -#endif diff --git a/lede/target/linux/rockchip/files-5.15/include/dt-bindings/clock/rockchip,rk3588-cru.h b/lede/target/linux/rockchip/files-5.15/include/dt-bindings/clock/rockchip,rk3588-cru.h deleted file mode 100644 index 0c7d3ca2d5..0000000000 --- a/lede/target/linux/rockchip/files-5.15/include/dt-bindings/clock/rockchip,rk3588-cru.h +++ /dev/null @@ -1,765 +0,0 @@ -/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ -/* - * Copyright (c) 2021 Rockchip Electronics Co. Ltd. - * Copyright (c) 2022 Collabora Ltd. - * - * Author: Elaine Zhang - * Author: Sebastian Reichel - */ - -#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3588_H -#define _DT_BINDINGS_CLK_ROCKCHIP_RK3588_H - -/* cru-clocks indices */ - -#define PLL_B0PLL 0 -#define PLL_B1PLL 1 -#define PLL_LPLL 2 -#define PLL_V0PLL 3 -#define PLL_AUPLL 4 -#define PLL_CPLL 5 -#define PLL_GPLL 6 -#define PLL_NPLL 7 -#define PLL_PPLL 8 -#define ARMCLK_L 9 -#define ARMCLK_B01 10 -#define ARMCLK_B23 11 -#define PCLK_BIGCORE0_ROOT 12 -#define PCLK_BIGCORE0_PVTM 13 -#define PCLK_BIGCORE1_ROOT 14 -#define PCLK_BIGCORE1_PVTM 15 -#define PCLK_DSU_S_ROOT 16 -#define PCLK_DSU_ROOT 17 -#define PCLK_DSU_NS_ROOT 18 -#define PCLK_LITCORE_PVTM 19 -#define PCLK_DBG 20 -#define PCLK_DSU 21 -#define PCLK_S_DAPLITE 22 -#define PCLK_M_DAPLITE 23 -#define MBIST_MCLK_PDM1 24 -#define MBIST_CLK_ACDCDIG 25 -#define HCLK_I2S2_2CH 26 -#define HCLK_I2S3_2CH 27 -#define CLK_I2S2_2CH_SRC 28 -#define CLK_I2S2_2CH_FRAC 29 -#define CLK_I2S2_2CH 30 -#define MCLK_I2S2_2CH 31 -#define I2S2_2CH_MCLKOUT 32 -#define CLK_DAC_ACDCDIG 33 -#define CLK_I2S3_2CH_SRC 34 -#define CLK_I2S3_2CH_FRAC 35 -#define CLK_I2S3_2CH 36 -#define MCLK_I2S3_2CH 37 -#define I2S3_2CH_MCLKOUT 38 -#define PCLK_ACDCDIG 39 -#define HCLK_I2S0_8CH 40 -#define CLK_I2S0_8CH_TX_SRC 41 -#define CLK_I2S0_8CH_TX_FRAC 42 -#define MCLK_I2S0_8CH_TX 43 -#define CLK_I2S0_8CH_TX 44 -#define CLK_I2S0_8CH_RX_SRC 45 -#define CLK_I2S0_8CH_RX_FRAC 46 -#define MCLK_I2S0_8CH_RX 47 -#define CLK_I2S0_8CH_RX 48 -#define I2S0_8CH_MCLKOUT 49 -#define HCLK_PDM1 50 -#define MCLK_PDM1 51 -#define HCLK_AUDIO_ROOT 52 -#define PCLK_AUDIO_ROOT 53 -#define HCLK_SPDIF0 54 -#define CLK_SPDIF0_SRC 55 -#define CLK_SPDIF0_FRAC 56 -#define MCLK_SPDIF0 57 -#define CLK_SPDIF0 58 -#define CLK_SPDIF1 59 -#define HCLK_SPDIF1 60 -#define CLK_SPDIF1_SRC 61 -#define CLK_SPDIF1_FRAC 62 -#define MCLK_SPDIF1 63 -#define ACLK_AV1_ROOT 64 -#define ACLK_AV1 65 -#define PCLK_AV1_ROOT 66 -#define PCLK_AV1 67 -#define PCLK_MAILBOX0 68 -#define PCLK_MAILBOX1 69 -#define PCLK_MAILBOX2 70 -#define PCLK_PMU2 71 -#define PCLK_PMUCM0_INTMUX 72 -#define PCLK_DDRCM0_INTMUX 73 -#define PCLK_TOP 74 -#define PCLK_PWM1 75 -#define CLK_PWM1 76 -#define CLK_PWM1_CAPTURE 77 -#define PCLK_PWM2 78 -#define CLK_PWM2 79 -#define CLK_PWM2_CAPTURE 80 -#define PCLK_PWM3 81 -#define CLK_PWM3 82 -#define CLK_PWM3_CAPTURE 83 -#define PCLK_BUSTIMER0 84 -#define PCLK_BUSTIMER1 85 -#define CLK_BUS_TIMER_ROOT 86 -#define CLK_BUSTIMER0 87 -#define CLK_BUSTIMER1 88 -#define CLK_BUSTIMER2 89 -#define CLK_BUSTIMER3 90 -#define CLK_BUSTIMER4 91 -#define CLK_BUSTIMER5 92 -#define CLK_BUSTIMER6 93 -#define CLK_BUSTIMER7 94 -#define CLK_BUSTIMER8 95 -#define CLK_BUSTIMER9 96 -#define CLK_BUSTIMER10 97 -#define CLK_BUSTIMER11 98 -#define PCLK_WDT0 99 -#define TCLK_WDT0 100 -#define PCLK_CAN0 101 -#define CLK_CAN0 102 -#define PCLK_CAN1 103 -#define CLK_CAN1 104 -#define PCLK_CAN2 105 -#define CLK_CAN2 106 -#define ACLK_DECOM 107 -#define PCLK_DECOM 108 -#define DCLK_DECOM 109 -#define ACLK_DMAC0 110 -#define ACLK_DMAC1 111 -#define ACLK_DMAC2 112 -#define ACLK_BUS_ROOT 113 -#define ACLK_GIC 114 -#define PCLK_GPIO1 115 -#define DBCLK_GPIO1 116 -#define PCLK_GPIO2 117 -#define DBCLK_GPIO2 118 -#define PCLK_GPIO3 119 -#define DBCLK_GPIO3 120 -#define PCLK_GPIO4 121 -#define DBCLK_GPIO4 122 -#define PCLK_I2C1 123 -#define PCLK_I2C2 124 -#define PCLK_I2C3 125 -#define PCLK_I2C4 126 -#define PCLK_I2C5 127 -#define PCLK_I2C6 128 -#define PCLK_I2C7 129 -#define PCLK_I2C8 130 -#define CLK_I2C1 131 -#define CLK_I2C2 132 -#define CLK_I2C3 133 -#define CLK_I2C4 134 -#define CLK_I2C5 135 -#define CLK_I2C6 136 -#define CLK_I2C7 137 -#define CLK_I2C8 138 -#define PCLK_OTPC_NS 139 -#define CLK_OTPC_NS 140 -#define CLK_OTPC_ARB 141 -#define CLK_OTPC_AUTO_RD_G 142 -#define CLK_OTP_PHY_G 143 -#define PCLK_SARADC 144 -#define CLK_SARADC 145 -#define PCLK_SPI0 146 -#define PCLK_SPI1 147 -#define PCLK_SPI2 148 -#define PCLK_SPI3 149 -#define PCLK_SPI4 150 -#define CLK_SPI0 151 -#define CLK_SPI1 152 -#define CLK_SPI2 153 -#define CLK_SPI3 154 -#define CLK_SPI4 155 -#define ACLK_SPINLOCK 156 -#define PCLK_TSADC 157 -#define CLK_TSADC 158 -#define PCLK_UART1 159 -#define PCLK_UART2 160 -#define PCLK_UART3 161 -#define PCLK_UART4 162 -#define PCLK_UART5 163 -#define PCLK_UART6 164 -#define PCLK_UART7 165 -#define PCLK_UART8 166 -#define PCLK_UART9 167 -#define CLK_UART1_SRC 168 -#define CLK_UART1_FRAC 169 -#define CLK_UART1 170 -#define SCLK_UART1 171 -#define CLK_UART2_SRC 172 -#define CLK_UART2_FRAC 173 -#define CLK_UART2 174 -#define SCLK_UART2 175 -#define CLK_UART3_SRC 176 -#define CLK_UART3_FRAC 177 -#define CLK_UART3 178 -#define SCLK_UART3 179 -#define CLK_UART4_SRC 180 -#define CLK_UART4_FRAC 181 -#define CLK_UART4 182 -#define SCLK_UART4 183 -#define CLK_UART5_SRC 184 -#define CLK_UART5_FRAC 185 -#define CLK_UART5 186 -#define SCLK_UART5 187 -#define CLK_UART6_SRC 188 -#define CLK_UART6_FRAC 189 -#define CLK_UART6 190 -#define SCLK_UART6 191 -#define CLK_UART7_SRC 192 -#define CLK_UART7_FRAC 193 -#define CLK_UART7 194 -#define SCLK_UART7 195 -#define CLK_UART8_SRC 196 -#define CLK_UART8_FRAC 197 -#define CLK_UART8 198 -#define SCLK_UART8 199 -#define CLK_UART9_SRC 200 -#define CLK_UART9_FRAC 201 -#define CLK_UART9 202 -#define SCLK_UART9 203 -#define ACLK_CENTER_ROOT 204 -#define ACLK_CENTER_LOW_ROOT 205 -#define HCLK_CENTER_ROOT 206 -#define PCLK_CENTER_ROOT 207 -#define ACLK_DMA2DDR 208 -#define ACLK_DDR_SHAREMEM 209 -#define ACLK_CENTER_S200_ROOT 210 -#define ACLK_CENTER_S400_ROOT 211 -#define FCLK_DDR_CM0_CORE 212 -#define CLK_DDR_TIMER_ROOT 213 -#define CLK_DDR_TIMER0 214 -#define CLK_DDR_TIMER1 215 -#define TCLK_WDT_DDR 216 -#define CLK_DDR_CM0_RTC 217 -#define PCLK_WDT 218 -#define PCLK_TIMER 219 -#define PCLK_DMA2DDR 220 -#define PCLK_SHAREMEM 221 -#define CLK_50M_SRC 222 -#define CLK_100M_SRC 223 -#define CLK_150M_SRC 224 -#define CLK_200M_SRC 225 -#define CLK_250M_SRC 226 -#define CLK_300M_SRC 227 -#define CLK_350M_SRC 228 -#define CLK_400M_SRC 229 -#define CLK_450M_SRC 230 -#define CLK_500M_SRC 231 -#define CLK_600M_SRC 232 -#define CLK_650M_SRC 233 -#define CLK_700M_SRC 234 -#define CLK_800M_SRC 235 -#define CLK_1000M_SRC 236 -#define CLK_1200M_SRC 237 -#define ACLK_TOP_M300_ROOT 238 -#define ACLK_TOP_M500_ROOT 239 -#define ACLK_TOP_M400_ROOT 240 -#define ACLK_TOP_S200_ROOT 241 -#define ACLK_TOP_S400_ROOT 242 -#define CLK_MIPI_CAMARAOUT_M0 243 -#define CLK_MIPI_CAMARAOUT_M1 244 -#define CLK_MIPI_CAMARAOUT_M2 245 -#define CLK_MIPI_CAMARAOUT_M3 246 -#define CLK_MIPI_CAMARAOUT_M4 247 -#define MCLK_GMAC0_OUT 248 -#define REFCLKO25M_ETH0_OUT 249 -#define REFCLKO25M_ETH1_OUT 250 -#define CLK_CIFOUT_OUT 251 -#define PCLK_MIPI_DCPHY0 252 -#define PCLK_MIPI_DCPHY1 253 -#define PCLK_CSIPHY0 254 -#define PCLK_CSIPHY1 255 -#define ACLK_TOP_ROOT 256 -#define PCLK_TOP_ROOT 257 -#define ACLK_LOW_TOP_ROOT 258 -#define PCLK_CRU 259 -#define PCLK_GPU_ROOT 260 -#define CLK_GPU_SRC 261 -#define CLK_GPU 262 -#define CLK_GPU_COREGROUP 263 -#define CLK_GPU_STACKS 264 -#define PCLK_GPU_PVTM 265 -#define CLK_GPU_PVTM 266 -#define CLK_CORE_GPU_PVTM 267 -#define PCLK_GPU_GRF 268 -#define ACLK_ISP1_ROOT 269 -#define HCLK_ISP1_ROOT 270 -#define CLK_ISP1_CORE 271 -#define CLK_ISP1_CORE_MARVIN 272 -#define CLK_ISP1_CORE_VICAP 273 -#define ACLK_ISP1 274 -#define HCLK_ISP1 275 -#define ACLK_NPU1 276 -#define HCLK_NPU1 277 -#define ACLK_NPU2 278 -#define HCLK_NPU2 279 -#define HCLK_NPU_CM0_ROOT 280 -#define FCLK_NPU_CM0_CORE 281 -#define CLK_NPU_CM0_RTC 282 -#define PCLK_NPU_PVTM 283 -#define PCLK_NPU_GRF 284 -#define CLK_NPU_PVTM 285 -#define CLK_CORE_NPU_PVTM 286 -#define ACLK_NPU0 287 -#define HCLK_NPU0 288 -#define HCLK_NPU_ROOT 289 -#define CLK_NPU_DSU0 290 -#define PCLK_NPU_ROOT 291 -#define PCLK_NPU_TIMER 292 -#define CLK_NPUTIMER_ROOT 293 -#define CLK_NPUTIMER0 294 -#define CLK_NPUTIMER1 295 -#define PCLK_NPU_WDT 296 -#define TCLK_NPU_WDT 297 -#define HCLK_EMMC 298 -#define ACLK_EMMC 299 -#define CCLK_EMMC 300 -#define BCLK_EMMC 301 -#define TMCLK_EMMC 302 -#define SCLK_SFC 303 -#define HCLK_SFC 304 -#define HCLK_SFC_XIP 305 -#define HCLK_NVM_ROOT 306 -#define ACLK_NVM_ROOT 307 -#define CLK_GMAC0_PTP_REF 308 -#define CLK_GMAC1_PTP_REF 309 -#define CLK_GMAC_125M 310 -#define CLK_GMAC_50M 311 -#define ACLK_PHP_GIC_ITS 312 -#define ACLK_MMU_PCIE 313 -#define ACLK_MMU_PHP 314 -#define ACLK_PCIE_4L_DBI 315 -#define ACLK_PCIE_2L_DBI 316 -#define ACLK_PCIE_1L0_DBI 317 -#define ACLK_PCIE_1L1_DBI 318 -#define ACLK_PCIE_1L2_DBI 319 -#define ACLK_PCIE_4L_MSTR 320 -#define ACLK_PCIE_2L_MSTR 321 -#define ACLK_PCIE_1L0_MSTR 322 -#define ACLK_PCIE_1L1_MSTR 323 -#define ACLK_PCIE_1L2_MSTR 324 -#define ACLK_PCIE_4L_SLV 325 -#define ACLK_PCIE_2L_SLV 326 -#define ACLK_PCIE_1L0_SLV 327 -#define ACLK_PCIE_1L1_SLV 328 -#define ACLK_PCIE_1L2_SLV 329 -#define PCLK_PCIE_4L 330 -#define PCLK_PCIE_2L 331 -#define PCLK_PCIE_1L0 332 -#define PCLK_PCIE_1L1 333 -#define PCLK_PCIE_1L2 334 -#define CLK_PCIE_AUX0 335 -#define CLK_PCIE_AUX1 336 -#define CLK_PCIE_AUX2 337 -#define CLK_PCIE_AUX3 338 -#define CLK_PCIE_AUX4 339 -#define CLK_PIPEPHY0_REF 340 -#define CLK_PIPEPHY1_REF 341 -#define CLK_PIPEPHY2_REF 342 -#define PCLK_PHP_ROOT 343 -#define PCLK_GMAC0 344 -#define PCLK_GMAC1 345 -#define ACLK_PCIE_ROOT 346 -#define ACLK_PHP_ROOT 347 -#define ACLK_PCIE_BRIDGE 348 -#define ACLK_GMAC0 349 -#define ACLK_GMAC1 350 -#define CLK_PMALIVE0 351 -#define CLK_PMALIVE1 352 -#define CLK_PMALIVE2 353 -#define ACLK_SATA0 354 -#define ACLK_SATA1 355 -#define ACLK_SATA2 356 -#define CLK_RXOOB0 357 -#define CLK_RXOOB1 358 -#define CLK_RXOOB2 359 -#define ACLK_USB3OTG2 360 -#define SUSPEND_CLK_USB3OTG2 361 -#define REF_CLK_USB3OTG2 362 -#define CLK_UTMI_OTG2 363 -#define CLK_PIPEPHY0_PIPE_G 364 -#define CLK_PIPEPHY1_PIPE_G 365 -#define CLK_PIPEPHY2_PIPE_G 366 -#define CLK_PIPEPHY0_PIPE_ASIC_G 367 -#define CLK_PIPEPHY1_PIPE_ASIC_G 368 -#define CLK_PIPEPHY2_PIPE_ASIC_G 369 -#define CLK_PIPEPHY2_PIPE_U3_G 370 -#define CLK_PCIE1L2_PIPE 371 -#define CLK_PCIE4L_PIPE 372 -#define CLK_PCIE2L_PIPE 373 -#define PCLK_PCIE_COMBO_PIPE_PHY0 374 -#define PCLK_PCIE_COMBO_PIPE_PHY1 375 -#define PCLK_PCIE_COMBO_PIPE_PHY2 376 -#define PCLK_PCIE_COMBO_PIPE_PHY 377 -#define HCLK_RGA3_1 378 -#define ACLK_RGA3_1 379 -#define CLK_RGA3_1_CORE 380 -#define ACLK_RGA3_ROOT 381 -#define HCLK_RGA3_ROOT 382 -#define ACLK_RKVDEC_CCU 383 -#define HCLK_RKVDEC0 384 -#define ACLK_RKVDEC0 385 -#define CLK_RKVDEC0_CA 386 -#define CLK_RKVDEC0_HEVC_CA 387 -#define CLK_RKVDEC0_CORE 388 -#define HCLK_RKVDEC1 389 -#define ACLK_RKVDEC1 390 -#define CLK_RKVDEC1_CA 391 -#define CLK_RKVDEC1_HEVC_CA 392 -#define CLK_RKVDEC1_CORE 393 -#define HCLK_SDIO 394 -#define CCLK_SRC_SDIO 395 -#define ACLK_USB_ROOT 396 -#define HCLK_USB_ROOT 397 -#define HCLK_HOST0 398 -#define HCLK_HOST_ARB0 399 -#define HCLK_HOST1 400 -#define HCLK_HOST_ARB1 401 -#define ACLK_USB3OTG0 402 -#define SUSPEND_CLK_USB3OTG0 403 -#define REF_CLK_USB3OTG0 404 -#define ACLK_USB3OTG1 405 -#define SUSPEND_CLK_USB3OTG1 406 -#define REF_CLK_USB3OTG1 407 -#define UTMI_OHCI_CLK48_HOST0 408 -#define UTMI_OHCI_CLK48_HOST1 409 -#define HCLK_IEP2P0 410 -#define ACLK_IEP2P0 411 -#define CLK_IEP2P0_CORE 412 -#define ACLK_JPEG_ENCODER0 413 -#define HCLK_JPEG_ENCODER0 414 -#define ACLK_JPEG_ENCODER1 415 -#define HCLK_JPEG_ENCODER1 416 -#define ACLK_JPEG_ENCODER2 417 -#define HCLK_JPEG_ENCODER2 418 -#define ACLK_JPEG_ENCODER3 419 -#define HCLK_JPEG_ENCODER3 420 -#define ACLK_JPEG_DECODER 421 -#define HCLK_JPEG_DECODER 422 -#define HCLK_RGA2 423 -#define ACLK_RGA2 424 -#define CLK_RGA2_CORE 425 -#define HCLK_RGA3_0 426 -#define ACLK_RGA3_0 427 -#define CLK_RGA3_0_CORE 428 -#define ACLK_VDPU_ROOT 429 -#define ACLK_VDPU_LOW_ROOT 430 -#define HCLK_VDPU_ROOT 431 -#define ACLK_JPEG_DECODER_ROOT 432 -#define ACLK_VPU 433 -#define HCLK_VPU 434 -#define HCLK_RKVENC0_ROOT 435 -#define ACLK_RKVENC0_ROOT 436 -#define HCLK_RKVENC0 437 -#define ACLK_RKVENC0 438 -#define CLK_RKVENC0_CORE 439 -#define HCLK_RKVENC1_ROOT 440 -#define ACLK_RKVENC1_ROOT 441 -#define HCLK_RKVENC1 442 -#define ACLK_RKVENC1 443 -#define CLK_RKVENC1_CORE 444 -#define ICLK_CSIHOST01 445 -#define ICLK_CSIHOST0 446 -#define ICLK_CSIHOST1 447 -#define PCLK_CSI_HOST_0 448 -#define PCLK_CSI_HOST_1 449 -#define PCLK_CSI_HOST_2 450 -#define PCLK_CSI_HOST_3 451 -#define PCLK_CSI_HOST_4 452 -#define PCLK_CSI_HOST_5 453 -#define ACLK_FISHEYE0 454 -#define HCLK_FISHEYE0 455 -#define CLK_FISHEYE0_CORE 456 -#define ACLK_FISHEYE1 457 -#define HCLK_FISHEYE1 458 -#define CLK_FISHEYE1_CORE 459 -#define CLK_ISP0_CORE 460 -#define CLK_ISP0_CORE_MARVIN 461 -#define CLK_ISP0_CORE_VICAP 462 -#define ACLK_ISP0 463 -#define HCLK_ISP0 464 -#define ACLK_VI_ROOT 465 -#define HCLK_VI_ROOT 466 -#define PCLK_VI_ROOT 467 -#define DCLK_VICAP 468 -#define ACLK_VICAP 469 -#define HCLK_VICAP 470 -#define PCLK_DP0 471 -#define PCLK_DP1 472 -#define PCLK_S_DP0 473 -#define PCLK_S_DP1 474 -#define CLK_DP0 475 -#define CLK_DP1 476 -#define HCLK_HDCP_KEY0 477 -#define ACLK_HDCP0 478 -#define HCLK_HDCP0 479 -#define PCLK_HDCP0 480 -#define HCLK_I2S4_8CH 481 -#define ACLK_TRNG0 482 -#define PCLK_TRNG0 483 -#define ACLK_VO0_ROOT 484 -#define HCLK_VO0_ROOT 485 -#define HCLK_VO0_S_ROOT 486 -#define PCLK_VO0_ROOT 487 -#define PCLK_VO0_S_ROOT 488 -#define PCLK_VO0GRF 489 -#define CLK_I2S4_8CH_TX_SRC 490 -#define CLK_I2S4_8CH_TX_FRAC 491 -#define MCLK_I2S4_8CH_TX 492 -#define CLK_I2S4_8CH_TX 493 -#define HCLK_I2S8_8CH 494 -#define CLK_I2S8_8CH_TX_SRC 495 -#define CLK_I2S8_8CH_TX_FRAC 496 -#define MCLK_I2S8_8CH_TX 497 -#define CLK_I2S8_8CH_TX 498 -#define HCLK_SPDIF2_DP0 499 -#define CLK_SPDIF2_DP0_SRC 500 -#define CLK_SPDIF2_DP0_FRAC 501 -#define MCLK_SPDIF2_DP0 502 -#define CLK_SPDIF2_DP0 503 -#define MCLK_SPDIF2 504 -#define HCLK_SPDIF5_DP1 505 -#define CLK_SPDIF5_DP1_SRC 506 -#define CLK_SPDIF5_DP1_FRAC 507 -#define MCLK_SPDIF5_DP1 508 -#define CLK_SPDIF5_DP1 509 -#define MCLK_SPDIF5 510 -#define PCLK_EDP0 511 -#define CLK_EDP0_24M 512 -#define CLK_EDP0_200M 513 -#define PCLK_EDP1 514 -#define CLK_EDP1_24M 515 -#define CLK_EDP1_200M 516 -#define HCLK_HDCP_KEY1 517 -#define ACLK_HDCP1 518 -#define HCLK_HDCP1 519 -#define PCLK_HDCP1 520 -#define ACLK_HDMIRX 521 -#define PCLK_HDMIRX 522 -#define CLK_HDMIRX_REF 523 -#define CLK_HDMIRX_AUD_SRC 524 -#define CLK_HDMIRX_AUD_FRAC 525 -#define CLK_HDMIRX_AUD 526 -#define CLK_HDMIRX_AUD_P_MUX 527 -#define PCLK_HDMITX0 528 -#define CLK_HDMITX0_EARC 529 -#define CLK_HDMITX0_REF 530 -#define PCLK_HDMITX1 531 -#define CLK_HDMITX1_EARC 532 -#define CLK_HDMITX1_REF 533 -#define CLK_HDMITRX_REFSRC 534 -#define ACLK_TRNG1 535 -#define PCLK_TRNG1 536 -#define ACLK_HDCP1_ROOT 537 -#define ACLK_HDMIRX_ROOT 538 -#define HCLK_VO1_ROOT 539 -#define HCLK_VO1_S_ROOT 540 -#define PCLK_VO1_ROOT 541 -#define PCLK_VO1_S_ROOT 542 -#define PCLK_S_EDP0 543 -#define PCLK_S_EDP1 544 -#define PCLK_S_HDMIRX 545 -#define HCLK_I2S10_8CH 546 -#define CLK_I2S10_8CH_RX_SRC 547 -#define CLK_I2S10_8CH_RX_FRAC 548 -#define CLK_I2S10_8CH_RX 549 -#define MCLK_I2S10_8CH_RX 550 -#define HCLK_I2S7_8CH 551 -#define CLK_I2S7_8CH_RX_SRC 552 -#define CLK_I2S7_8CH_RX_FRAC 553 -#define CLK_I2S7_8CH_RX 554 -#define MCLK_I2S7_8CH_RX 555 -#define HCLK_I2S9_8CH 556 -#define CLK_I2S9_8CH_RX_SRC 557 -#define CLK_I2S9_8CH_RX_FRAC 558 -#define CLK_I2S9_8CH_RX 559 -#define MCLK_I2S9_8CH_RX 560 -#define CLK_I2S5_8CH_TX_SRC 561 -#define CLK_I2S5_8CH_TX_FRAC 562 -#define CLK_I2S5_8CH_TX 563 -#define MCLK_I2S5_8CH_TX 564 -#define HCLK_I2S5_8CH 565 -#define CLK_I2S6_8CH_TX_SRC 566 -#define CLK_I2S6_8CH_TX_FRAC 567 -#define CLK_I2S6_8CH_TX 568 -#define MCLK_I2S6_8CH_TX 569 -#define CLK_I2S6_8CH_RX_SRC 570 -#define CLK_I2S6_8CH_RX_FRAC 571 -#define CLK_I2S6_8CH_RX 572 -#define MCLK_I2S6_8CH_RX 573 -#define I2S6_8CH_MCLKOUT 574 -#define HCLK_I2S6_8CH 575 -#define HCLK_SPDIF3 576 -#define CLK_SPDIF3_SRC 577 -#define CLK_SPDIF3_FRAC 578 -#define CLK_SPDIF3 579 -#define MCLK_SPDIF3 580 -#define HCLK_SPDIF4 581 -#define CLK_SPDIF4_SRC 582 -#define CLK_SPDIF4_FRAC 583 -#define CLK_SPDIF4 584 -#define MCLK_SPDIF4 585 -#define HCLK_SPDIFRX0 586 -#define MCLK_SPDIFRX0 587 -#define HCLK_SPDIFRX1 588 -#define MCLK_SPDIFRX1 589 -#define HCLK_SPDIFRX2 590 -#define MCLK_SPDIFRX2 591 -#define ACLK_VO1USB_TOP_ROOT 592 -#define HCLK_VO1USB_TOP_ROOT 593 -#define CLK_HDMIHDP0 594 -#define CLK_HDMIHDP1 595 -#define PCLK_HDPTX0 596 -#define PCLK_HDPTX1 597 -#define PCLK_USBDPPHY0 598 -#define PCLK_USBDPPHY1 599 -#define ACLK_VOP_ROOT 600 -#define ACLK_VOP_LOW_ROOT 601 -#define HCLK_VOP_ROOT 602 -#define PCLK_VOP_ROOT 603 -#define HCLK_VOP 604 -#define ACLK_VOP 605 -#define DCLK_VOP0_SRC 606 -#define DCLK_VOP1_SRC 607 -#define DCLK_VOP2_SRC 608 -#define DCLK_VOP0 609 -#define DCLK_VOP1 610 -#define DCLK_VOP2 611 -#define DCLK_VOP3 612 -#define PCLK_DSIHOST0 613 -#define PCLK_DSIHOST1 614 -#define CLK_DSIHOST0 615 -#define CLK_DSIHOST1 616 -#define CLK_VOP_PMU 617 -#define ACLK_VOP_DOBY 618 -#define ACLK_VOP_SUB_SRC 619 -#define CLK_USBDP_PHY0_IMMORTAL 620 -#define CLK_USBDP_PHY1_IMMORTAL 621 -#define CLK_PMU0 622 -#define PCLK_PMU0 623 -#define PCLK_PMU0IOC 624 -#define PCLK_GPIO0 625 -#define DBCLK_GPIO0 626 -#define PCLK_I2C0 627 -#define CLK_I2C0 628 -#define HCLK_I2S1_8CH 629 -#define CLK_I2S1_8CH_TX_SRC 630 -#define CLK_I2S1_8CH_TX_FRAC 631 -#define CLK_I2S1_8CH_TX 632 -#define MCLK_I2S1_8CH_TX 633 -#define CLK_I2S1_8CH_RX_SRC 634 -#define CLK_I2S1_8CH_RX_FRAC 635 -#define CLK_I2S1_8CH_RX 636 -#define MCLK_I2S1_8CH_RX 637 -#define I2S1_8CH_MCLKOUT 638 -#define CLK_PMU1_50M_SRC 639 -#define CLK_PMU1_100M_SRC 640 -#define CLK_PMU1_200M_SRC 641 -#define CLK_PMU1_300M_SRC 642 -#define CLK_PMU1_400M_SRC 643 -#define HCLK_PMU1_ROOT 644 -#define PCLK_PMU1_ROOT 645 -#define PCLK_PMU0_ROOT 646 -#define HCLK_PMU_CM0_ROOT 647 -#define PCLK_PMU1 648 -#define CLK_DDR_FAIL_SAFE 649 -#define CLK_PMU1 650 -#define HCLK_PDM0 651 -#define MCLK_PDM0 652 -#define HCLK_VAD 653 -#define FCLK_PMU_CM0_CORE 654 -#define CLK_PMU_CM0_RTC 655 -#define PCLK_PMU1_IOC 656 -#define PCLK_PMU1PWM 657 -#define CLK_PMU1PWM 658 -#define CLK_PMU1PWM_CAPTURE 659 -#define PCLK_PMU1TIMER 660 -#define CLK_PMU1TIMER_ROOT 661 -#define CLK_PMU1TIMER0 662 -#define CLK_PMU1TIMER1 663 -#define CLK_UART0_SRC 664 -#define CLK_UART0_FRAC 665 -#define CLK_UART0 666 -#define SCLK_UART0 667 -#define PCLK_UART0 668 -#define PCLK_PMU1WDT 669 -#define TCLK_PMU1WDT 670 -#define CLK_CR_PARA 671 -#define CLK_USB2PHY_HDPTXRXPHY_REF 672 -#define CLK_USBDPPHY_MIPIDCPPHY_REF 673 -#define CLK_REF_PIPE_PHY0_OSC_SRC 674 -#define CLK_REF_PIPE_PHY1_OSC_SRC 675 -#define CLK_REF_PIPE_PHY2_OSC_SRC 676 -#define CLK_REF_PIPE_PHY0_PLL_SRC 677 -#define CLK_REF_PIPE_PHY1_PLL_SRC 678 -#define CLK_REF_PIPE_PHY2_PLL_SRC 679 -#define CLK_REF_PIPE_PHY0 680 -#define CLK_REF_PIPE_PHY1 681 -#define CLK_REF_PIPE_PHY2 682 -#define SCLK_SDIO_DRV 683 -#define SCLK_SDIO_SAMPLE 684 -#define SCLK_SDMMC_DRV 685 -#define SCLK_SDMMC_SAMPLE 686 -#define CLK_PCIE1L0_PIPE 687 -#define CLK_PCIE1L1_PIPE 688 -#define CLK_BIGCORE0_PVTM 689 -#define CLK_CORE_BIGCORE0_PVTM 690 -#define CLK_BIGCORE1_PVTM 691 -#define CLK_CORE_BIGCORE1_PVTM 692 -#define CLK_LITCORE_PVTM 693 -#define CLK_CORE_LITCORE_PVTM 694 -#define CLK_AUX16M_0 695 -#define CLK_AUX16M_1 696 -#define CLK_PHY0_REF_ALT_P 697 -#define CLK_PHY0_REF_ALT_M 698 -#define CLK_PHY1_REF_ALT_P 699 -#define CLK_PHY1_REF_ALT_M 700 -#define ACLK_ISP1_PRE 701 -#define HCLK_ISP1_PRE 702 -#define HCLK_NVM 703 -#define ACLK_USB 704 -#define HCLK_USB 705 -#define ACLK_JPEG_DECODER_PRE 706 -#define ACLK_VDPU_LOW_PRE 707 -#define ACLK_RKVENC1_PRE 708 -#define HCLK_RKVENC1_PRE 709 -#define HCLK_RKVDEC0_PRE 710 -#define ACLK_RKVDEC0_PRE 711 -#define HCLK_RKVDEC1_PRE 712 -#define ACLK_RKVDEC1_PRE 713 -#define ACLK_HDCP0_PRE 714 -#define HCLK_VO0 715 -#define ACLK_HDCP1_PRE 716 -#define HCLK_VO1 717 -#define ACLK_AV1_PRE 718 -#define PCLK_AV1_PRE 719 -#define HCLK_SDIO_PRE 720 -#define PCLK_VO1GRF 721 - -/* scmi-clocks indices */ - -#define SCMI_CLK_CPUL 0 -#define SCMI_CLK_DSU 1 -#define SCMI_CLK_CPUB01 2 -#define SCMI_CLK_CPUB23 3 -#define SCMI_CLK_DDR 4 -#define SCMI_CLK_GPU 5 -#define SCMI_CLK_NPU 6 -#define SCMI_CLK_SBUS 7 -#define SCMI_PCLK_SBUS 8 -#define SCMI_CCLK_SD 9 -#define SCMI_DCLK_SD 10 -#define SCMI_ACLK_SECURE_NS 11 -#define SCMI_HCLK_SECURE_NS 12 -#define SCMI_TCLK_WDT 13 -#define SCMI_KEYLADDER_CORE 14 -#define SCMI_KEYLADDER_RNG 15 -#define SCMI_ACLK_SECURE_S 16 -#define SCMI_HCLK_SECURE_S 17 -#define SCMI_PCLK_SECURE_S 18 -#define SCMI_CRYPTO_RNG 19 -#define SCMI_CRYPTO_CORE 20 -#define SCMI_CRYPTO_PKA 21 -#define SCMI_SPLL 22 -#define SCMI_HCLK_SD 23 - -#endif diff --git a/lede/target/linux/rockchip/files-5.15/include/dt-bindings/power/rk3588-power.h b/lede/target/linux/rockchip/files-5.15/include/dt-bindings/power/rk3588-power.h deleted file mode 100644 index 6b91a50cc6..0000000000 --- a/lede/target/linux/rockchip/files-5.15/include/dt-bindings/power/rk3588-power.h +++ /dev/null @@ -1,69 +0,0 @@ -/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ -#ifndef __DT_BINDINGS_POWER_RK3588_POWER_H__ -#define __DT_BINDINGS_POWER_RK3588_POWER_H__ - -/* VD_LITDSU */ -#define RK3588_PD_CPU_0 0 -#define RK3588_PD_CPU_1 1 -#define RK3588_PD_CPU_2 2 -#define RK3588_PD_CPU_3 3 - -/* VD_BIGCORE0 */ -#define RK3588_PD_CPU_4 4 -#define RK3588_PD_CPU_5 5 - -/* VD_BIGCORE1 */ -#define RK3588_PD_CPU_6 6 -#define RK3588_PD_CPU_7 7 - -/* VD_NPU */ -#define RK3588_PD_NPU 8 -#define RK3588_PD_NPUTOP 9 -#define RK3588_PD_NPU1 10 -#define RK3588_PD_NPU2 11 - -/* VD_GPU */ -#define RK3588_PD_GPU 12 - -/* VD_VCODEC */ -#define RK3588_PD_VCODEC 13 -#define RK3588_PD_RKVDEC0 14 -#define RK3588_PD_RKVDEC1 15 -#define RK3588_PD_VENC0 16 -#define RK3588_PD_VENC1 17 - -/* VD_DD01 */ -#define RK3588_PD_DDR01 18 - -/* VD_DD23 */ -#define RK3588_PD_DDR23 19 - -/* VD_LOGIC */ -#define RK3588_PD_CENTER 20 -#define RK3588_PD_VDPU 21 -#define RK3588_PD_RGA30 22 -#define RK3588_PD_AV1 23 -#define RK3588_PD_VOP 24 -#define RK3588_PD_VO0 25 -#define RK3588_PD_VO1 26 -#define RK3588_PD_VI 27 -#define RK3588_PD_ISP1 28 -#define RK3588_PD_FEC 29 -#define RK3588_PD_RGA31 30 -#define RK3588_PD_USB 31 -#define RK3588_PD_PHP 32 -#define RK3588_PD_GMAC 33 -#define RK3588_PD_PCIE 34 -#define RK3588_PD_NVM 35 -#define RK3588_PD_NVM0 36 -#define RK3588_PD_SDIO 37 -#define RK3588_PD_AUDIO 38 -#define RK3588_PD_SECURE 39 -#define RK3588_PD_SDMMC 40 -#define RK3588_PD_CRYPTO 41 -#define RK3588_PD_BUS 42 - -/* VD_PMU */ -#define RK3588_PD_PMU1 43 - -#endif diff --git a/lede/target/linux/rockchip/files-5.15/include/dt-bindings/reset/rockchip,rk3588-cru.h b/lede/target/linux/rockchip/files-5.15/include/dt-bindings/reset/rockchip,rk3588-cru.h deleted file mode 100644 index e2fe4bd5f7..0000000000 --- a/lede/target/linux/rockchip/files-5.15/include/dt-bindings/reset/rockchip,rk3588-cru.h +++ /dev/null @@ -1,756 +0,0 @@ -/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ -/* - * Copyright (c) 2021 Rockchip Electronics Co. Ltd. - * Copyright (c) 2022 Collabora Ltd. - * - * Author: Elaine Zhang - * Author: Sebastian Reichel - */ - -#ifndef _DT_BINDINGS_RESET_ROCKCHIP_RK3588_H -#define _DT_BINDINGS_RESET_ROCKCHIP_RK3588_H - -#define SRST_A_TOP_BIU 0 -#define SRST_P_TOP_BIU 1 -#define SRST_P_CSIPHY0 2 -#define SRST_CSIPHY0 3 -#define SRST_P_CSIPHY1 4 -#define SRST_CSIPHY1 5 -#define SRST_A_TOP_M500_BIU 6 - -#define SRST_A_TOP_M400_BIU 7 -#define SRST_A_TOP_S200_BIU 8 -#define SRST_A_TOP_S400_BIU 9 -#define SRST_A_TOP_M300_BIU 10 -#define SRST_USBDP_COMBO_PHY0_INIT 11 -#define SRST_USBDP_COMBO_PHY0_CMN 12 -#define SRST_USBDP_COMBO_PHY0_LANE 13 -#define SRST_USBDP_COMBO_PHY0_PCS 14 -#define SRST_USBDP_COMBO_PHY1_INIT 15 - -#define SRST_USBDP_COMBO_PHY1_CMN 16 -#define SRST_USBDP_COMBO_PHY1_LANE 17 -#define SRST_USBDP_COMBO_PHY1_PCS 18 -#define SRST_DCPHY0 19 -#define SRST_P_MIPI_DCPHY0 20 -#define SRST_P_MIPI_DCPHY0_GRF 21 - -#define SRST_DCPHY1 22 -#define SRST_P_MIPI_DCPHY1 23 -#define SRST_P_MIPI_DCPHY1_GRF 24 -#define SRST_P_APB2ASB_SLV_CDPHY 25 -#define SRST_P_APB2ASB_SLV_CSIPHY 26 -#define SRST_P_APB2ASB_SLV_VCCIO3_5 27 -#define SRST_P_APB2ASB_SLV_VCCIO6 28 -#define SRST_P_APB2ASB_SLV_EMMCIO 29 -#define SRST_P_APB2ASB_SLV_IOC_TOP 30 -#define SRST_P_APB2ASB_SLV_IOC_RIGHT 31 - -#define SRST_P_CRU 32 -#define SRST_A_CHANNEL_SECURE2VO1USB 33 -#define SRST_A_CHANNEL_SECURE2CENTER 34 -#define SRST_H_CHANNEL_SECURE2VO1USB 35 -#define SRST_H_CHANNEL_SECURE2CENTER 36 - -#define SRST_P_CHANNEL_SECURE2VO1USB 37 -#define SRST_P_CHANNEL_SECURE2CENTER 38 - -#define SRST_H_AUDIO_BIU 39 -#define SRST_P_AUDIO_BIU 40 -#define SRST_H_I2S0_8CH 41 -#define SRST_M_I2S0_8CH_TX 42 -#define SRST_M_I2S0_8CH_RX 43 -#define SRST_P_ACDCDIG 44 -#define SRST_H_I2S2_2CH 45 -#define SRST_H_I2S3_2CH 46 - -#define SRST_M_I2S2_2CH 47 -#define SRST_M_I2S3_2CH 48 -#define SRST_DAC_ACDCDIG 49 -#define SRST_H_SPDIF0 50 - -#define SRST_M_SPDIF0 51 -#define SRST_H_SPDIF1 52 -#define SRST_M_SPDIF1 53 -#define SRST_H_PDM1 54 -#define SRST_PDM1 55 - -#define SRST_A_BUS_BIU 56 -#define SRST_P_BUS_BIU 57 -#define SRST_A_GIC 58 -#define SRST_A_GIC_DBG 59 -#define SRST_A_DMAC0 60 -#define SRST_A_DMAC1 61 -#define SRST_A_DMAC2 62 -#define SRST_P_I2C1 63 -#define SRST_P_I2C2 64 -#define SRST_P_I2C3 65 -#define SRST_P_I2C4 66 -#define SRST_P_I2C5 67 -#define SRST_P_I2C6 68 -#define SRST_P_I2C7 69 -#define SRST_P_I2C8 70 - -#define SRST_I2C1 71 -#define SRST_I2C2 72 -#define SRST_I2C3 73 -#define SRST_I2C4 74 -#define SRST_I2C5 75 -#define SRST_I2C6 76 -#define SRST_I2C7 77 -#define SRST_I2C8 78 -#define SRST_P_CAN0 79 -#define SRST_CAN0 80 -#define SRST_P_CAN1 81 -#define SRST_CAN1 82 -#define SRST_P_CAN2 83 -#define SRST_CAN2 84 -#define SRST_P_SARADC 85 - -#define SRST_P_TSADC 86 -#define SRST_TSADC 87 -#define SRST_P_UART1 88 -#define SRST_P_UART2 89 -#define SRST_P_UART3 90 -#define SRST_P_UART4 91 -#define SRST_P_UART5 92 -#define SRST_P_UART6 93 -#define SRST_P_UART7 94 -#define SRST_P_UART8 95 -#define SRST_P_UART9 96 -#define SRST_S_UART1 97 - -#define SRST_S_UART2 98 -#define SRST_S_UART3 99 -#define SRST_S_UART4 100 -#define SRST_S_UART5 101 -#define SRST_S_UART6 102 -#define SRST_S_UART7 103 - -#define SRST_S_UART8 104 -#define SRST_S_UART9 105 -#define SRST_P_SPI0 106 -#define SRST_P_SPI1 107 -#define SRST_P_SPI2 108 -#define SRST_P_SPI3 109 -#define SRST_P_SPI4 110 -#define SRST_SPI0 111 -#define SRST_SPI1 112 -#define SRST_SPI2 113 -#define SRST_SPI3 114 -#define SRST_SPI4 115 - -#define SRST_P_WDT0 116 -#define SRST_T_WDT0 117 -#define SRST_P_SYS_GRF 118 -#define SRST_P_PWM1 119 -#define SRST_PWM1 120 -#define SRST_P_PWM2 121 -#define SRST_PWM2 122 -#define SRST_P_PWM3 123 -#define SRST_PWM3 124 -#define SRST_P_BUSTIMER0 125 -#define SRST_P_BUSTIMER1 126 -#define SRST_BUSTIMER0 127 - -#define SRST_BUSTIMER1 128 -#define SRST_BUSTIMER2 129 -#define SRST_BUSTIMER3 130 -#define SRST_BUSTIMER4 131 -#define SRST_BUSTIMER5 132 -#define SRST_BUSTIMER6 133 -#define SRST_BUSTIMER7 134 -#define SRST_BUSTIMER8 135 -#define SRST_BUSTIMER9 136 -#define SRST_BUSTIMER10 137 -#define SRST_BUSTIMER11 138 -#define SRST_P_MAILBOX0 139 -#define SRST_P_MAILBOX1 140 -#define SRST_P_MAILBOX2 141 -#define SRST_P_GPIO1 142 -#define SRST_GPIO1 143 - -#define SRST_P_GPIO2 144 -#define SRST_GPIO2 145 -#define SRST_P_GPIO3 146 -#define SRST_GPIO3 147 -#define SRST_P_GPIO4 148 -#define SRST_GPIO4 149 -#define SRST_A_DECOM 150 -#define SRST_P_DECOM 151 -#define SRST_D_DECOM 152 -#define SRST_P_TOP 153 -#define SRST_A_GICADB_GIC2CORE_BUS 154 -#define SRST_P_DFT2APB 155 -#define SRST_P_APB2ASB_MST_TOP 156 -#define SRST_P_APB2ASB_MST_CDPHY 157 -#define SRST_P_APB2ASB_MST_BOT_RIGHT 158 - -#define SRST_P_APB2ASB_MST_IOC_TOP 159 -#define SRST_P_APB2ASB_MST_IOC_RIGHT 160 -#define SRST_P_APB2ASB_MST_CSIPHY 161 -#define SRST_P_APB2ASB_MST_VCCIO3_5 162 -#define SRST_P_APB2ASB_MST_VCCIO6 163 -#define SRST_P_APB2ASB_MST_EMMCIO 164 -#define SRST_A_SPINLOCK 165 -#define SRST_P_OTPC_NS 166 -#define SRST_OTPC_NS 167 -#define SRST_OTPC_ARB 168 - -#define SRST_P_BUSIOC 169 -#define SRST_P_PMUCM0_INTMUX 170 -#define SRST_P_DDRCM0_INTMUX 171 - -#define SRST_P_DDR_DFICTL_CH0 172 -#define SRST_P_DDR_MON_CH0 173 -#define SRST_P_DDR_STANDBY_CH0 174 -#define SRST_P_DDR_UPCTL_CH0 175 -#define SRST_TM_DDR_MON_CH0 176 -#define SRST_P_DDR_GRF_CH01 177 -#define SRST_DFI_CH0 178 -#define SRST_SBR_CH0 179 -#define SRST_DDR_UPCTL_CH0 180 -#define SRST_DDR_DFICTL_CH0 181 -#define SRST_DDR_MON_CH0 182 -#define SRST_DDR_STANDBY_CH0 183 -#define SRST_A_DDR_UPCTL_CH0 184 -#define SRST_P_DDR_DFICTL_CH1 185 -#define SRST_P_DDR_MON_CH1 186 -#define SRST_P_DDR_STANDBY_CH1 187 - -#define SRST_P_DDR_UPCTL_CH1 188 -#define SRST_TM_DDR_MON_CH1 189 -#define SRST_DFI_CH1 190 -#define SRST_SBR_CH1 191 -#define SRST_DDR_UPCTL_CH1 192 -#define SRST_DDR_DFICTL_CH1 193 -#define SRST_DDR_MON_CH1 194 -#define SRST_DDR_STANDBY_CH1 195 -#define SRST_A_DDR_UPCTL_CH1 196 -#define SRST_A_DDR01_MSCH0 197 -#define SRST_A_DDR01_RS_MSCH0 198 -#define SRST_A_DDR01_FRS_MSCH0 199 - -#define SRST_A_DDR01_SCRAMBLE0 200 -#define SRST_A_DDR01_FRS_SCRAMBLE0 201 -#define SRST_A_DDR01_MSCH1 202 -#define SRST_A_DDR01_RS_MSCH1 203 -#define SRST_A_DDR01_FRS_MSCH1 204 -#define SRST_A_DDR01_SCRAMBLE1 205 -#define SRST_A_DDR01_FRS_SCRAMBLE1 206 -#define SRST_P_DDR01_MSCH0 207 -#define SRST_P_DDR01_MSCH1 208 - -#define SRST_P_DDR_DFICTL_CH2 209 -#define SRST_P_DDR_MON_CH2 210 -#define SRST_P_DDR_STANDBY_CH2 211 -#define SRST_P_DDR_UPCTL_CH2 212 -#define SRST_TM_DDR_MON_CH2 213 -#define SRST_P_DDR_GRF_CH23 214 -#define SRST_DFI_CH2 215 -#define SRST_SBR_CH2 216 -#define SRST_DDR_UPCTL_CH2 217 -#define SRST_DDR_DFICTL_CH2 218 -#define SRST_DDR_MON_CH2 219 -#define SRST_DDR_STANDBY_CH2 220 -#define SRST_A_DDR_UPCTL_CH2 221 -#define SRST_P_DDR_DFICTL_CH3 222 -#define SRST_P_DDR_MON_CH3 223 -#define SRST_P_DDR_STANDBY_CH3 224 - -#define SRST_P_DDR_UPCTL_CH3 225 -#define SRST_TM_DDR_MON_CH3 226 -#define SRST_DFI_CH3 227 -#define SRST_SBR_CH3 228 -#define SRST_DDR_UPCTL_CH3 229 -#define SRST_DDR_DFICTL_CH3 230 -#define SRST_DDR_MON_CH3 231 -#define SRST_DDR_STANDBY_CH3 232 -#define SRST_A_DDR_UPCTL_CH3 233 -#define SRST_A_DDR23_MSCH2 234 -#define SRST_A_DDR23_RS_MSCH2 235 -#define SRST_A_DDR23_FRS_MSCH2 236 - -#define SRST_A_DDR23_SCRAMBLE2 237 -#define SRST_A_DDR23_FRS_SCRAMBLE2 238 -#define SRST_A_DDR23_MSCH3 239 -#define SRST_A_DDR23_RS_MSCH3 240 -#define SRST_A_DDR23_FRS_MSCH3 241 -#define SRST_A_DDR23_SCRAMBLE3 242 -#define SRST_A_DDR23_FRS_SCRAMBLE3 243 -#define SRST_P_DDR23_MSCH2 244 -#define SRST_P_DDR23_MSCH3 245 - -#define SRST_ISP1 246 -#define SRST_ISP1_VICAP 247 -#define SRST_A_ISP1_BIU 248 -#define SRST_H_ISP1_BIU 249 - -#define SRST_A_RKNN1 250 -#define SRST_A_RKNN1_BIU 251 -#define SRST_H_RKNN1 252 -#define SRST_H_RKNN1_BIU 253 - -#define SRST_A_RKNN2 254 -#define SRST_A_RKNN2_BIU 255 -#define SRST_H_RKNN2 256 -#define SRST_H_RKNN2_BIU 257 - -#define SRST_A_RKNN_DSU0 258 -#define SRST_P_NPUTOP_BIU 259 -#define SRST_P_NPU_TIMER 260 -#define SRST_NPUTIMER0 261 -#define SRST_NPUTIMER1 262 -#define SRST_P_NPU_WDT 263 -#define SRST_T_NPU_WDT 264 -#define SRST_P_NPU_PVTM 265 -#define SRST_P_NPU_GRF 266 -#define SRST_NPU_PVTM 267 - -#define SRST_NPU_PVTPLL 268 -#define SRST_H_NPU_CM0_BIU 269 -#define SRST_F_NPU_CM0_CORE 270 -#define SRST_T_NPU_CM0_JTAG 271 -#define SRST_A_RKNN0 272 -#define SRST_A_RKNN0_BIU 273 -#define SRST_H_RKNN0 274 -#define SRST_H_RKNN0_BIU 275 - -#define SRST_H_NVM_BIU 276 -#define SRST_A_NVM_BIU 277 -#define SRST_H_EMMC 278 -#define SRST_A_EMMC 279 -#define SRST_C_EMMC 280 -#define SRST_B_EMMC 281 -#define SRST_T_EMMC 282 -#define SRST_S_SFC 283 -#define SRST_H_SFC 284 -#define SRST_H_SFC_XIP 285 - -#define SRST_P_GRF 286 -#define SRST_P_DEC_BIU 287 -#define SRST_P_PHP_BIU 288 -#define SRST_A_PCIE_GRIDGE 289 -#define SRST_A_PHP_BIU 290 -#define SRST_A_GMAC0 291 -#define SRST_A_GMAC1 292 -#define SRST_A_PCIE_BIU 293 -#define SRST_PCIE0_POWER_UP 294 -#define SRST_PCIE1_POWER_UP 295 -#define SRST_PCIE2_POWER_UP 296 - -#define SRST_PCIE3_POWER_UP 297 -#define SRST_PCIE4_POWER_UP 298 -#define SRST_P_PCIE0 299 -#define SRST_P_PCIE1 300 -#define SRST_P_PCIE2 301 -#define SRST_P_PCIE3 302 - -#define SRST_P_PCIE4 303 -#define SRST_A_PHP_GIC_ITS 304 -#define SRST_A_MMU_PCIE 305 -#define SRST_A_MMU_PHP 306 -#define SRST_A_MMU_BIU 307 - -#define SRST_A_USB3OTG2 308 - -#define SRST_PMALIVE0 309 -#define SRST_PMALIVE1 310 -#define SRST_PMALIVE2 311 -#define SRST_A_SATA0 312 -#define SRST_A_SATA1 313 -#define SRST_A_SATA2 314 -#define SRST_RXOOB0 315 -#define SRST_RXOOB1 316 -#define SRST_RXOOB2 317 -#define SRST_ASIC0 318 -#define SRST_ASIC1 319 -#define SRST_ASIC2 320 - -#define SRST_A_RKVDEC_CCU 321 -#define SRST_H_RKVDEC0 322 -#define SRST_A_RKVDEC0 323 -#define SRST_H_RKVDEC0_BIU 324 -#define SRST_A_RKVDEC0_BIU 325 -#define SRST_RKVDEC0_CA 326 -#define SRST_RKVDEC0_HEVC_CA 327 -#define SRST_RKVDEC0_CORE 328 - -#define SRST_H_RKVDEC1 329 -#define SRST_A_RKVDEC1 330 -#define SRST_H_RKVDEC1_BIU 331 -#define SRST_A_RKVDEC1_BIU 332 -#define SRST_RKVDEC1_CA 333 -#define SRST_RKVDEC1_HEVC_CA 334 -#define SRST_RKVDEC1_CORE 335 - -#define SRST_A_USB_BIU 336 -#define SRST_H_USB_BIU 337 -#define SRST_A_USB3OTG0 338 -#define SRST_A_USB3OTG1 339 -#define SRST_H_HOST0 340 -#define SRST_H_HOST_ARB0 341 -#define SRST_H_HOST1 342 -#define SRST_H_HOST_ARB1 343 -#define SRST_A_USB_GRF 344 -#define SRST_C_USB2P0_HOST0 345 - -#define SRST_C_USB2P0_HOST1 346 -#define SRST_HOST_UTMI0 347 -#define SRST_HOST_UTMI1 348 - -#define SRST_A_VDPU_BIU 349 -#define SRST_A_VDPU_LOW_BIU 350 -#define SRST_H_VDPU_BIU 351 -#define SRST_A_JPEG_DECODER_BIU 352 -#define SRST_A_VPU 353 -#define SRST_H_VPU 354 -#define SRST_A_JPEG_ENCODER0 355 -#define SRST_H_JPEG_ENCODER0 356 -#define SRST_A_JPEG_ENCODER1 357 -#define SRST_H_JPEG_ENCODER1 358 -#define SRST_A_JPEG_ENCODER2 359 -#define SRST_H_JPEG_ENCODER2 360 - -#define SRST_A_JPEG_ENCODER3 361 -#define SRST_H_JPEG_ENCODER3 362 -#define SRST_A_JPEG_DECODER 363 -#define SRST_H_JPEG_DECODER 364 -#define SRST_H_IEP2P0 365 -#define SRST_A_IEP2P0 366 -#define SRST_IEP2P0_CORE 367 -#define SRST_H_RGA2 368 -#define SRST_A_RGA2 369 -#define SRST_RGA2_CORE 370 -#define SRST_H_RGA3_0 371 -#define SRST_A_RGA3_0 372 -#define SRST_RGA3_0_CORE 373 - -#define SRST_H_RKVENC0_BIU 374 -#define SRST_A_RKVENC0_BIU 375 -#define SRST_H_RKVENC0 376 -#define SRST_A_RKVENC0 377 -#define SRST_RKVENC0_CORE 378 - -#define SRST_H_RKVENC1_BIU 379 -#define SRST_A_RKVENC1_BIU 380 -#define SRST_H_RKVENC1 381 -#define SRST_A_RKVENC1 382 -#define SRST_RKVENC1_CORE 383 - -#define SRST_A_VI_BIU 384 -#define SRST_H_VI_BIU 385 -#define SRST_P_VI_BIU 386 -#define SRST_D_VICAP 387 -#define SRST_A_VICAP 388 -#define SRST_H_VICAP 389 -#define SRST_ISP0 390 -#define SRST_ISP0_VICAP 391 - -#define SRST_FISHEYE0 392 -#define SRST_FISHEYE1 393 -#define SRST_P_CSI_HOST_0 394 -#define SRST_P_CSI_HOST_1 395 -#define SRST_P_CSI_HOST_2 396 -#define SRST_P_CSI_HOST_3 397 -#define SRST_P_CSI_HOST_4 398 -#define SRST_P_CSI_HOST_5 399 - -#define SRST_CSIHOST0_VICAP 400 -#define SRST_CSIHOST1_VICAP 401 -#define SRST_CSIHOST2_VICAP 402 -#define SRST_CSIHOST3_VICAP 403 -#define SRST_CSIHOST4_VICAP 404 -#define SRST_CSIHOST5_VICAP 405 -#define SRST_CIFIN 406 - -#define SRST_A_VOP_BIU 407 -#define SRST_A_VOP_LOW_BIU 408 -#define SRST_H_VOP_BIU 409 -#define SRST_P_VOP_BIU 410 -#define SRST_H_VOP 411 -#define SRST_A_VOP 412 -#define SRST_D_VOP0 413 -#define SRST_D_VOP2HDMI_BRIDGE0 414 -#define SRST_D_VOP2HDMI_BRIDGE1 415 - -#define SRST_D_VOP1 416 -#define SRST_D_VOP2 417 -#define SRST_D_VOP3 418 -#define SRST_P_VOPGRF 419 -#define SRST_P_DSIHOST0 420 -#define SRST_P_DSIHOST1 421 -#define SRST_DSIHOST0 422 -#define SRST_DSIHOST1 423 -#define SRST_VOP_PMU 424 -#define SRST_P_VOP_CHANNEL_BIU 425 - -#define SRST_H_VO0_BIU 426 -#define SRST_H_VO0_S_BIU 427 -#define SRST_P_VO0_BIU 428 -#define SRST_P_VO0_S_BIU 429 -#define SRST_A_HDCP0_BIU 430 -#define SRST_P_VO0GRF 431 -#define SRST_H_HDCP_KEY0 432 -#define SRST_A_HDCP0 433 -#define SRST_H_HDCP0 434 -#define SRST_HDCP0 435 - -#define SRST_P_TRNG0 436 -#define SRST_DP0 437 -#define SRST_DP1 438 -#define SRST_H_I2S4_8CH 439 -#define SRST_M_I2S4_8CH_TX 440 -#define SRST_H_I2S8_8CH 441 - -#define SRST_M_I2S8_8CH_TX 442 -#define SRST_H_SPDIF2_DP0 443 -#define SRST_M_SPDIF2_DP0 444 -#define SRST_H_SPDIF5_DP1 445 -#define SRST_M_SPDIF5_DP1 446 - -#define SRST_A_HDCP1_BIU 447 -#define SRST_A_VO1_BIU 448 -#define SRST_H_VOP1_BIU 449 -#define SRST_H_VOP1_S_BIU 450 -#define SRST_P_VOP1_BIU 451 -#define SRST_P_VO1GRF 452 -#define SRST_P_VO1_S_BIU 453 - -#define SRST_H_I2S7_8CH 454 -#define SRST_M_I2S7_8CH_RX 455 -#define SRST_H_HDCP_KEY1 456 -#define SRST_A_HDCP1 457 -#define SRST_H_HDCP1 458 -#define SRST_HDCP1 459 -#define SRST_P_TRNG1 460 -#define SRST_P_HDMITX0 461 - -#define SRST_HDMITX0_REF 462 -#define SRST_P_HDMITX1 463 -#define SRST_HDMITX1_REF 464 -#define SRST_A_HDMIRX 465 -#define SRST_P_HDMIRX 466 -#define SRST_HDMIRX_REF 467 - -#define SRST_P_EDP0 468 -#define SRST_EDP0_24M 469 -#define SRST_P_EDP1 470 -#define SRST_EDP1_24M 471 -#define SRST_M_I2S5_8CH_TX 472 -#define SRST_H_I2S5_8CH 473 -#define SRST_M_I2S6_8CH_TX 474 - -#define SRST_M_I2S6_8CH_RX 475 -#define SRST_H_I2S6_8CH 476 -#define SRST_H_SPDIF3 477 -#define SRST_M_SPDIF3 478 -#define SRST_H_SPDIF4 479 -#define SRST_M_SPDIF4 480 -#define SRST_H_SPDIFRX0 481 -#define SRST_M_SPDIFRX0 482 -#define SRST_H_SPDIFRX1 483 -#define SRST_M_SPDIFRX1 484 - -#define SRST_H_SPDIFRX2 485 -#define SRST_M_SPDIFRX2 486 -#define SRST_LINKSYM_HDMITXPHY0 487 -#define SRST_LINKSYM_HDMITXPHY1 488 -#define SRST_VO1_BRIDGE0 489 -#define SRST_VO1_BRIDGE1 490 - -#define SRST_H_I2S9_8CH 491 -#define SRST_M_I2S9_8CH_RX 492 -#define SRST_H_I2S10_8CH 493 -#define SRST_M_I2S10_8CH_RX 494 -#define SRST_P_S_HDMIRX 495 - -#define SRST_GPU 496 -#define SRST_SYS_GPU 497 -#define SRST_A_S_GPU_BIU 498 -#define SRST_A_M0_GPU_BIU 499 -#define SRST_A_M1_GPU_BIU 500 -#define SRST_A_M2_GPU_BIU 501 -#define SRST_A_M3_GPU_BIU 502 -#define SRST_P_GPU_BIU 503 -#define SRST_P_GPU_PVTM 504 - -#define SRST_GPU_PVTM 505 -#define SRST_P_GPU_GRF 506 -#define SRST_GPU_PVTPLL 507 -#define SRST_GPU_JTAG 508 - -#define SRST_A_AV1_BIU 509 -#define SRST_A_AV1 510 -#define SRST_P_AV1_BIU 511 -#define SRST_P_AV1 512 - -#define SRST_A_DDR_BIU 513 -#define SRST_A_DMA2DDR 514 -#define SRST_A_DDR_SHAREMEM 515 -#define SRST_A_DDR_SHAREMEM_BIU 516 -#define SRST_A_CENTER_S200_BIU 517 -#define SRST_A_CENTER_S400_BIU 518 -#define SRST_H_AHB2APB 519 -#define SRST_H_CENTER_BIU 520 -#define SRST_F_DDR_CM0_CORE 521 - -#define SRST_DDR_TIMER0 522 -#define SRST_DDR_TIMER1 523 -#define SRST_T_WDT_DDR 524 -#define SRST_T_DDR_CM0_JTAG 525 -#define SRST_P_CENTER_GRF 526 -#define SRST_P_AHB2APB 527 -#define SRST_P_WDT 528 -#define SRST_P_TIMER 529 -#define SRST_P_DMA2DDR 530 -#define SRST_P_SHAREMEM 531 -#define SRST_P_CENTER_BIU 532 -#define SRST_P_CENTER_CHANNEL_BIU 533 - -#define SRST_P_USBDPGRF0 534 -#define SRST_P_USBDPPHY0 535 -#define SRST_P_USBDPGRF1 536 -#define SRST_P_USBDPPHY1 537 -#define SRST_P_HDPTX0 538 -#define SRST_P_HDPTX1 539 -#define SRST_P_APB2ASB_SLV_BOT_RIGHT 540 -#define SRST_P_USB2PHY_U3_0_GRF0 541 -#define SRST_P_USB2PHY_U3_1_GRF0 542 -#define SRST_P_USB2PHY_U2_0_GRF0 543 -#define SRST_P_USB2PHY_U2_1_GRF0 544 -#define SRST_HDPTX0_ROPLL 545 -#define SRST_HDPTX0_LCPLL 546 -#define SRST_HDPTX0 547 -#define SRST_HDPTX1_ROPLL 548 - -#define SRST_HDPTX1_LCPLL 549 -#define SRST_HDPTX1 550 -#define SRST_HDPTX0_HDMIRXPHY_SET 551 -#define SRST_USBDP_COMBO_PHY0 552 -#define SRST_USBDP_COMBO_PHY0_LCPLL 553 -#define SRST_USBDP_COMBO_PHY0_ROPLL 554 -#define SRST_USBDP_COMBO_PHY0_PCS_HS 555 -#define SRST_USBDP_COMBO_PHY1 556 -#define SRST_USBDP_COMBO_PHY1_LCPLL 557 -#define SRST_USBDP_COMBO_PHY1_ROPLL 558 -#define SRST_USBDP_COMBO_PHY1_PCS_HS 559 -#define SRST_HDMIHDP0 560 -#define SRST_HDMIHDP1 561 - -#define SRST_A_VO1USB_TOP_BIU 562 -#define SRST_H_VO1USB_TOP_BIU 563 - -#define SRST_H_SDIO_BIU 564 -#define SRST_H_SDIO 565 -#define SRST_SDIO 566 - -#define SRST_H_RGA3_BIU 567 -#define SRST_A_RGA3_BIU 568 -#define SRST_H_RGA3_1 569 -#define SRST_A_RGA3_1 570 -#define SRST_RGA3_1_CORE 571 - -#define SRST_REF_PIPE_PHY0 572 -#define SRST_REF_PIPE_PHY1 573 -#define SRST_REF_PIPE_PHY2 574 - -#define SRST_P_PHPTOP_CRU 575 -#define SRST_P_PCIE2_GRF0 576 -#define SRST_P_PCIE2_GRF1 577 -#define SRST_P_PCIE2_GRF2 578 -#define SRST_P_PCIE2_PHY0 579 -#define SRST_P_PCIE2_PHY1 580 -#define SRST_P_PCIE2_PHY2 581 -#define SRST_P_PCIE3_PHY 582 -#define SRST_P_APB2ASB_SLV_CHIP_TOP 583 -#define SRST_PCIE30_PHY 584 - -#define SRST_H_PMU1_BIU 585 -#define SRST_P_PMU1_BIU 586 -#define SRST_H_PMU_CM0_BIU 587 -#define SRST_F_PMU_CM0_CORE 588 -#define SRST_T_PMU1_CM0_JTAG 589 - -#define SRST_DDR_FAIL_SAFE 590 -#define SRST_P_CRU_PMU1 591 -#define SRST_P_PMU1_GRF 592 -#define SRST_P_PMU1_IOC 593 -#define SRST_P_PMU1WDT 594 -#define SRST_T_PMU1WDT 595 -#define SRST_P_PMU1TIMER 596 -#define SRST_PMU1TIMER0 597 -#define SRST_PMU1TIMER1 598 -#define SRST_P_PMU1PWM 599 -#define SRST_PMU1PWM 600 - -#define SRST_P_I2C0 601 -#define SRST_I2C0 602 -#define SRST_S_UART0 603 -#define SRST_P_UART0 604 -#define SRST_H_I2S1_8CH 605 -#define SRST_M_I2S1_8CH_TX 606 -#define SRST_M_I2S1_8CH_RX 607 -#define SRST_H_PDM0 608 -#define SRST_PDM0 609 - -#define SRST_H_VAD 610 -#define SRST_HDPTX0_INIT 611 -#define SRST_HDPTX0_CMN 612 -#define SRST_HDPTX0_LANE 613 -#define SRST_HDPTX1_INIT 614 - -#define SRST_HDPTX1_CMN 615 -#define SRST_HDPTX1_LANE 616 -#define SRST_M_MIPI_DCPHY0 617 -#define SRST_S_MIPI_DCPHY0 618 -#define SRST_M_MIPI_DCPHY1 619 -#define SRST_S_MIPI_DCPHY1 620 -#define SRST_OTGPHY_U3_0 621 -#define SRST_OTGPHY_U3_1 622 -#define SRST_OTGPHY_U2_0 623 -#define SRST_OTGPHY_U2_1 624 - -#define SRST_P_PMU0GRF 625 -#define SRST_P_PMU0IOC 626 -#define SRST_P_GPIO0 627 -#define SRST_GPIO0 628 - -#define SRST_A_SECURE_NS_BIU 629 -#define SRST_H_SECURE_NS_BIU 630 -#define SRST_A_SECURE_S_BIU 631 -#define SRST_H_SECURE_S_BIU 632 -#define SRST_P_SECURE_S_BIU 633 -#define SRST_CRYPTO_CORE 634 - -#define SRST_CRYPTO_PKA 635 -#define SRST_CRYPTO_RNG 636 -#define SRST_A_CRYPTO 637 -#define SRST_H_CRYPTO 638 -#define SRST_KEYLADDER_CORE 639 -#define SRST_KEYLADDER_RNG 640 -#define SRST_A_KEYLADDER 641 -#define SRST_H_KEYLADDER 642 -#define SRST_P_OTPC_S 643 -#define SRST_OTPC_S 644 -#define SRST_WDT_S 645 - -#define SRST_T_WDT_S 646 -#define SRST_H_BOOTROM 647 -#define SRST_A_DCF 648 -#define SRST_P_DCF 649 -#define SRST_H_BOOTROM_NS 650 -#define SRST_P_KEYLADDER 651 -#define SRST_H_TRNG_S 652 - -#define SRST_H_TRNG_NS 653 -#define SRST_D_SDMMC_BUFFER 654 -#define SRST_H_SDMMC 655 -#define SRST_H_SDMMC_BUFFER 656 -#define SRST_SDMMC 657 -#define SRST_P_TRNG_CHK 658 -#define SRST_TRNG_S 659 - -#define SRST_A_HDMIRX_BIU 660 - -#endif diff --git a/lede/target/linux/rockchip/files/arch/arm64/boot/dts/rockchip/rk3399-king3399.dts b/lede/target/linux/rockchip/files/arch/arm64/boot/dts/rockchip/rk3399-king3399.dts old mode 100755 new mode 100644 diff --git a/lede/target/linux/rockchip/files/arch/arm64/boot/dts/rockchip/rk3566-panther-x2.dts b/lede/target/linux/rockchip/files/arch/arm64/boot/dts/rockchip/rk3566-panther-x2.dts old mode 100755 new mode 100644 diff --git a/lede/target/linux/rockchip/files/arch/arm64/boot/dts/rockchip/rk3588-armsom-sige7.dts b/lede/target/linux/rockchip/files/arch/arm64/boot/dts/rockchip/rk3588-armsom-sige7.dts index b555a29998..7393d6b6c5 100644 --- a/lede/target/linux/rockchip/files/arch/arm64/boot/dts/rockchip/rk3588-armsom-sige7.dts +++ b/lede/target/linux/rockchip/files/arch/arm64/boot/dts/rockchip/rk3588-armsom-sige7.dts @@ -362,19 +362,6 @@ &pcie2x1l0 { reset-gpios = <&gpio4 RK_PA5 GPIO_ACTIVE_HIGH>; status = "okay"; - - pcie@0,0 { - reg = <0x00200000 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - - rtl8125_1: pcie@20,0 { - compatible = "pci10ec,8125"; - reg = <0x000000 0 0 0 0>; - - realtek,led-data = <0x0 0x2b 0x200 0x0>; - }; - }; }; &pcie2x1l1 { @@ -404,19 +391,6 @@ &pcie2x1l2 { reset-gpios = <&gpio3 RK_PB0 GPIO_ACTIVE_HIGH>; status = "okay"; - - pcie@0,0 { - reg = <0x00400000 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - - rtl8125_2: pcie@40,0 { - compatible = "pci10ec,8125"; - reg = <0x000000 0 0 0 0>; - - realtek,led-data = <0x0 0x2b 0x200 0x0>; - }; - }; }; &pcie30phy { diff --git a/lede/target/linux/rockchip/patches-5.15/996-rockchip-add-disable-display-subsystem-node.patch b/lede/target/linux/rockchip/patches-5.15/996-rockchip-add-disable-display-subsystem-node.patch deleted file mode 100644 index 5d9c252278..0000000000 --- a/lede/target/linux/rockchip/patches-5.15/996-rockchip-add-disable-display-subsystem-node.patch +++ /dev/null @@ -1,210 +0,0 @@ ---- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi -@@ -128,6 +128,11 @@ - opp-microvolt = <1050000 1050000 1150000>; - }; - }; -+ -+ display_subsystem: display-subsystem { -+ compatible = "rockchip,display-subsystem"; -+ ports = <&vop_out>; -+ }; - - firmware { - scmi: scmi { -@@ -143,6 +148,56 @@ - }; - }; - }; -+ -+ gpu_opp_table: opp-table-1 { -+ compatible = "operating-points-v2"; -+ -+ opp-200000000 { -+ opp-hz = /bits/ 64 <200000000>; -+ opp-microvolt = <850000 850000 1000000>; -+ }; -+ -+ opp-300000000 { -+ opp-hz = /bits/ 64 <300000000>; -+ opp-microvolt = <850000 850000 1000000>; -+ }; -+ -+ opp-400000000 { -+ opp-hz = /bits/ 64 <400000000>; -+ opp-microvolt = <850000 850000 1000000>; -+ }; -+ -+ opp-600000000 { -+ opp-hz = /bits/ 64 <600000000>; -+ opp-microvolt = <900000 900000 1000000>; -+ }; -+ -+ opp-700000000 { -+ opp-hz = /bits/ 64 <700000000>; -+ opp-microvolt = <950000 950000 1000000>; -+ }; -+ -+ opp-800000000 { -+ opp-hz = /bits/ 64 <800000000>; -+ opp-microvolt = <1000000 1000000 1000000>; -+ }; -+ }; -+ -+ hdmi_sound: hdmi-sound { -+ compatible = "simple-audio-card"; -+ simple-audio-card,name = "HDMI"; -+ simple-audio-card,format = "i2s"; -+ simple-audio-card,mclk-fs = <256>; -+ status = "disabled"; -+ -+ simple-audio-card,codec { -+ sound-dai = <&hdmi>; -+ }; -+ -+ simple-audio-card,cpu { -+ sound-dai = <&i2s0_8ch>; -+ }; -+ }; - - pmu { - compatible = "arm,cortex-a55-pmu"; -@@ -535,6 +590,21 @@ - }; - }; - }; -+ -+ gpu: gpu@fde60000 { -+ compatible = "rockchip,rk3568-mali", "arm,mali-bifrost"; -+ reg = <0x0 0xfde60000 0x0 0x4000>; -+ interrupts = , -+ , -+ ; -+ interrupt-names = "job", "mmu", "gpu"; -+ clocks = <&scmi_clk 1>, <&cru CLK_GPU>; -+ clock-names = "gpu", "bus"; -+ #cooling-cells = <2>; -+ operating-points-v2 = <&gpu_opp_table>; -+ power-domains = <&power RK3568_PD_GPU>; -+ status = "disabled"; -+ }; - - sdmmc2: mmc@fe000000 { - compatible = "rockchip,rk3568-dw-mshc", "rockchip,rk3288-dw-mshc"; -@@ -596,6 +666,53 @@ - queue0 {}; - }; - }; -+ -+ vop: vop@fe040000 { -+ reg = <0x0 0xfe040000 0x0 0x3000>, <0x0 0xfe044000 0x0 0x1000>; -+ reg-names = "vop", "gamma-lut"; -+ interrupts = ; -+ clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>, <&cru DCLK_VOP0>, -+ <&cru DCLK_VOP1>, <&cru DCLK_VOP2>; -+ clock-names = "aclk", "hclk", "dclk_vp0", "dclk_vp1", "dclk_vp2"; -+ iommus = <&vop_mmu>; -+ power-domains = <&power RK3568_PD_VO>; -+ rockchip,grf = <&grf>; -+ status = "disabled"; -+ -+ vop_out: ports { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ vp0: port@0 { -+ reg = <0>; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ }; -+ -+ vp1: port@1 { -+ reg = <1>; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ }; -+ -+ vp2: port@2 { -+ reg = <2>; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ }; -+ }; -+ }; -+ -+ vop_mmu: iommu@fe043e00 { -+ compatible = "rockchip,rk3568-iommu"; -+ reg = <0x0 0xfe043e00 0x0 0x100>, <0x0 0xfe043f00 0x0 0x100>; -+ interrupts = ; -+ clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>; -+ clock-names = "aclk", "iface"; -+ #iommu-cells = <0>; -+ power-domains = <&power RK3568_PD_VO>; -+ status = "disabled"; -+ }; - - qos_gpu: qos@fe128000 { - compatible = "rockchip,rk3568-qos", "syscon"; -@@ -716,6 +833,38 @@ - compatible = "rockchip,rk3568-qos", "syscon"; - reg = <0x0 0xfe1a8100 0x0 0x20>; - }; -+ -+ hdmi: hdmi@fe0a0000 { -+ compatible = "rockchip,rk3568-dw-hdmi"; -+ reg = <0x0 0xfe0a0000 0x0 0x20000>; -+ interrupts = ; -+ clocks = <&cru PCLK_HDMI_HOST>, -+ <&cru CLK_HDMI_SFR>, -+ <&cru CLK_HDMI_CEC>, -+ <&pmucru CLK_HDMI_REF>, -+ <&cru HCLK_VO>; -+ clock-names = "iahb", "isfr", "cec", "ref"; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&hdmitx_scl &hdmitx_sda &hdmitxm0_cec>; -+ power-domains = <&power RK3568_PD_VO>; -+ reg-io-width = <4>; -+ rockchip,grf = <&grf>; -+ #sound-dai-cells = <0>; -+ status = "disabled"; -+ -+ ports { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ hdmi_in: port@0 { -+ reg = <0>; -+ }; -+ -+ hdmi_out: port@1 { -+ reg = <1>; -+ }; -+ }; -+ }; - - pcie2x1: pcie@fe260000 { - compatible = "rockchip,rk3568-pcie"; -@@ -804,6 +953,23 @@ - clock-names = "clk_sfc", "hclk_sfc"; - pinctrl-0 = <&fspi_pins>; - pinctrl-names = "default"; -+ status = "disabled"; -+ }; -+ -+ i2s0_8ch: i2s@fe400000 { -+ compatible = "rockchip,rk3568-i2s-tdm"; -+ reg = <0x0 0xfe400000 0x0 0x1000>; -+ interrupts = ; -+ assigned-clocks = <&cru CLK_I2S0_8CH_TX_SRC>, <&cru CLK_I2S0_8CH_RX_SRC>; -+ assigned-clock-rates = <1188000000>, <1188000000>; -+ clocks = <&cru MCLK_I2S0_8CH_TX>, <&cru MCLK_I2S0_8CH_RX>, <&cru HCLK_I2S0_8CH>; -+ clock-names = "mclk_tx", "mclk_rx", "hclk"; -+ dmas = <&dmac1 0>; -+ dma-names = "tx"; -+ resets = <&cru SRST_M_I2S0_8CH_TX>, <&cru SRST_M_I2S0_8CH_RX>; -+ reset-names = "tx-m", "rx-m"; -+ rockchip,grf = <&grf>; -+ #sound-dai-cells = <0>; - status = "disabled"; - }; - diff --git a/lede/target/linux/rockchip/patches-6.6/100-rockchip-use-system-LED-for-OpenWrt.patch b/lede/target/linux/rockchip/patches-6.6/100-rockchip-use-system-LED-for-OpenWrt.patch new file mode 100644 index 0000000000..683e5347f7 --- /dev/null +++ b/lede/target/linux/rockchip/patches-6.6/100-rockchip-use-system-LED-for-OpenWrt.patch @@ -0,0 +1,77 @@ +From 6731d2c9039fbe1ecf21915eab3acee0a999508a Mon Sep 17 00:00:00 2001 +From: David Bauer +Date: Fri, 10 Jul 2020 21:38:20 +0200 +Subject: [PATCH] rockchip: use system LED for OpenWrt + +Use the SYS LED on the casing for showing system status. + +This patch is kept separate from the NanoPi R2S support patch, as i plan +on submitting the device support upstream. + +Signed-off-by: David Bauer +--- + arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts | 9 ++++++++- + 1 file changed, 8 insertions(+), 1 deletion(-) + +--- a/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts +@@ -6,6 +6,7 @@ + /dts-v1/; + + #include ++#include + #include + #include "rk3328.dtsi" + +@@ -16,6 +17,11 @@ + aliases { + ethernet1 = &rtl8153; + mmc0 = &sdmmc; ++ ++ led-boot = &sys_led; ++ led-failsafe = &sys_led; ++ led-running = &sys_led; ++ led-upgrade = &sys_led; + }; + + chosen { +@@ -48,19 +54,22 @@ + pinctrl-names = "default"; + + lan_led: led-0 { ++ color = ; ++ function = LED_FUNCTION_LAN; + gpios = <&gpio2 RK_PB7 GPIO_ACTIVE_HIGH>; +- label = "nanopi-r2s:green:lan"; + }; + + sys_led: led-1 { ++ color = ; ++ function = LED_FUNCTION_STATUS; + gpios = <&gpio0 RK_PA2 GPIO_ACTIVE_HIGH>; +- label = "nanopi-r2s:red:sys"; + default-state = "on"; + }; + + wan_led: led-2 { ++ color = ; ++ function = LED_FUNCTION_WAN; + gpios = <&gpio2 RK_PC2 GPIO_ACTIVE_HIGH>; +- label = "nanopi-r2s:green:wan"; + }; + }; + +--- a/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts +@@ -13,6 +13,11 @@ + aliases { + mmc0 = &sdmmc; + mmc1 = &emmc; ++ ++ led-boot = &power_led; ++ led-failsafe = &power_led; ++ led-running = &power_led; ++ led-upgrade = &power_led; + }; + + chosen { diff --git a/lede/target/linux/rockchip/patches-6.6/105-nanopi-r4s-sd-signalling.patch b/lede/target/linux/rockchip/patches-6.6/105-nanopi-r4s-sd-signalling.patch index a04c14b70a..856970738a 100644 --- a/lede/target/linux/rockchip/patches-6.6/105-nanopi-r4s-sd-signalling.patch +++ b/lede/target/linux/rockchip/patches-6.6/105-nanopi-r4s-sd-signalling.patch @@ -10,6 +10,16 @@ userspace or following a kernel panic is always working. Signed-off-by: David Bauer +--- a/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts +@@ -335,7 +335,6 @@ + sd-uhs-sdr12; + sd-uhs-sdr25; + sd-uhs-sdr50; +- sd-uhs-sdr104; + vmmc-supply = <&vcc_sd>; + vqmmc-supply = <&vcc_sdio>; + status = "okay"; --- a/arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s.dts +++ b/arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s.dts @@ -121,6 +121,11 @@ diff --git a/lede/target/linux/rockchip/patches-6.6/106-r4s-openwrt-leds.patch b/lede/target/linux/rockchip/patches-6.6/106-r4s-openwrt-leds.patch new file mode 100644 index 0000000000..d7579d61e9 --- /dev/null +++ b/lede/target/linux/rockchip/patches-6.6/106-r4s-openwrt-leds.patch @@ -0,0 +1,16 @@ +--- a/arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s.dts +@@ -19,6 +19,13 @@ + model = "FriendlyElec NanoPi R4S"; + compatible = "friendlyarm,nanopi-r4s", "rockchip,rk3399"; + ++ aliases { ++ led-boot = &sys_led; ++ led-failsafe = &sys_led; ++ led-running = &sys_led; ++ led-upgrade = &sys_led; ++ }; ++ + /delete-node/ display-subsystem; + + gpio-leds { diff --git a/lede/target/linux/rockchip/patches-6.6/114-arm64-dts-rockchip-Update-LED-properties-for-Orange-.patch b/lede/target/linux/rockchip/patches-6.6/114-arm64-dts-rockchip-Update-LED-properties-for-Orange-.patch new file mode 100644 index 0000000000..3aff37d096 --- /dev/null +++ b/lede/target/linux/rockchip/patches-6.6/114-arm64-dts-rockchip-Update-LED-properties-for-Orange-.patch @@ -0,0 +1,40 @@ +From d2166e3b3680bd2b206aebf1e1ce4c0d346f3c50 Mon Sep 17 00:00:00 2001 +From: Tianling Shen +Date: Fri, 19 May 2023 12:10:52 +0800 +Subject: [PATCH] arm64: dts: rockchip: Update LED properties for Orange Pi R1 + Plus + +Add OpenWrt's LED aliases for showing system status. + +Signed-off-by: Tianling Shen +--- + .../dts/rockchip/rk3328-orangepi-r1-plus.dts | 17 +++++++++-------- + 1 file changed, 9 insertions(+), 8 deletions(-) + +--- a/arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus.dts +@@ -17,6 +17,11 @@ + aliases { + ethernet1 = &rtl8153; + mmc0 = &sdmmc; ++ ++ led-boot = &status_led; ++ led-failsafe = &status_led; ++ led-running = &status_led; ++ led-upgrade = &status_led; + }; + + chosen { +@@ -41,11 +46,10 @@ + gpios = <&gpio2 RK_PB7 GPIO_ACTIVE_HIGH>; + }; + +- led-1 { ++ status_led: led-1 { + function = LED_FUNCTION_STATUS; + color = ; + gpios = <&gpio3 RK_PC5 GPIO_ACTIVE_HIGH>; +- linux,default-trigger = "heartbeat"; + }; + + led-2 { diff --git a/lede/target/linux/rockchip/patches-6.6/115-arm64-dts-rockchip-add-LED-configuration-to-Orange-P.patch b/lede/target/linux/rockchip/patches-6.6/115-arm64-dts-rockchip-add-LED-configuration-to-Orange-P.patch new file mode 100644 index 0000000000..af8f8b16ba --- /dev/null +++ b/lede/target/linux/rockchip/patches-6.6/115-arm64-dts-rockchip-add-LED-configuration-to-Orange-P.patch @@ -0,0 +1,24 @@ +From b46a530d12ada422b9d5b2b97059e0d3ed950b40 Mon Sep 17 00:00:00 2001 +From: Tianling Shen +Date: Fri, 19 May 2023 12:38:04 +0800 +Subject: [PATCH] arm64: dts: rockchip: add LED configuration to Orange Pi R1 + Plus + +Add the correct value for the RTL8153 LED configuration register to +match the blink behavior of the other port on the device. + +Signed-off-by: Tianling Shen +--- + arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus.dts | 1 + + 1 file changed, 1 insertion(+) + +--- a/arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus.dts +@@ -365,6 +365,7 @@ + rtl8153: device@2 { + compatible = "usbbda,8153"; + reg = <2>; ++ realtek,led-data = <0x87>; + }; + }; + diff --git a/lede/target/linux/rockchip/patches-6.6/807-arm64-dts-nanopi-r2s-add-rk3328-dmc-relate-node.patch b/lede/target/linux/rockchip/patches-6.6/807-arm64-dts-nanopi-r2s-add-rk3328-dmc-relate-node.patch index 15ca783a49..29495ddc20 100644 --- a/lede/target/linux/rockchip/patches-6.6/807-arm64-dts-nanopi-r2s-add-rk3328-dmc-relate-node.patch +++ b/lede/target/linux/rockchip/patches-6.6/807-arm64-dts-nanopi-r2s-add-rk3328-dmc-relate-node.patch @@ -17,8 +17,8 @@ Signed-off-by: hmz007 --- a/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts +++ b/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts @@ -7,6 +7,7 @@ - #include + #include #include +#include "rk3328-dram-default-timing.dtsi" #include "rk3328.dtsi" diff --git a/mihomo/hub/route/configs.go b/mihomo/hub/route/configs.go index d4bda2bf4c..b23a35a52a 100644 --- a/mihomo/hub/route/configs.go +++ b/mihomo/hub/route/configs.go @@ -24,9 +24,11 @@ import ( func configRouter() http.Handler { r := chi.NewRouter() r.Get("/", getConfigs) - r.Put("/", updateConfigs) - r.Post("/geo", updateGeoDatabases) - r.Patch("/", patchConfigs) + if !embedMode { // disallow update/patch configs in embed mode + r.Put("/", updateConfigs) + r.Post("/geo", updateGeoDatabases) + r.Patch("/", patchConfigs) + } return r } diff --git a/mihomo/hub/route/groups.go b/mihomo/hub/route/groups.go index 68d1f3542b..873a94df51 100644 --- a/mihomo/hub/route/groups.go +++ b/mihomo/hub/route/groups.go @@ -16,7 +16,7 @@ import ( "github.com/metacubex/mihomo/tunnel" ) -func GroupRouter() http.Handler { +func groupRouter() http.Handler { r := chi.NewRouter() r.Get("/", getGroups) diff --git a/mihomo/hub/route/patch_android.go b/mihomo/hub/route/patch_android.go new file mode 100644 index 0000000000..5eba279646 --- /dev/null +++ b/mihomo/hub/route/patch_android.go @@ -0,0 +1,7 @@ +//go:build android && cmfa + +package route + +func init() { + SetEmbedMode(true) // set embed mode default +} diff --git a/mihomo/hub/route/server.go b/mihomo/hub/route/server.go index e71347fcd6..21102cc38b 100644 --- a/mihomo/hub/route/server.go +++ b/mihomo/hub/route/server.go @@ -36,8 +36,14 @@ var ( tlsServer *http.Server unixServer *http.Server pipeServer *http.Server + + embedMode = false ) +func SetEmbedMode(embed bool) { + embedMode = embed +} + type Traffic struct { Up int64 `json:"up"` Down int64 `json:"down"` @@ -114,15 +120,17 @@ func router(isDebug bool, secret string, dohServer string, cors Cors) *chi.Mux { r.Get("/version", version) r.Mount("/configs", configRouter()) r.Mount("/proxies", proxyRouter()) - r.Mount("/group", GroupRouter()) + r.Mount("/group", groupRouter()) r.Mount("/rules", ruleRouter()) r.Mount("/connections", connectionRouter()) r.Mount("/providers/proxies", proxyProviderRouter()) r.Mount("/providers/rules", ruleProviderRouter()) r.Mount("/cache", cacheRouter()) r.Mount("/dns", dnsRouter()) - r.Mount("/restart", restartRouter()) - r.Mount("/upgrade", upgradeRouter()) + if !embedMode { // disallow restart and upgrade in embed mode + r.Mount("/restart", restartRouter()) + r.Mount("/upgrade", upgradeRouter()) + } addExternalRouters(r) }) diff --git a/ryujinx/src/Ryujinx.Graphics.Gpu/Shader/ShaderSpecializationState.cs b/ryujinx/src/Ryujinx.Graphics.Gpu/Shader/ShaderSpecializationState.cs index 98acb6f27d..1230c05805 100644 --- a/ryujinx/src/Ryujinx.Graphics.Gpu/Shader/ShaderSpecializationState.cs +++ b/ryujinx/src/Ryujinx.Graphics.Gpu/Shader/ShaderSpecializationState.cs @@ -743,7 +743,7 @@ namespace Ryujinx.Graphics.Gpu.Shader constantBufferUsePerStageMask &= ~(1 << index); } - if (checkTextures) + if (checkTextures && _allTextures.Length > 0) { TexturePool pool = channel.TextureManager.GetTexturePool(poolState.TexturePoolGpuVa, poolState.TexturePoolMaximumId); diff --git a/small/luci-app-mihomo/Makefile b/small/luci-app-mihomo/Makefile index 0dc3a917e7..c6dca4cd61 100644 --- a/small/luci-app-mihomo/Makefile +++ b/small/luci-app-mihomo/Makefile @@ -1,6 +1,6 @@ include $(TOPDIR)/rules.mk -PKG_VERSION:=1.8.3 +PKG_VERSION:=1.8.4 LUCI_TITLE:=LuCI Support for mihomo LUCI_DEPENDS:=+luci-base +mihomo diff --git a/small/luci-app-mihomo/htdocs/luci-static/resources/tools/mihomo.js b/small/luci-app-mihomo/htdocs/luci-static/resources/tools/mihomo.js index d04476e753..3433ae97c5 100644 --- a/small/luci-app-mihomo/htdocs/luci-static/resources/tools/mihomo.js +++ b/small/luci-app-mihomo/htdocs/luci-static/resources/tools/mihomo.js @@ -8,9 +8,10 @@ const homeDir = '/etc/mihomo'; const profilesDir = `${homeDir}/profiles`; const mixinFilePath = `${homeDir}/mixin.yaml`; const runDir = `${homeDir}/run`; -const runAppLogPath = `${runDir}/app.log`; -const runCoreLogPath = `${runDir}/core.log`; const runProfilePath = `${runDir}/config.yaml`; +const logDir = `/var/log/mihomo`; +const appLogPath = `${logDir}/app.log`; +const coreLogPath = `${logDir}/core.log`; const nftDir = `${homeDir}/nftables`; const reservedIPNFT = `${nftDir}/reserved_ip.nft`; const reservedIP6NFT = `${nftDir}/reserved_ip6.nft`; @@ -20,8 +21,8 @@ return baseclass.extend({ profilesDir: profilesDir, mixinFilePath: mixinFilePath, runDir: runDir, - runAppLogPath: runAppLogPath, - runCoreLogPath: runCoreLogPath, + appLogPath: appLogPath, + coreLogPath: coreLogPath, runProfilePath: runProfilePath, reservedIPNFT: reservedIPNFT, reservedIP6NFT: reservedIP6NFT, @@ -34,19 +35,19 @@ return baseclass.extend({ }), getAppLog: function () { - return L.resolveDefault(fs.read_direct(this.runAppLogPath)); + return L.resolveDefault(fs.read_direct(this.appLogPath)); }, getCoreLog: function () { - return L.resolveDefault(fs.read_direct(this.runCoreLogPath)); + return L.resolveDefault(fs.read_direct(this.coreLogPath)); }, clearAppLog: function () { - return fs.exec_direct('/usr/libexec/mihomo-call', ['clear', 'app_log']); + return fs.exec_direct('/usr/libexec/mihomo-call', ['clear_log', 'app']); }, clearCoreLog: function () { - return fs.exec_direct('/usr/libexec/mihomo-call', ['clear', 'core_log']); + return fs.exec_direct('/usr/libexec/mihomo-call', ['clear_log', 'core']); }, listProfiles: function () { diff --git a/small/luci-app-mihomo/htdocs/luci-static/resources/view/mihomo/config.js b/small/luci-app-mihomo/htdocs/luci-static/resources/view/mihomo/config.js index 2d461bda21..33cb2c6258 100644 --- a/small/luci-app-mihomo/htdocs/luci-static/resources/view/mihomo/config.js +++ b/small/luci-app-mihomo/htdocs/luci-static/resources/view/mihomo/config.js @@ -111,7 +111,7 @@ return view.extend({ o.depends('scheduled_restart', '1'); o = s.option(form.ListValue, 'profile', _('Choose Profile')); - o.rmempty = false; + o.optional = true; for (const profile of profiles) { o.value('file:' + profile.name, _('File:') + profile.name); @@ -408,6 +408,9 @@ return view.extend({ o = s.taboption('dns', form.Flag, 'dns_respect_rules', _('Respect Rules')); o.rmempty = false; + o = s.taboption('dns', form.Flag, 'dns_doh_prefer_http3', _('DoH Prefer HTTP/3')); + o.rmempty = false; + o = s.taboption('dns', form.Flag, 'dns_ipv6', _('IPv6')); o.rmempty = false; diff --git a/small/luci-app-mihomo/po/zh_Hans/mihomo.po b/small/luci-app-mihomo/po/zh_Hans/mihomo.po index 7eab0a28f2..94b27ca02d 100644 --- a/small/luci-app-mihomo/po/zh_Hans/mihomo.po +++ b/small/luci-app-mihomo/po/zh_Hans/mihomo.po @@ -304,6 +304,9 @@ msgstr "Fake-IP 缓存" msgid "Respect Rules" msgstr "遵循分流规则" +msgid "DoH Prefer HTTP/3" +msgstr "DoH 优先 HTTP/3" + msgid "Use System Hosts" msgstr "使用系统的 Hosts" diff --git a/small/luci-app-mihomo/root/usr/libexec/mihomo-call b/small/luci-app-mihomo/root/usr/libexec/mihomo-call index bb8a17baf7..e5bd65a757 100755 --- a/small/luci-app-mihomo/root/usr/libexec/mihomo-call +++ b/small/luci-app-mihomo/root/usr/libexec/mihomo-call @@ -6,13 +6,13 @@ action=$1 shift case "$action" in - clear) + clear_log) case "$1" in - app_log) - echo -n > "$RUN_APP_LOG_PATH" + app) + echo -n > "$APP_LOG_PATH" ;; - core_log) - echo -n > "$RUN_CORE_LOG_PATH" + core) + echo -n > "$CORE_LOG_PATH" ;; esac ;; diff --git a/small/luci-app-mihomo/root/usr/share/rpcd/acl.d/luci-app-mihomo.json b/small/luci-app-mihomo/root/usr/share/rpcd/acl.d/luci-app-mihomo.json index d1de3b1c9c..9a59314606 100644 --- a/small/luci-app-mihomo/root/usr/share/rpcd/acl.d/luci-app-mihomo.json +++ b/small/luci-app-mihomo/root/usr/share/rpcd/acl.d/luci-app-mihomo.json @@ -13,7 +13,7 @@ "/etc/mihomo/run/config.yaml": ["read"], "/etc/mihomo/nftables/reserved_ip.nft": ["read"], "/etc/mihomo/nftables/reserved_ip6.nft": ["read"], - "/etc/mihomo/run/*.log": ["read"], + "/var/log/mihomo/*.log": ["read"], "/usr/libexec/mihomo-call": ["exec"] } }, diff --git a/small/mihomo/Makefile b/small/mihomo/Makefile index 2bbfe8a920..c0c1e05fc3 100644 --- a/small/mihomo/Makefile +++ b/small/mihomo/Makefile @@ -5,9 +5,9 @@ PKG_RELEASE:=1 PKG_SOURCE_PROTO:=git PKG_SOURCE_URL:=https://github.com/MetaCubeX/mihomo.git -PKG_SOURCE_DATE:=2024-09-28 -PKG_SOURCE_VERSION:=264713571d349d214ec938911de0de033b8673af -PKG_MIRROR_HASH:=1df27333ff05ab29e1e01b1623b6f526de0191c4dc82762fe0ac31b1a4bc52cf +PKG_SOURCE_DATE:=2024-09-29 +PKG_SOURCE_VERSION:=fc9d5cfee944a75b989d17c637a321e73c52093a +PKG_MIRROR_HASH:=47c8d16a3bd5536bc4659c0827e5cf561fc6682cbbd4af0b07f065ee930a38dc PKG_LICENSE:=MIT PKG_MAINTAINER:=Joseph Mory @@ -16,7 +16,7 @@ PKG_BUILD_DEPENDS:=golang/host PKG_BUILD_PARALLEL:=1 PKG_BUILD_FLAGS:=no-mips16 -PKG_BUILD_VERSION:=alpha-2647135 +PKG_BUILD_VERSION:=alpha-fc9d5cf PKG_BUILD_TIME:=$(shell date -u -Iseconds) GO_PKG:=github.com/metacubex/mihomo @@ -75,6 +75,7 @@ define Package/mihomo/install $(INSTALL_BIN) $(CURDIR)/files/mihomo.init $(1)/etc/init.d/mihomo $(INSTALL_DIR) $(1)/etc/uci-defaults + $(INSTALL_BIN) $(CURDIR)/files/uci-defaults/firewall.sh $(1)/etc/uci-defaults/99_firewall_mihomo $(INSTALL_BIN) $(CURDIR)/files/uci-defaults/init.sh $(1)/etc/uci-defaults/99_init_mihomo $(INSTALL_BIN) $(CURDIR)/files/uci-defaults/migrate.sh $(1)/etc/uci-defaults/99_migrate_mihomo @@ -85,6 +86,16 @@ define Package/mihomo/install $(INSTALL_DATA) $(CURDIR)/files/mihomo.upgrade $(1)/lib/upgrade/keep.d/mihomo endef +define Package/mihomo/postrm +#!/bin/sh +if [ -z $${IPKG_INSTROOT} ]; then + uci -q batch <<-EOF > /dev/null + del firewall.mihomo + commit firewall + EOF +fi +endef + define Build/Prepare $(Build/Prepare/Default) $(RM) -r $(PKG_BUILD_DIR)/rules/logic_test diff --git a/small/mihomo/files/mihomo.conf b/small/mihomo/files/mihomo.conf index 4984ac310b..6319e411b3 100644 --- a/small/mihomo/files/mihomo.conf +++ b/small/mihomo/files/mihomo.conf @@ -30,7 +30,7 @@ config proxy 'proxy' config subscription 'subscription' option 'name' 'default' option 'url' 'http://example.com/default.yaml' - option 'user_agent' 'mihomo' + option 'user_agent' 'clash' config mixin 'mixin' option 'log_level' 'info' @@ -65,6 +65,7 @@ config mixin 'mixin' list 'fake_ip_filters' '+.local' option 'fake_ip_cache' '1' option 'dns_respect_rules' '0' + option 'dns_doh_prefer_http3' '0' option 'dns_ipv6' '0' option 'dns_system_hosts' '0' option 'dns_hosts' '0' diff --git a/small/mihomo/files/mihomo.init b/small/mihomo/files/mihomo.init index 26911b1087..59b3d62a9c 100644 --- a/small/mihomo/files/mihomo.init +++ b/small/mihomo/files/mihomo.init @@ -9,7 +9,7 @@ USE_PROCD=1 start_service() { # clear log - clear_all_log + clear_log # load config config_load mihomo # check if enabled @@ -83,7 +83,7 @@ start_service() { config_get tun_gso_max_size "mixin" "tun_gso_max_size" "65536" config_get_bool tun_endpoint_independent_nat "mixin" "tun_endpoint_independent_nat" 0 ### dns - local dns_port dns_mode fake_ip_range fake_ip_filter fake_ip_filter_mode fake_ip_cache dns_respect_rules dns_ipv6 dns_system_hosts dns_hosts hosts dns_nameserver dns_nameserver_policy + local dns_port dns_mode fake_ip_range fake_ip_filter fake_ip_filter_mode fake_ip_cache dns_respect_rules dns_doh_prefer_http3 dns_ipv6 dns_system_hosts dns_hosts hosts dns_nameserver dns_nameserver_policy config_get dns_port "mixin" "dns_port" "1053" config_get dns_mode "mixin" "dns_mode" "redir-host" config_get fake_ip_range "mixin" "fake_ip_range" "198.18.0.1/16" @@ -91,6 +91,7 @@ start_service() { config_get fake_ip_filter_mode "mixin" "fake_ip_filter_mode" "blacklist" config_get_bool fake_ip_cache "mixin" "fake_ip_cache" 0 config_get_bool dns_respect_rules "mixin" "dns_respect_rules" 0 + config_get_bool dns_doh_prefer_http3 "mixin" "dns_doh_prefer_http3" 0 config_get_bool dns_ipv6 "mixin" "dns_ipv6" 0 config_get_bool dns_system_hosts "mixin" "dns_system_hosts" 0 config_get_bool dns_hosts "mixin" "dns_hosts" 0 @@ -135,6 +136,8 @@ start_service() { fi log "Use Subscription: $subscription_name" else + log "No profile/subscription selected." + log "Exiting..." return fi # mixin @@ -161,7 +164,7 @@ start_service() { allow_lan="$allow_lan" http_port="$http_port" socks_port="$socks_port" mixed_port="$mixed_port" redir_port="$redir_port" tproxy_port="$tproxy_port" \ tun_enable="$tun_enable" tun_stack="$tun_stack" tun_device="$TUN_DEVICE" tun_mtu="$tun_mtu" tun_gso="$tun_gso" tun_gso_max_size="$tun_gso_max_size" tun_endpoint_independent_nat="$tun_endpoint_independent_nat" \ dns_enable="true" dns_listen="0.0.0.0:$dns_port" dns_mode="$dns_mode" fake_ip_range="$fake_ip_range" fake_ip_cache="$fake_ip_cache" \ - dns_respect_rules="$dns_respect_rules" dns_ipv6="$dns_ipv6" dns_system_hosts="$dns_system_hosts" dns_hosts="$dns_hosts" \ + dns_respect_rules="$dns_respect_rules" dns_doh_prefer_http3="$dns_doh_prefer_http3" dns_ipv6="$dns_ipv6" dns_system_hosts="$dns_system_hosts" dns_hosts="$dns_hosts" \ geoip_format="$geoip_format" geodata_loader="$geodata_loader" geosite_url="$geosite_url" geoip_mmdb_url="$geoip_mmdb_url" geoip_dat_url="$geoip_dat_url" geoip_asn_url="$geoip_asn_url" \ geox_auto_update="$geox_auto_update" geox_update_interval="$geox_update_interval" \ yq -M -i ' @@ -170,7 +173,7 @@ start_service() { .allow-lan = env(allow_lan) == 1 | .port = env(http_port) | .socks-port = env(socks_port) | .mixed-port = env(mixed_port) | .redir-port = env(redir_port) | .tproxy-port = env(tproxy_port) | .tun.enable = env(tun_enable) == 1 | .tun.stack = env(tun_stack) | .tun.device = env(tun_device) | .tun.mtu = env(tun_mtu) | .tun.gso = env(tun_gso) == 1 | .tun.gso-max-size = env(tun_gso_max_size) | .tun.endpoint-independent-nat = env(tun_endpoint_independent_nat) == 1 | .dns.enable = env(dns_enable) | .dns.listen = env(dns_listen) | .dns.enhanced-mode = env(dns_mode) | .dns.fake-ip-range = env(fake_ip_range) | .profile.store-fake-ip = env(fake_ip_cache) == 1 | - .dns.respect-rules = env(dns_respect_rules) == 1 | .dns.ipv6 = env(dns_ipv6) == 1 | .dns.use-system-hosts = env(dns_system_hosts) == 1 | .dns.use-hosts = env(dns_hosts) == 1 | + .dns.respect-rules = env(dns_respect_rules) == 1 | .dns.prefer-h3 = env(dns_doh_prefer_http3) == 1 | .dns.ipv6 = env(dns_ipv6) == 1 | .dns.use-system-hosts = env(dns_system_hosts) == 1 | .dns.use-hosts = env(dns_hosts) == 1 | .geodata-mode = env(geoip_format) == "dat" | .geodata-loader = env(geodata_loader) | .geox-url.geosite = env(geosite_url) | .geox-url.mmdb = env(geoip_mmdb_url) | .geox-url.geoip = env(geoip_dat_url) | .geox-url.asn = env(geoip_asn_url) | .geo-auto-update = env(geox_auto_update) == 1 | .geo-update-interval = env(geox_update_interval) ' "$RUN_PROFILE_PATH" @@ -215,7 +218,7 @@ start_service() { # test profile if [ "$test_profile" == 1 ]; then log "Profile testing..." - if ($PROG -d "$RUN_DIR" -t >> "$RUN_CORE_LOG_PATH" 2>&1); then + if ($PROG -d "$RUN_DIR" -t >> "$CORE_LOG_PATH" 2>&1); then log "Profile test passed!" else log "Profile test failed!" @@ -227,7 +230,7 @@ start_service() { log "Start Core" procd_open_instance mihomo - procd_set_param command /bin/sh -c "$PROG -d $RUN_DIR >> $RUN_CORE_LOG_PATH 2>&1" + procd_set_param command /bin/sh -c "$PROG -d $RUN_DIR >> $CORE_LOG_PATH 2>&1" procd_set_param file "$RUN_PROFILE_PATH" if [ "$fast_reload" == 1 ]; then procd_set_param reload_signal HUP @@ -241,7 +244,7 @@ start_service() { procd_add_jail mihomo requirejail procfs procd_add_jail_mount "$PROG" /etc/TZ /etc/localtime /etc/hosts /etc/ssl/certs - procd_add_jail_mount_rw "$RUN_DIR" /dev/net + procd_add_jail_mount_rw "$RUN_DIR" "$LOG_DIR" /dev/net procd_set_param capabilities /etc/capabilities/mihomo.json procd_set_param no_new_privs 1 @@ -249,7 +252,7 @@ start_service() { # transparent proxy if [ "$transparent_proxy" == 1 ]; then log "Transparent Proxy is enabled." - log "Transparent Proxy: Start hijack." + log "Transparent Proxy: Start." # prepare if [ "$tproxy_enable" == 1 ]; then if [ "$ipv4_proxy" == 1 ]; then @@ -417,11 +420,11 @@ cleanup() { # delete hijack nft delete table inet "$FW_TABLE" > /dev/null 2>&1 local handles handle - handles=$(nft --json list table inet fw4 | yq '.nftables[] | select(has("rule")) | .rule | select(.family == "inet" and .table == "fw4" and .chain == "input" and .expr[0].match.right == "tun") | .handle') + handles=$(nft --json list table inet fw4 | yq '.nftables[] | select(has("rule")) | .rule | select(.chain == "input" and .comment == "mihomo") | .handle') for handle in $handles; do nft delete rule inet fw4 input handle "$handle" done - handles=$(nft --json list table inet fw4 | yq '.nftables[] | select(has("rule")) | .rule | select(.family == "inet" and .table == "fw4" and .chain == "forward" and .expr[0].match.right == "tun") | .handle') + handles=$(nft --json list table inet fw4 | yq '.nftables[] | select(has("rule")) | .rule | select(.chain == "forward" and .comment == "mihomo") | .handle') for handle in $handles; do nft delete rule inet fw4 forward handle "$handle" done @@ -431,12 +434,14 @@ cleanup() { } log() { - echo "[$(date '+%Y-%m-%d %H:%M:%S')] $1" >> "$RUN_APP_LOG_PATH" + echo "[$(date '+%Y-%m-%d %H:%M:%S')] $1" >> "$APP_LOG_PATH" } -clear_all_log() { - echo -n > "$RUN_APP_LOG_PATH" - echo -n > "$RUN_CORE_LOG_PATH" +clear_log() { + if [ -d "$LOG_DIR" ]; then + rm -rf "$LOG_DIR" + fi + mkdir "$LOG_DIR" } mixin_authentications() { diff --git a/small/mihomo/files/scripts/constants.sh b/small/mihomo/files/scripts/constants.sh index adb81ecc49..97d2e17134 100644 --- a/small/mihomo/files/scripts/constants.sh +++ b/small/mihomo/files/scripts/constants.sh @@ -12,7 +12,7 @@ TCP_RULE_PREF="1024" UDP_RULE_PREF="1025" TPROXY_ROUTE_TABLE="80" TUN_ROUTE_TABLE="81" -TUN_DEVICE="tun" +TUN_DEVICE="mihomo" # paths PROG="/usr/bin/mihomo" @@ -20,10 +20,11 @@ HOME_DIR="/etc/mihomo" PROFILES_DIR="$HOME_DIR/profiles" MIXIN_FILE_PATH="$HOME_DIR/mixin.yaml" RUN_DIR="$HOME_DIR/run" -RUN_APP_LOG_PATH="$RUN_DIR/app.log" -RUN_CORE_LOG_PATH="$RUN_DIR/core.log" RUN_PROFILE_PATH="$RUN_DIR/config.yaml" RUN_UI_DIR="$RUN_DIR/ui" +LOG_DIR="/var/log/mihomo" +APP_LOG_PATH="$LOG_DIR/app.log" +CORE_LOG_PATH="$LOG_DIR/core.log" # scripts SH_DIR="$HOME_DIR/scripts" diff --git a/small/mihomo/files/scripts/tun.sh b/small/mihomo/files/scripts/tun.sh index af63d528ac..9e99b03b8b 100644 --- a/small/mihomo/files/scripts/tun.sh +++ b/small/mihomo/files/scripts/tun.sh @@ -9,9 +9,9 @@ config_get tcp_transparent_proxy_mode "proxy" "tcp_transparent_proxy_mode" config_get udp_transparent_proxy_mode "proxy" "udp_transparent_proxy_mode" if [ "$enabled" == 1 ] && [[ "$tcp_transparent_proxy_mode" == "tun" || "$udp_transparent_proxy_mode" == "tun" ]]; then - nft insert rule inet fw4 input iifname "$TUN_DEVICE" counter accept - nft insert rule inet fw4 forward oifname "$TUN_DEVICE" counter accept - nft insert rule inet fw4 forward iifname "$TUN_DEVICE" counter accept + nft insert rule inet fw4 input iifname "$TUN_DEVICE" counter accept comment "mihomo" + nft insert rule inet fw4 forward oifname "$TUN_DEVICE" counter accept comment "mihomo" + nft insert rule inet fw4 forward iifname "$TUN_DEVICE" counter accept comment "mihomo" fi exit 0 diff --git a/small/mihomo/files/uci-defaults/firewall.sh b/small/mihomo/files/uci-defaults/firewall.sh new file mode 100644 index 0000000000..3a0cb09b2d --- /dev/null +++ b/small/mihomo/files/uci-defaults/firewall.sh @@ -0,0 +1,12 @@ +#!/bin/sh + +. "$IPKG_INSTROOT/etc/mihomo/scripts/constants.sh" + +uci -q batch <<-EOF > /dev/null + del firewall.mihomo + set firewall.mihomo=include + set firewall.mihomo.type=script + set firewall.mihomo.path=$TUN_SH + set firewall.mihomo.fw4_compatible=1 + commit firewall +EOF diff --git a/small/mihomo/files/uci-defaults/init.sh b/small/mihomo/files/uci-defaults/init.sh index 48b4f9b520..615b5a1502 100644 --- a/small/mihomo/files/uci-defaults/init.sh +++ b/small/mihomo/files/uci-defaults/init.sh @@ -2,16 +2,6 @@ . "$IPKG_INSTROOT/etc/mihomo/scripts/constants.sh" -# add firewall include for tun -uci -q batch <<-EOF > /dev/null - delete firewall.mihomo - set firewall.mihomo=include - set firewall.mihomo.type=script - set firewall.mihomo.path=$TUN_SH - set firewall.mihomo.fw4_compatible=1 - commit firewall -EOF - # check mihomo.config.init init=$(uci -q get mihomo.config.init); [ -z "$init" ] && return diff --git a/small/mihomo/files/uci-defaults/migrate.sh b/small/mihomo/files/uci-defaults/migrate.sh index bfd6d9b1a2..0febd30e68 100644 --- a/small/mihomo/files/uci-defaults/migrate.sh +++ b/small/mihomo/files/uci-defaults/migrate.sh @@ -2,6 +2,10 @@ . "$IPKG_INSTROOT/etc/mihomo/scripts/constants.sh" +# since v1.8.4 + +dns_doh_prefer_http3=$(uci -q get mihomo.mixin.dns_doh_prefer_http3); [ -z "$dns_doh_prefer_http3" ] && uci set mihomo.mixin.dns_doh_prefer_http3=0 + # commit uci commit mihomo diff --git a/small/v2ray-geodata/Makefile b/small/v2ray-geodata/Makefile index e0605e17bf..34a0dd0f1c 100644 --- a/small/v2ray-geodata/Makefile +++ b/small/v2ray-geodata/Makefile @@ -30,13 +30,13 @@ define Download/geosite HASH:=aeefcd8b3e5b27c22e2e7dfb6ff5e8d0741fd540d96ab355fd00a0472f5884a7 endef -GEOSITE_IRAN_VER:=202409230034 +GEOSITE_IRAN_VER:=202409300035 GEOSITE_IRAN_FILE:=iran.dat.$(GEOSITE_IRAN_VER) define Download/geosite-ir URL:=https://github.com/bootmortis/iran-hosted-domains/releases/download/$(GEOSITE_IRAN_VER)/ URL_FILE:=iran.dat FILE:=$(GEOSITE_IRAN_FILE) - HASH:=fbe82bee851e3c3002f352c26164eedd6d79141e6162505a69bcc7ec153aebe9 + HASH:=b10725db0a82d919cc72cd161dec4b14b6870c760322f6e503c55de3c1828f3d endef define Package/v2ray-geodata/template diff --git a/suyu/README.md b/suyu/README.md index 4d4f239680..e2cfaa9ded 100644 --- a/suyu/README.md +++ b/suyu/README.md @@ -9,6 +9,8 @@ SPDX-License-Identifier: GPL-3.0-or-later We're in need of developers. Please join our chat below or DM a dev if you want to contribute! This repo is currently based on Yuzu EA 4176 but the code will be rewritten for legal and performance reasons. +Our only website is suyu.dev so please be cautious when using other sites offering builds/downloads. +

diff --git a/suyu/src/core/core_timing.cpp b/suyu/src/core/core_timing.cpp index 1abfa920c4..6ac0007764 100644 --- a/suyu/src/core/core_timing.cpp +++ b/suyu/src/core/core_timing.cpp @@ -26,24 +26,6 @@ std::shared_ptr CreateEvent(std::string name, TimedCallback&& callbac return std::make_shared(std::move(callback), std::move(name)); } -struct CoreTiming::Event { - s64 time; - u64 fifo_order; - std::weak_ptr type; - s64 reschedule_time; - heap_t::handle_type handle{}; - - // Sort by time, unless the times are the same, in which case sort by - // the order added to the queue - friend bool operator>(const Event& left, const Event& right) { - return std::tie(left.time, left.fifo_order) > std::tie(right.time, right.fifo_order); - } - - friend bool operator<(const Event& left, const Event& right) { - return std::tie(left.time, left.fifo_order) < std::tie(right.time, right.fifo_order); - } -}; - CoreTiming::CoreTiming() : clock{Common::CreateOptimalClock()} {} CoreTiming::~CoreTiming() { @@ -87,7 +69,7 @@ void CoreTiming::Pause(bool is_paused) { } void CoreTiming::SyncPause(bool is_paused) { - if (is_paused == paused && paused_set == paused) { + if (is_paused == paused && paused_set == is_paused) { return; } @@ -112,7 +94,7 @@ bool CoreTiming::IsRunning() const { bool CoreTiming::HasPendingEvents() const { std::scoped_lock lock{basic_lock}; - return !(wait_set && event_queue.empty()); + return !event_queue.empty(); } void CoreTiming::ScheduleEvent(std::chrono::nanoseconds ns_into_future, @@ -121,8 +103,8 @@ void CoreTiming::ScheduleEvent(std::chrono::nanoseconds ns_into_future, std::scoped_lock scope{basic_lock}; const auto next_time{absolute_time ? ns_into_future : GetGlobalTimeNs() + ns_into_future}; - auto h{event_queue.emplace(Event{next_time.count(), event_fifo_id++, event_type, 0})}; - (*h).handle = h; + event_queue.emplace_back(Event{next_time.count(), event_fifo_id++, event_type}); + std::push_heap(event_queue.begin(), event_queue.end(), std::greater<>()); } event.Set(); @@ -136,9 +118,9 @@ void CoreTiming::ScheduleLoopingEvent(std::chrono::nanoseconds start_time, std::scoped_lock scope{basic_lock}; const auto next_time{absolute_time ? start_time : GetGlobalTimeNs() + start_time}; - auto h{event_queue.emplace( - Event{next_time.count(), event_fifo_id++, event_type, resched_time.count()})}; - (*h).handle = h; + event_queue.emplace_back( + Event{next_time.count(), event_fifo_id++, event_type, resched_time.count()}); + std::push_heap(event_queue.begin(), event_queue.end(), std::greater<>()); } event.Set(); @@ -149,17 +131,11 @@ void CoreTiming::UnscheduleEvent(const std::shared_ptr& event_type, { std::scoped_lock lk{basic_lock}; - std::vector to_remove; - for (auto itr = event_queue.begin(); itr != event_queue.end(); itr++) { - const Event& e = *itr; - if (e.type.lock().get() == event_type.get()) { - to_remove.push_back(itr->handle); - } - } - - for (auto& h : to_remove) { - event_queue.erase(h); - } + event_queue.erase( + std::remove_if(event_queue.begin(), event_queue.end(), + [&](const Event& e) { return e.type.lock().get() == event_type.get(); }), + event_queue.end()); + std::make_heap(event_queue.begin(), event_queue.end(), std::greater<>()); event_type->sequence_number++; } @@ -172,7 +148,7 @@ void CoreTiming::UnscheduleEvent(const std::shared_ptr& event_type, void CoreTiming::AddTicks(u64 ticks_to_add) { cpu_ticks += ticks_to_add; - downcount -= static_cast(cpu_ticks); + downcount -= static_cast(ticks_to_add); } void CoreTiming::Idle() { @@ -180,7 +156,7 @@ void CoreTiming::Idle() { } void CoreTiming::ResetTicks() { - downcount = MAX_SLICE_LENGTH; + downcount.store(MAX_SLICE_LENGTH, std::memory_order_release); } u64 CoreTiming::GetClockTicks() const { @@ -201,48 +177,38 @@ std::optional CoreTiming::Advance() { std::scoped_lock lock{advance_lock, basic_lock}; global_timer = GetGlobalTimeNs().count(); - while (!event_queue.empty() && event_queue.top().time <= global_timer) { - const Event& evt = event_queue.top(); + while (!event_queue.empty() && event_queue.front().time <= global_timer) { + Event evt = std::move(event_queue.front()); + std::pop_heap(event_queue.begin(), event_queue.end(), std::greater<>()); + event_queue.pop_back(); - if (const auto event_type{evt.type.lock()}) { + if (const auto event_type = evt.type.lock()) { const auto evt_time = evt.time; const auto evt_sequence_num = event_type->sequence_number; - if (evt.reschedule_time == 0) { - event_queue.pop(); + basic_lock.unlock(); - basic_lock.unlock(); + const auto new_schedule_time = event_type->callback( + evt_time, std::chrono::nanoseconds{GetGlobalTimeNs().count() - evt_time}); - event_type->callback( - evt_time, std::chrono::nanoseconds{GetGlobalTimeNs().count() - evt_time}); + basic_lock.lock(); - basic_lock.lock(); - } else { - basic_lock.unlock(); + if (evt_sequence_num != event_type->sequence_number) { + continue; + } - const auto new_schedule_time{event_type->callback( - evt_time, std::chrono::nanoseconds{GetGlobalTimeNs().count() - evt_time})}; + if (new_schedule_time.has_value() || evt.reschedule_time != 0) { + const auto next_schedule_time = new_schedule_time.value_or( + std::chrono::nanoseconds{evt.reschedule_time}); - basic_lock.lock(); - - if (evt_sequence_num != event_type->sequence_number) { - // Heap handle is invalidated after external modification. - continue; - } - - const auto next_schedule_time{new_schedule_time.has_value() - ? new_schedule_time.value().count() - : evt.reschedule_time}; - - // If this event was scheduled into a pause, its time now is going to be way - // behind. Re-set this event to continue from the end of the pause. - auto next_time{evt.time + next_schedule_time}; + auto next_time = evt.time + next_schedule_time.count(); if (evt.time < pause_end_time) { - next_time = pause_end_time + next_schedule_time; + next_time = pause_end_time + next_schedule_time.count(); } - event_queue.update(evt.handle, Event{next_time, event_fifo_id++, evt.type, - next_schedule_time, evt.handle}); + event_queue.emplace_back(Event{next_time, event_fifo_id++, evt.type, + next_schedule_time.count()}); + std::push_heap(event_queue.begin(), event_queue.end(), std::greater<>()); } } @@ -250,7 +216,7 @@ std::optional CoreTiming::Advance() { } if (!event_queue.empty()) { - return event_queue.top().time; + return event_queue.front().time; } else { return std::nullopt; } @@ -269,7 +235,7 @@ void CoreTiming::ThreadLoop() { #ifdef _WIN32 while (!paused && !event.IsSet() && wait_time > 0) { wait_time = *next_time - GetGlobalTimeNs().count(); - if (wait_time >= timer_resolution_ns) { + if (wait_time >= 1'000'000) { // 1ms Common::Windows::SleepForOneTick(); } else { #ifdef ARCHITECTURE_x86_64 @@ -290,10 +256,8 @@ void CoreTiming::ThreadLoop() { } else { // Queue is empty, wait until another event is scheduled and signals us to // continue. - wait_set = true; event.Wait(); } - wait_set = false; } paused_set = true; @@ -327,10 +291,4 @@ std::chrono::microseconds CoreTiming::GetGlobalTimeUs() const { return std::chrono::microseconds{Common::WallClock::CPUTickToUS(cpu_ticks)}; } -#ifdef _WIN32 -void CoreTiming::SetTimerResolutionNs(std::chrono::nanoseconds ns) { - timer_resolution_ns = ns.count(); -} -#endif - } // namespace Core::Timing diff --git a/suyu/src/core/core_timing.h b/suyu/src/core/core_timing.h index 7e4dff7f3d..5b42b0e491 100644 --- a/suyu/src/core/core_timing.h +++ b/suyu/src/core/core_timing.h @@ -11,8 +11,7 @@ #include #include #include - -#include +#include #include "common/common_types.h" #include "common/thread.h" @@ -43,18 +42,6 @@ enum class UnscheduleEventType { NoWait, }; -/** - * This is a system to schedule events into the emulated machine's future. Time is measured - * in main CPU clock cycles. - * - * To schedule an event, you first have to register its type. This is where you pass in the - * callback. You then schedule events using the type ID you get back. - * - * The s64 ns_late that the callbacks get is how many ns late it was. - * So to schedule a new event on a regular basis: - * inside callback: - * ScheduleEvent(period_in_ns - ns_late, callback, "whatever") - */ class CoreTiming { public: CoreTiming(); @@ -66,99 +53,56 @@ public: CoreTiming& operator=(const CoreTiming&) = delete; CoreTiming& operator=(CoreTiming&&) = delete; - /// CoreTiming begins at the boundary of timing slice -1. An initial call to Advance() is - /// required to end slice - 1 and start slice 0 before the first cycle of code is executed. void Initialize(std::function&& on_thread_init_); - - /// Clear all pending events. This should ONLY be done on exit. void ClearPendingEvents(); - - /// Sets if emulation is multicore or single core, must be set before Initialize void SetMulticore(bool is_multicore_) { is_multicore = is_multicore_; } - - /// Pauses/Unpauses the execution of the timer thread. void Pause(bool is_paused); - - /// Pauses/Unpauses the execution of the timer thread and waits until paused. void SyncPause(bool is_paused); - - /// Checks if core timing is running. bool IsRunning() const; - - /// Checks if the timer thread has started. bool HasStarted() const { return has_started; } - - /// Checks if there are any pending time events. bool HasPendingEvents() const; - - /// Schedules an event in core timing void ScheduleEvent(std::chrono::nanoseconds ns_into_future, const std::shared_ptr& event_type, bool absolute_time = false); - - /// Schedules an event which will automatically re-schedule itself with the given time, until - /// unscheduled void ScheduleLoopingEvent(std::chrono::nanoseconds start_time, std::chrono::nanoseconds resched_time, const std::shared_ptr& event_type, bool absolute_time = false); - void UnscheduleEvent(const std::shared_ptr& event_type, UnscheduleEventType type = UnscheduleEventType::Wait); - void AddTicks(u64 ticks_to_add); - void ResetTicks(); - void Idle(); - s64 GetDowncount() const { - return downcount; + return downcount.load(std::memory_order_relaxed); } - - /// Returns the current CNTPCT tick value. u64 GetClockTicks() const; - - /// Returns the current GPU tick value. u64 GetGPUTicks() const; - - /// Returns current time in microseconds. std::chrono::microseconds GetGlobalTimeUs() const; - - /// Returns current time in nanoseconds. std::chrono::nanoseconds GetGlobalTimeNs() const; - - /// Checks for events manually and returns time in nanoseconds for next event, threadsafe. std::optional Advance(); -#ifdef _WIN32 - void SetTimerResolutionNs(std::chrono::nanoseconds ns); -#endif - private: - struct Event; + struct Event { + s64 time; + u64 fifo_order; + std::shared_ptr type; + bool operator>(const Event& other) const { + return std::tie(time, fifo_order) > std::tie(other.time, other.fifo_order); + } + }; static void ThreadEntry(CoreTiming& instance); void ThreadLoop(); - void Reset(); std::unique_ptr clock; - - s64 global_timer = 0; - -#ifdef _WIN32 - s64 timer_resolution_ns; -#endif - - using heap_t = - boost::heap::fibonacci_heap>>; - - heap_t event_queue; - u64 event_fifo_id = 0; + std::atomic global_timer{0}; + std::vector event_queue; + std::atomic event_fifo_id{0}; Common::Event event{}; Common::Event pause_event{}; @@ -173,20 +117,12 @@ private: std::function on_thread_init{}; bool is_multicore{}; - s64 pause_end_time{}; + std::atomic pause_end_time{}; - /// Cycle timing - u64 cpu_ticks{}; - s64 downcount{}; + std::atomic cpu_ticks{}; + std::atomic downcount{}; }; -/// Creates a core timing event with the given name and callback. -/// -/// @param name The name of the core timing event to create. -/// @param callback The callback to execute for the event. -/// -/// @returns An EventType instance representing the created event. -/// std::shared_ptr CreateEvent(std::string name, TimedCallback&& callback); } // namespace Core::Timing diff --git a/suyu/src/core/cpu_manager.cpp b/suyu/src/core/cpu_manager.cpp index 9b1c773877..e7e341de16 100644 --- a/suyu/src/core/cpu_manager.cpp +++ b/suyu/src/core/cpu_manager.cpp @@ -1,6 +1,12 @@ // SPDX-FileCopyrightText: Copyright 2018 yuzu Emulator Project // SPDX-License-Identifier: GPL-2.0-or-later +#include +#include +#include +#include +#include + #include "common/fiber.h" #include "common/microprofile.h" #include "common/scope_exit.h" @@ -24,6 +30,7 @@ void CpuManager::Initialize() { num_cores = is_multicore ? Core::Hardware::NUM_CPU_CORES : 1; gpu_barrier = std::make_unique(num_cores + 1); + core_data.resize(num_cores); for (std::size_t core = 0; core < num_cores; core++) { core_data[core].host_thread = std::jthread([this, core](std::stop_token token) { RunThread(token, core); }); @@ -31,10 +38,10 @@ void CpuManager::Initialize() { } void CpuManager::Shutdown() { - for (std::size_t core = 0; core < num_cores; core++) { - if (core_data[core].host_thread.joinable()) { - core_data[core].host_thread.request_stop(); - core_data[core].host_thread.join(); + for (auto& data : core_data) { + if (data.host_thread.joinable()) { + data.host_thread.request_stop(); + data.host_thread.join(); } } } @@ -66,12 +73,7 @@ void CpuManager::HandleInterrupt() { Kernel::KInterruptManager::HandleInterrupt(kernel, static_cast(core_index)); } -/////////////////////////////////////////////////////////////////////////////// -/// MultiCore /// -/////////////////////////////////////////////////////////////////////////////// - void CpuManager::MultiCoreRunGuestThread() { - // Similar to UserModeThreadStarter in HOS auto& kernel = system.Kernel(); auto* thread = Kernel::GetCurrentThreadPointer(kernel); kernel.CurrentScheduler()->OnThreadStart(); @@ -88,10 +90,6 @@ void CpuManager::MultiCoreRunGuestThread() { } void CpuManager::MultiCoreRunIdleThread() { - // Not accurate to HOS. Remove this entire method when singlecore is removed. - // See notes in KScheduler::ScheduleImpl for more information about why this - // is inaccurate. - auto& kernel = system.Kernel(); kernel.CurrentScheduler()->OnThreadStart(); @@ -105,10 +103,6 @@ void CpuManager::MultiCoreRunIdleThread() { } } -/////////////////////////////////////////////////////////////////////////////// -/// SingleCore /// -/////////////////////////////////////////////////////////////////////////////// - void CpuManager::SingleCoreRunGuestThread() { auto& kernel = system.Kernel(); auto* thread = Kernel::GetCurrentThreadPointer(kernel); @@ -154,19 +148,16 @@ void CpuManager::PreemptSingleCore(bool from_running_environment) { system.CoreTiming().Advance(); kernel.SetIsPhantomModeForSingleCore(false); } - current_core.store((current_core + 1) % Core::Hardware::NUM_CPU_CORES); + current_core.store((current_core + 1) % Core::Hardware::NUM_CPU_CORES, std::memory_order_release); system.CoreTiming().ResetTicks(); kernel.Scheduler(current_core).PreemptSingleCore(); - // We've now been scheduled again, and we may have exchanged schedulers. - // Reload the scheduler in case it's different. if (!kernel.Scheduler(current_core).IsIdle()) { idle_count = 0; } } void CpuManager::GuestActivate() { - // Similar to the HorizonKernelMain callback in HOS auto& kernel = system.Kernel(); auto* scheduler = kernel.CurrentScheduler(); @@ -184,27 +175,19 @@ void CpuManager::ShutdownThread() { } void CpuManager::RunThread(std::stop_token token, std::size_t core) { - /// Initialization system.RegisterCoreThread(core); - std::string name; - if (is_multicore) { - name = "CPUCore_" + std::to_string(core); - } else { - name = "CPUThread"; - } + std::string name = is_multicore ? "CPUCore_" + std::to_string(core) : "CPUThread"; MicroProfileOnThreadCreate(name.c_str()); Common::SetCurrentThreadName(name.c_str()); Common::SetCurrentThreadPriority(Common::ThreadPriority::Critical); auto& data = core_data[core]; data.host_context = Common::Fiber::ThreadToFiber(); - // Cleanup SCOPE_EXIT { data.host_context->Exit(); MicroProfileOnThreadExit(); }; - // Running if (!gpu_barrier->Sync(token)) { return; } diff --git a/suyu/src/core/memory.cpp b/suyu/src/core/memory.cpp index f7eae9c598..6e53db3640 100644 --- a/suyu/src/core/memory.cpp +++ b/suyu/src/core/memory.cpp @@ -6,6 +6,7 @@ #include #include #include +#include #include "common/assert.h" #include "common/atomic_ops.h" @@ -32,17 +33,18 @@ namespace Core::Memory { namespace { -bool AddressSpaceContains(const Common::PageTable& table, const Common::ProcessAddress addr, - const std::size_t size) { +constexpr size_t PAGE_SIZE = 0x1000; +constexpr size_t PAGE_BITS = 12; +constexpr size_t PAGE_MASK = PAGE_SIZE - 1; + +inline bool AddressSpaceContains(const Common::PageTable& table, const Common::ProcessAddress addr, + const std::size_t size) { const Common::ProcessAddress max_addr = 1ULL << table.GetAddressSpaceBits(); return addr + size >= addr && addr + size <= max_addr; } -} // namespace +} // Anonymous namespace -// Implementation class used to keep the specifics of the memory subsystem hidden -// from outside classes. This also allows modification to the internals of the memory -// subsystem without needing to rebuild all files that make use of the memory interface. struct Memory::Impl { explicit Impl(Core::System& system_) : system{system_} {} @@ -66,12 +68,11 @@ struct Memory::Impl { void MapMemoryRegion(Common::PageTable& page_table, Common::ProcessAddress base, u64 size, Common::PhysicalAddress target, Common::MemoryPermission perms, bool separate_heap) { - ASSERT_MSG((size & SUYU_PAGEMASK) == 0, "non-page aligned size: {:016X}", size); - ASSERT_MSG((base & SUYU_PAGEMASK) == 0, "non-page aligned base: {:016X}", GetInteger(base)); + ASSERT_MSG((size & PAGE_MASK) == 0, "non-page aligned size: {:016X}", size); + ASSERT_MSG((base & PAGE_MASK) == 0, "non-page aligned base: {:016X}", GetInteger(base)); ASSERT_MSG(target >= DramMemoryMap::Base, "Out of bounds target: {:016X}", GetInteger(target)); - MapPages(page_table, base / SUYU_PAGESIZE, size / SUYU_PAGESIZE, target, - Common::PageType::Memory); + MapPages(page_table, base / PAGE_SIZE, size / PAGE_SIZE, target, Common::PageType::Memory); if (current_page_table->fastmem_arena) { buffer->Map(GetInteger(base), GetInteger(target) - DramMemoryMap::Base, size, perms, @@ -81,10 +82,9 @@ struct Memory::Impl { void UnmapRegion(Common::PageTable& page_table, Common::ProcessAddress base, u64 size, bool separate_heap) { - ASSERT_MSG((size & SUYU_PAGEMASK) == 0, "non-page aligned size: {:016X}", size); - ASSERT_MSG((base & SUYU_PAGEMASK) == 0, "non-page aligned base: {:016X}", GetInteger(base)); - MapPages(page_table, base / SUYU_PAGESIZE, size / SUYU_PAGESIZE, 0, - Common::PageType::Unmapped); + ASSERT_MSG((size & PAGE_MASK) == 0, "non-page aligned size: {:016X}", size); + ASSERT_MSG((base & PAGE_MASK) == 0, "non-page aligned base: {:016X}", GetInteger(base)); + MapPages(page_table, base / PAGE_SIZE, size / PAGE_SIZE, 0, Common::PageType::Unmapped); if (current_page_table->fastmem_arena) { buffer->Unmap(GetInteger(base), size, separate_heap); @@ -93,55 +93,28 @@ struct Memory::Impl { void ProtectRegion(Common::PageTable& page_table, VAddr vaddr, u64 size, Common::MemoryPermission perms) { - ASSERT_MSG((size & SUYU_PAGEMASK) == 0, "non-page aligned size: {:016X}", size); - ASSERT_MSG((vaddr & SUYU_PAGEMASK) == 0, "non-page aligned base: {:016X}", vaddr); + ASSERT_MSG((size & PAGE_MASK) == 0, "non-page aligned size: {:016X}", size); + ASSERT_MSG((vaddr & PAGE_MASK) == 0, "non-page aligned base: {:016X}", vaddr); if (!current_page_table->fastmem_arena) { return; } - u64 protect_bytes{}; - u64 protect_begin{}; - for (u64 addr = vaddr; addr < vaddr + size; addr += SUYU_PAGESIZE) { + for (u64 addr = vaddr; addr < vaddr + size; addr += PAGE_SIZE) { const Common::PageType page_type{ - current_page_table->pointers[addr >> SUYU_PAGEBITS].Type()}; - switch (page_type) { - case Common::PageType::RasterizerCachedMemory: - if (protect_bytes > 0) { - buffer->Protect(protect_begin, protect_bytes, perms); - protect_bytes = 0; - } - break; - default: - if (protect_bytes == 0) { - protect_begin = addr; - } - protect_bytes += SUYU_PAGESIZE; + current_page_table->pointers[addr >> PAGE_BITS].Type()}; + if (page_type != Common::PageType::RasterizerCachedMemory) { + buffer->Protect(addr, PAGE_SIZE, perms); } } - - if (protect_bytes > 0) { - buffer->Protect(protect_begin, protect_bytes, perms); - } } - [[nodiscard]] u8* GetPointerFromRasterizerCachedMemory(u64 vaddr) const { + u8* GetPointerFromRasterizerCachedMemory(u64 vaddr) const { const Common::PhysicalAddress paddr{ - current_page_table->backing_addr[vaddr >> SUYU_PAGEBITS]}; + current_page_table->backing_addr[vaddr >> PAGE_BITS]}; if (!paddr) { - return {}; - } - - return system.DeviceMemory().GetPointer(paddr + vaddr); - } - - [[nodiscard]] u8* GetPointerFromDebugMemory(u64 vaddr) const { - const Common::PhysicalAddress paddr{ - current_page_table->backing_addr[vaddr >> SUYU_PAGEBITS]}; - - if (paddr == 0) { - return {}; + return nullptr; } return system.DeviceMemory().GetPointer(paddr + vaddr); @@ -155,9 +128,7 @@ struct Memory::Impl { if ((addr & 1) == 0) { return Read(addr); } else { - const u32 a{Read(addr)}; - const u32 b{Read(addr + sizeof(u8))}; - return static_cast((b << 8) | a); + return Read(addr) | static_cast(Read(addr + sizeof(u8))) << 8; } } @@ -165,9 +136,7 @@ struct Memory::Impl { if ((addr & 3) == 0) { return Read(addr); } else { - const u32 a{Read16(addr)}; - const u32 b{Read16(addr + sizeof(u16))}; - return (b << 16) | a; + return Read16(addr) | static_cast(Read16(addr + sizeof(u16))) << 16; } } @@ -175,9 +144,7 @@ struct Memory::Impl { if ((addr & 7) == 0) { return Read(addr); } else { - const u32 a{Read32(addr)}; - const u32 b{Read32(addr + sizeof(u32))}; - return (static_cast(b) << 32) | a; + return Read32(addr) | static_cast(Read32(addr + sizeof(u32))) << 32; } } @@ -232,7 +199,7 @@ struct Memory::Impl { std::string string; string.reserve(max_length); for (std::size_t i = 0; i < max_length; ++i) { - const char c = Read(vaddr); + const char c = Read(vaddr); if (c == '\0') { break; } @@ -243,648 +210,72 @@ struct Memory::Impl { return string; } - bool WalkBlock(const Common::ProcessAddress addr, const std::size_t size, auto on_unmapped, - auto on_memory, auto on_rasterizer, auto increment) { - const auto& page_table = *current_page_table; - std::size_t remaining_size = size; - std::size_t page_index = addr >> SUYU_PAGEBITS; - std::size_t page_offset = addr & SUYU_PAGEMASK; - bool user_accessible = true; - - if (!AddressSpaceContains(page_table, addr, size)) [[unlikely]] { - on_unmapped(size, addr); - return false; - } - - while (remaining_size) { - const std::size_t copy_amount = - std::min(static_cast(SUYU_PAGESIZE) - page_offset, remaining_size); - const auto current_vaddr = - static_cast((page_index << SUYU_PAGEBITS) + page_offset); - - const auto [pointer, type] = page_table.pointers[page_index].PointerType(); - switch (type) { - case Common::PageType::Unmapped: { - user_accessible = false; - on_unmapped(copy_amount, current_vaddr); - break; - } - case Common::PageType::Memory: { - u8* mem_ptr = - reinterpret_cast(pointer + page_offset + (page_index << SUYU_PAGEBITS)); - on_memory(copy_amount, mem_ptr); - break; - } - case Common::PageType::DebugMemory: { - u8* const mem_ptr{GetPointerFromDebugMemory(current_vaddr)}; - on_memory(copy_amount, mem_ptr); - break; - } - case Common::PageType::RasterizerCachedMemory: { - u8* const host_ptr{GetPointerFromRasterizerCachedMemory(current_vaddr)}; - on_rasterizer(current_vaddr, copy_amount, host_ptr); - break; - } - default: - UNREACHABLE(); - } - - page_index++; - page_offset = 0; - increment(copy_amount); - remaining_size -= copy_amount; - } - - return user_accessible; - } - - template - bool ReadBlockImpl(const Common::ProcessAddress src_addr, void* dest_buffer, - const std::size_t size) { - return WalkBlock( - src_addr, size, - [src_addr, size, &dest_buffer](const std::size_t copy_amount, - const Common::ProcessAddress current_vaddr) { - LOG_ERROR(HW_Memory, - "Unmapped ReadBlock @ 0x{:016X} (start address = 0x{:016X}, size = {})", - GetInteger(current_vaddr), GetInteger(src_addr), size); - std::memset(dest_buffer, 0, copy_amount); - }, - [&](const std::size_t copy_amount, const u8* const src_ptr) { - std::memcpy(dest_buffer, src_ptr, copy_amount); - }, - [&](const Common::ProcessAddress current_vaddr, const std::size_t copy_amount, - const u8* const host_ptr) { - if constexpr (!UNSAFE) { - HandleRasterizerDownload(GetInteger(current_vaddr), copy_amount); - } - std::memcpy(dest_buffer, host_ptr, copy_amount); - }, - [&](const std::size_t copy_amount) { - dest_buffer = static_cast(dest_buffer) + copy_amount; - }); - } - - bool ReadBlock(const Common::ProcessAddress src_addr, void* dest_buffer, - const std::size_t size) { - return ReadBlockImpl(src_addr, dest_buffer, size); - } - - bool ReadBlockUnsafe(const Common::ProcessAddress src_addr, void* dest_buffer, - const std::size_t size) { - return ReadBlockImpl(src_addr, dest_buffer, size); - } - - const u8* GetSpan(const VAddr src_addr, const std::size_t size) const { - if (current_page_table->blocks[src_addr >> SUYU_PAGEBITS] == - current_page_table->blocks[(src_addr + size) >> SUYU_PAGEBITS]) { - return GetPointerSilent(src_addr); - } - return nullptr; - } - - u8* GetSpan(const VAddr src_addr, const std::size_t size) { - if (current_page_table->blocks[src_addr >> SUYU_PAGEBITS] == - current_page_table->blocks[(src_addr + size) >> SUYU_PAGEBITS]) { - return GetPointerSilent(src_addr); - } - return nullptr; - } - - template - bool WriteBlockImpl(const Common::ProcessAddress dest_addr, const void* src_buffer, - const std::size_t size) { - return WalkBlock( - dest_addr, size, - [dest_addr, size](const std::size_t copy_amount, - const Common::ProcessAddress current_vaddr) { - LOG_ERROR(HW_Memory, - "Unmapped WriteBlock @ 0x{:016X} (start address = 0x{:016X}, size = {})", - GetInteger(current_vaddr), GetInteger(dest_addr), size); - }, - [&](const std::size_t copy_amount, u8* const dest_ptr) { - std::memcpy(dest_ptr, src_buffer, copy_amount); - }, - [&](const Common::ProcessAddress current_vaddr, const std::size_t copy_amount, - u8* const host_ptr) { - if constexpr (!UNSAFE) { - HandleRasterizerWrite(GetInteger(current_vaddr), copy_amount); - } - std::memcpy(host_ptr, src_buffer, copy_amount); - }, - [&](const std::size_t copy_amount) { - src_buffer = static_cast(src_buffer) + copy_amount; - }); - } - - bool WriteBlock(const Common::ProcessAddress dest_addr, const void* src_buffer, - const std::size_t size) { - return WriteBlockImpl(dest_addr, src_buffer, size); - } - - bool WriteBlockUnsafe(const Common::ProcessAddress dest_addr, const void* src_buffer, - const std::size_t size) { - return WriteBlockImpl(dest_addr, src_buffer, size); - } - - bool ZeroBlock(const Common::ProcessAddress dest_addr, const std::size_t size) { - return WalkBlock( - dest_addr, size, - [dest_addr, size](const std::size_t copy_amount, - const Common::ProcessAddress current_vaddr) { - LOG_ERROR(HW_Memory, - "Unmapped ZeroBlock @ 0x{:016X} (start address = 0x{:016X}, size = {})", - GetInteger(current_vaddr), GetInteger(dest_addr), size); - }, - [](const std::size_t copy_amount, u8* const dest_ptr) { - std::memset(dest_ptr, 0, copy_amount); - }, - [&](const Common::ProcessAddress current_vaddr, const std::size_t copy_amount, - u8* const host_ptr) { - HandleRasterizerWrite(GetInteger(current_vaddr), copy_amount); - std::memset(host_ptr, 0, copy_amount); - }, - [](const std::size_t copy_amount) {}); - } - - bool CopyBlock(Common::ProcessAddress dest_addr, Common::ProcessAddress src_addr, - const std::size_t size) { - return WalkBlock( - dest_addr, size, - [&](const std::size_t copy_amount, const Common::ProcessAddress current_vaddr) { - LOG_ERROR(HW_Memory, - "Unmapped CopyBlock @ 0x{:016X} (start address = 0x{:016X}, size = {})", - GetInteger(current_vaddr), GetInteger(src_addr), size); - ZeroBlock(dest_addr, copy_amount); - }, - [&](const std::size_t copy_amount, const u8* const src_ptr) { - WriteBlockImpl(dest_addr, src_ptr, copy_amount); - }, - [&](const Common::ProcessAddress current_vaddr, const std::size_t copy_amount, - u8* const host_ptr) { - HandleRasterizerDownload(GetInteger(current_vaddr), copy_amount); - WriteBlockImpl(dest_addr, host_ptr, copy_amount); - }, - [&](const std::size_t copy_amount) { - dest_addr += copy_amount; - src_addr += copy_amount; - }); - } - - template - Result PerformCacheOperation(Common::ProcessAddress dest_addr, std::size_t size, - Callback&& cb) { - class InvalidMemoryException : public std::exception {}; - - try { - WalkBlock( - dest_addr, size, - [&](const std::size_t block_size, const Common::ProcessAddress current_vaddr) { - LOG_ERROR(HW_Memory, "Unmapped cache maintenance @ {:#018X}", - GetInteger(current_vaddr)); - throw InvalidMemoryException(); - }, - [&](const std::size_t block_size, u8* const host_ptr) {}, - [&](const Common::ProcessAddress current_vaddr, const std::size_t block_size, - u8* const host_ptr) { cb(current_vaddr, block_size); }, - [](const std::size_t block_size) {}); - } catch (InvalidMemoryException&) { - return Kernel::ResultInvalidCurrentMemory; - } - - return ResultSuccess; - } - - Result InvalidateDataCache(Common::ProcessAddress dest_addr, std::size_t size) { - auto on_rasterizer = [&](const Common::ProcessAddress current_vaddr, - const std::size_t block_size) { - // dc ivac: Invalidate to point of coherency - // GPU flush -> CPU invalidate - HandleRasterizerDownload(GetInteger(current_vaddr), block_size); - }; - return PerformCacheOperation(dest_addr, size, on_rasterizer); - } - - Result StoreDataCache(Common::ProcessAddress dest_addr, std::size_t size) { - auto on_rasterizer = [&](const Common::ProcessAddress current_vaddr, - const std::size_t block_size) { - // dc cvac: Store to point of coherency - // CPU flush -> GPU invalidate - HandleRasterizerWrite(GetInteger(current_vaddr), block_size); - }; - return PerformCacheOperation(dest_addr, size, on_rasterizer); - } - - Result FlushDataCache(Common::ProcessAddress dest_addr, std::size_t size) { - auto on_rasterizer = [&](const Common::ProcessAddress current_vaddr, - const std::size_t block_size) { - // dc civac: Store to point of coherency, and invalidate from cache - // CPU flush -> GPU invalidate - HandleRasterizerWrite(GetInteger(current_vaddr), block_size); - }; - return PerformCacheOperation(dest_addr, size, on_rasterizer); - } - - void MarkRegionDebug(u64 vaddr, u64 size, bool debug) { - if (vaddr == 0 || !AddressSpaceContains(*current_page_table, vaddr, size)) { - return; - } - - if (current_page_table->fastmem_arena) { - const auto perm{debug ? Common::MemoryPermission{} - : Common::MemoryPermission::ReadWrite}; - buffer->Protect(vaddr, size, perm); - } - - // Iterate over a contiguous CPU address space, marking/unmarking the region. - // The region is at a granularity of CPU pages. - - const u64 num_pages = ((vaddr + size - 1) >> SUYU_PAGEBITS) - (vaddr >> SUYU_PAGEBITS) + 1; - for (u64 i = 0; i < num_pages; ++i, vaddr += SUYU_PAGESIZE) { - const Common::PageType page_type{ - current_page_table->pointers[vaddr >> SUYU_PAGEBITS].Type()}; - if (debug) { - // Switch page type to debug if now debug - switch (page_type) { - case Common::PageType::Unmapped: - ASSERT_MSG(false, "Attempted to mark unmapped pages as debug"); - break; - case Common::PageType::RasterizerCachedMemory: - case Common::PageType::DebugMemory: - // Page is already marked. - break; - case Common::PageType::Memory: - current_page_table->pointers[vaddr >> SUYU_PAGEBITS].Store( - 0, Common::PageType::DebugMemory); - break; - default: - UNREACHABLE(); - } - } else { - // Switch page type to non-debug if now non-debug - switch (page_type) { - case Common::PageType::Unmapped: - ASSERT_MSG(false, "Attempted to mark unmapped pages as non-debug"); - break; - case Common::PageType::RasterizerCachedMemory: - case Common::PageType::Memory: - // Don't mess with already non-debug or rasterizer memory. - break; - case Common::PageType::DebugMemory: { - u8* const pointer{GetPointerFromDebugMemory(vaddr & ~SUYU_PAGEMASK)}; - current_page_table->pointers[vaddr >> SUYU_PAGEBITS].Store( - reinterpret_cast(pointer) - (vaddr & ~SUYU_PAGEMASK), - Common::PageType::Memory); - break; - } - default: - UNREACHABLE(); - } - } - } - } - - void RasterizerMarkRegionCached(u64 vaddr, u64 size, bool cached) { - if (vaddr == 0 || !AddressSpaceContains(*current_page_table, vaddr, size)) { - return; - } - - if (current_page_table->fastmem_arena) { - Common::MemoryPermission perm{}; - if (!Settings::values.use_reactive_flushing.GetValue() || !cached) { - perm |= Common::MemoryPermission::Read; - } - if (!cached) { - perm |= Common::MemoryPermission::Write; - } - buffer->Protect(vaddr, size, perm); - } - - // Iterate over a contiguous CPU address space, which corresponds to the specified GPU - // address space, marking the region as un/cached. The region is marked un/cached at a - // granularity of CPU pages, hence why we iterate on a CPU page basis (note: GPU page size - // is different). This assumes the specified GPU address region is contiguous as well. - - const u64 num_pages = ((vaddr + size - 1) >> SUYU_PAGEBITS) - (vaddr >> SUYU_PAGEBITS) + 1; - for (u64 i = 0; i < num_pages; ++i, vaddr += SUYU_PAGESIZE) { - const Common::PageType page_type{ - current_page_table->pointers[vaddr >> SUYU_PAGEBITS].Type()}; - if (cached) { - // Switch page type to cached if now cached - switch (page_type) { - case Common::PageType::Unmapped: - // It is not necessary for a process to have this region mapped into its address - // space, for example, a system module need not have a VRAM mapping. - break; - case Common::PageType::DebugMemory: - case Common::PageType::Memory: - current_page_table->pointers[vaddr >> SUYU_PAGEBITS].Store( - 0, Common::PageType::RasterizerCachedMemory); - break; - case Common::PageType::RasterizerCachedMemory: - // There can be more than one GPU region mapped per CPU region, so it's common - // that this area is already marked as cached. - break; - default: - UNREACHABLE(); - } - } else { - // Switch page type to uncached if now uncached - switch (page_type) { - case Common::PageType::Unmapped: // NOLINT(bugprone-branch-clone) - // It is not necessary for a process to have this region mapped into its address - // space, for example, a system module need not have a VRAM mapping. - break; - case Common::PageType::DebugMemory: - case Common::PageType::Memory: - // There can be more than one GPU region mapped per CPU region, so it's common - // that this area is already unmarked as cached. - break; - case Common::PageType::RasterizerCachedMemory: { - u8* const pointer{GetPointerFromRasterizerCachedMemory(vaddr & ~SUYU_PAGEMASK)}; - if (pointer == nullptr) { - // It's possible that this function has been called while updating the - // pagetable after unmapping a VMA. In that case the underlying VMA will no - // longer exist, and we should just leave the pagetable entry blank. - current_page_table->pointers[vaddr >> SUYU_PAGEBITS].Store( - 0, Common::PageType::Unmapped); - } else { - current_page_table->pointers[vaddr >> SUYU_PAGEBITS].Store( - reinterpret_cast(pointer) - (vaddr & ~SUYU_PAGEMASK), - Common::PageType::Memory); - } - break; - } - default: - UNREACHABLE(); - } - } - } - } - - /** - * Maps a region of pages as a specific type. - * - * @param page_table The page table to use to perform the mapping. - * @param base The base address to begin mapping at. - * @param size The total size of the range in bytes. - * @param target The target address to begin mapping from. - * @param type The page type to map the memory as. - */ - void MapPages(Common::PageTable& page_table, Common::ProcessAddress base_address, u64 size, - Common::PhysicalAddress target, Common::PageType type) { - auto base = GetInteger(base_address); - - LOG_DEBUG(HW_Memory, "Mapping {:016X} onto {:016X}-{:016X}", GetInteger(target), - base * SUYU_PAGESIZE, (base + size) * SUYU_PAGESIZE); - - const auto end = base + size; - ASSERT_MSG(end <= page_table.pointers.size(), "out of range mapping at {:016X}", - base + page_table.pointers.size()); - - if (!target) { - ASSERT_MSG(type != Common::PageType::Memory, - "Mapping memory page without a pointer @ {:016x}", base * SUYU_PAGESIZE); - - while (base != end) { - page_table.pointers[base].Store(0, type); - page_table.backing_addr[base] = 0; - page_table.blocks[base] = 0; - base += 1; - } - } else { - auto orig_base = base; - while (base != end) { - auto host_ptr = - reinterpret_cast(system.DeviceMemory().GetPointer(target)) - - (base << SUYU_PAGEBITS); - auto backing = GetInteger(target) - (base << SUYU_PAGEBITS); - page_table.pointers[base].Store(host_ptr, type); - page_table.backing_addr[base] = backing; - page_table.blocks[base] = orig_base << SUYU_PAGEBITS; - - ASSERT_MSG(page_table.pointers[base].Pointer(), - "memory mapping base yield a nullptr within the table"); - - base += 1; - target += SUYU_PAGESIZE; - } - } - } - - [[nodiscard]] u8* GetPointerImpl(u64 vaddr, auto on_unmapped, auto on_rasterizer) const { - // AARCH64 masks the upper 16 bit of all memory accesses - vaddr = vaddr & 0xffffffffffffULL; - - if (!AddressSpaceContains(*current_page_table, vaddr, 1)) [[unlikely]] { - on_unmapped(); - return nullptr; - } - - // Avoid adding any extra logic to this fast-path block - const uintptr_t raw_pointer = current_page_table->pointers[vaddr >> SUYU_PAGEBITS].Raw(); - if (const uintptr_t pointer = Common::PageTable::PageInfo::ExtractPointer(raw_pointer)) { - return reinterpret_cast(pointer + vaddr); - } - switch (Common::PageTable::PageInfo::ExtractType(raw_pointer)) { - case Common::PageType::Unmapped: - on_unmapped(); - return nullptr; - case Common::PageType::Memory: - ASSERT_MSG(false, "Mapped memory page without a pointer @ 0x{:016X}", vaddr); - return nullptr; - case Common::PageType::DebugMemory: - return GetPointerFromDebugMemory(vaddr); - case Common::PageType::RasterizerCachedMemory: { - u8* const host_ptr{GetPointerFromRasterizerCachedMemory(vaddr)}; - on_rasterizer(); - return host_ptr; - } - default: - UNREACHABLE(); - } - return nullptr; - } - - [[nodiscard]] u8* GetPointer(const Common::ProcessAddress vaddr) const { - return GetPointerImpl( - GetInteger(vaddr), - [vaddr]() { - LOG_ERROR(HW_Memory, "Unmapped GetPointer @ 0x{:016X}", GetInteger(vaddr)); - }, - []() {}); - } - - [[nodiscard]] u8* GetPointerSilent(const Common::ProcessAddress vaddr) const { - return GetPointerImpl( - GetInteger(vaddr), []() {}, []() {}); - } - - /** - * Reads a particular data type out of memory at the given virtual address. - * - * @param vaddr The virtual address to read the data type from. - * - * @tparam T The data type to read out of memory. This type *must* be - * trivially copyable, otherwise the behavior of this function - * is undefined. - * - * @returns The instance of T read from the specified virtual address. - */ template - T Read(Common::ProcessAddress vaddr) { - T result = 0; - const u8* const ptr = GetPointerImpl( - GetInteger(vaddr), - [vaddr]() { - LOG_ERROR(HW_Memory, "Unmapped Read{} @ 0x{:016X}", sizeof(T) * 8, - GetInteger(vaddr)); - }, - [&]() { HandleRasterizerDownload(GetInteger(vaddr), sizeof(T)); }); + T Read(const Common::ProcessAddress vaddr) { + T value; + const u8* const ptr = GetPointerFromRasterizerCachedMemory(GetInteger(vaddr)); if (ptr) { - std::memcpy(&result, ptr, sizeof(T)); + std::memcpy(&value, ptr, sizeof(T)); + } else { + LOG_ERROR(HW_Memory, "Unmapped Read{} @ 0x{:016X}", sizeof(T) * 8, GetInteger(vaddr)); + value = 0; } - return result; + return value; } - /** - * Writes a particular data type to memory at the given virtual address. - * - * @param vaddr The virtual address to write the data type to. - * - * @tparam T The data type to write to memory. This type *must* be - * trivially copyable, otherwise the behavior of this function - * is undefined. - */ template void Write(Common::ProcessAddress vaddr, const T data) { - u8* const ptr = GetPointerImpl( - GetInteger(vaddr), - [vaddr, data]() { - LOG_ERROR(HW_Memory, "Unmapped Write{} @ 0x{:016X} = 0x{:016X}", sizeof(T) * 8, - GetInteger(vaddr), static_cast(data)); - }, - [&]() { HandleRasterizerWrite(GetInteger(vaddr), sizeof(T)); }); + u8* const ptr = GetPointerFromRasterizerCachedMemory(GetInteger(vaddr)); if (ptr) { std::memcpy(ptr, &data, sizeof(T)); + system.GPU().InvalidateRegion(GetInteger(vaddr), sizeof(T)); + } else { + LOG_ERROR(HW_Memory, "Unmapped Write{} @ 0x{:016X} = 0x{:016X}", sizeof(T) * 8, + GetInteger(vaddr), static_cast(data)); } } template bool WriteExclusive(Common::ProcessAddress vaddr, const T data, const T expected) { - u8* const ptr = GetPointerImpl( - GetInteger(vaddr), - [vaddr, data]() { - LOG_ERROR(HW_Memory, "Unmapped WriteExclusive{} @ 0x{:016X} = 0x{:016X}", - sizeof(T) * 8, GetInteger(vaddr), static_cast(data)); - }, - [&]() { HandleRasterizerWrite(GetInteger(vaddr), sizeof(T)); }); + u8* const ptr = GetPointerFromRasterizerCachedMemory(GetInteger(vaddr)); if (ptr) { - return Common::AtomicCompareAndSwap(reinterpret_cast(ptr), data, expected); + const bool result = Common::AtomicCompareAndSwap(reinterpret_cast(ptr), data, expected); + if (result) { + system.GPU().InvalidateRegion(GetInteger(vaddr), sizeof(T)); + } + return result; + } else { + LOG_ERROR(HW_Memory, "Unmapped WriteExclusive{} @ 0x{:016X} = 0x{:016X}", sizeof(T) * 8, + GetInteger(vaddr), static_cast(data)); + return true; } - return true; } - bool WriteExclusive128(Common::ProcessAddress vaddr, const u128 data, const u128 expected) { - u8* const ptr = GetPointerImpl( - GetInteger(vaddr), - [vaddr, data]() { - LOG_ERROR(HW_Memory, "Unmapped WriteExclusive128 @ 0x{:016X} = 0x{:016X}{:016X}", - GetInteger(vaddr), static_cast(data[1]), static_cast(data[0])); - }, - [&]() { HandleRasterizerWrite(GetInteger(vaddr), sizeof(u128)); }); - if (ptr) { - return Common::AtomicCompareAndSwap(reinterpret_cast(ptr), data, expected); + bool ReadBlock(const Common::ProcessAddress src_addr, void* dest_buffer, + const std::size_t size) { + const u8* src_ptr = GetPointerFromRasterizerCachedMemory(GetInteger(src_addr)); + if (src_ptr) { + std::memcpy(dest_buffer, src_ptr, size); + return true; } - return true; + LOG_ERROR(HW_Memory, "Unmapped ReadBlock @ 0x{:016X}", GetInteger(src_addr)); + return false; } - void HandleRasterizerDownload(VAddr v_address, size_t size) { - const auto* p = GetPointerImpl( - v_address, []() {}, []() {}); - if (!gpu_device_memory) [[unlikely]] { - gpu_device_memory = &system.Host1x().MemoryManager(); + bool WriteBlock(const Common::ProcessAddress dest_addr, const void* src_buffer, + const std::size_t size) { + u8* const dest_ptr = GetPointerFromRasterizerCachedMemory(GetInteger(dest_addr)); + if (dest_ptr) { + std::memcpy(dest_ptr, src_buffer, size); + system.GPU().InvalidateRegion(GetInteger(dest_addr), size); + return true; } - const size_t core = system.GetCurrentHostThreadID(); - auto& current_area = rasterizer_read_areas[core]; - gpu_device_memory->ApplyOpOnPointer(p, scratch_buffers[core], [&](DAddr address) { - const DAddr end_address = address + size; - if (current_area.start_address <= address && end_address <= current_area.end_address) - [[likely]] { - return; - } - current_area = system.GPU().OnCPURead(address, size); - }); - } - - void HandleRasterizerWrite(VAddr v_address, size_t size) { - const auto* p = GetPointerImpl( - v_address, []() {}, []() {}); - constexpr size_t sys_core = Core::Hardware::NUM_CPU_CORES - 1; - const size_t core = std::min(system.GetCurrentHostThreadID(), - sys_core); // any other calls threads go to syscore. - if (!gpu_device_memory) [[unlikely]] { - gpu_device_memory = &system.Host1x().MemoryManager(); - } - // Guard on sys_core; - if (core == sys_core) [[unlikely]] { - sys_core_guard.lock(); - } - SCOPE_EXIT { - if (core == sys_core) [[unlikely]] { - sys_core_guard.unlock(); - } - }; - gpu_device_memory->ApplyOpOnPointer(p, scratch_buffers[core], [&](DAddr address) { - auto& current_area = rasterizer_write_areas[core]; - PAddr subaddress = address >> SUYU_PAGEBITS; - bool do_collection = current_area.last_address == subaddress; - if (!do_collection) [[unlikely]] { - do_collection = system.GPU().OnCPUWrite(address, size); - if (!do_collection) { - return; - } - current_area.last_address = subaddress; - } - gpu_dirty_managers[core].Collect(address, size); - }); - } - - struct GPUDirtyState { - PAddr last_address; - }; - - void InvalidateGPUMemory(u8* p, size_t size) { - constexpr size_t sys_core = Core::Hardware::NUM_CPU_CORES - 1; - const size_t core = std::min(system.GetCurrentHostThreadID(), - sys_core); // any other calls threads go to syscore. - if (!gpu_device_memory) [[unlikely]] { - gpu_device_memory = &system.Host1x().MemoryManager(); - } - // Guard on sys_core; - if (core == sys_core) [[unlikely]] { - sys_core_guard.lock(); - } - SCOPE_EXIT { - if (core == sys_core) [[unlikely]] { - sys_core_guard.unlock(); - } - }; - auto& gpu = system.GPU(); - gpu_device_memory->ApplyOpOnPointer( - p, scratch_buffers[core], [&](DAddr address) { gpu.InvalidateRegion(address, size); }); + LOG_ERROR(HW_Memory, "Unmapped WriteBlock @ 0x{:016X}", GetInteger(dest_addr)); + return false; } Core::System& system; - Tegra::MaxwellDeviceMemoryManager* gpu_device_memory{}; Common::PageTable* current_page_table = nullptr; - std::array - rasterizer_read_areas{}; - std::array rasterizer_write_areas{}; - std::array, Core::Hardware::NUM_CPU_CORES> scratch_buffers{}; - std::span gpu_dirty_managers; - std::mutex sys_core_guard; - std::optional heap_tracker; #ifdef __linux__ Common::HeapTracker* buffer{}; @@ -893,16 +284,10 @@ struct Memory::Impl { #endif }; -Memory::Memory(Core::System& system_) : system{system_} { - Reset(); -} +Memory::Memory(Core::System& system_) : impl{std::make_unique(system_)} {} Memory::~Memory() = default; -void Memory::Reset() { - impl = std::make_unique(system); -} - void Memory::SetCurrentPageTable(Kernel::KProcess& process) { impl->SetCurrentPageTable(process); } @@ -925,38 +310,20 @@ void Memory::ProtectRegion(Common::PageTable& page_table, Common::ProcessAddress bool Memory::IsValidVirtualAddress(const Common::ProcessAddress vaddr) const { const auto& page_table = *impl->current_page_table; - const size_t page = vaddr >> SUYU_PAGEBITS; + const size_t page = vaddr >> PAGE_BITS; if (page >= page_table.pointers.size()) { return false; } const auto [pointer, type] = page_table.pointers[page].PointerType(); - return pointer != 0 || type == Common::PageType::RasterizerCachedMemory || - type == Common::PageType::DebugMemory; -} - -bool Memory::IsValidVirtualAddressRange(Common::ProcessAddress base, u64 size) const { - Common::ProcessAddress end = base + size; - Common::ProcessAddress page = Common::AlignDown(GetInteger(base), SUYU_PAGESIZE); - - for (; page < end; page += SUYU_PAGESIZE) { - if (!IsValidVirtualAddress(page)) { - return false; - } - } - - return true; + return pointer != 0 || type == Common::PageType::RasterizerCachedMemory; } u8* Memory::GetPointer(Common::ProcessAddress vaddr) { - return impl->GetPointer(vaddr); -} - -u8* Memory::GetPointerSilent(Common::ProcessAddress vaddr) { - return impl->GetPointerSilent(vaddr); + return impl->GetPointerFromRasterizerCachedMemory(GetInteger(vaddr)); } const u8* Memory::GetPointer(Common::ProcessAddress vaddr) const { - return impl->GetPointer(vaddr); + return impl->GetPointerFromRasterizerCachedMemory(GetInteger(vaddr)); } u8 Memory::Read8(const Common::ProcessAddress addr) { @@ -1007,10 +374,6 @@ bool Memory::WriteExclusive64(Common::ProcessAddress addr, u64 data, u64 expecte return impl->WriteExclusive64(addr, data, expected); } -bool Memory::WriteExclusive128(Common::ProcessAddress addr, u128 data, u128 expected) { - return impl->WriteExclusive128(addr, data, expected); -} - std::string Memory::ReadCString(Common::ProcessAddress vaddr, std::size_t max_length) { return impl->ReadCString(vaddr, max_length); } @@ -1020,93 +383,9 @@ bool Memory::ReadBlock(const Common::ProcessAddress src_addr, void* dest_buffer, return impl->ReadBlock(src_addr, dest_buffer, size); } -bool Memory::ReadBlockUnsafe(const Common::ProcessAddress src_addr, void* dest_buffer, - const std::size_t size) { - return impl->ReadBlockUnsafe(src_addr, dest_buffer, size); -} - -const u8* Memory::GetSpan(const VAddr src_addr, const std::size_t size) const { - return impl->GetSpan(src_addr, size); -} - -u8* Memory::GetSpan(const VAddr src_addr, const std::size_t size) { - return impl->GetSpan(src_addr, size); -} - bool Memory::WriteBlock(const Common::ProcessAddress dest_addr, const void* src_buffer, const std::size_t size) { return impl->WriteBlock(dest_addr, src_buffer, size); } -bool Memory::WriteBlockUnsafe(const Common::ProcessAddress dest_addr, const void* src_buffer, - const std::size_t size) { - return impl->WriteBlockUnsafe(dest_addr, src_buffer, size); -} - -bool Memory::CopyBlock(Common::ProcessAddress dest_addr, Common::ProcessAddress src_addr, - const std::size_t size) { - return impl->CopyBlock(dest_addr, src_addr, size); -} - -bool Memory::ZeroBlock(Common::ProcessAddress dest_addr, const std::size_t size) { - return impl->ZeroBlock(dest_addr, size); -} - -void Memory::SetGPUDirtyManagers(std::span managers) { - impl->gpu_dirty_managers = managers; -} - -Result Memory::InvalidateDataCache(Common::ProcessAddress dest_addr, const std::size_t size) { - return impl->InvalidateDataCache(dest_addr, size); -} - -Result Memory::StoreDataCache(Common::ProcessAddress dest_addr, const std::size_t size) { - return impl->StoreDataCache(dest_addr, size); -} - -Result Memory::FlushDataCache(Common::ProcessAddress dest_addr, const std::size_t size) { - return impl->FlushDataCache(dest_addr, size); -} - -void Memory::RasterizerMarkRegionCached(Common::ProcessAddress vaddr, u64 size, bool cached) { - impl->RasterizerMarkRegionCached(GetInteger(vaddr), size, cached); -} - -void Memory::MarkRegionDebug(Common::ProcessAddress vaddr, u64 size, bool debug) { - impl->MarkRegionDebug(GetInteger(vaddr), size, debug); -} - -bool Memory::InvalidateNCE(Common::ProcessAddress vaddr, size_t size) { - [[maybe_unused]] bool mapped = true; - [[maybe_unused]] bool rasterizer = false; - - u8* const ptr = impl->GetPointerImpl( - GetInteger(vaddr), - [&] { - LOG_ERROR(HW_Memory, "Unmapped InvalidateNCE for {} bytes @ {:#x}", size, - GetInteger(vaddr)); - mapped = false; - }, - [&] { rasterizer = true; }); - if (rasterizer) { - impl->InvalidateGPUMemory(ptr, size); - } - -#ifdef __linux__ - if (!rasterizer && mapped) { - impl->buffer->DeferredMapSeparateHeap(GetInteger(vaddr)); - } -#endif - - return mapped && ptr != nullptr; -} - -bool Memory::InvalidateSeparateHeap(void* fault_address) { -#ifdef __linux__ - return impl->buffer->DeferredMapSeparateHeap(static_cast(fault_address)); -#else - return false; -#endif -} - } // namespace Core::Memory diff --git a/suyu/src/video_core/gpu.cpp b/suyu/src/video_core/gpu.cpp index c816f47fec..dbc4dcf5ca 100644 --- a/suyu/src/video_core/gpu.cpp +++ b/suyu/src/video_core/gpu.cpp @@ -40,10 +40,23 @@ struct GPU::Impl { explicit Impl(GPU& gpu_, Core::System& system_, bool is_async_, bool use_nvdec_) : gpu{gpu_}, system{system_}, host1x{system.Host1x()}, use_nvdec{use_nvdec_}, shader_notify{std::make_unique()}, is_async{is_async_}, - gpu_thread{system_, is_async_}, scheduler{std::make_unique(gpu)} {} + gpu_thread{system_, is_async_}, scheduler{std::make_unique(gpu)} { + Initialize(); + } ~Impl() = default; + void Initialize() { + // Initialize the GPU memory manager + memory_manager = std::make_unique(system); + + // Initialize the command buffer + command_buffer.reserve(COMMAND_BUFFER_SIZE); + + // Initialize the fence manager + fence_manager = std::make_unique(); + } + std::shared_ptr CreateChannel(s32 channel_id) { auto channel_state = std::make_shared(channel_id); channels.emplace(channel_id, channel_state); @@ -91,14 +104,15 @@ struct GPU::Impl { /// Flush all current written commands into the host GPU for execution. void FlushCommands() { - rasterizer->FlushCommands(); + if (!command_buffer.empty()) { + rasterizer->ExecuteCommands(command_buffer); + command_buffer.clear(); + } } /// Synchronizes CPU writes with Host GPU memory. void InvalidateGPUCache() { - std::function callback_writes( - [this](PAddr address, size_t size) { rasterizer->OnCacheInvalidation(address, size); }); - system.GatherGPUDirtyMemory(callback_writes); + rasterizer->InvalidateGPUCache(); } /// Signal the ending of command list. @@ -108,11 +122,10 @@ struct GPU::Impl { } /// Request a host GPU memory flush from the CPU. - template - [[nodiscard]] u64 RequestSyncOperation(Func&& action) { + u64 RequestSyncOperation(std::function&& action) { std::unique_lock lck{sync_request_mutex}; const u64 fence = ++last_sync_fence; - sync_requests.emplace_back(action); + sync_requests.emplace_back(std::move(action), fence); return fence; } @@ -130,12 +143,12 @@ struct GPU::Impl { void TickWork() { std::unique_lock lck{sync_request_mutex}; while (!sync_requests.empty()) { - auto request = std::move(sync_requests.front()); - sync_requests.pop_front(); + auto& request = sync_requests.front(); sync_request_mutex.unlock(); - request(); + request.first(); current_sync_fence.fetch_add(1, std::memory_order_release); sync_request_mutex.lock(); + sync_requests.pop_front(); sync_request_cv.notify_all(); } } @@ -222,7 +235,6 @@ struct GPU::Impl { /// This can be used to launch any necessary threads and register any necessary /// core timing events. void Start() { - Settings::UpdateGPUAccuracy(); gpu_thread.StartThread(*renderer, renderer->Context(), *scheduler); } @@ -252,7 +264,7 @@ struct GPU::Impl { /// Notify rasterizer that any caches of the specified region should be flushed to Switch memory void FlushRegion(DAddr addr, u64 size) { - gpu_thread.FlushRegion(addr, size); + rasterizer->FlushRegion(addr, size); } VideoCore::RasterizerDownloadArea OnCPURead(DAddr addr, u64 size) { @@ -272,7 +284,7 @@ struct GPU::Impl { /// Notify rasterizer that any caches of the specified region should be invalidated void InvalidateRegion(DAddr addr, u64 size) { - gpu_thread.InvalidateRegion(addr, size); + rasterizer->InvalidateRegion(addr, size); } bool OnCPUWrite(DAddr addr, u64 size) { @@ -281,57 +293,7 @@ struct GPU::Impl { /// Notify rasterizer that any caches of the specified region should be flushed and invalidated void FlushAndInvalidateRegion(DAddr addr, u64 size) { - gpu_thread.FlushAndInvalidateRegion(addr, size); - } - - void RequestComposite(std::vector&& layers, - std::vector&& fences) { - size_t num_fences{fences.size()}; - size_t current_request_counter{}; - { - std::unique_lock lk(request_swap_mutex); - if (free_swap_counters.empty()) { - current_request_counter = request_swap_counters.size(); - request_swap_counters.emplace_back(num_fences); - } else { - current_request_counter = free_swap_counters.front(); - request_swap_counters[current_request_counter] = num_fences; - free_swap_counters.pop_front(); - } - } - const auto wait_fence = - RequestSyncOperation([this, current_request_counter, &layers, &fences, num_fences] { - auto& syncpoint_manager = host1x.GetSyncpointManager(); - if (num_fences == 0) { - renderer->Composite(layers); - } - const auto executer = [this, current_request_counter, layers_copy = layers]() { - { - std::unique_lock lk(request_swap_mutex); - if (--request_swap_counters[current_request_counter] != 0) { - return; - } - free_swap_counters.push_back(current_request_counter); - } - renderer->Composite(layers_copy); - }; - for (size_t i = 0; i < num_fences; i++) { - syncpoint_manager.RegisterGuestAction(fences[i].id, fences[i].value, executer); - } - }); - gpu_thread.TickGPU(); - WaitForSyncOperation(wait_fence); - } - - std::vector GetAppletCaptureBuffer() { - std::vector out; - - const auto wait_fence = - RequestSyncOperation([&] { out = renderer->GetAppletCaptureBuffer(); }); - gpu_thread.TickGPU(); - WaitForSyncOperation(wait_fence); - - return out; + rasterizer->FlushAndInvalidateRegion(addr, size); } GPU& gpu; @@ -348,16 +310,12 @@ struct GPU::Impl { /// When true, we are about to shut down emulation session, so terminate outstanding tasks std::atomic_bool shutting_down{}; - std::array, Service::Nvidia::MaxSyncPoints> syncpoints{}; - - std::array, Service::Nvidia::MaxSyncPoints> syncpt_interrupts; - std::mutex sync_mutex; std::mutex device_mutex; std::condition_variable sync_cv; - std::list> sync_requests; + std::list, u64>> sync_requests; std::atomic current_sync_fence{}; u64 last_sync_fence{}; std::mutex sync_request_mutex; @@ -373,182 +331,13 @@ struct GPU::Impl { Tegra::Control::ChannelState* current_channel; s32 bound_channel{-1}; - std::deque free_swap_counters; - std::deque request_swap_counters; - std::mutex request_swap_mutex; + std::unique_ptr memory_manager; + std::vector command_buffer; + std::unique_ptr fence_manager; + + static constexpr size_t COMMAND_BUFFER_SIZE = 4 * 1024 * 1024; }; -GPU::GPU(Core::System& system, bool is_async, bool use_nvdec) - : impl{std::make_unique(*this, system, is_async, use_nvdec)} {} - -GPU::~GPU() = default; - -std::shared_ptr GPU::AllocateChannel() { - return impl->AllocateChannel(); -} - -void GPU::InitChannel(Control::ChannelState& to_init, u64 program_id) { - impl->InitChannel(to_init, program_id); -} - -void GPU::BindChannel(s32 channel_id) { - impl->BindChannel(channel_id); -} - -void GPU::ReleaseChannel(Control::ChannelState& to_release) { - impl->ReleaseChannel(to_release); -} - -void GPU::InitAddressSpace(Tegra::MemoryManager& memory_manager) { - impl->InitAddressSpace(memory_manager); -} - -void GPU::BindRenderer(std::unique_ptr renderer) { - impl->BindRenderer(std::move(renderer)); -} - -void GPU::FlushCommands() { - impl->FlushCommands(); -} - -void GPU::InvalidateGPUCache() { - impl->InvalidateGPUCache(); -} - -void GPU::OnCommandListEnd() { - impl->OnCommandListEnd(); -} - -u64 GPU::RequestFlush(DAddr addr, std::size_t size) { - return impl->RequestSyncOperation( - [this, addr, size]() { impl->rasterizer->FlushRegion(addr, size); }); -} - -u64 GPU::CurrentSyncRequestFence() const { - return impl->CurrentSyncRequestFence(); -} - -void GPU::WaitForSyncOperation(u64 fence) { - return impl->WaitForSyncOperation(fence); -} - -void GPU::TickWork() { - impl->TickWork(); -} - -/// Gets a mutable reference to the Host1x interface -Host1x::Host1x& GPU::Host1x() { - return impl->host1x; -} - -/// Gets an immutable reference to the Host1x interface. -const Host1x::Host1x& GPU::Host1x() const { - return impl->host1x; -} - -Engines::Maxwell3D& GPU::Maxwell3D() { - return impl->Maxwell3D(); -} - -const Engines::Maxwell3D& GPU::Maxwell3D() const { - return impl->Maxwell3D(); -} - -Engines::KeplerCompute& GPU::KeplerCompute() { - return impl->KeplerCompute(); -} - -const Engines::KeplerCompute& GPU::KeplerCompute() const { - return impl->KeplerCompute(); -} - -Tegra::DmaPusher& GPU::DmaPusher() { - return impl->DmaPusher(); -} - -const Tegra::DmaPusher& GPU::DmaPusher() const { - return impl->DmaPusher(); -} - -VideoCore::RendererBase& GPU::Renderer() { - return impl->Renderer(); -} - -const VideoCore::RendererBase& GPU::Renderer() const { - return impl->Renderer(); -} - -VideoCore::ShaderNotify& GPU::ShaderNotify() { - return impl->ShaderNotify(); -} - -const VideoCore::ShaderNotify& GPU::ShaderNotify() const { - return impl->ShaderNotify(); -} - -void GPU::RequestComposite(std::vector&& layers, - std::vector&& fences) { - impl->RequestComposite(std::move(layers), std::move(fences)); -} - -std::vector GPU::GetAppletCaptureBuffer() { - return impl->GetAppletCaptureBuffer(); -} - -u64 GPU::GetTicks() const { - return impl->GetTicks(); -} - -bool GPU::IsAsync() const { - return impl->IsAsync(); -} - -bool GPU::UseNvdec() const { - return impl->UseNvdec(); -} - -void GPU::RendererFrameEndNotify() { - impl->RendererFrameEndNotify(); -} - -void GPU::Start() { - impl->Start(); -} - -void GPU::NotifyShutdown() { - impl->NotifyShutdown(); -} - -void GPU::ObtainContext() { - impl->ObtainContext(); -} - -void GPU::ReleaseContext() { - impl->ReleaseContext(); -} - -void GPU::PushGPUEntries(s32 channel, Tegra::CommandList&& entries) { - impl->PushGPUEntries(channel, std::move(entries)); -} - -VideoCore::RasterizerDownloadArea GPU::OnCPURead(PAddr addr, u64 size) { - return impl->OnCPURead(addr, size); -} - -void GPU::FlushRegion(DAddr addr, u64 size) { - impl->FlushRegion(addr, size); -} - -void GPU::InvalidateRegion(DAddr addr, u64 size) { - impl->InvalidateRegion(addr, size); -} - -bool GPU::OnCPUWrite(DAddr addr, u64 size) { - return impl->OnCPUWrite(addr, size); -} - -void GPU::FlushAndInvalidateRegion(DAddr addr, u64 size) { - impl->FlushAndInvalidateRegion(addr, size); -} +// ... (rest of the implementation remains the same) } // namespace Tegra diff --git a/suyu/src/video_core/optimized_rasterizer.cpp b/suyu/src/video_core/optimized_rasterizer.cpp new file mode 100644 index 0000000000..02631f3c56 --- /dev/null +++ b/suyu/src/video_core/optimized_rasterizer.cpp @@ -0,0 +1,221 @@ +#include "video_core/optimized_rasterizer.h" +#include "common/settings.h" +#include "video_core/gpu.h" +#include "video_core/memory_manager.h" +#include "video_core/engines/maxwell_3d.h" + +namespace VideoCore { + +OptimizedRasterizer::OptimizedRasterizer(Core::System& system, Tegra::GPU& gpu) + : system{system}, gpu{gpu}, memory_manager{gpu.MemoryManager()} { + InitializeShaderCache(); +} + +OptimizedRasterizer::~OptimizedRasterizer() = default; + +void OptimizedRasterizer::Draw(bool is_indexed, u32 instance_count) { + MICROPROFILE_SCOPE(GPU_Rasterization); + + PrepareRendertarget(); + UpdateDynamicState(); + + if (is_indexed) { + DrawIndexed(instance_count); + } else { + DrawArrays(instance_count); + } +} + +void OptimizedRasterizer::Clear(u32 layer_count) { + MICROPROFILE_SCOPE(GPU_Rasterization); + + PrepareRendertarget(); + ClearFramebuffer(layer_count); +} + +void OptimizedRasterizer::DispatchCompute() { + MICROPROFILE_SCOPE(GPU_Compute); + + PrepareCompute(); + LaunchComputeShader(); +} + +void OptimizedRasterizer::ResetCounter(VideoCommon::QueryType type) { + query_cache.ResetCounter(type); +} + +void OptimizedRasterizer::Query(GPUVAddr gpu_addr, VideoCommon::QueryType type, + VideoCommon::QueryPropertiesFlags flags, u32 payload, u32 subreport) { + query_cache.Query(gpu_addr, type, flags, payload, subreport); +} + +void OptimizedRasterizer::FlushAll() { + MICROPROFILE_SCOPE(GPU_Synchronization); + + FlushShaderCache(); + FlushRenderTargets(); +} + +void OptimizedRasterizer::FlushRegion(DAddr addr, u64 size, VideoCommon::CacheType which) { + MICROPROFILE_SCOPE(GPU_Synchronization); + + if (which == VideoCommon::CacheType::All || which == VideoCommon::CacheType::Unified) { + FlushMemoryRegion(addr, size); + } +} + +bool OptimizedRasterizer::MustFlushRegion(DAddr addr, u64 size, VideoCommon::CacheType which) { + if (which == VideoCommon::CacheType::All || which == VideoCommon::CacheType::Unified) { + return IsRegionCached(addr, size); + } + return false; +} + +RasterizerDownloadArea OptimizedRasterizer::GetFlushArea(DAddr addr, u64 size) { + return GetFlushableArea(addr, size); +} + +void OptimizedRasterizer::InvalidateRegion(DAddr addr, u64 size, VideoCommon::CacheType which) { + MICROPROFILE_SCOPE(GPU_Synchronization); + + if (which == VideoCommon::CacheType::All || which == VideoCommon::CacheType::Unified) { + InvalidateMemoryRegion(addr, size); + } +} + +void OptimizedRasterizer::OnCacheInvalidation(PAddr addr, u64 size) { + MICROPROFILE_SCOPE(GPU_Synchronization); + + InvalidateCachedRegion(addr, size); +} + +bool OptimizedRasterizer::OnCPUWrite(PAddr addr, u64 size) { + return HandleCPUWrite(addr, size); +} + +void OptimizedRasterizer::InvalidateGPUCache() { + MICROPROFILE_SCOPE(GPU_Synchronization); + + InvalidateAllCache(); +} + +void OptimizedRasterizer::UnmapMemory(DAddr addr, u64 size) { + MICROPROFILE_SCOPE(GPU_Synchronization); + + UnmapGPUMemoryRegion(addr, size); +} + +void OptimizedRasterizer::ModifyGPUMemory(size_t as_id, GPUVAddr addr, u64 size) { + MICROPROFILE_SCOPE(GPU_Synchronization); + + UpdateMappedGPUMemory(as_id, addr, size); +} + +void OptimizedRasterizer::FlushAndInvalidateRegion(DAddr addr, u64 size, VideoCommon::CacheType which) { + MICROPROFILE_SCOPE(GPU_Synchronization); + + if (which == VideoCommon::CacheType::All || which == VideoCommon::CacheType::Unified) { + FlushAndInvalidateMemoryRegion(addr, size); + } +} + +void OptimizedRasterizer::WaitForIdle() { + MICROPROFILE_SCOPE(GPU_Synchronization); + + WaitForGPUIdle(); +} + +void OptimizedRasterizer::FragmentBarrier() { + MICROPROFILE_SCOPE(GPU_Synchronization); + + InsertFragmentBarrier(); +} + +void OptimizedRasterizer::TiledCacheBarrier() { + MICROPROFILE_SCOPE(GPU_Synchronization); + + InsertTiledCacheBarrier(); +} + +void OptimizedRasterizer::FlushCommands() { + MICROPROFILE_SCOPE(GPU_Synchronization); + + SubmitCommands(); +} + +void OptimizedRasterizer::TickFrame() { + MICROPROFILE_SCOPE(GPU_Synchronization); + + EndFrame(); +} + +void OptimizedRasterizer::PrepareRendertarget() { + const auto& regs{gpu.Maxwell3D().regs}; + const auto& framebuffer{regs.framebuffer}; + + render_targets.resize(framebuffer.num_color_buffers); + for (std::size_t index = 0; index < framebuffer.num_color_buffers; ++index) { + render_targets[index] = GetColorBuffer(index); + } + + depth_stencil = GetDepthBuffer(); +} + +void OptimizedRasterizer::UpdateDynamicState() { + const auto& regs{gpu.Maxwell3D().regs}; + + UpdateViewport(regs.viewport_transform); + UpdateScissor(regs.scissor_test); + UpdateDepthBias(regs.polygon_offset_units, regs.polygon_offset_clamp, regs.polygon_offset_factor); + UpdateBlendConstants(regs.blend_color); + UpdateStencilFaceMask(regs.stencil_front_func_mask, regs.stencil_back_func_mask); +} + +void OptimizedRasterizer::DrawIndexed(u32 instance_count) { + const auto& draw_state{gpu.Maxwell3D().draw_manager->GetDrawState()}; + const auto& index_buffer{memory_manager.ReadBlockUnsafe(draw_state.index_buffer.Address(), + draw_state.index_buffer.size)}; + + shader_cache.BindComputeShader(); + shader_cache.BindGraphicsShader(); + + DrawElementsInstanced(draw_state.topology, draw_state.index_buffer.count, + draw_state.index_buffer.format, index_buffer.data(), instance_count); +} + +void OptimizedRasterizer::DrawArrays(u32 instance_count) { + const auto& draw_state{gpu.Maxwell3D().draw_manager->GetDrawState()}; + + shader_cache.BindComputeShader(); + shader_cache.BindGraphicsShader(); + + DrawArraysInstanced(draw_state.topology, draw_state.vertex_buffer.first, + draw_state.vertex_buffer.count, instance_count); +} + +void OptimizedRasterizer::ClearFramebuffer(u32 layer_count) { + const auto& regs{gpu.Maxwell3D().regs}; + const auto& clear_state{regs.clear_buffers}; + + if (clear_state.R || clear_state.G || clear_state.B || clear_state.A) { + ClearColorBuffers(clear_state.R, clear_state.G, clear_state.B, clear_state.A, + regs.clear_color[0], regs.clear_color[1], regs.clear_color[2], + regs.clear_color[3], layer_count); + } + + if (clear_state.Z || clear_state.S) { + ClearDepthStencilBuffer(clear_state.Z, clear_state.S, regs.clear_depth, regs.clear_stencil, + layer_count); + } +} + +void OptimizedRasterizer::PrepareCompute() { + shader_cache.BindComputeShader(); +} + +void OptimizedRasterizer::LaunchComputeShader() { + const auto& launch_desc{gpu.KeplerCompute().launch_description}; + DispatchCompute(launch_desc.grid_dim_x, launch_desc.grid_dim_y, launch_desc.grid_dim_z); +} + +} // namespace VideoCore \ No newline at end of file diff --git a/suyu/src/video_core/optimized_rasterizer.h b/suyu/src/video_core/optimized_rasterizer.h new file mode 100644 index 0000000000..9c9fe1f35e --- /dev/null +++ b/suyu/src/video_core/optimized_rasterizer.h @@ -0,0 +1,73 @@ +#pragma once + +#include +#include +#include "common/common_types.h" +#include "video_core/rasterizer_interface.h" +#include "video_core/engines/maxwell_3d.h" + +namespace Core { +class System; +} + +namespace Tegra { +class GPU; +class MemoryManager; +} + +namespace VideoCore { + +class ShaderCache; +class QueryCache; + +class OptimizedRasterizer final : public RasterizerInterface { +public: + explicit OptimizedRasterizer(Core::System& system, Tegra::GPU& gpu); + ~OptimizedRasterizer() override; + + void Draw(bool is_indexed, u32 instance_count) override; + void Clear(u32 layer_count) override; + void DispatchCompute() override; + void ResetCounter(VideoCommon::QueryType type) override; + void Query(GPUVAddr gpu_addr, VideoCommon::QueryType type, + VideoCommon::QueryPropertiesFlags flags, u32 payload, u32 subreport) override; + void FlushAll() override; + void FlushRegion(DAddr addr, u64 size, VideoCommon::CacheType which) override; + bool MustFlushRegion(DAddr addr, u64 size, VideoCommon::CacheType which) override; + RasterizerDownloadArea GetFlushArea(DAddr addr, u64 size) override; + void InvalidateRegion(DAddr addr, u64 size, VideoCommon::CacheType which) override; + void OnCacheInvalidation(PAddr addr, u64 size) override; + bool OnCPUWrite(PAddr addr, u64 size) override; + void InvalidateGPUCache() override; + void UnmapMemory(DAddr addr, u64 size) override; + void ModifyGPUMemory(size_t as_id, GPUVAddr addr, u64 size) override; + void FlushAndInvalidateRegion(DAddr addr, u64 size, VideoCommon::CacheType which) override; + void WaitForIdle() override; + void FragmentBarrier() override; + void TiledCacheBarrier() override; + void FlushCommands() override; + void TickFrame() override; + +private: + void PrepareRendertarget(); + void UpdateDynamicState(); + void DrawIndexed(u32 instance_count); + void DrawArrays(u32 instance_count); + void ClearFramebuffer(u32 layer_count); + void PrepareCompute(); + void LaunchComputeShader(); + + Core::System& system; + Tegra::GPU& gpu; + Tegra::MemoryManager& memory_manager; + + std::unique_ptr shader_cache; + std::unique_ptr query_cache; + + std::vector render_targets; + DepthStencilConfig depth_stencil; + + // Add any additional member variables needed for the optimized rasterizer +}; + +} // namespace VideoCore \ No newline at end of file diff --git a/suyu/src/video_core/shader_cache.cpp b/suyu/src/video_core/shader_cache.cpp index a281f5d541..c32bd88b22 100644 --- a/suyu/src/video_core/shader_cache.cpp +++ b/suyu/src/video_core/shader_cache.cpp @@ -3,9 +3,18 @@ #include #include +#include +#include +#include +#include +#include #include #include "common/assert.h" +#include "common/fs/file.h" +#include "common/fs/path_util.h" +#include "common/logging/log.h" +#include "common/thread_worker.h" #include "shader_recompiler/frontend/maxwell/control_flow.h" #include "shader_recompiler/object_pool.h" #include "video_core/control/channel_state.h" @@ -19,233 +28,288 @@ namespace VideoCommon { +constexpr size_t MAX_SHADER_CACHE_SIZE = 1024 * 1024 * 1024; // 1GB + +class ShaderCacheWorker : public Common::ThreadWorker { +public: + explicit ShaderCacheWorker(const std::string& name) : ThreadWorker(name) {} + ~ShaderCacheWorker() = default; + + void CompileShader(ShaderInfo* shader) { + Push([shader]() { + // Compile shader here + // This is a placeholder for the actual compilation process + std::this_thread::sleep_for(std::chrono::milliseconds(10)); + shader->is_compiled.store(true, std::memory_order_release); + }); + } +}; + +class ShaderCache::Impl { +public: + explicit Impl(Tegra::MaxwellDeviceMemoryManager& device_memory_) + : device_memory{device_memory_}, workers{CreateWorkers()} { + LoadCache(); + } + + ~Impl() { + SaveCache(); + } + + void InvalidateRegion(VAddr addr, size_t size) { + std::scoped_lock lock{invalidation_mutex}; + InvalidatePagesInRegion(addr, size); + RemovePendingShaders(); + } + + void OnCacheInvalidation(VAddr addr, size_t size) { + std::scoped_lock lock{invalidation_mutex}; + InvalidatePagesInRegion(addr, size); + } + + void SyncGuestHost() { + std::scoped_lock lock{invalidation_mutex}; + RemovePendingShaders(); + } + + bool RefreshStages(std::array& unique_hashes); + const ShaderInfo* ComputeShader(); + void GetGraphicsEnvironments(GraphicsEnvironments& result, const std::array& unique_hashes); + + ShaderInfo* TryGet(VAddr addr) const { + std::scoped_lock lock{lookup_mutex}; + + const auto it = lookup_cache.find(addr); + if (it == lookup_cache.end()) { + return nullptr; + } + return it->second->data; + } + + void Register(std::unique_ptr data, VAddr addr, size_t size) { + std::scoped_lock lock{invalidation_mutex, lookup_mutex}; + + const VAddr addr_end = addr + size; + Entry* const entry = NewEntry(addr, addr_end, data.get()); + + const u64 page_end = (addr_end + SUYU_PAGESIZE - 1) >> SUYU_PAGEBITS; + for (u64 page = addr >> SUYU_PAGEBITS; page < page_end; ++page) { + invalidation_cache[page].push_back(entry); + } + + storage.push_back(std::move(data)); + + device_memory.UpdatePagesCachedCount(addr, size, 1); + } + +private: + std::vector> CreateWorkers() { + const size_t num_workers = std::thread::hardware_concurrency(); + std::vector> workers; + workers.reserve(num_workers); + for (size_t i = 0; i < num_workers; ++i) { + workers.emplace_back(std::make_unique(fmt::format("ShaderWorker{}", i))); + } + return workers; + } + + void LoadCache() { + const auto cache_dir = Common::FS::GetSuyuPath(Common::FS::SuyuPath::ShaderDir); + std::filesystem::create_directories(cache_dir); + + const auto cache_file = cache_dir / "shader_cache.bin"; + if (!std::filesystem::exists(cache_file)) { + return; + } + + std::ifstream file(cache_file, std::ios::binary); + if (!file) { + LOG_ERROR(Render_Vulkan, "Failed to open shader cache file for reading"); + return; + } + + size_t num_entries; + file.read(reinterpret_cast(&num_entries), sizeof(num_entries)); + + for (size_t i = 0; i < num_entries; ++i) { + VAddr addr; + size_t size; + file.read(reinterpret_cast(&addr), sizeof(addr)); + file.read(reinterpret_cast(&size), sizeof(size)); + + auto info = std::make_unique(); + file.read(reinterpret_cast(info.get()), sizeof(ShaderInfo)); + + Register(std::move(info), addr, size); + } + } + + void SaveCache() { + const auto cache_dir = Common::FS::GetSuyuPath(Common::FS::SuyuPath::ShaderDir); + std::filesystem::create_directories(cache_dir); + + const auto cache_file = cache_dir / "shader_cache.bin"; + std::ofstream file(cache_file, std::ios::binary | std::ios::trunc); + if (!file) { + LOG_ERROR(Render_Vulkan, "Failed to open shader cache file for writing"); + return; + } + + const size_t num_entries = storage.size(); + file.write(reinterpret_cast(&num_entries), sizeof(num_entries)); + + for (const auto& shader : storage) { + const VAddr addr = shader->addr; + const size_t size = shader->size_bytes; + file.write(reinterpret_cast(&addr), sizeof(addr)); + file.write(reinterpret_cast(&size), sizeof(size)); + file.write(reinterpret_cast(shader.get()), sizeof(ShaderInfo)); + } + } + + void InvalidatePagesInRegion(VAddr addr, size_t size) { + const VAddr addr_end = addr + size; + const u64 page_end = (addr_end + SUYU_PAGESIZE - 1) >> SUYU_PAGEBITS; + for (u64 page = addr >> SUYU_PAGEBITS; page < page_end; ++page) { + auto it = invalidation_cache.find(page); + if (it == invalidation_cache.end()) { + continue; + } + InvalidatePageEntries(it->second, addr, addr_end); + } + } + + void RemovePendingShaders() { + if (marked_for_removal.empty()) { + return; + } + // Remove duplicates + std::sort(marked_for_removal.begin(), marked_for_removal.end()); + marked_for_removal.erase(std::unique(marked_for_removal.begin(), marked_for_removal.end()), + marked_for_removal.end()); + + std::vector removed_shaders; + + std::scoped_lock lock{lookup_mutex}; + for (Entry* const entry : marked_for_removal) { + removed_shaders.push_back(entry->data); + + const auto it = lookup_cache.find(entry->addr_start); + ASSERT(it != lookup_cache.end()); + lookup_cache.erase(it); + } + marked_for_removal.clear(); + + if (!removed_shaders.empty()) { + RemoveShadersFromStorage(removed_shaders); + } + } + + void InvalidatePageEntries(std::vector& entries, VAddr addr, VAddr addr_end) { + size_t index = 0; + while (index < entries.size()) { + Entry* const entry = entries[index]; + if (!entry->Overlaps(addr, addr_end)) { + ++index; + continue; + } + + UnmarkMemory(entry); + RemoveEntryFromInvalidationCache(entry); + marked_for_removal.push_back(entry); + } + } + + void RemoveEntryFromInvalidationCache(const Entry* entry) { + const u64 page_end = (entry->addr_end + SUYU_PAGESIZE - 1) >> SUYU_PAGEBITS; + for (u64 page = entry->addr_start >> SUYU_PAGEBITS; page < page_end; ++page) { + const auto entries_it = invalidation_cache.find(page); + ASSERT(entries_it != invalidation_cache.end()); + std::vector& entries = entries_it->second; + + const auto entry_it = std::find(entries.begin(), entries.end(), entry); + ASSERT(entry_it != entries.end()); + entries.erase(entry_it); + } + } + + void UnmarkMemory(Entry* entry) { + if (!entry->is_memory_marked) { + return; + } + entry->is_memory_marked = false; + + const VAddr addr = entry->addr_start; + const size_t size = entry->addr_end - addr; + device_memory.UpdatePagesCachedCount(addr, size, -1); + } + + void RemoveShadersFromStorage(const std::vector& removed_shaders) { + storage.erase( + std::remove_if(storage.begin(), storage.end(), + [&removed_shaders](const std::unique_ptr& shader) { + return std::find(removed_shaders.begin(), removed_shaders.end(), + shader.get()) != removed_shaders.end(); + }), + storage.end()); + } + + Entry* NewEntry(VAddr addr, VAddr addr_end, ShaderInfo* data) { + auto entry = std::make_unique(Entry{addr, addr_end, data}); + Entry* const entry_pointer = entry.get(); + + lookup_cache.emplace(addr, std::move(entry)); + return entry_pointer; + } + + Tegra::MaxwellDeviceMemoryManager& device_memory; + std::vector> workers; + + mutable std::mutex lookup_mutex; + std::mutex invalidation_mutex; + + std::unordered_map> lookup_cache; + std::unordered_map> invalidation_cache; + std::vector> storage; + std::vector marked_for_removal; +}; + +ShaderCache::ShaderCache(Tegra::MaxwellDeviceMemoryManager& device_memory_) + : impl{std::make_unique(device_memory_)} {} + +ShaderCache::~ShaderCache() = default; + void ShaderCache::InvalidateRegion(VAddr addr, size_t size) { - std::scoped_lock lock{invalidation_mutex}; - InvalidatePagesInRegion(addr, size); - RemovePendingShaders(); + impl->InvalidateRegion(addr, size); } void ShaderCache::OnCacheInvalidation(VAddr addr, size_t size) { - std::scoped_lock lock{invalidation_mutex}; - InvalidatePagesInRegion(addr, size); + impl->OnCacheInvalidation(addr, size); } void ShaderCache::SyncGuestHost() { - std::scoped_lock lock{invalidation_mutex}; - RemovePendingShaders(); + impl->SyncGuestHost(); } -ShaderCache::ShaderCache(Tegra::MaxwellDeviceMemoryManager& device_memory_) - : device_memory{device_memory_} {} - bool ShaderCache::RefreshStages(std::array& unique_hashes) { - auto& dirty{maxwell3d->dirty.flags}; - if (!dirty[VideoCommon::Dirty::Shaders]) { - return last_shaders_valid; - } - dirty[VideoCommon::Dirty::Shaders] = false; - - const GPUVAddr base_addr{maxwell3d->regs.program_region.Address()}; - for (size_t index = 0; index < Tegra::Engines::Maxwell3D::Regs::MaxShaderProgram; ++index) { - if (!maxwell3d->regs.IsShaderConfigEnabled(index)) { - unique_hashes[index] = 0; - continue; - } - const auto& shader_config{maxwell3d->regs.pipelines[index]}; - const auto program{static_cast(index)}; - if (program == Tegra::Engines::Maxwell3D::Regs::ShaderType::Pixel && - !maxwell3d->regs.rasterize_enable) { - unique_hashes[index] = 0; - continue; - } - const GPUVAddr shader_addr{base_addr + shader_config.offset}; - const std::optional cpu_shader_addr{gpu_memory->GpuToCpuAddress(shader_addr)}; - if (!cpu_shader_addr) { - LOG_ERROR(HW_GPU, "Invalid GPU address for shader 0x{:016x}", shader_addr); - last_shaders_valid = false; - return false; - } - const ShaderInfo* shader_info{TryGet(*cpu_shader_addr)}; - if (!shader_info) { - const u32 start_address{shader_config.offset}; - GraphicsEnvironment env{*maxwell3d, *gpu_memory, program, base_addr, start_address}; - shader_info = MakeShaderInfo(env, *cpu_shader_addr); - } - shader_infos[index] = shader_info; - unique_hashes[index] = shader_info->unique_hash; - } - last_shaders_valid = true; - return true; + return impl->RefreshStages(unique_hashes); } const ShaderInfo* ShaderCache::ComputeShader() { - const GPUVAddr program_base{kepler_compute->regs.code_loc.Address()}; - const auto& qmd{kepler_compute->launch_description}; - const GPUVAddr shader_addr{program_base + qmd.program_start}; - const std::optional cpu_shader_addr{gpu_memory->GpuToCpuAddress(shader_addr)}; - if (!cpu_shader_addr) { - LOG_ERROR(HW_GPU, "Invalid GPU address for shader 0x{:016x}", shader_addr); - return nullptr; - } - if (const ShaderInfo* const shader = TryGet(*cpu_shader_addr)) { - return shader; - } - ComputeEnvironment env{*kepler_compute, *gpu_memory, program_base, qmd.program_start}; - return MakeShaderInfo(env, *cpu_shader_addr); + return impl->ComputeShader(); } void ShaderCache::GetGraphicsEnvironments(GraphicsEnvironments& result, const std::array& unique_hashes) { - size_t env_index{}; - const GPUVAddr base_addr{maxwell3d->regs.program_region.Address()}; - for (size_t index = 0; index < NUM_PROGRAMS; ++index) { - if (unique_hashes[index] == 0) { - continue; - } - const auto program{static_cast(index)}; - auto& env{result.envs[index]}; - const u32 start_address{maxwell3d->regs.pipelines[index].offset}; - env = GraphicsEnvironment{*maxwell3d, *gpu_memory, program, base_addr, start_address}; - env.SetCachedSize(shader_infos[index]->size_bytes); - result.env_ptrs[env_index++] = &env; - } + impl->GetGraphicsEnvironments(result, unique_hashes); } ShaderInfo* ShaderCache::TryGet(VAddr addr) const { - std::scoped_lock lock{lookup_mutex}; - - const auto it = lookup_cache.find(addr); - if (it == lookup_cache.end()) { - return nullptr; - } - return it->second->data; + return impl->TryGet(addr); } void ShaderCache::Register(std::unique_ptr data, VAddr addr, size_t size) { - std::scoped_lock lock{invalidation_mutex, lookup_mutex}; - - const VAddr addr_end = addr + size; - Entry* const entry = NewEntry(addr, addr_end, data.get()); - - const u64 page_end = (addr_end + SUYU_PAGESIZE - 1) >> SUYU_PAGEBITS; - for (u64 page = addr >> SUYU_PAGEBITS; page < page_end; ++page) { - invalidation_cache[page].push_back(entry); - } - - storage.push_back(std::move(data)); - - device_memory.UpdatePagesCachedCount(addr, size, 1); -} - -void ShaderCache::InvalidatePagesInRegion(VAddr addr, size_t size) { - const VAddr addr_end = addr + size; - const u64 page_end = (addr_end + SUYU_PAGESIZE - 1) >> SUYU_PAGEBITS; - for (u64 page = addr >> SUYU_PAGEBITS; page < page_end; ++page) { - auto it = invalidation_cache.find(page); - if (it == invalidation_cache.end()) { - continue; - } - InvalidatePageEntries(it->second, addr, addr_end); - } -} - -void ShaderCache::RemovePendingShaders() { - if (marked_for_removal.empty()) { - return; - } - // Remove duplicates - std::ranges::sort(marked_for_removal); - marked_for_removal.erase(std::unique(marked_for_removal.begin(), marked_for_removal.end()), - marked_for_removal.end()); - - boost::container::small_vector removed_shaders; - - std::scoped_lock lock{lookup_mutex}; - for (Entry* const entry : marked_for_removal) { - removed_shaders.push_back(entry->data); - - const auto it = lookup_cache.find(entry->addr_start); - ASSERT(it != lookup_cache.end()); - lookup_cache.erase(it); - } - marked_for_removal.clear(); - - if (!removed_shaders.empty()) { - RemoveShadersFromStorage(removed_shaders); - } -} - -void ShaderCache::InvalidatePageEntries(std::vector& entries, VAddr addr, VAddr addr_end) { - size_t index = 0; - while (index < entries.size()) { - Entry* const entry = entries[index]; - if (!entry->Overlaps(addr, addr_end)) { - ++index; - continue; - } - - UnmarkMemory(entry); - RemoveEntryFromInvalidationCache(entry); - marked_for_removal.push_back(entry); - } -} - -void ShaderCache::RemoveEntryFromInvalidationCache(const Entry* entry) { - const u64 page_end = (entry->addr_end + SUYU_PAGESIZE - 1) >> SUYU_PAGEBITS; - for (u64 page = entry->addr_start >> SUYU_PAGEBITS; page < page_end; ++page) { - const auto entries_it = invalidation_cache.find(page); - ASSERT(entries_it != invalidation_cache.end()); - std::vector& entries = entries_it->second; - - const auto entry_it = std::ranges::find(entries, entry); - ASSERT(entry_it != entries.end()); - entries.erase(entry_it); - } -} - -void ShaderCache::UnmarkMemory(Entry* entry) { - if (!entry->is_memory_marked) { - return; - } - entry->is_memory_marked = false; - - const VAddr addr = entry->addr_start; - const size_t size = entry->addr_end - addr; - device_memory.UpdatePagesCachedCount(addr, size, -1); -} - -void ShaderCache::RemoveShadersFromStorage(std::span removed_shaders) { - // Remove them from the cache - std::erase_if(storage, [&removed_shaders](const std::unique_ptr& shader) { - return std::ranges::find(removed_shaders, shader.get()) != removed_shaders.end(); - }); -} - -ShaderCache::Entry* ShaderCache::NewEntry(VAddr addr, VAddr addr_end, ShaderInfo* data) { - auto entry = std::make_unique(Entry{addr, addr_end, data}); - Entry* const entry_pointer = entry.get(); - - lookup_cache.emplace(addr, std::move(entry)); - return entry_pointer; -} - -const ShaderInfo* ShaderCache::MakeShaderInfo(GenericEnvironment& env, VAddr cpu_addr) { - auto info = std::make_unique(); - if (const std::optional cached_hash{env.Analyze()}) { - info->unique_hash = *cached_hash; - info->size_bytes = env.CachedSizeBytes(); - } else { - // Slow path, not really hit on commercial games - // Build a control flow graph to get the real shader size - Shader::ObjectPool flow_block; - Shader::Maxwell::Flow::CFG cfg{env, flow_block, env.StartAddress()}; - info->unique_hash = env.CalculateHash(); - info->size_bytes = env.ReadSizeBytes(); - } - const size_t size_bytes{info->size_bytes}; - const ShaderInfo* const result{info.get()}; - Register(std::move(info), cpu_addr, size_bytes); - return result; + impl->Register(std::move(data), addr, size); } } // namespace VideoCommon diff --git a/v2rayn/v2rayN/v2rayN/App.xaml b/v2rayn/v2rayN/v2rayN/App.xaml index e8c8bfb146..844c6af97e 100644 --- a/v2rayn/v2rayN/v2rayN/App.xaml +++ b/v2rayn/v2rayN/v2rayN/App.xaml @@ -186,7 +186,7 @@ x:Key="WindowGlobal" BasedOn="{StaticResource {x:Type Window}}" TargetType="{x:Type Window}"> - + @@ -194,7 +194,7 @@ x:Key="ViewGlobal" BasedOn="{StaticResource {x:Type UserControl}}" TargetType="{x:Type UserControl}"> - + diff --git a/v2rayng/V2rayNG/app/build.gradle.kts b/v2rayng/V2rayNG/app/build.gradle.kts index e039de7b64..c3fd2db820 100644 --- a/v2rayng/V2rayNG/app/build.gradle.kts +++ b/v2rayng/V2rayNG/app/build.gradle.kts @@ -11,8 +11,8 @@ android { applicationId = "com.v2ray.ang" minSdk = 21 targetSdk = 34 - versionCode = 597 - versionName = "1.9.4" + versionCode = 598 + versionName = "1.9.5" multiDexEnabled = true splits { abi { diff --git a/v2rayng/V2rayNG/app/src/main/kotlin/com/v2ray/ang/dto/ConfigResult.kt b/v2rayng/V2rayNG/app/src/main/kotlin/com/v2ray/ang/dto/ConfigResult.kt new file mode 100644 index 0000000000..1c3d97fff1 --- /dev/null +++ b/v2rayng/V2rayNG/app/src/main/kotlin/com/v2ray/ang/dto/ConfigResult.kt @@ -0,0 +1,9 @@ +package com.v2ray.ang.dto + +data class ConfigResult ( + var status: Boolean, + var guid: String? = null, + var content: String = "", + var domainPort: String? = null, +) + diff --git a/v2rayng/V2rayNG/app/src/main/kotlin/com/v2ray/ang/dto/Hysteria2Bean.kt b/v2rayng/V2rayNG/app/src/main/kotlin/com/v2ray/ang/dto/Hysteria2Bean.kt index c04f71b273..c671541d16 100644 --- a/v2rayng/V2rayNG/app/src/main/kotlin/com/v2ray/ang/dto/Hysteria2Bean.kt +++ b/v2rayng/V2rayNG/app/src/main/kotlin/com/v2ray/ang/dto/Hysteria2Bean.kt @@ -6,6 +6,7 @@ data class Hysteria2Bean( val lazy: Boolean? = true, val obfs: ObfsBean? = null, val socks5: Socks5Bean? = null, + val http: Socks5Bean? = null, val tls: TlsBean? = null, ) { data class ObfsBean( diff --git a/v2rayng/V2rayNG/app/src/main/kotlin/com/v2ray/ang/extension/_Ext.kt b/v2rayng/V2rayNG/app/src/main/kotlin/com/v2ray/ang/extension/_Ext.kt index 8f839409d0..ab78ed8d5d 100644 --- a/v2rayng/V2rayNG/app/src/main/kotlin/com/v2ray/ang/extension/_Ext.kt +++ b/v2rayng/V2rayNG/app/src/main/kotlin/com/v2ray/ang/extension/_Ext.kt @@ -5,10 +5,12 @@ import android.content.Context import android.content.Intent import android.content.IntentFilter import android.os.Build +import android.os.Bundle import android.widget.Toast import com.v2ray.ang.AngApplication import me.drakeet.support.toast.ToastCompat import org.json.JSONObject +import java.io.Serializable import java.net.URI import java.net.URLConnection @@ -81,4 +83,14 @@ fun Context.listenForPackageChanges(onetime: Boolean = true, callback: () -> Uni addDataScheme("package") }) } - } \ No newline at end of file + } + +inline fun Bundle.serializable(key: String): T? = when { + Build.VERSION.SDK_INT >= Build.VERSION_CODES.TIRAMISU -> getSerializable(key, T::class.java) + else -> @Suppress("DEPRECATION") getSerializable(key) as? T +} + +inline fun Intent.serializable(key: String): T? = when { + Build.VERSION.SDK_INT >= Build.VERSION_CODES.TIRAMISU -> getSerializableExtra(key, T::class.java) + else -> @Suppress("DEPRECATION") getSerializableExtra(key) as? T +} \ No newline at end of file diff --git a/v2rayng/V2rayNG/app/src/main/kotlin/com/v2ray/ang/service/SubscriptionUpdater.kt b/v2rayng/V2rayNG/app/src/main/kotlin/com/v2ray/ang/service/SubscriptionUpdater.kt index 449b8835ca..587fb5ef5b 100644 --- a/v2rayng/V2rayNG/app/src/main/kotlin/com/v2ray/ang/service/SubscriptionUpdater.kt +++ b/v2rayng/V2rayNG/app/src/main/kotlin/com/v2ray/ang/service/SubscriptionUpdater.kt @@ -15,6 +15,7 @@ import com.v2ray.ang.AppConfig.SUBSCRIPTION_UPDATE_CHANNEL import com.v2ray.ang.AppConfig.SUBSCRIPTION_UPDATE_CHANNEL_NAME import com.v2ray.ang.R import com.v2ray.ang.util.AngConfigManager +import com.v2ray.ang.util.AngConfigManager.updateConfigViaSub import com.v2ray.ang.util.MmkvManager import com.v2ray.ang.util.Utils @@ -40,8 +41,8 @@ object SubscriptionUpdater { val subs = MmkvManager.decodeSubscriptions().filter { it.second.autoUpdate } - for (i in subs) { - val subscription = i.second + for (sub in subs) { + val subItem = sub.second if (Build.VERSION.SDK_INT >= Build.VERSION_CODES.O) { notification.setChannelId(SUBSCRIPTION_UPDATE_CHANNEL) @@ -56,11 +57,10 @@ object SubscriptionUpdater { notificationManager.notify(3, notification.build()) Log.d( AppConfig.ANG_PACKAGE, - "subscription automatic update: ---${subscription.remarks}" + "subscription automatic update: ---${subItem.remarks}" ) - val configs = Utils.getUrlContentWithCustomUserAgent(subscription.url) - AngConfigManager.importBatchConfig(configs, i.first, false) - notification.setContentText("Updating ${subscription.remarks}") + updateConfigViaSub(Pair(sub.first, subItem)) + notification.setContentText("Updating ${subItem.remarks}") } notificationManager.cancel(3) return Result.success() diff --git a/v2rayng/V2rayNG/app/src/main/kotlin/com/v2ray/ang/service/V2RayServiceManager.kt b/v2rayng/V2rayNG/app/src/main/kotlin/com/v2ray/ang/service/V2RayServiceManager.kt index fea3dd496c..3c3b211628 100644 --- a/v2rayng/V2rayNG/app/src/main/kotlin/com/v2ray/ang/service/V2RayServiceManager.kt +++ b/v2rayng/V2rayNG/app/src/main/kotlin/com/v2ray/ang/service/V2RayServiceManager.kt @@ -164,7 +164,7 @@ object V2RayServiceManager { MessageUtil.sendMsg2UI(service, AppConfig.MSG_STATE_START_SUCCESS, "") showNotification() - PluginUtil.runPlugin(service, config) + PluginUtil.runPlugin(service, config, result.domainPort) } else { MessageUtil.sendMsg2UI(service, AppConfig.MSG_STATE_START_FAILURE, "") cancelNotification() diff --git a/v2rayng/V2rayNG/app/src/main/kotlin/com/v2ray/ang/service/V2RayTestService.kt b/v2rayng/V2rayNG/app/src/main/kotlin/com/v2ray/ang/service/V2RayTestService.kt index 6d6dc0aa9d..b90efdfd27 100644 --- a/v2rayng/V2rayNG/app/src/main/kotlin/com/v2ray/ang/service/V2RayTestService.kt +++ b/v2rayng/V2rayNG/app/src/main/kotlin/com/v2ray/ang/service/V2RayTestService.kt @@ -3,12 +3,18 @@ package com.v2ray.ang.service import android.app.Service import android.content.Intent import android.os.IBinder +import android.util.Log import com.v2ray.ang.AppConfig.MSG_MEASURE_CONFIG import com.v2ray.ang.AppConfig.MSG_MEASURE_CONFIG_CANCEL import com.v2ray.ang.AppConfig.MSG_MEASURE_CONFIG_SUCCESS +import com.v2ray.ang.dto.EConfigType +import com.v2ray.ang.extension.serializable import com.v2ray.ang.util.MessageUtil +import com.v2ray.ang.util.MmkvManager +import com.v2ray.ang.util.PluginUtil import com.v2ray.ang.util.SpeedtestUtil import com.v2ray.ang.util.Utils +import com.v2ray.ang.util.V2rayConfigUtil import go.Seq import kotlinx.coroutines.CoroutineScope import kotlinx.coroutines.Job @@ -30,10 +36,10 @@ class V2RayTestService : Service() { override fun onStartCommand(intent: Intent?, flags: Int, startId: Int): Int { when (intent?.getIntExtra("key", 0)) { MSG_MEASURE_CONFIG -> { - val contentPair = intent.getSerializableExtra("content") as Pair + val guid = intent.serializable("content") ?: "" realTestScope.launch { - val result = SpeedtestUtil.realPing(contentPair.second) - MessageUtil.sendMsg2UI(this@V2RayTestService, MSG_MEASURE_CONFIG_SUCCESS, Pair(contentPair.first, result)) + val result = startRealPing(guid) + MessageUtil.sendMsg2UI(this@V2RayTestService, MSG_MEASURE_CONFIG_SUCCESS, Pair(guid, result)) } } @@ -47,4 +53,29 @@ class V2RayTestService : Service() { override fun onBind(intent: Intent?): IBinder? { return null } + + private fun startRealPing(guid: String): Long { + val retFailure = -1L + + val server = MmkvManager.decodeServerConfig(guid) ?: return retFailure + if (server.getProxyOutbound()?.protocol?.equals(EConfigType.HYSTERIA2.name, true) == true) { + val socksPort = Utils.findFreePort(listOf(0)) + PluginUtil.runPlugin(this, server, "0:${socksPort}") + Thread.sleep(1000L) + + var delay = SpeedtestUtil.testConnection(this, socksPort) + if (delay.first < 0) { + Thread.sleep(10L) + delay = SpeedtestUtil.testConnection(this, socksPort) + } + PluginUtil.stopPlugin() + return delay.first + } else { + val config = V2rayConfigUtil.getV2rayConfig(this, guid) + if (!config.status) { + return retFailure + } + return SpeedtestUtil.realPing(config.content) + } + } } diff --git a/v2rayng/V2rayNG/app/src/main/kotlin/com/v2ray/ang/service/V2RayVpnService.kt b/v2rayng/V2rayNG/app/src/main/kotlin/com/v2ray/ang/service/V2RayVpnService.kt index c42e33fb06..fc33653d25 100644 --- a/v2rayng/V2rayNG/app/src/main/kotlin/com/v2ray/ang/service/V2RayVpnService.kt +++ b/v2rayng/V2rayNG/app/src/main/kotlin/com/v2ray/ang/service/V2RayVpnService.kt @@ -203,7 +203,7 @@ class V2RayVpnService : VpnService(), ServiceControl { } private fun runTun2socks() { - val socksPort = Utils.parseInt(settingsStorage?.decodeString(AppConfig.PREF_SOCKS_PORT), AppConfig.PORT_SOCKS.toInt()) + val socksPort = SettingsManager.getSocksPort() val cmd = arrayListOf( File(applicationContext.applicationInfo.nativeLibraryDir, TUN2SOCKS).absolutePath, "--netif-ipaddr", PRIVATE_VLAN4_ROUTER, diff --git a/v2rayng/V2rayNG/app/src/main/kotlin/com/v2ray/ang/ui/RoutingSettingActivity.kt b/v2rayng/V2rayNG/app/src/main/kotlin/com/v2ray/ang/ui/RoutingSettingActivity.kt index 0789934d01..f6c12a96ed 100644 --- a/v2rayng/V2rayNG/app/src/main/kotlin/com/v2ray/ang/ui/RoutingSettingActivity.kt +++ b/v2rayng/V2rayNG/app/src/main/kotlin/com/v2ray/ang/ui/RoutingSettingActivity.kt @@ -10,13 +10,14 @@ import androidx.appcompat.app.AlertDialog import androidx.lifecycle.lifecycleScope import androidx.recyclerview.widget.ItemTouchHelper import androidx.recyclerview.widget.LinearLayoutManager -import com.google.gson.Gson + import com.v2ray.ang.AppConfig import com.v2ray.ang.R import com.v2ray.ang.databinding.ActivityRoutingSettingBinding import com.v2ray.ang.dto.RulesetItem import com.v2ray.ang.extension.toast import com.v2ray.ang.helper.SimpleItemTouchHelperCallback +import com.v2ray.ang.util.JsonUtil import com.v2ray.ang.util.MmkvManager import com.v2ray.ang.util.MmkvManager.settingsStorage import com.v2ray.ang.util.SettingsManager @@ -141,7 +142,7 @@ class RoutingSettingActivity : BaseActivity() { if (rulesetList.isNullOrEmpty()) { toast(R.string.toast_failure) } else { - Utils.setClipboard(this, Gson().toJson(rulesetList)) + Utils.setClipboard(this, JsonUtil.toJson(rulesetList)) toast(R.string.toast_success) } true diff --git a/v2rayng/V2rayNG/app/src/main/kotlin/com/v2ray/ang/ui/ServerCustomConfigActivity.kt b/v2rayng/V2rayNG/app/src/main/kotlin/com/v2ray/ang/ui/ServerCustomConfigActivity.kt index 4dba53437c..d6891270a8 100644 --- a/v2rayng/V2rayNG/app/src/main/kotlin/com/v2ray/ang/ui/ServerCustomConfigActivity.kt +++ b/v2rayng/V2rayNG/app/src/main/kotlin/com/v2ray/ang/ui/ServerCustomConfigActivity.kt @@ -8,13 +8,14 @@ import android.widget.Toast import androidx.appcompat.app.AlertDialog import com.blacksquircle.ui.editorkit.utils.EditorTheme import com.blacksquircle.ui.language.json.JsonLanguage -import com.google.gson.Gson + import com.v2ray.ang.R import com.v2ray.ang.databinding.ActivityServerCustomConfigBinding import com.v2ray.ang.dto.EConfigType import com.v2ray.ang.dto.ServerConfig import com.v2ray.ang.dto.V2rayConfig import com.v2ray.ang.extension.toast +import com.v2ray.ang.util.JsonUtil import com.v2ray.ang.util.MmkvManager import com.v2ray.ang.util.Utils import me.drakeet.support.toast.ToastCompat @@ -78,7 +79,7 @@ class ServerCustomConfigActivity : BaseActivity() { } val v2rayConfig = try { - Gson().fromJson(binding.editor.text.toString(), V2rayConfig::class.java) + JsonUtil.fromJson(binding.editor.text.toString(), V2rayConfig::class.java) } catch (e: Exception) { e.printStackTrace() ToastCompat.makeText(this, "${getString(R.string.toast_malformed_josn)} ${e.cause?.message}", Toast.LENGTH_LONG).show() diff --git a/v2rayng/V2rayNG/app/src/main/kotlin/com/v2ray/ang/ui/UserAssetActivity.kt b/v2rayng/V2rayNG/app/src/main/kotlin/com/v2ray/ang/ui/UserAssetActivity.kt index 00983e2d19..82ab0d88c5 100644 --- a/v2rayng/V2rayNG/app/src/main/kotlin/com/v2ray/ang/ui/UserAssetActivity.kt +++ b/v2rayng/V2rayNG/app/src/main/kotlin/com/v2ray/ang/ui/UserAssetActivity.kt @@ -31,6 +31,7 @@ import com.v2ray.ang.extension.toTrafficString import com.v2ray.ang.extension.toast import com.v2ray.ang.util.MmkvManager import com.v2ray.ang.util.MmkvManager.settingsStorage +import com.v2ray.ang.util.SettingsManager import com.v2ray.ang.util.Utils import kotlinx.coroutines.Dispatchers import kotlinx.coroutines.launch @@ -176,7 +177,7 @@ class UserAssetActivity : BaseActivity() { .show() toast(R.string.msg_downloading_content) - val httpPort = Utils.parseInt(settingsStorage?.decodeString(AppConfig.PREF_HTTP_PORT), AppConfig.PORT_HTTP.toInt()) + val httpPort = SettingsManager.getHttpPort() var assets = MmkvManager.decodeAssetUrls() assets = addBuiltInGeoItems(assets) diff --git a/v2rayng/V2rayNG/app/src/main/kotlin/com/v2ray/ang/util/AngConfigManager.kt b/v2rayng/V2rayNG/app/src/main/kotlin/com/v2ray/ang/util/AngConfigManager.kt index 997ec8607b..b4e1b7c49b 100644 --- a/v2rayng/V2rayNG/app/src/main/kotlin/com/v2ray/ang/util/AngConfigManager.kt +++ b/v2rayng/V2rayNG/app/src/main/kotlin/com/v2ray/ang/util/AngConfigManager.kt @@ -4,7 +4,7 @@ import android.content.Context import android.graphics.Bitmap import android.text.TextUtils import android.util.Log -import com.google.gson.Gson + import com.google.gson.GsonBuilder import com.google.gson.JsonPrimitive import com.google.gson.JsonSerializationContext @@ -14,7 +14,6 @@ import com.v2ray.ang.AppConfig import com.v2ray.ang.AppConfig.HY2 import com.v2ray.ang.R import com.v2ray.ang.dto.* -import com.v2ray.ang.util.MmkvManager.settingsStorage import com.v2ray.ang.util.fmt.Hysteria2Fmt import com.v2ray.ang.util.fmt.ShadowsocksFmt import com.v2ray.ang.util.fmt.SocksFmt @@ -279,34 +278,21 @@ object AngConfigManager { && server.contains("routing") ) { try { - //val gson = GsonBuilder().setPrettyPrinting().create() - val gson = GsonBuilder() - .setPrettyPrinting() - .disableHtmlEscaping() - .registerTypeAdapter( // custom serialiser is needed here since JSON by default parse number as Double, core will fail to start - object : TypeToken() {}.type, - JsonSerializer { src: Double?, _: Type?, _: JsonSerializationContext? -> - JsonPrimitive( - src?.toInt() - ) - } - ) - .create() val serverList: Array = - Gson().fromJson(server, Array::class.java) + JsonUtil.fromJson(server, Array::class.java) if (serverList.isNotEmpty()) { var count = 0 for (srv in serverList.reversed()) { val config = ServerConfig.create(EConfigType.CUSTOM) config.fullConfig = - Gson().fromJson(Gson().toJson(srv), V2rayConfig::class.java) + JsonUtil.fromJson(JsonUtil.toJson(srv), V2rayConfig::class.java) config.remarks = config.fullConfig?.remarks ?: ("%04d-".format(count + 1) + System.currentTimeMillis() .toString()) config.subscriptionId = subid val key = MmkvManager.encodeServerConfig("", config) - MmkvManager.encodeServerRaw(key, gson.toJson(srv)) + MmkvManager.encodeServerRaw(key, JsonUtil.toJsonPretty(srv)) count += 1 } return count @@ -319,7 +305,7 @@ object AngConfigManager { // For compatibility val config = ServerConfig.create(EConfigType.CUSTOM) config.subscriptionId = subid - config.fullConfig = Gson().fromJson(server, V2rayConfig::class.java) + config.fullConfig = JsonUtil.fromJson(server, V2rayConfig::class.java) config.remarks = config.fullConfig?.remarks ?: System.currentTimeMillis().toString() val key = MmkvManager.encodeServerConfig("", config) MmkvManager.encodeServerRaw(key, server) @@ -374,19 +360,17 @@ object AngConfigManager { return 0 } Log.d(AppConfig.ANG_PACKAGE, url) + var configText = try { - Utils.getUrlContentWithCustomUserAgent(url) + val httpPort = SettingsManager.getHttpPort() + Utils.getUrlContentWithCustomUserAgent(url, 30000, httpPort) } catch (e: Exception) { e.printStackTrace() "" } if (configText.isEmpty()) { configText = try { - val httpPort = Utils.parseInt( - settingsStorage?.decodeString(AppConfig.PREF_HTTP_PORT), - AppConfig.PORT_HTTP.toInt() - ) - Utils.getUrlContentWithCustomUserAgent(url, 30000, httpPort) + Utils.getUrlContentWithCustomUserAgent(url) } catch (e: Exception) { e.printStackTrace() "" diff --git a/v2rayng/V2rayNG/app/src/main/kotlin/com/v2ray/ang/util/JsonUtil.kt b/v2rayng/V2rayNG/app/src/main/kotlin/com/v2ray/ang/util/JsonUtil.kt new file mode 100644 index 0000000000..0c1c950a83 --- /dev/null +++ b/v2rayng/V2rayNG/app/src/main/kotlin/com/v2ray/ang/util/JsonUtil.kt @@ -0,0 +1,37 @@ +package com.v2ray.ang.util + +import com.google.gson.Gson +import com.google.gson.GsonBuilder +import com.google.gson.JsonPrimitive +import com.google.gson.JsonSerializationContext +import com.google.gson.JsonSerializer +import com.google.gson.reflect.TypeToken +import java.lang.reflect.Type + +object JsonUtil { + private var gson = Gson() + + fun toJson(src: Any?): String { + return gson.toJson(src) + } + + fun fromJson(json: String, cls: Class): T { + return gson.fromJson(json, cls) + } + + fun toJsonPretty(src: Any?): String { + val gsonPre = GsonBuilder() + .setPrettyPrinting() + .disableHtmlEscaping() + .registerTypeAdapter( // custom serialiser is needed here since JSON by default parse number as Double, core will fail to start + object : TypeToken() {}.type, + JsonSerializer { src: Double?, _: Type?, _: JsonSerializationContext? -> + JsonPrimitive( + src?.toInt() + ) + } + ) + .create() + return gsonPre.toJson(src) + } +} \ No newline at end of file diff --git a/v2rayng/V2rayNG/app/src/main/kotlin/com/v2ray/ang/util/MmkvManager.kt b/v2rayng/V2rayNG/app/src/main/kotlin/com/v2ray/ang/util/MmkvManager.kt index 2a04f89bad..4787ffee35 100644 --- a/v2rayng/V2rayNG/app/src/main/kotlin/com/v2ray/ang/util/MmkvManager.kt +++ b/v2rayng/V2rayNG/app/src/main/kotlin/com/v2ray/ang/util/MmkvManager.kt @@ -1,6 +1,6 @@ package com.v2ray.ang.util -import com.google.gson.Gson + import com.tencent.mmkv.MMKV import com.v2ray.ang.AppConfig.PREF_IS_BOOTED import com.v2ray.ang.AppConfig.PREF_ROUTING_RULESET @@ -49,7 +49,7 @@ object MmkvManager { } fun encodeServerList(serverList: MutableList) { - mainStorage.encode(KEY_ANG_CONFIGS, Gson().toJson(serverList)) + mainStorage.encode(KEY_ANG_CONFIGS, JsonUtil.toJson(serverList)) } fun decodeServerList(): MutableList { @@ -57,7 +57,7 @@ object MmkvManager { return if (json.isNullOrBlank()) { mutableListOf() } else { - Gson().fromJson(json, Array::class.java).toMutableList() + JsonUtil.fromJson(json, Array::class.java).toMutableList() } } @@ -69,7 +69,7 @@ object MmkvManager { if (json.isNullOrBlank()) { return null } - return Gson().fromJson(json, ServerConfig::class.java) + return JsonUtil.fromJson(json, ServerConfig::class.java) } fun decodeProfileConfig(guid: String): ProfileItem? { @@ -80,12 +80,12 @@ object MmkvManager { if (json.isNullOrBlank()) { return null } - return Gson().fromJson(json, ProfileItem::class.java) + return JsonUtil.fromJson(json, ProfileItem::class.java) } fun encodeServerConfig(guid: String, config: ServerConfig): String { val key = guid.ifBlank { Utils.getUuid() } - serverStorage.encode(key, Gson().toJson(config)) + serverStorage.encode(key, JsonUtil.toJson(config)) val serverList = decodeServerList() if (!serverList.contains(key)) { serverList.add(0, key) @@ -101,7 +101,7 @@ object MmkvManager { server = config.getProxyOutbound()?.getServerAddress(), serverPort = config.getProxyOutbound()?.getServerPort(), ) - profileStorage.encode(key, Gson().toJson(profile)) + profileStorage.encode(key, JsonUtil.toJson(profile)) return key } @@ -141,7 +141,7 @@ object MmkvManager { if (json.isNullOrBlank()) { return null } - return Gson().fromJson(json, ServerAffiliationInfo::class.java) + return JsonUtil.fromJson(json, ServerAffiliationInfo::class.java) } fun encodeServerTestDelayMillis(guid: String, testResult: Long) { @@ -150,14 +150,14 @@ object MmkvManager { } val aff = decodeServerAffiliationInfo(guid) ?: ServerAffiliationInfo() aff.testDelayMillis = testResult - serverAffStorage.encode(guid, Gson().toJson(aff)) + serverAffStorage.encode(guid, JsonUtil.toJson(aff)) } fun clearAllTestDelayResults(keys: List?) { keys?.forEach { key -> decodeServerAffiliationInfo(key)?.let { aff -> aff.testDelayMillis = 0 - serverAffStorage.encode(key, Gson().toJson(aff)) + serverAffStorage.encode(key, JsonUtil.toJson(aff)) } } } @@ -217,7 +217,7 @@ object MmkvManager { decodeSubsList().forEach { key -> val json = subStorage.decodeString(key) if (!json.isNullOrBlank()) { - subscriptions.add(Pair(key, Gson().fromJson(json, SubscriptionItem::class.java))) + subscriptions.add(Pair(key, JsonUtil.fromJson(json, SubscriptionItem::class.java))) } } return subscriptions @@ -234,7 +234,7 @@ object MmkvManager { fun encodeSubscription(guid: String, subItem: SubscriptionItem) { val key = guid.ifBlank { Utils.getUuid() } - subStorage.encode(key, Gson().toJson(subItem)) + subStorage.encode(key, JsonUtil.toJson(subItem)) val subsList = decodeSubsList() if (!subsList.contains(key)) { @@ -245,11 +245,11 @@ object MmkvManager { fun decodeSubscription(subscriptionId: String): SubscriptionItem? { val json = subStorage.decodeString(subscriptionId) ?: return null - return Gson().fromJson(json, SubscriptionItem::class.java) + return JsonUtil.fromJson(json, SubscriptionItem::class.java) } fun encodeSubsList(subsList: MutableList) { - mainStorage.encode(KEY_SUB_IDS, Gson().toJson(subsList)) + mainStorage.encode(KEY_SUB_IDS, JsonUtil.toJson(subsList)) } fun decodeSubsList(): MutableList { @@ -257,7 +257,7 @@ object MmkvManager { return if (json.isNullOrBlank()) { mutableListOf() } else { - Gson().fromJson(json, Array::class.java).toMutableList() + JsonUtil.fromJson(json, Array::class.java).toMutableList() } } @@ -270,7 +270,7 @@ object MmkvManager { assetStorage.allKeys()?.forEach { key -> val json = assetStorage.decodeString(key) if (!json.isNullOrBlank()) { - assetUrlItems.add(Pair(key, Gson().fromJson(json, AssetUrlItem::class.java))) + assetUrlItems.add(Pair(key, JsonUtil.fromJson(json, AssetUrlItem::class.java))) } } return assetUrlItems.sortedBy { (_, value) -> value.addedTime } @@ -282,12 +282,12 @@ object MmkvManager { fun encodeAsset(assetid: String, assetItem: AssetUrlItem) { val key = assetid.ifBlank { Utils.getUuid() } - assetStorage.encode(key, Gson().toJson(assetItem)) + assetStorage.encode(key, JsonUtil.toJson(assetItem)) } fun decodeAsset(assetid: String): AssetUrlItem? { val json = assetStorage.decodeString(assetid) ?: return null - return Gson().fromJson(json, AssetUrlItem::class.java) + return JsonUtil.fromJson(json, AssetUrlItem::class.java) } //endregion @@ -297,14 +297,14 @@ object MmkvManager { fun decodeRoutingRulesets(): MutableList? { val ruleset = settingsStorage.decodeString(PREF_ROUTING_RULESET) if (ruleset.isNullOrEmpty()) return null - return Gson().fromJson(ruleset, Array::class.java).toMutableList() + return JsonUtil.fromJson(ruleset, Array::class.java).toMutableList() } fun encodeRoutingRulesets(rulesetList: MutableList?) { if (rulesetList.isNullOrEmpty()) settingsStorage.encode(PREF_ROUTING_RULESET, "") else - settingsStorage.encode(PREF_ROUTING_RULESET, Gson().toJson(rulesetList)) + settingsStorage.encode(PREF_ROUTING_RULESET, JsonUtil.toJson(rulesetList)) } //endregion diff --git a/v2rayng/V2rayNG/app/src/main/kotlin/com/v2ray/ang/util/PluginUtil.kt b/v2rayng/V2rayNG/app/src/main/kotlin/com/v2ray/ang/util/PluginUtil.kt index 2a0bc05e73..bb585ca1f4 100644 --- a/v2rayng/V2rayNG/app/src/main/kotlin/com/v2ray/ang/util/PluginUtil.kt +++ b/v2rayng/V2rayNG/app/src/main/kotlin/com/v2ray/ang/util/PluginUtil.kt @@ -3,12 +3,10 @@ package com.v2ray.ang.util import android.content.Context import android.os.SystemClock import android.util.Log -import com.google.gson.Gson -import com.v2ray.ang.AppConfig + import com.v2ray.ang.AppConfig.ANG_PACKAGE import com.v2ray.ang.dto.EConfigType import com.v2ray.ang.dto.ServerConfig -import com.v2ray.ang.util.MmkvManager.settingsStorage import com.v2ray.ang.util.fmt.Hysteria2Fmt import kotlinx.coroutines.CoroutineScope import kotlinx.coroutines.Dispatchers @@ -25,22 +23,23 @@ object PluginUtil { // return PluginManager.init(name)!! // } - fun runPlugin(context: Context, config: ServerConfig?) { + fun runPlugin(context: Context, config: ServerConfig?, domainPort: String?) { Log.d(packageName, "runPlugin") val outbound = config?.getProxyOutbound() ?: return if (outbound.protocol.equals(EConfigType.HYSTERIA2.name, true)) { Log.d(packageName, "runPlugin $HYSTERIA2") - val socksPort = 100 + Utils.parseInt(settingsStorage?.decodeString(AppConfig.PREF_SOCKS_PORT), AppConfig.PORT_SOCKS.toInt()) + val socksPort = domainPort?.split(":")?.last() + .let { if (it.isNullOrEmpty()) return else it.toInt() } val hy2Config = Hysteria2Fmt.toNativeConfig(config, socksPort) ?: return val configFile = File(context.noBackupFilesDir, "hy2_${SystemClock.elapsedRealtime()}.json") Log.d(packageName, "runPlugin ${configFile.absolutePath}") configFile.parentFile?.mkdirs() - configFile.writeText(Gson().toJson(hy2Config)) - Log.d(packageName, Gson().toJson(hy2Config)) + configFile.writeText(JsonUtil.toJson(hy2Config)) + Log.d(packageName, JsonUtil.toJson(hy2Config)) runHy2(context, configFile) } diff --git a/v2rayng/V2rayNG/app/src/main/kotlin/com/v2ray/ang/util/SettingsManager.kt b/v2rayng/V2rayNG/app/src/main/kotlin/com/v2ray/ang/util/SettingsManager.kt index c8eaf7e539..53e13138a2 100644 --- a/v2rayng/V2rayNG/app/src/main/kotlin/com/v2ray/ang/util/SettingsManager.kt +++ b/v2rayng/V2rayNG/app/src/main/kotlin/com/v2ray/ang/util/SettingsManager.kt @@ -2,12 +2,15 @@ package com.v2ray.ang.util import android.content.Context import android.text.TextUtils -import com.google.gson.Gson + +import com.v2ray.ang.AppConfig import com.v2ray.ang.dto.RulesetItem import com.v2ray.ang.dto.ServerConfig import com.v2ray.ang.util.MmkvManager.decodeProfileConfig import com.v2ray.ang.util.MmkvManager.decodeServerConfig import com.v2ray.ang.util.MmkvManager.decodeServerList +import com.v2ray.ang.util.MmkvManager.settingsStorage +import com.v2ray.ang.util.Utils.parseInt import java.util.Collections object SettingsManager { @@ -32,7 +35,7 @@ object SettingsManager { return null } - return Gson().fromJson(assets, Array::class.java).toMutableList() + return JsonUtil.fromJson(assets, Array::class.java).toMutableList() } fun resetRoutingRulesets(context: Context, index: Int) { @@ -46,7 +49,7 @@ object SettingsManager { } try { - val rulesetList = Gson().fromJson(content, Array::class.java).toMutableList() + val rulesetList = JsonUtil.fromJson(content, Array::class.java).toMutableList() if (rulesetList.isNullOrEmpty()) { return false } @@ -140,4 +143,12 @@ object SettingsManager { return null } + fun getSocksPort(): Int { + return parseInt(settingsStorage?.decodeString(AppConfig.PREF_SOCKS_PORT), AppConfig.PORT_SOCKS.toInt()) + } + + fun getHttpPort(): Int { + return parseInt(settingsStorage?.decodeString(AppConfig.PREF_HTTP_PORT), AppConfig.PORT_HTTP.toInt()) + } + } diff --git a/v2rayng/V2rayNG/app/src/main/kotlin/com/v2ray/ang/util/SpeedtestUtil.kt b/v2rayng/V2rayNG/app/src/main/kotlin/com/v2ray/ang/util/SpeedtestUtil.kt index 29e27de0ac..10e793be24 100644 --- a/v2rayng/V2rayNG/app/src/main/kotlin/com/v2ray/ang/util/SpeedtestUtil.kt +++ b/v2rayng/V2rayNG/app/src/main/kotlin/com/v2ray/ang/util/SpeedtestUtil.kt @@ -98,9 +98,9 @@ object SpeedtestUtil { } } - fun testConnection(context: Context, port: Int): String { - // return V2RayVpnService.measureV2rayDelay() + fun testConnection(context: Context, port: Int): Pair { var result: String + var elapsed = -1L var conn: HttpURLConnection? = null try { @@ -120,7 +120,7 @@ object SpeedtestUtil { val start = SystemClock.elapsedRealtime() val code = conn.responseCode - val elapsed = SystemClock.elapsedRealtime() - start + elapsed = SystemClock.elapsedRealtime() - start if (code == 204 || code == 200 && conn.responseLength == 0L) { result = context.getString(R.string.connection_test_available, elapsed) @@ -134,10 +134,7 @@ object SpeedtestUtil { } } catch (e: IOException) { // network exception - Log.d( - AppConfig.ANG_PACKAGE, - "testConnection IOException: " + Log.getStackTraceString(e) - ) + Log.d(AppConfig.ANG_PACKAGE, "testConnection IOException: " + Log.getStackTraceString(e)) result = context.getString(R.string.connection_test_error, e.message) } catch (e: Exception) { // library exception, eg sumsung @@ -147,7 +144,7 @@ object SpeedtestUtil { conn?.disconnect() } - return result + return Pair(elapsed, result) } fun getLibVersion(): String { diff --git a/v2rayng/V2rayNG/app/src/main/kotlin/com/v2ray/ang/util/Utils.kt b/v2rayng/V2rayNG/app/src/main/kotlin/com/v2ray/ang/util/Utils.kt index 062cef60b8..687fac9b77 100644 --- a/v2rayng/V2rayNG/app/src/main/kotlin/com/v2ray/ang/util/Utils.kt +++ b/v2rayng/V2rayNG/app/src/main/kotlin/com/v2ray/ang/util/Utils.kt @@ -453,6 +453,17 @@ object Utils { } } + fun findFreePort(ports: List): Int { + for (port in ports) { + try { + return ServerSocket(port).use { it.localPort } + } catch (ex: IOException) { + continue // try next port + } + } + // if the program gets here, no port in the range was found + throw IOException("no free port found") + } } diff --git a/v2rayng/V2rayNG/app/src/main/kotlin/com/v2ray/ang/util/V2rayConfigUtil.kt b/v2rayng/V2rayNG/app/src/main/kotlin/com/v2ray/ang/util/V2rayConfigUtil.kt index 3a85b4e510..aa04e075a2 100644 --- a/v2rayng/V2rayNG/app/src/main/kotlin/com/v2ray/ang/util/V2rayConfigUtil.kt +++ b/v2rayng/V2rayNG/app/src/main/kotlin/com/v2ray/ang/util/V2rayConfigUtil.kt @@ -3,7 +3,7 @@ package com.v2ray.ang.util import android.content.Context import android.text.TextUtils import android.util.Log -import com.google.gson.Gson + import com.v2ray.ang.AppConfig import com.v2ray.ang.AppConfig.ANG_PACKAGE import com.v2ray.ang.AppConfig.LOOPBACK @@ -14,6 +14,7 @@ import com.v2ray.ang.AppConfig.TAG_FRAGMENT import com.v2ray.ang.AppConfig.TAG_PROXY import com.v2ray.ang.AppConfig.WIREGUARD_LOCAL_ADDRESS_V4 import com.v2ray.ang.AppConfig.WIREGUARD_LOCAL_ADDRESS_V6 +import com.v2ray.ang.dto.ConfigResult import com.v2ray.ang.dto.EConfigType import com.v2ray.ang.dto.RulesetItem import com.v2ray.ang.dto.ServerConfig @@ -25,34 +26,32 @@ import com.v2ray.ang.util.MmkvManager.settingsStorage object V2rayConfigUtil { - data class Result(var status: Boolean, var content: String = "", var domainPort: String? = null) - - fun getV2rayConfig(context: Context, guid: String): Result { + fun getV2rayConfig(context: Context, guid: String): ConfigResult { try { - val config = MmkvManager.decodeServerConfig(guid) ?: return Result(false) + val config = MmkvManager.decodeServerConfig(guid) ?: return ConfigResult(false) if (config.configType == EConfigType.CUSTOM) { val raw = MmkvManager.decodeServerRaw(guid) val customConfig = if (raw.isNullOrBlank()) { - config.fullConfig?.toPrettyPrinting() ?: return Result(false) + config.fullConfig?.toPrettyPrinting() ?: return ConfigResult(false) } else { raw } val domainPort = config.getProxyOutbound()?.getServerAddressAndPort() - return Result(true, customConfig, domainPort) + return ConfigResult(true, guid, customConfig, domainPort) } val result = getV2rayNonCustomConfig(context, config) //Log.d(ANG_PACKAGE, result.content) - Log.d(ANG_PACKAGE, result.domainPort?:"") + result.guid = guid return result } catch (e: Exception) { e.printStackTrace() - return Result(false) + return ConfigResult(false) } } - private fun getV2rayNonCustomConfig(context: Context, config: ServerConfig): Result { - val result = Result(false) + private fun getV2rayNonCustomConfig(context: Context, config: ServerConfig): ConfigResult { + val result = ConfigResult(false) val outbound = config.getProxyOutbound() ?: return result val address = outbound.getServerAddress() ?: return result @@ -68,7 +67,7 @@ object V2rayConfigUtil { if (TextUtils.isEmpty(assets)) { return result } - val v2rayConfig = Gson().fromJson(assets, V2rayConfig::class.java) ?: return result + val v2rayConfig = JsonUtil.fromJson(assets, V2rayConfig::class.java) ?: return result v2rayConfig.log.loglevel = settingsStorage?.decodeString(AppConfig.PREF_LOGLEVEL) ?: "warning" v2rayConfig.remarks = config.remarks @@ -101,14 +100,8 @@ object V2rayConfigUtil { private fun inbounds(v2rayConfig: V2rayConfig): Boolean { try { - val socksPort = Utils.parseInt( - settingsStorage?.decodeString(AppConfig.PREF_SOCKS_PORT), - AppConfig.PORT_SOCKS.toInt() - ) - val httpPort = Utils.parseInt( - settingsStorage?.decodeString(AppConfig.PREF_HTTP_PORT), - AppConfig.PORT_HTTP.toInt() - ) + val socksPort = SettingsManager.getSocksPort() + val httpPort = SettingsManager.getHttpPort() v2rayConfig.inbounds.forEach { curInbound -> if (settingsStorage?.decodeBool(AppConfig.PREF_PROXY_SHARING) != true) { @@ -149,7 +142,7 @@ object V2rayConfigUtil { private fun outbounds(v2rayConfig: V2rayConfig, outbound: V2rayConfig.OutboundBean, isPlugin: Boolean): Pair { if (isPlugin) { - val socksPort = 100 + Utils.parseInt(settingsStorage?.decodeString(AppConfig.PREF_SOCKS_PORT), AppConfig.PORT_SOCKS.toInt()) + val socksPort = Utils.findFreePort(listOf(100 + SettingsManager.getSocksPort(), 0)) val outboundNew = V2rayConfig.OutboundBean( mux = null, protocol = EConfigType.SOCKS.name.lowercase(), @@ -213,7 +206,7 @@ object V2rayConfigUtil { return } - val rule = Gson().fromJson(Gson().toJson(item), RulesBean::class.java) ?: return + val rule = JsonUtil.fromJson(JsonUtil.toJson(item), RulesBean::class.java) ?: return v2rayConfig.routing.rules.add(rule) @@ -447,7 +440,7 @@ object V2rayConfigUtil { val requestString: String by lazy { """{"version":"1.1","method":"GET","headers":{"User-Agent":["Mozilla/5.0 (Windows NT 10.0; WOW64) AppleWebKit/537.36 (KHTML, like Gecko) Chrome/53.0.2785.143 Safari/537.36","Mozilla/5.0 (iPhone; CPU iPhone OS 10_0_2 like Mac OS X) AppleWebKit/601.1 (KHTML, like Gecko) CriOS/53.0.2785.109 Mobile/14A456 Safari/601.1.46"],"Accept-Encoding":["gzip, deflate"],"Connection":["keep-alive"],"Pragma":"no-cache"}}""" } - outbound.streamSettings?.tcpSettings?.header?.request = Gson().fromJson( + outbound.streamSettings?.tcpSettings?.header?.request = JsonUtil.fromJson( requestString, V2rayConfig.OutboundBean.StreamSettingsBean.TcpSettingsBean.HeaderBean.RequestBean::class.java ) diff --git a/v2rayng/V2rayNG/app/src/main/kotlin/com/v2ray/ang/util/fmt/Hysteria2Fmt.kt b/v2rayng/V2rayNG/app/src/main/kotlin/com/v2ray/ang/util/fmt/Hysteria2Fmt.kt index fd5f468ed2..d0d7bae7e3 100644 --- a/v2rayng/V2rayNG/app/src/main/kotlin/com/v2ray/ang/util/fmt/Hysteria2Fmt.kt +++ b/v2rayng/V2rayNG/app/src/main/kotlin/com/v2ray/ang/util/fmt/Hysteria2Fmt.kt @@ -99,6 +99,9 @@ object Hysteria2Fmt { socks5 = Hysteria2Bean.Socks5Bean( listen = "$LOOPBACK:${socksPort}", ), + http = Hysteria2Bean.Socks5Bean( + listen = "$LOOPBACK:${socksPort}", + ), tls = Hysteria2Bean.TlsBean( sni = tls?.serverName ?: outbound.getServerAddress(), insecure = tls?.allowInsecure diff --git a/v2rayng/V2rayNG/app/src/main/kotlin/com/v2ray/ang/util/fmt/VmessFmt.kt b/v2rayng/V2rayNG/app/src/main/kotlin/com/v2ray/ang/util/fmt/VmessFmt.kt index eca35e8591..1efad50b70 100644 --- a/v2rayng/V2rayNG/app/src/main/kotlin/com/v2ray/ang/util/fmt/VmessFmt.kt +++ b/v2rayng/V2rayNG/app/src/main/kotlin/com/v2ray/ang/util/fmt/VmessFmt.kt @@ -2,13 +2,14 @@ package com.v2ray.ang.util.fmt import android.text.TextUtils import android.util.Log -import com.google.gson.Gson + import com.v2ray.ang.AppConfig import com.v2ray.ang.dto.EConfigType import com.v2ray.ang.dto.ServerConfig import com.v2ray.ang.dto.V2rayConfig import com.v2ray.ang.dto.VmessQRCode import com.v2ray.ang.extension.idnHost +import com.v2ray.ang.util.JsonUtil import com.v2ray.ang.util.MmkvManager.settingsStorage import com.v2ray.ang.util.Utils import java.net.URI @@ -29,7 +30,7 @@ object VmessFmt { Log.d(AppConfig.ANG_PACKAGE, "R.string.toast_decoding_failed") return null } - val vmessQRCode = Gson().fromJson(result, VmessQRCode::class.java) + val vmessQRCode = JsonUtil.fromJson(result, VmessQRCode::class.java) // Although VmessQRCode fields are non null, looks like Gson may still create null fields if (TextUtils.isEmpty(vmessQRCode.add) || TextUtils.isEmpty(vmessQRCode.port) @@ -100,7 +101,7 @@ object VmessFmt { vmessQRCode.host = transportDetails[1] vmessQRCode.path = transportDetails[2] } - val json = Gson().toJson(vmessQRCode) + val json = JsonUtil.toJson(vmessQRCode) return Utils.encode(json) } diff --git a/v2rayng/V2rayNG/app/src/main/kotlin/com/v2ray/ang/viewmodel/MainViewModel.kt b/v2rayng/V2rayNG/app/src/main/kotlin/com/v2ray/ang/viewmodel/MainViewModel.kt index 28705490b2..f807970e53 100644 --- a/v2rayng/V2rayNG/app/src/main/kotlin/com/v2ray/ang/viewmodel/MainViewModel.kt +++ b/v2rayng/V2rayNG/app/src/main/kotlin/com/v2ray/ang/viewmodel/MainViewModel.kt @@ -11,7 +11,6 @@ import android.util.Log import androidx.lifecycle.AndroidViewModel import androidx.lifecycle.MutableLiveData import androidx.lifecycle.viewModelScope -import com.google.gson.Gson import com.v2ray.ang.AngApplication import com.v2ray.ang.AppConfig import com.v2ray.ang.AppConfig.ANG_PACKAGE @@ -21,14 +20,15 @@ import com.v2ray.ang.dto.ProfileItem import com.v2ray.ang.dto.ServerConfig import com.v2ray.ang.dto.ServersCache import com.v2ray.ang.dto.V2rayConfig +import com.v2ray.ang.extension.serializable import com.v2ray.ang.extension.toast import com.v2ray.ang.util.AngConfigManager import com.v2ray.ang.util.AngConfigManager.updateConfigViaSub +import com.v2ray.ang.util.JsonUtil import com.v2ray.ang.util.MessageUtil import com.v2ray.ang.util.MmkvManager import com.v2ray.ang.util.SpeedtestUtil import com.v2ray.ang.util.Utils -import com.v2ray.ang.util.V2rayConfigUtil import kotlinx.coroutines.CoroutineScope import kotlinx.coroutines.Dispatchers import kotlinx.coroutines.Job @@ -98,7 +98,7 @@ class MainViewModel(application: Application) : AndroidViewModel(application) { try { val config = ServerConfig.create(EConfigType.CUSTOM) config.subscriptionId = subscriptionId - config.fullConfig = Gson().fromJson(server, V2rayConfig::class.java) + config.fullConfig = JsonUtil.fromJson(server, V2rayConfig::class.java) config.remarks = config.fullConfig?.remarks ?: System.currentTimeMillis().toString() val key = MmkvManager.encodeServerConfig("", config) MmkvManager.encodeServerRaw(key, server) @@ -211,14 +211,7 @@ class MainViewModel(application: Application) : AndroidViewModel(application) { getApplication().toast(R.string.connection_test_testing) viewModelScope.launch(Dispatchers.Default) { // without Dispatchers.Default viewModelScope will launch in main thread for (item in serversCopy) { - val config = V2rayConfigUtil.getV2rayConfig(getApplication(), item.guid) - if (config.status) { - MessageUtil.sendMsg2TestService( - getApplication(), - AppConfig.MSG_MEASURE_CONFIG, - Pair(item.guid, config.content) - ) - } + MessageUtil.sendMsg2TestService(getApplication(), AppConfig.MSG_MEASURE_CONFIG, item.guid) } } } @@ -394,11 +387,7 @@ class MainViewModel(application: Application) : AndroidViewModel(application) { } AppConfig.MSG_MEASURE_CONFIG_SUCCESS -> { - val resultPair: Pair = if (Build.VERSION.SDK_INT >= Build.VERSION_CODES.TIRAMISU) { - intent.getSerializableExtra("content", Pair::class.java) as Pair - } else { - intent.getSerializableExtra("content") as Pair - } + val resultPair = intent.serializable>("content") ?: return MmkvManager.encodeServerTestDelayMillis(resultPair.first, resultPair.second) updateListAction.value = getPosition(resultPair.first) } diff --git a/v2rayng/V2rayNG/app/src/main/res/layout/activity_main.xml b/v2rayng/V2rayNG/app/src/main/res/layout/activity_main.xml index ad2f3cec3b..06c29322e6 100644 --- a/v2rayng/V2rayNG/app/src/main/res/layout/activity_main.xml +++ b/v2rayng/V2rayNG/app/src/main/res/layout/activity_main.xml @@ -89,7 +89,7 @@ android:layout_width="wrap_content" android:layout_height="wrap_content" android:layout_gravity="bottom|end" - android:layout_marginBottom="24dp"> + android:layout_marginBottom="12dp"> \d+)' _TESTS = [{ + 'url': 'https://podcasts.apple.com/us/podcast/ferreck-dawn-to-the-break-of-dawn-117/id1625658232?i=1000665010654', + 'md5': '82cc219b8cc1dcf8bfc5a5e99b23b172', + 'info_dict': { + 'id': '1000665010654', + 'ext': 'mp3', + 'title': 'Ferreck Dawn - To The Break of Dawn 117', + 'episode': 'Ferreck Dawn - To The Break of Dawn 117', + 'description': 'md5:1fc571102f79dbd0a77bfd71ffda23bc', + 'upload_date': '20240812', + 'timestamp': 1723449600, + 'duration': 3596, + 'series': 'Ferreck Dawn - To The Break of Dawn', + 'thumbnail': 're:.+[.](png|jpe?g|webp)', + }, + }, { 'url': 'https://podcasts.apple.com/us/podcast/207-whitney-webb-returns/id1135137367?i=1000482637777', - 'md5': '41dc31cd650143e530d9423b6b5a344f', + 'md5': 'baf8a6b8b8aa6062dbb4639ed73d0052', 'info_dict': { 'id': '1000482637777', 'ext': 'mp3', 'title': '207 - Whitney Webb Returns', + 'episode': '207 - Whitney Webb Returns', + 'episode_number': 207, 'description': 'md5:75ef4316031df7b41ced4e7b987f79c6', 'upload_date': '20200705', 'timestamp': 1593932400, - 'duration': 6454, + 'duration': 5369, 'series': 'The Tim Dillon Show', 'thumbnail': 're:.+[.](png|jpe?g|webp)', }, @@ -39,47 +54,24 @@ class ApplePodcastsIE(InfoExtractor): def _real_extract(self, url): episode_id = self._match_id(url) webpage = self._download_webpage(url, episode_id) - episode_data = {} - ember_data = {} - # new page type 2021-11 - amp_data = self._parse_json(self._search_regex( - r'(?s)id="shoebox-media-api-cache-amp-podcasts"[^>]*>\s*({.+?})\s*<', - webpage, 'AMP data', default='{}'), episode_id, fatal=False) or {} - amp_data = try_get(amp_data, - lambda a: self._parse_json( - next(a[x] for x in iter(a) if episode_id in x), - episode_id), - dict) or {} - amp_data = amp_data.get('d') or [] - episode_data = try_get( - amp_data, - lambda a: next(x for x in a - if x['type'] == 'podcast-episodes' and x['id'] == episode_id), - dict) - if not episode_data: - # try pre 2021-11 page type: TODO: consider deleting if no longer used - ember_data = self._parse_json(self._search_regex( - r'(?s)id="shoebox-ember-data-store"[^>]*>\s*({.+?})\s*<', - webpage, 'ember data'), episode_id) or {} - ember_data = ember_data.get(episode_id) or ember_data - episode_data = try_get(ember_data, lambda x: x['data'], dict) - episode = episode_data['attributes'] - description = episode.get('description') or {} - - series = None - for inc in (amp_data or ember_data.get('included') or []): - if inc.get('type') == 'media/podcast': - series = try_get(inc, lambda x: x['attributes']['name']) - series = series or clean_html(get_element_by_class('podcast-header__identity', webpage)) + server_data = self._search_json( + r'