mirror of
https://github.com/bolucat/Archive.git
synced 2025-12-24 13:28:37 +08:00
Update On Sat Nov 15 19:34:53 CET 2025
This commit is contained in:
github-action[bot]
@@ -1,2 +1,2 @@
|
||||
LINUX_VERSION-6.12 = .58
|
||||
LINUX_KERNEL_HASH-6.12.58 = 5f1c4c546660a6a81046fdfa6195306bad2c8d17c0d69876dc100a85ad4613ac
|
||||
LINUX_VERSION-6.12 = .56
|
||||
LINUX_KERNEL_HASH-6.12.56 = 55432b2af352f7bf3053c348d8549df2f2deeaa4a361c65d638c2f3b2ca7ec96
|
||||
|
||||
@@ -1,2 +1,2 @@
|
||||
LINUX_VERSION-6.6 = .116
|
||||
LINUX_KERNEL_HASH-6.6.116 = a9a59742c29be284c205dc87cbe9b065f9688488132c8f5a6057a5539230a51d
|
||||
LINUX_VERSION-6.6 = .115
|
||||
LINUX_KERNEL_HASH-6.6.115 = 0a98c05e8d0f6b49fad71b8d779410a0811ea5ae17d81744fe30718633fd9047
|
||||
|
||||
@@ -8,7 +8,7 @@
|
||||
include $(TOPDIR)/rules.mk
|
||||
|
||||
PKG_NAME:=uboot-rk35xx
|
||||
PKG_RELEASE:=2
|
||||
PKG_RELEASE:=1
|
||||
|
||||
PKG_SOURCE_PROTO:=git
|
||||
PKG_SOURCE_URL:=https://github.com/radxa/u-boot
|
||||
@@ -38,19 +38,6 @@ define U-Boot/evb-rk3528
|
||||
SOC:=rk3528
|
||||
endef
|
||||
|
||||
define U-Boot/evb-rk3566
|
||||
BUILD_SUBTARGET:=armv8
|
||||
NAME:=RK3566 Evaluation
|
||||
BUILD_DEVICES:= \
|
||||
radxa_zero-3e \
|
||||
radxa_zero-3w
|
||||
DEPENDS:=+PACKAGE_u-boot-evb-rk3566:rkbin-rk3566
|
||||
ATF:=rk3568_bl31_v1.44.elf
|
||||
DDR:=rk3566_ddr_1056MHz_v1.23.bin
|
||||
UBOOT_CONFIG:=rk3566
|
||||
SOC:=rk3568
|
||||
endef
|
||||
|
||||
define U-Boot/evb-rk3576
|
||||
BUILD_SUBTARGET:=armv8
|
||||
NAME:=RK3576 Evaluation
|
||||
@@ -66,23 +53,9 @@ define U-Boot/evb-rk3576
|
||||
SOC:=rk3576
|
||||
endef
|
||||
|
||||
define U-Boot/evb-rk3588
|
||||
BUILD_SUBTARGET:=armv8
|
||||
NAME:=RK3588 Evaluation
|
||||
BUILD_DEVICES:= \
|
||||
radxa_rock-5c
|
||||
DEPENDS:=+PACKAGE_u-boot-evb-rk3588:rkbin-rk3588
|
||||
ATF:=rk3588_bl31_v1.47.elf
|
||||
DDR:=rk3588_ddr_lp4_2112MHz_lp5_2400MHz_v1.18.bin
|
||||
UBOOT_CONFIG:=rk3588
|
||||
SOC:=rk3588
|
||||
endef
|
||||
|
||||
UBOOT_TARGETS := \
|
||||
evb-rk3528 \
|
||||
evb-rk3566 \
|
||||
evb-rk3576 \
|
||||
evb-rk3588
|
||||
evb-rk3576
|
||||
|
||||
UBOOT_CONFIGURE_VARS += USE_PRIVATE_LIBGCC=yes
|
||||
|
||||
|
||||
@@ -6,15 +6,6 @@
|
||||
CONFIG_RK_AVB_LIBAVB_USER=y
|
||||
-CONFIG_OPTEE_CLIENT=y
|
||||
-CONFIG_OPTEE_V2=y
|
||||
--- a/configs/rk3568_defconfig
|
||||
+++ b/configs/rk3568_defconfig
|
||||
@@ -222,6 +222,3 @@
|
||||
CONFIG_AVB_LIBAVB_ATX=y
|
||||
CONFIG_AVB_LIBAVB_USER=y
|
||||
CONFIG_RK_AVB_LIBAVB_USER=y
|
||||
-CONFIG_OPTEE_CLIENT=y
|
||||
-CONFIG_OPTEE_V2=y
|
||||
-CONFIG_OPTEE_ALWAYS_USE_SECURITY_PARTITION=y
|
||||
--- a/configs/rk3576_defconfig
|
||||
+++ b/configs/rk3576_defconfig
|
||||
@@ -224,6 +224,3 @@ CONFIG_AVB_LIBAVB_AB=y
|
||||
@@ -24,12 +15,3 @@
|
||||
-CONFIG_OPTEE_CLIENT=y
|
||||
-CONFIG_OPTEE_V2=y
|
||||
-CONFIG_OPTEE_ALWAYS_USE_SECURITY_PARTITION=y
|
||||
--- a/configs/rk3588_defconfig
|
||||
+++ b/configs/rk3588_defconfig
|
||||
@@ -232,6 +232,3 @@
|
||||
CONFIG_AVB_LIBAVB_ATX=y
|
||||
CONFIG_AVB_LIBAVB_USER=y
|
||||
CONFIG_RK_AVB_LIBAVB_USER=y
|
||||
-CONFIG_OPTEE_CLIENT=y
|
||||
-CONFIG_OPTEE_V2=y
|
||||
-CONFIG_OPTEE_ALWAYS_USE_SECURITY_PARTITION=y
|
||||
|
||||
@@ -1,224 +0,0 @@
|
||||
CONFIG_ARM=y
|
||||
CONFIG_ARCH_ROCKCHIP=y
|
||||
CONFIG_SPL_LIBCOMMON_SUPPORT=y
|
||||
CONFIG_SPL_LIBGENERIC_SUPPORT=y
|
||||
CONFIG_SYS_MALLOC_F_LEN=0x80000
|
||||
CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-rockchip/make_fit_atf.sh"
|
||||
CONFIG_ROCKCHIP_RK3568=y
|
||||
CONFIG_ROCKCHIP_FIT_IMAGE=y
|
||||
CONFIG_ROCKCHIP_VENDOR_PARTITION=y
|
||||
CONFIG_DM_DMC=y
|
||||
CONFIG_ROCKCHIP_DMC_FSP=y
|
||||
CONFIG_ROCKCHIP_FIT_IMAGE_PACK=y
|
||||
CONFIG_ROCKCHIP_NEW_IDB=y
|
||||
CONFIG_SPL_SERIAL_SUPPORT=y
|
||||
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
|
||||
CONFIG_TARGET_EVB_RK3568=y
|
||||
CONFIG_SPL_LIBDISK_SUPPORT=y
|
||||
CONFIG_SPL_NAND_SUPPORT=y
|
||||
CONFIG_SPL_SPI_FLASH_SUPPORT=y
|
||||
CONFIG_SPL_SPI_SUPPORT=y
|
||||
CONFIG_DEFAULT_DEVICE_TREE="rk3568-evb"
|
||||
CONFIG_DEBUG_UART=y
|
||||
CONFIG_IMAGE_GZIP=y
|
||||
CONFIG_FIT=y
|
||||
CONFIG_FIT_IMAGE_POST_PROCESS=y
|
||||
CONFIG_FIT_HW_CRYPTO=y
|
||||
CONFIG_SPL_LOAD_FIT=y
|
||||
CONFIG_SPL_FIT_IMAGE_POST_PROCESS=y
|
||||
CONFIG_SPL_FIT_HW_CRYPTO=y
|
||||
# CONFIG_SPL_SYS_DCACHE_OFF is not set
|
||||
CONFIG_BOOTDELAY=0
|
||||
CONFIG_SYS_CONSOLE_INFO_QUIET=y
|
||||
# CONFIG_DISPLAY_CPUINFO is not set
|
||||
CONFIG_ANDROID_BOOTLOADER=y
|
||||
CONFIG_ANDROID_AVB=y
|
||||
CONFIG_ANDROID_BOOT_IMAGE_HASH=y
|
||||
CONFIG_BOARD_RNG_SEED=y
|
||||
CONFIG_SPL_BOARD_INIT=y
|
||||
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
|
||||
# CONFIG_SPL_LEGACY_IMAGE_SUPPORT is not set
|
||||
CONFIG_SPL_SEPARATE_BSS=y
|
||||
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION=y
|
||||
CONFIG_SPL_SHA256_SUPPORT=y
|
||||
CONFIG_SPL_CRYPTO_SUPPORT=y
|
||||
CONFIG_SPL_HASH_SUPPORT=y
|
||||
CONFIG_SPL_MMC_WRITE=y
|
||||
CONFIG_SPL_MTD_SUPPORT=y
|
||||
CONFIG_SPL_MTD_WRITE=y
|
||||
CONFIG_SPL_SPI_FLASH_SFDP_SUPPORT=y
|
||||
CONFIG_SPL_ATF=y
|
||||
CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
|
||||
CONFIG_SPL_AB=y
|
||||
CONFIG_FASTBOOT_BUF_ADDR=0xc00800
|
||||
CONFIG_FASTBOOT_BUF_SIZE=0x04000000
|
||||
CONFIG_FASTBOOT_FLASH=y
|
||||
CONFIG_FASTBOOT_FLASH_MMC_DEV=0
|
||||
CONFIG_CMD_BOOTZ=y
|
||||
CONFIG_CMD_DTIMG=y
|
||||
# CONFIG_CMD_ELF is not set
|
||||
# CONFIG_CMD_IMI is not set
|
||||
# CONFIG_CMD_IMLS is not set
|
||||
# CONFIG_CMD_XIMG is not set
|
||||
# CONFIG_CMD_LZMADEC is not set
|
||||
# CONFIG_CMD_UNZIP is not set
|
||||
# CONFIG_CMD_FLASH is not set
|
||||
# CONFIG_CMD_FPGA is not set
|
||||
CONFIG_CMD_GPT=y
|
||||
# CONFIG_CMD_LOADB is not set
|
||||
# CONFIG_CMD_LOADS is not set
|
||||
CONFIG_CMD_BOOT_ANDROID=y
|
||||
CONFIG_CMD_BOOT_ROCKCHIP=y
|
||||
CONFIG_CMD_MMC=y
|
||||
CONFIG_CMD_MTD=y
|
||||
CONFIG_CMD_NAND=y
|
||||
CONFIG_CMD_USB=y
|
||||
CONFIG_CMD_USB_MASS_STORAGE=y
|
||||
# CONFIG_CMD_ITEST is not set
|
||||
# CONFIG_CMD_SETEXPR is not set
|
||||
CONFIG_CMD_TFTPPUT=y
|
||||
CONFIG_CMD_TFTP_BOOTM=y
|
||||
CONFIG_CMD_TFTP_FLASH=y
|
||||
# CONFIG_CMD_MISC is not set
|
||||
# CONFIG_CMD_CHARGE_DISPLAY is not set
|
||||
CONFIG_CMD_MTD_BLK=y
|
||||
# CONFIG_SPL_DOS_PARTITION is not set
|
||||
# CONFIG_ISO_PARTITION is not set
|
||||
CONFIG_EFI_PARTITION_ENTRIES_NUMBERS=64
|
||||
CONFIG_SPL_OF_CONTROL=y
|
||||
CONFIG_SPL_DTB_MINIMUM=y
|
||||
CONFIG_OF_LIVE=y
|
||||
CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
|
||||
# CONFIG_NET_TFTP_VARS is not set
|
||||
CONFIG_REGMAP=y
|
||||
CONFIG_SPL_REGMAP=y
|
||||
CONFIG_SYSCON=y
|
||||
CONFIG_SPL_SYSCON=y
|
||||
CONFIG_CLK=y
|
||||
CONFIG_SPL_CLK=y
|
||||
CONFIG_CLK_SCMI=y
|
||||
CONFIG_DM_CRYPTO=y
|
||||
CONFIG_SPL_DM_CRYPTO=y
|
||||
CONFIG_ROCKCHIP_CRYPTO_V2=y
|
||||
CONFIG_SPL_ROCKCHIP_CRYPTO_V2=y
|
||||
CONFIG_DM_RNG=y
|
||||
CONFIG_RNG_ROCKCHIP=y
|
||||
CONFIG_SCMI_FIRMWARE=y
|
||||
CONFIG_ROCKCHIP_GPIO=y
|
||||
CONFIG_ROCKCHIP_GPIO_V2=y
|
||||
CONFIG_SYS_I2C_ROCKCHIP=y
|
||||
CONFIG_DM_KEY=y
|
||||
CONFIG_RK8XX_PWRKEY=y
|
||||
CONFIG_ADC_KEY=y
|
||||
CONFIG_MISC=y
|
||||
CONFIG_SPL_MISC=y
|
||||
CONFIG_ROCKCHIP_OTP=y
|
||||
CONFIG_SPL_ROCKCHIP_SECURE_OTP=y
|
||||
CONFIG_MMC_DW=y
|
||||
CONFIG_MMC_DW_ROCKCHIP=y
|
||||
CONFIG_MMC_SDHCI=y
|
||||
CONFIG_MMC_SDHCI_SDMA=y
|
||||
CONFIG_MMC_SDHCI_ROCKCHIP=y
|
||||
CONFIG_MTD=y
|
||||
CONFIG_MTD_BLK=y
|
||||
CONFIG_MTD_DEVICE=y
|
||||
CONFIG_NAND=y
|
||||
CONFIG_NAND_ROCKCHIP_V9=y
|
||||
CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
|
||||
CONFIG_SYS_NAND_U_BOOT_OFFS=0x8000
|
||||
CONFIG_SYS_NAND_U_BOOT_OFFS_REDUND=0x10000
|
||||
CONFIG_MTD_SPI_NAND=y
|
||||
CONFIG_SPI_FLASH=y
|
||||
CONFIG_SF_DEFAULT_SPEED=20000000
|
||||
CONFIG_SPI_FLASH_EON=y
|
||||
CONFIG_SPI_FLASH_GIGADEVICE=y
|
||||
CONFIG_SPI_FLASH_MACRONIX=y
|
||||
CONFIG_SPI_FLASH_WINBOND=y
|
||||
CONFIG_SPI_FLASH_XMC=y
|
||||
CONFIG_SPI_FLASH_MTD=y
|
||||
CONFIG_DM_ETH=y
|
||||
CONFIG_DM_ETH_PHY=y
|
||||
CONFIG_DWC_ETH_QOS=y
|
||||
CONFIG_GMAC_ROCKCHIP=y
|
||||
CONFIG_PHY_ROCKCHIP_INNO_USB2=y
|
||||
CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y
|
||||
CONFIG_PHY_ROCKCHIP_NANENG_EDP=y
|
||||
CONFIG_PINCTRL=y
|
||||
CONFIG_SPL_PINCTRL=y
|
||||
CONFIG_DM_FUEL_GAUGE=y
|
||||
CONFIG_POWER_FG_RK817=y
|
||||
CONFIG_IO_DOMAIN=y
|
||||
CONFIG_ROCKCHIP_IO_DOMAIN=y
|
||||
CONFIG_DM_PMIC=y
|
||||
CONFIG_PMIC_RK8XX=y
|
||||
CONFIG_REGULATOR_FAN53555=y
|
||||
CONFIG_REGULATOR_PWM=y
|
||||
CONFIG_DM_REGULATOR_FIXED=y
|
||||
CONFIG_DM_REGULATOR_GPIO=y
|
||||
CONFIG_REGULATOR_RK8XX=y
|
||||
CONFIG_DM_CHARGE_DISPLAY=y
|
||||
CONFIG_CHARGE_ANIMATION=y
|
||||
CONFIG_PWM_ROCKCHIP=y
|
||||
CONFIG_RAM=y
|
||||
CONFIG_SPL_RAM=y
|
||||
CONFIG_TPL_RAM=y
|
||||
CONFIG_DM_RAMDISK=y
|
||||
CONFIG_RAMDISK_RO=y
|
||||
CONFIG_ROCKCHIP_SDRAM_COMMON=y
|
||||
CONFIG_ROCKCHIP_TPL_INIT_DRAM_TYPE=0
|
||||
CONFIG_DM_RESET=y
|
||||
CONFIG_SPL_DM_RESET=y
|
||||
CONFIG_SPL_RESET_ROCKCHIP=y
|
||||
CONFIG_BAUDRATE=1500000
|
||||
CONFIG_DEBUG_UART_BASE=0xFE660000
|
||||
CONFIG_DEBUG_UART_CLOCK=24000000
|
||||
CONFIG_DEBUG_UART_SHIFT=2
|
||||
CONFIG_ROCKCHIP_SFC=y
|
||||
CONFIG_SYSRESET=y
|
||||
CONFIG_USB=y
|
||||
CONFIG_USB_XHCI_HCD=y
|
||||
CONFIG_USB_XHCI_DWC3=y
|
||||
CONFIG_USB_EHCI_HCD=y
|
||||
CONFIG_USB_EHCI_GENERIC=y
|
||||
CONFIG_USB_OHCI_HCD=y
|
||||
CONFIG_USB_OHCI_GENERIC=y
|
||||
CONFIG_USB_DWC3=y
|
||||
CONFIG_USB_DWC3_GADGET=y
|
||||
CONFIG_USB_DWC3_GENERIC=y
|
||||
CONFIG_USB_STORAGE=y
|
||||
CONFIG_USB_GADGET=y
|
||||
CONFIG_USB_GADGET_MANUFACTURER="Rockchip"
|
||||
CONFIG_USB_GADGET_VENDOR_NUM=0x2207
|
||||
CONFIG_USB_GADGET_PRODUCT_NUM=0x350a
|
||||
CONFIG_USB_GADGET_DOWNLOAD=y
|
||||
CONFIG_DM_VIDEO=y
|
||||
CONFIG_DISPLAY=y
|
||||
CONFIG_DRM_ROCKCHIP=y
|
||||
CONFIG_DRM_ROCKCHIP_DW_HDMI=y
|
||||
CONFIG_DRM_ROCKCHIP_INNO_MIPI_PHY=y
|
||||
CONFIG_DRM_ROCKCHIP_INNO_VIDEO_COMBO_PHY=y
|
||||
CONFIG_DRM_ROCKCHIP_DW_MIPI_DSI=y
|
||||
CONFIG_DRM_ROCKCHIP_ANALOGIX_DP=y
|
||||
CONFIG_DRM_ROCKCHIP_LVDS=y
|
||||
CONFIG_DRM_ROCKCHIP_RGB=y
|
||||
CONFIG_ROCKCHIP_CUBIC_LUT_SIZE=9
|
||||
CONFIG_LCD=y
|
||||
CONFIG_USE_TINY_PRINTF=y
|
||||
CONFIG_SPL_TINY_MEMSET=y
|
||||
CONFIG_RSA=y
|
||||
CONFIG_SPL_RSA=y
|
||||
CONFIG_RSA_N_SIZE=0x200
|
||||
CONFIG_RSA_E_SIZE=0x10
|
||||
CONFIG_RSA_C_SIZE=0x20
|
||||
CONFIG_XBC=y
|
||||
CONFIG_SHA512=y
|
||||
CONFIG_LZ4=y
|
||||
CONFIG_LZMA=y
|
||||
CONFIG_SPL_GZIP=y
|
||||
CONFIG_ERRNO_STR=y
|
||||
# CONFIG_EFI_LOADER is not set
|
||||
CONFIG_AVB_LIBAVB=y
|
||||
CONFIG_AVB_LIBAVB_AB=y
|
||||
CONFIG_AVB_LIBAVB_ATX=y
|
||||
CONFIG_AVB_LIBAVB_USER=y
|
||||
CONFIG_RK_AVB_LIBAVB_USER=y
|
||||
@@ -236,6 +236,14 @@ define U-Boot/panther-x2-rk3566
|
||||
panther_x2
|
||||
endef
|
||||
|
||||
define U-Boot/radxa-zero-3-rk3566
|
||||
$(U-Boot/rk3566/Default)
|
||||
NAME:=ZERO 3E/3W
|
||||
BUILD_DEVICES:= \
|
||||
radxa_zero-3e \
|
||||
radxa_zero-3w
|
||||
endef
|
||||
|
||||
define U-Boot/rock-3c-rk3566
|
||||
$(U-Boot/rk3566/Default)
|
||||
NAME:=ROCK 3C
|
||||
@@ -451,11 +459,19 @@ define U-Boot/rock5a-rk3588s
|
||||
radxa_rock-5a
|
||||
endef
|
||||
|
||||
define U-Boot/rock-5c-rk3588s
|
||||
$(U-Boot/rk3588/Default)
|
||||
NAME:=ROCK 5C/5C Lite
|
||||
BUILD_DEVICES:= \
|
||||
radxa_rock-5c
|
||||
endef
|
||||
|
||||
UBOOT_TARGETS := \
|
||||
generic-rk3528 \
|
||||
radxa-e20c-rk3528 \
|
||||
nanopi-r3s-rk3566 \
|
||||
panther-x2-rk3566 \
|
||||
radxa-zero-3-rk3566 \
|
||||
rock-3c-rk3566 \
|
||||
bpi-r2-pro-rk3568 \
|
||||
generic-rk3568 \
|
||||
@@ -480,6 +496,7 @@ UBOOT_TARGETS := \
|
||||
nanopi-r6s-rk3588s \
|
||||
orangepi-5-rk3588s \
|
||||
rock5a-rk3588s \
|
||||
rock-5c-rk3588s \
|
||||
dlfr100-rk3399 \
|
||||
h3399pc-rk3399 \
|
||||
fine3399-rk3399 \
|
||||
|
||||
@@ -0,0 +1,32 @@
|
||||
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
|
||||
From: Jonas Karlman <jonas@kwiboo.se>
|
||||
Date: Sun, 10 Aug 2025 22:26:31 +0000
|
||||
Subject: rockchip: rk3588s-rock-5c: Add support for ROCK 5C Lite variant
|
||||
|
||||
Add Kconfig option OF_SYSTEM_SETUP=y to support booting ROCK 5C Lite
|
||||
boards with a RK3582 SoC. CPU and GPU cores are failed based on ip-state
|
||||
and policy.
|
||||
|
||||
Tested on a ROCK 5C Lite v1.1:
|
||||
|
||||
cpu-code: 35 82
|
||||
ip-state: 00 80 00 (otp)
|
||||
ip-state: c0 80 04 (policy)
|
||||
remove cpu-map cluster2
|
||||
fail rkvdec1
|
||||
fail rkvenc1
|
||||
fail cpu cpu@600
|
||||
fail cpu cpu@700
|
||||
|
||||
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
|
||||
|
||||
--- a/configs/rock-5c-rk3588s_defconfig
|
||||
+++ b/configs/rock-5c-rk3588s_defconfig
|
||||
@@ -18,6 +18,7 @@ CONFIG_FIT_VERBOSE=y
|
||||
CONFIG_SPL_FIT_SIGNATURE=y
|
||||
CONFIG_SPL_LOAD_FIT=y
|
||||
CONFIG_LEGACY_IMAGE_FORMAT=y
|
||||
+CONFIG_OF_SYSTEM_SETUP=y
|
||||
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3588s-rock-5c.dtb"
|
||||
# CONFIG_DISPLAY_CPUINFO is not set
|
||||
CONFIG_SPL_MAX_SIZE=0x40000
|
||||
@@ -0,0 +1,48 @@
|
||||
From 8680ecfcb4570e5f68a7b1bc237dfdfcf65b389e Mon Sep 17 00:00:00 2001
|
||||
From: Dave Stevenson <dave.stevenson@raspberrypi.com>
|
||||
Date: Thu, 21 Dec 2023 18:01:59 +0000
|
||||
Subject: [PATCH] media: i2c: adv7180: Use MEDIA_BUS_FMT_UYVY8_1X16 for CSI2
|
||||
output
|
||||
|
||||
CSI2 devices are meant to use the 1Xnn formats rather than 2Xnn
|
||||
such as MEDIA_BUS_FMT_UYVY8_2X8.
|
||||
|
||||
For devices with ADV7180_FLAG_MIPI_CSI2 set, use
|
||||
MEDIA_BUS_FMT_UYVY8_1X16.
|
||||
|
||||
Signed-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com>
|
||||
---
|
||||
drivers/media/i2c/adv7180.c | 12 ++++++++++--
|
||||
1 file changed, 10 insertions(+), 2 deletions(-)
|
||||
|
||||
--- a/drivers/media/i2c/adv7180.c
|
||||
+++ b/drivers/media/i2c/adv7180.c
|
||||
@@ -737,10 +737,15 @@ static int adv7180_enum_mbus_code(struct
|
||||
struct v4l2_subdev_state *sd_state,
|
||||
struct v4l2_subdev_mbus_code_enum *code)
|
||||
{
|
||||
+ struct adv7180_state *state = to_state(sd);
|
||||
+
|
||||
if (code->index != 0)
|
||||
return -EINVAL;
|
||||
|
||||
- code->code = MEDIA_BUS_FMT_UYVY8_2X8;
|
||||
+ if (state->chip_info->flags & ADV7180_FLAG_MIPI_CSI2)
|
||||
+ code->code = MEDIA_BUS_FMT_UYVY8_1X16;
|
||||
+ else
|
||||
+ code->code = MEDIA_BUS_FMT_UYVY8_2X8;
|
||||
|
||||
return 0;
|
||||
}
|
||||
@@ -750,7 +755,10 @@ static int adv7180_mbus_fmt(struct v4l2_
|
||||
{
|
||||
struct adv7180_state *state = to_state(sd);
|
||||
|
||||
- fmt->code = MEDIA_BUS_FMT_UYVY8_2X8;
|
||||
+ if (state->chip_info->flags & ADV7180_FLAG_MIPI_CSI2)
|
||||
+ fmt->code = MEDIA_BUS_FMT_UYVY8_1X16;
|
||||
+ else
|
||||
+ fmt->code = MEDIA_BUS_FMT_UYVY8_2X8;
|
||||
fmt->colorspace = V4L2_COLORSPACE_SMPTE170M;
|
||||
fmt->width = 720;
|
||||
fmt->height = state->curr_norm & V4L2_STD_525_60 ? 480 : 576;
|
||||
@@ -0,0 +1,98 @@
|
||||
From 7e58b9c99676d641ef76edd9c097f1c3c4e6c464 Mon Sep 17 00:00:00 2001
|
||||
From: Dave Stevenson <dave.stevenson@raspberrypi.com>
|
||||
Date: Thu, 21 Dec 2023 18:03:34 +0000
|
||||
Subject: [PATCH] media: i2c: adv7180: Add support for V4L2_CID_LINK_FREQ
|
||||
|
||||
For CSI2 receivers that need to know the link frequency,
|
||||
add it as a control to the driver.
|
||||
Interlaced modes are 216Mbp/s or 108MHz, whilst going through
|
||||
the I2P to deinterlace gives 432Mb/s or 216MHz.
|
||||
|
||||
Signed-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com>
|
||||
---
|
||||
drivers/media/i2c/adv7180.c | 32 +++++++++++++++++++++++++++++++-
|
||||
1 file changed, 31 insertions(+), 1 deletion(-)
|
||||
|
||||
--- a/drivers/media/i2c/adv7180.c
|
||||
+++ b/drivers/media/i2c/adv7180.c
|
||||
@@ -189,6 +189,16 @@
|
||||
/* Initial number of frames to skip to avoid possible garbage */
|
||||
#define ADV7180_NUM_OF_SKIP_FRAMES 2
|
||||
|
||||
+enum adv7180_link_freq_idx {
|
||||
+ INTERLACED_IDX,
|
||||
+ I2P_IDX,
|
||||
+};
|
||||
+
|
||||
+static const s64 adv7180_link_freqs[] = {
|
||||
+ [INTERLACED_IDX] = 108000000,
|
||||
+ [I2P_IDX] = 216000000,
|
||||
+};
|
||||
+
|
||||
static int dbg_input;
|
||||
module_param(dbg_input, int, 0644);
|
||||
MODULE_PARM_DESC(dbg_input, "Input number (0-31)");
|
||||
@@ -229,6 +239,7 @@ struct adv7180_state {
|
||||
const struct adv7180_chip_info *chip_info;
|
||||
enum v4l2_field field;
|
||||
bool force_bt656_4;
|
||||
+ struct v4l2_ctrl *link_freq;
|
||||
};
|
||||
#define to_adv7180_sd(_ctrl) (&container_of(_ctrl->handler, \
|
||||
struct adv7180_state, \
|
||||
@@ -630,6 +641,9 @@ static int adv7180_s_ctrl(struct v4l2_ct
|
||||
|
||||
if (ret)
|
||||
return ret;
|
||||
+ if (ctrl->flags & V4L2_CTRL_FLAG_READ_ONLY)
|
||||
+ goto unlock;
|
||||
+
|
||||
val = ctrl->val;
|
||||
switch (ctrl->id) {
|
||||
case V4L2_CID_BRIGHTNESS:
|
||||
@@ -671,6 +685,7 @@ static int adv7180_s_ctrl(struct v4l2_ct
|
||||
ret = -EINVAL;
|
||||
}
|
||||
|
||||
+unlock:
|
||||
mutex_unlock(&state->mutex);
|
||||
return ret;
|
||||
}
|
||||
@@ -691,7 +706,7 @@ static const struct v4l2_ctrl_config adv
|
||||
|
||||
static int adv7180_init_controls(struct adv7180_state *state)
|
||||
{
|
||||
- v4l2_ctrl_handler_init(&state->ctrl_hdl, 4);
|
||||
+ v4l2_ctrl_handler_init(&state->ctrl_hdl, 5);
|
||||
|
||||
v4l2_ctrl_new_std(&state->ctrl_hdl, &adv7180_ctrl_ops,
|
||||
V4L2_CID_BRIGHTNESS, ADV7180_BRI_MIN,
|
||||
@@ -717,6 +732,17 @@ static int adv7180_init_controls(struct
|
||||
test_pattern_menu);
|
||||
}
|
||||
|
||||
+ if (state->chip_info->flags & ADV7180_FLAG_MIPI_CSI2) {
|
||||
+ state->link_freq =
|
||||
+ v4l2_ctrl_new_int_menu(&state->ctrl_hdl,
|
||||
+ &adv7180_ctrl_ops,
|
||||
+ V4L2_CID_LINK_FREQ,
|
||||
+ ARRAY_SIZE(adv7180_link_freqs) - 1,
|
||||
+ 0, adv7180_link_freqs);
|
||||
+ if (state->link_freq)
|
||||
+ state->link_freq->flags |= V4L2_CTRL_FLAG_READ_ONLY;
|
||||
+ }
|
||||
+
|
||||
state->sd.ctrl_handler = &state->ctrl_hdl;
|
||||
if (state->ctrl_hdl.error) {
|
||||
int err = state->ctrl_hdl.error;
|
||||
@@ -849,6 +875,10 @@ static int adv7180_set_pad_format(struct
|
||||
adv7180_set_power(state, false);
|
||||
adv7180_set_field_mode(state);
|
||||
adv7180_set_power(state, true);
|
||||
+ if (state->chip_info->flags & ADV7180_FLAG_MIPI_CSI2)
|
||||
+ __v4l2_ctrl_s_ctrl(state->link_freq,
|
||||
+ (state->field == V4L2_FIELD_NONE) ?
|
||||
+ I2P_IDX : INTERLACED_IDX);
|
||||
}
|
||||
} else {
|
||||
framefmt = v4l2_subdev_state_get_format(sd_state, 0);
|
||||
@@ -0,0 +1,125 @@
|
||||
From 9989fcd49c52500a2bf1f6d49411690dec45d2dc Mon Sep 17 00:00:00 2001
|
||||
From: =?UTF-8?q?Marko=20M=C3=A4kel=C3=A4?= <marko.makela@iki.fi>
|
||||
Date: Sat, 2 Aug 2025 12:47:08 +0300
|
||||
Subject: [PATCH] clk: qcom: gcc-ipq6018: rework nss_port5 clock to multiple
|
||||
conf
|
||||
|
||||
Rework nss_port5 to use the new multiple configuration implementation
|
||||
and correctly fix the clocks for this port under some corner case.
|
||||
|
||||
In OpenWrt, this patch avoids intermittent dmesg errors of the form
|
||||
nss_port5_rx_clk_src: rcg didn't update its configuration.
|
||||
|
||||
This is a mechanical, straightforward port of
|
||||
commit e88f03230dc07aa3293b6aeb078bd27370bb2594
|
||||
("clk: qcom: gcc-ipq8074: rework nss_port5/6 clock to multiple conf")
|
||||
to gcc-ipq6018, with two conflicts resolved: different frequency of the
|
||||
P_XO clock source, and only 5 Ethernet ports.
|
||||
|
||||
This was originally developed by JiaY-shi <shi05275@163.com>.
|
||||
|
||||
Link: https://lore.kernel.org/all/20231220221724.3822-4-ansuelsmth@gmail.com/
|
||||
Signed-off-by: Marko Mäkelä <marko.makela@iki.fi>
|
||||
Tested-by: Marko Mäkelä <marko.makela@iki.fi>
|
||||
---
|
||||
drivers/clk/qcom/gcc-ipq6018.c | 60 +++++++++++++++++++++-------------
|
||||
1 file changed, 38 insertions(+), 22 deletions(-)
|
||||
|
||||
--- a/drivers/clk/qcom/gcc-ipq6018.c
|
||||
+++ b/drivers/clk/qcom/gcc-ipq6018.c
|
||||
@@ -511,15 +511,23 @@ static struct clk_rcg2 apss_ahb_clk_src
|
||||
},
|
||||
};
|
||||
|
||||
-static const struct freq_tbl ftbl_nss_port5_rx_clk_src[] = {
|
||||
- F(24000000, P_XO, 1, 0, 0),
|
||||
- F(25000000, P_UNIPHY1_RX, 12.5, 0, 0),
|
||||
- F(25000000, P_UNIPHY0_RX, 5, 0, 0),
|
||||
- F(78125000, P_UNIPHY1_RX, 4, 0, 0),
|
||||
- F(125000000, P_UNIPHY1_RX, 2.5, 0, 0),
|
||||
- F(125000000, P_UNIPHY0_RX, 1, 0, 0),
|
||||
- F(156250000, P_UNIPHY1_RX, 2, 0, 0),
|
||||
- F(312500000, P_UNIPHY1_RX, 1, 0, 0),
|
||||
+static const struct freq_conf ftbl_nss_port5_rx_clk_src_25[] = {
|
||||
+ C(P_UNIPHY1_RX, 12.5, 0, 0),
|
||||
+ C(P_UNIPHY0_RX, 5, 0, 0),
|
||||
+};
|
||||
+
|
||||
+static const struct freq_conf ftbl_nss_port5_rx_clk_src_125[] = {
|
||||
+ C(P_UNIPHY1_RX, 2.5, 0, 0),
|
||||
+ C(P_UNIPHY0_RX, 1, 0, 0),
|
||||
+};
|
||||
+
|
||||
+static const struct freq_multi_tbl ftbl_nss_port5_rx_clk_src[] = {
|
||||
+ FMS(24000000, P_XO, 1, 0, 0),
|
||||
+ FM(25000000, ftbl_nss_port5_rx_clk_src_25),
|
||||
+ FMS(78125000, P_UNIPHY1_RX, 4, 0, 0),
|
||||
+ FM(125000000, ftbl_nss_port5_rx_clk_src_125),
|
||||
+ FMS(156250000, P_UNIPHY1_RX, 2, 0, 0),
|
||||
+ FMS(312500000, P_UNIPHY1_RX, 1, 0, 0),
|
||||
{ }
|
||||
};
|
||||
|
||||
@@ -547,26 +555,34 @@ gcc_xo_uniphy0_rx_tx_uniphy1_rx_tx_ubi32
|
||||
|
||||
static struct clk_rcg2 nss_port5_rx_clk_src = {
|
||||
.cmd_rcgr = 0x68060,
|
||||
- .freq_tbl = ftbl_nss_port5_rx_clk_src,
|
||||
+ .freq_multi_tbl = ftbl_nss_port5_rx_clk_src,
|
||||
.hid_width = 5,
|
||||
.parent_map = gcc_xo_uniphy0_rx_tx_uniphy1_rx_tx_ubi32_bias_map,
|
||||
.clkr.hw.init = &(struct clk_init_data){
|
||||
.name = "nss_port5_rx_clk_src",
|
||||
.parent_data = gcc_xo_uniphy0_rx_tx_uniphy1_rx_tx_ubi32_bias,
|
||||
.num_parents = 7,
|
||||
- .ops = &clk_rcg2_ops,
|
||||
+ .ops = &clk_rcg2_fm_ops,
|
||||
},
|
||||
};
|
||||
|
||||
-static const struct freq_tbl ftbl_nss_port5_tx_clk_src[] = {
|
||||
- F(24000000, P_XO, 1, 0, 0),
|
||||
- F(25000000, P_UNIPHY1_TX, 12.5, 0, 0),
|
||||
- F(25000000, P_UNIPHY0_TX, 5, 0, 0),
|
||||
- F(78125000, P_UNIPHY1_TX, 4, 0, 0),
|
||||
- F(125000000, P_UNIPHY1_TX, 2.5, 0, 0),
|
||||
- F(125000000, P_UNIPHY0_TX, 1, 0, 0),
|
||||
- F(156250000, P_UNIPHY1_TX, 2, 0, 0),
|
||||
- F(312500000, P_UNIPHY1_TX, 1, 0, 0),
|
||||
+static const struct freq_conf ftbl_nss_port5_tx_clk_src_25[] = {
|
||||
+ C(P_UNIPHY1_TX, 12.5, 0, 0),
|
||||
+ C(P_UNIPHY0_TX, 5, 0, 0),
|
||||
+};
|
||||
+
|
||||
+static const struct freq_conf ftbl_nss_port5_tx_clk_src_125[] = {
|
||||
+ C(P_UNIPHY1_TX, 2.5, 0, 0),
|
||||
+ C(P_UNIPHY0_TX, 1, 0, 0),
|
||||
+};
|
||||
+
|
||||
+static const struct freq_multi_tbl ftbl_nss_port5_tx_clk_src[] = {
|
||||
+ FMS(24000000, P_XO, 1, 0, 0),
|
||||
+ FM(25000000, ftbl_nss_port5_tx_clk_src_25),
|
||||
+ FMS(78125000, P_UNIPHY1_TX, 4, 0, 0),
|
||||
+ FM(125000000, ftbl_nss_port5_tx_clk_src_125),
|
||||
+ FMS(156250000, P_UNIPHY1_TX, 2, 0, 0),
|
||||
+ FMS(312500000, P_UNIPHY1_TX, 1, 0, 0),
|
||||
{ }
|
||||
};
|
||||
|
||||
@@ -594,14 +610,14 @@ gcc_xo_uniphy0_tx_rx_uniphy1_tx_rx_ubi32
|
||||
|
||||
static struct clk_rcg2 nss_port5_tx_clk_src = {
|
||||
.cmd_rcgr = 0x68068,
|
||||
- .freq_tbl = ftbl_nss_port5_tx_clk_src,
|
||||
+ .freq_multi_tbl = ftbl_nss_port5_tx_clk_src,
|
||||
.hid_width = 5,
|
||||
.parent_map = gcc_xo_uniphy0_tx_rx_uniphy1_tx_rx_ubi32_bias_map,
|
||||
.clkr.hw.init = &(struct clk_init_data){
|
||||
.name = "nss_port5_tx_clk_src",
|
||||
.parent_data = gcc_xo_uniphy0_tx_rx_uniphy1_tx_rx_ubi32_bias,
|
||||
.num_parents = 7,
|
||||
- .ops = &clk_rcg2_ops,
|
||||
+ .ops = &clk_rcg2_fm_ops,
|
||||
},
|
||||
};
|
||||
|
||||
@@ -35,7 +35,6 @@
|
||||
|
||||
led_green: led-green {
|
||||
color = <LED_COLOR_ID_GREEN>;
|
||||
default-state = "on";
|
||||
function = LED_FUNCTION_HEARTBEAT;
|
||||
gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
@@ -111,78 +110,6 @@
|
||||
cpu-supply = <&vdd_cpu>;
|
||||
};
|
||||
|
||||
&gpio0 {
|
||||
gpio-line-names =
|
||||
/* GPIO0_A0 - A7 */
|
||||
"", "", "", "", "", "", "", "",
|
||||
/* GPIO0_B0 - B7 */
|
||||
"", "", "", "", "", "", "", "",
|
||||
/* GPIO0_C0 - C7 */
|
||||
"", "", "", "", "", "", "", "",
|
||||
/* GPIO0_D0 - D7 */
|
||||
"pin-10 [GPIO0_D0]", "pin-08 [GPIO0_D1]", "",
|
||||
"", "", "", "", "";
|
||||
};
|
||||
|
||||
&gpio1 {
|
||||
gpio-line-names =
|
||||
/* GPIO1_A0 - A7 */
|
||||
"pin-03 [GPIO1_A0]", "pin-05 [GPIO1_A1]", "",
|
||||
"", "pin-37 [GPIO1_A4]", "",
|
||||
"", "",
|
||||
/* GPIO1_B0 - B7 */
|
||||
"", "", "", "", "", "", "", "",
|
||||
/* GPIO1_C0 - C7 */
|
||||
"", "", "", "", "", "", "", "",
|
||||
/* GPIO1_D0 - D7 */
|
||||
"", "", "", "", "", "", "", "";
|
||||
};
|
||||
|
||||
&gpio2 {
|
||||
gpio-line-names =
|
||||
/* GPIO2_A0 - A7 */
|
||||
"", "", "", "", "", "", "", "",
|
||||
/* GPIO2_B0 - B7 */
|
||||
"", "", "", "", "", "", "", "",
|
||||
/* GPIO2_C0 - C7 */
|
||||
"", "", "", "", "", "", "", "",
|
||||
/* GPIO2_D0 - D7 */
|
||||
"", "", "", "", "", "", "", "";
|
||||
};
|
||||
|
||||
&gpio3 {
|
||||
gpio-line-names =
|
||||
/* GPIO3_A0 - A7 */
|
||||
"", "pin-11 [GPIO3_A1]", "pin-13 [GPIO3_A2]",
|
||||
"pin-12 [GPIO3_A3]", "pin-35 [GPIO3_A4]", "pin-40 [GPIO3_A5]",
|
||||
"pin-38 [GPIO3_A6]", "pin-36 [GPIO3_A7]",
|
||||
/* GPIO3_B0 - B7 */
|
||||
"pin-15 [GPIO3_B0]", "pin-16 [GPIO3_B1]", "pin-18 [GPIO3_B2]",
|
||||
"pin-29 [GPIO3_B3]", "pin-31 [GPIO3_B4]", "",
|
||||
"", "",
|
||||
/* GPIO3_C0 - C7 */
|
||||
"", "pin-22 [GPIO3_C1]", "pin-32 [GPIO3_C2]",
|
||||
"pin-33 [GPIO3_C3]", "pin-07 [GPIO3_C4]", "",
|
||||
"", "",
|
||||
/* GPIO3_D0 - D7 */
|
||||
"", "", "", "", "", "", "", "";
|
||||
};
|
||||
|
||||
&gpio4 {
|
||||
gpio-line-names =
|
||||
/* GPIO4_A0 - A7 */
|
||||
"", "", "", "", "", "", "", "",
|
||||
/* GPIO4_B0 - B7 */
|
||||
"", "", "pin-27 [GPIO4_B2]",
|
||||
"pin-28 [GPIO4_B3]", "", "", "", "",
|
||||
/* GPIO4_C0 - C7 */
|
||||
"", "", "pin-23 [GPIO4_C2]",
|
||||
"pin-19 [GPIO4_C3]", "", "pin-21 [GPIO4_C5]",
|
||||
"pin-24 [GPIO4_C6]", "",
|
||||
/* GPIO4_D0 - D7 */
|
||||
"", "", "", "", "", "", "", "";
|
||||
};
|
||||
|
||||
&gpu {
|
||||
mali-supply = <&vdd_gpu_npu>;
|
||||
status = "okay";
|
||||
|
||||
@@ -57,8 +57,6 @@
|
||||
cap-mmc-highspeed;
|
||||
max-frequency = <200000000>;
|
||||
mmc-hs200-1_8v;
|
||||
no-sd;
|
||||
no-sdio;
|
||||
non-removable;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe>;
|
||||
@@ -73,8 +71,6 @@
|
||||
cap-sdio-irq;
|
||||
keep-power-in-suspend;
|
||||
mmc-pwrseq = <&sdio_pwrseq>;
|
||||
no-mmc;
|
||||
no-sd;
|
||||
non-removable;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&sdmmc1_bus4 &sdmmc1_clk &sdmmc1_cmd>;
|
||||
@@ -19,10 +19,10 @@
|
||||
ethernet0 = &gmac1;
|
||||
mmc0 = &sdhci;
|
||||
mmc1 = &sdmmc;
|
||||
led-boot = &led_green;
|
||||
led-failsafe = &led_green;
|
||||
led-running = &led_green;
|
||||
led-upgrade = &led_green;
|
||||
led-boot = &led;
|
||||
led-failsafe = &led;
|
||||
led-running = &led;
|
||||
led-upgrade = &led;
|
||||
};
|
||||
|
||||
chosen {
|
||||
@@ -40,30 +40,19 @@
|
||||
"Headphone", "Headphones";
|
||||
};
|
||||
|
||||
hdmi0-con {
|
||||
compatible = "hdmi-connector";
|
||||
type = "a";
|
||||
|
||||
port {
|
||||
hdmi0_con_in: endpoint {
|
||||
remote-endpoint = <&hdmi0_out_con>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
leds {
|
||||
compatible = "gpio-leds";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&led_pins>;
|
||||
|
||||
led_green: led-0 {
|
||||
led-0 {
|
||||
color = <LED_COLOR_ID_GREEN>;
|
||||
default-state = "on";
|
||||
function = LED_FUNCTION_POWER;
|
||||
gpios = <&gpio3 RK_PC4 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
led-1 {
|
||||
led: led-1 {
|
||||
color = <LED_COLOR_ID_BLUE>;
|
||||
function = LED_FUNCTION_HEARTBEAT;
|
||||
gpios = <&gpio3 RK_PD5 GPIO_ACTIVE_HIGH>;
|
||||
@@ -241,6 +230,7 @@
|
||||
};
|
||||
|
||||
&gmac1 {
|
||||
clock_in_out = "output";
|
||||
phy-handle = <&rgmii_phy1>;
|
||||
phy-mode = "rgmii-id";
|
||||
phy-supply = <&vcc_3v3_s0>;
|
||||
@@ -259,31 +249,6 @@
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&hdmi0 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&hdmim0_tx0_cec
|
||||
&hdmim1_tx0_hpd
|
||||
&hdmim0_tx0_scl
|
||||
&hdmim0_tx0_sda>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&hdmi0_in {
|
||||
hdmi0_in_vp0: endpoint {
|
||||
remote-endpoint = <&vp0_out_hdmi0>;
|
||||
};
|
||||
};
|
||||
|
||||
&hdmi0_out {
|
||||
hdmi0_out_con: endpoint {
|
||||
remote-endpoint = <&hdmi0_con_in>;
|
||||
};
|
||||
};
|
||||
|
||||
&hdptxphy0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&i2c0 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&i2c0m2_xfer>;
|
||||
@@ -457,10 +422,6 @@
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pd_gpu {
|
||||
domain-supply = <&vdd_gpu_s0>;
|
||||
};
|
||||
|
||||
&pinctrl {
|
||||
leds {
|
||||
led_pins: led-pins {
|
||||
@@ -525,8 +486,6 @@
|
||||
bus-width = <8>;
|
||||
mmc-hs400-1_8v;
|
||||
mmc-hs400-enhanced-strobe;
|
||||
no-sdio;
|
||||
no-sd;
|
||||
non-removable;
|
||||
status = "okay";
|
||||
};
|
||||
@@ -536,8 +495,6 @@
|
||||
cap-mmc-highspeed;
|
||||
cap-sd-highspeed;
|
||||
disable-wp;
|
||||
no-sdio;
|
||||
no-mmc;
|
||||
sd-uhs-sdr104;
|
||||
vmmc-supply = <&vcc_3v3_s3>;
|
||||
vqmmc-supply = <&vccio_sd_s0>;
|
||||
@@ -879,8 +836,8 @@
|
||||
};
|
||||
|
||||
&tsadc {
|
||||
rockchip,hw-tshut-mode = <1>; /* tshut mode 0:CRU 1:GPIO */
|
||||
rockchip,hw-tshut-polarity = <0>; /* tshut polarity 0:LOW 1:HIGH */
|
||||
rockchip,hw-tshut-mode = <1>;
|
||||
rockchip,hw-tshut-polarity = <0>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
@@ -898,7 +855,6 @@
|
||||
};
|
||||
|
||||
&u2phy2_host {
|
||||
/* connected to USB hub, which is powered by vcc_5v0 */
|
||||
phy-supply = <&vcc_5v0>;
|
||||
status = "okay";
|
||||
};
|
||||
@@ -941,18 +897,3 @@
|
||||
&usb_host2_xhci {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&vop_mmu {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&vop {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&vp0 {
|
||||
vp0_out_hdmi0: endpoint@ROCKCHIP_VOP2_EP_HDMI0 {
|
||||
reg = <ROCKCHIP_VOP2_EP_HDMI0>;
|
||||
remote-endpoint = <&hdmi0_in_vp0>;
|
||||
};
|
||||
};
|
||||
|
||||
@@ -528,28 +528,25 @@ define Device/radxa_rock-5c
|
||||
DEVICE_VENDOR := Radxa
|
||||
DEVICE_MODEL := ROCK 5C/5C Lite
|
||||
SOC := rk3588s
|
||||
UBOOT_DEVICE_NAME := evb-rk3588
|
||||
IMAGE/sysupgrade.img.gz := boot-common | boot-script | pine64-img | gzip | append-metadata
|
||||
DEVICE_PACKAGES := blkdiscard block-mount kmod-ata-ahci kmod-hwmon-pwmfan kmod-nvme kmod-r8168 kmod-r8125 kmod-hwmon-pwmfan kmod-aic8800u wpad-openssl
|
||||
UBOOT_DEVICE_NAME := rock-5c-rk3588s
|
||||
DEVICE_PACKAGES := kmod-aic8800u wpad-openssl
|
||||
endef
|
||||
TARGET_DEVICES += radxa_rock-5c
|
||||
|
||||
define Device/radxa_zero-3e
|
||||
DEVICE_VENDOR := Radxa
|
||||
DEVICE_MODEL := ZERO 3E
|
||||
SOC := rk3566
|
||||
UBOOT_DEVICE_NAME := evb-rk3566
|
||||
IMAGE/sysupgrade.img.gz := boot-common | boot-script | pine64-img | gzip | append-metadata
|
||||
DEVICE_DTS := rockchip/rk3566-radxa-zero-3e
|
||||
UBOOT_DEVICE_NAME := radxa-zero-3-rk3566
|
||||
endef
|
||||
TARGET_DEVICES += radxa_zero-3e
|
||||
|
||||
define Device/radxa_zero-3w
|
||||
DEVICE_VENDOR := Radxa
|
||||
DEVICE_MODEL := ZERO 3W
|
||||
SOC := rk3566
|
||||
UBOOT_DEVICE_NAME := evb-rk3566
|
||||
DEVICE_DTS := rockchip/rk3566-radxa-zero-3w
|
||||
DEVICE_PACKAGES := kmod-aic8800s wpad-openssl
|
||||
IMAGE/sysupgrade.img.gz := boot-common | boot-script | pine64-img | gzip | append-metadata
|
||||
UBOOT_DEVICE_NAME := radxa-zero-3-rk3566
|
||||
endef
|
||||
TARGET_DEVICES += radxa_zero-3w
|
||||
|
||||
|
||||
@@ -1,444 +0,0 @@
|
||||
From 4294e32111781b3de4d73b944cbd1bc1662a9a7a Mon Sep 17 00:00:00 2001
|
||||
From: Sam Edwards <cfsworks@gmail.com>
|
||||
Date: Wed, 11 Sep 2024 19:50:30 -0700
|
||||
Subject: arm64: dts: rockchip: Split up RK3588's PCIe pinctrls
|
||||
|
||||
These pinctrls manage the low-speed PCIe signals:
|
||||
- CLKREQ#: An output on the RK3588 (both RC or EP modes), used to
|
||||
request that external clock-generation circuitry provide a clock.
|
||||
- PERST#: An input on the RK3588 in EP mode, used to detect a reset
|
||||
signal from the RC. In RC mode, the hardware does not use this signal:
|
||||
Linux itself generates it by putting the pin in GPIO mode.
|
||||
- WAKE#: In EP mode, this is an output; in RC mode, this is an input.
|
||||
|
||||
Each of these signals serves a distinct purpose, and more importantly,
|
||||
PERST# should not be muxed when the RK3588 is in the RC role. Bundling
|
||||
them together in pinctrl groups prevents proper use: indeed, almost none
|
||||
of the current board-specific .dts files make any use of them.
|
||||
(Exception: Rock 5A recently had a patch land that misuses _pins; this
|
||||
patch corrects that.)
|
||||
|
||||
However, on some RK3588 boards, the PCIe 3 controller will indefinitely
|
||||
stall the boot if CLKREQ# is not muxed (details in the next patch).
|
||||
This patch unbundles the signals to allow them to be used.
|
||||
|
||||
Signed-off-by: Sam Edwards <CFSworks@gmail.com>
|
||||
Link: https://lore.kernel.org/r/20240912025034.180233-2-CFSworks@gmail.com
|
||||
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
||||
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk3588-base-pinctrl.dtsi
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3588-base-pinctrl.dtsi
|
||||
@@ -1612,23 +1612,43 @@
|
||||
|
||||
pcie20x1 {
|
||||
/omit-if-no-ref/
|
||||
- pcie20x1m0_pins: pcie20x1m0-pins {
|
||||
+ pcie20x1m0_clkreqn: pcie20x1m0-clkreqn {
|
||||
rockchip,pins =
|
||||
/* pcie20x1_2_clkreqn_m0 */
|
||||
- <3 RK_PC7 4 &pcfg_pull_none>,
|
||||
+ <3 RK_PC7 4 &pcfg_pull_none>;
|
||||
+ };
|
||||
+
|
||||
+ /omit-if-no-ref/
|
||||
+ pcie20x1m0_perstn: pcie20x1m0-perstn {
|
||||
+ rockchip,pins =
|
||||
/* pcie20x1_2_perstn_m0 */
|
||||
- <3 RK_PD1 4 &pcfg_pull_none>,
|
||||
+ <3 RK_PD1 4 &pcfg_pull_none>;
|
||||
+ };
|
||||
+
|
||||
+ /omit-if-no-ref/
|
||||
+ pcie20x1m0_waken: pcie20x1m0-waken {
|
||||
+ rockchip,pins =
|
||||
/* pcie20x1_2_waken_m0 */
|
||||
<3 RK_PD0 4 &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
- pcie20x1m1_pins: pcie20x1m1-pins {
|
||||
+ pcie20x1m1_clkreqn: pcie20x1m1-clkreqn {
|
||||
rockchip,pins =
|
||||
/* pcie20x1_2_clkreqn_m1 */
|
||||
- <4 RK_PB7 4 &pcfg_pull_none>,
|
||||
+ <4 RK_PB7 4 &pcfg_pull_none>;
|
||||
+ };
|
||||
+
|
||||
+ /omit-if-no-ref/
|
||||
+ pcie20x1m1_perstn: pcie20x1m1-perstn {
|
||||
+ rockchip,pins =
|
||||
/* pcie20x1_2_perstn_m1 */
|
||||
- <4 RK_PC1 4 &pcfg_pull_none>,
|
||||
+ <4 RK_PC1 4 &pcfg_pull_none>;
|
||||
+ };
|
||||
+
|
||||
+ /omit-if-no-ref/
|
||||
+ pcie20x1m1_waken: pcie20x1m1-waken {
|
||||
+ rockchip,pins =
|
||||
/* pcie20x1_2_waken_m1 */
|
||||
<4 RK_PC0 4 &pcfg_pull_none>;
|
||||
};
|
||||
@@ -1654,52 +1674,127 @@
|
||||
|
||||
pcie30x1 {
|
||||
/omit-if-no-ref/
|
||||
- pcie30x1m0_pins: pcie30x1m0-pins {
|
||||
+ pcie30x1m0_0_clkreqn: pcie30x1m0-0-clkreqn {
|
||||
rockchip,pins =
|
||||
/* pcie30x1_0_clkreqn_m0 */
|
||||
- <0 RK_PC0 12 &pcfg_pull_none>,
|
||||
+ <0 RK_PC0 12 &pcfg_pull_none>;
|
||||
+ };
|
||||
+
|
||||
+ /omit-if-no-ref/
|
||||
+ pcie30x1m0_0_perstn: pcie30x1m0-0-perstn {
|
||||
+ rockchip,pins =
|
||||
/* pcie30x1_0_perstn_m0 */
|
||||
- <0 RK_PC5 12 &pcfg_pull_none>,
|
||||
+ <0 RK_PC5 12 &pcfg_pull_none>;
|
||||
+ };
|
||||
+
|
||||
+ /omit-if-no-ref/
|
||||
+ pcie30x1m0_0_waken: pcie30x1m0-0-waken {
|
||||
+ rockchip,pins =
|
||||
/* pcie30x1_0_waken_m0 */
|
||||
- <0 RK_PC4 12 &pcfg_pull_none>,
|
||||
+ <0 RK_PC4 12 &pcfg_pull_none>;
|
||||
+ };
|
||||
+
|
||||
+ /omit-if-no-ref/
|
||||
+ pcie30x1m0_1_clkreqn: pcie30x1m0-1-clkreqn {
|
||||
+ rockchip,pins =
|
||||
/* pcie30x1_1_clkreqn_m0 */
|
||||
- <0 RK_PB5 12 &pcfg_pull_none>,
|
||||
+ <0 RK_PB5 12 &pcfg_pull_none>;
|
||||
+ };
|
||||
+
|
||||
+ /omit-if-no-ref/
|
||||
+ pcie30x1m0_1_perstn: pcie30x1m0-1-perstn {
|
||||
+ rockchip,pins =
|
||||
/* pcie30x1_1_perstn_m0 */
|
||||
- <0 RK_PB7 12 &pcfg_pull_none>,
|
||||
+ <0 RK_PB7 12 &pcfg_pull_none>;
|
||||
+ };
|
||||
+
|
||||
+ /omit-if-no-ref/
|
||||
+ pcie30x1m0_1_waken: pcie30x1m0-1-waken {
|
||||
+ rockchip,pins =
|
||||
/* pcie30x1_1_waken_m0 */
|
||||
<0 RK_PB6 12 &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
- pcie30x1m1_pins: pcie30x1m1-pins {
|
||||
+ pcie30x1m1_0_clkreqn: pcie30x1m1-0-clkreqn {
|
||||
rockchip,pins =
|
||||
/* pcie30x1_0_clkreqn_m1 */
|
||||
- <4 RK_PA3 4 &pcfg_pull_none>,
|
||||
+ <4 RK_PA3 4 &pcfg_pull_none>;
|
||||
+ };
|
||||
+
|
||||
+ /omit-if-no-ref/
|
||||
+ pcie30x1m1_0_perstn: pcie30x1m1-0-perstn {
|
||||
+ rockchip,pins =
|
||||
/* pcie30x1_0_perstn_m1 */
|
||||
- <4 RK_PA5 4 &pcfg_pull_none>,
|
||||
+ <4 RK_PA5 4 &pcfg_pull_none>;
|
||||
+ };
|
||||
+
|
||||
+ /omit-if-no-ref/
|
||||
+ pcie30x1m1_0_waken: pcie30x1m1-0-waken {
|
||||
+ rockchip,pins =
|
||||
/* pcie30x1_0_waken_m1 */
|
||||
- <4 RK_PA4 4 &pcfg_pull_none>,
|
||||
+ <4 RK_PA4 4 &pcfg_pull_none>;
|
||||
+ };
|
||||
+
|
||||
+ /omit-if-no-ref/
|
||||
+ pcie30x1m1_1_clkreqn: pcie30x1m1-1-clkreqn {
|
||||
+ rockchip,pins =
|
||||
/* pcie30x1_1_clkreqn_m1 */
|
||||
- <4 RK_PA0 4 &pcfg_pull_none>,
|
||||
+ <4 RK_PA0 4 &pcfg_pull_none>;
|
||||
+ };
|
||||
+
|
||||
+ /omit-if-no-ref/
|
||||
+ pcie30x1m1_1_perstn: pcie30x1m1-1-perstn {
|
||||
+ rockchip,pins =
|
||||
/* pcie30x1_1_perstn_m1 */
|
||||
- <4 RK_PA2 4 &pcfg_pull_none>,
|
||||
+ <4 RK_PA2 4 &pcfg_pull_none>;
|
||||
+ };
|
||||
+
|
||||
+ /omit-if-no-ref/
|
||||
+ pcie30x1m1_1_waken: pcie30x1m1-1-waken {
|
||||
+ rockchip,pins =
|
||||
/* pcie30x1_1_waken_m1 */
|
||||
<4 RK_PA1 4 &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
- pcie30x1m2_pins: pcie30x1m2-pins {
|
||||
+ pcie30x1m2_0_clkreqn: pcie30x1m2-0-clkreqn {
|
||||
rockchip,pins =
|
||||
/* pcie30x1_0_clkreqn_m2 */
|
||||
- <1 RK_PB5 4 &pcfg_pull_none>,
|
||||
+ <1 RK_PB5 4 &pcfg_pull_none>;
|
||||
+ };
|
||||
+
|
||||
+ /omit-if-no-ref/
|
||||
+ pcie30x1m2_0_perstn: pcie30x1m2-0-perstn {
|
||||
+ rockchip,pins =
|
||||
/* pcie30x1_0_perstn_m2 */
|
||||
- <1 RK_PB4 4 &pcfg_pull_none>,
|
||||
+ <1 RK_PB4 4 &pcfg_pull_none>;
|
||||
+ };
|
||||
+
|
||||
+ /omit-if-no-ref/
|
||||
+ pcie30x1m2_0_waken: pcie30x1m2-0-waken {
|
||||
+ rockchip,pins =
|
||||
/* pcie30x1_0_waken_m2 */
|
||||
- <1 RK_PB3 4 &pcfg_pull_none>,
|
||||
+ <1 RK_PB3 4 &pcfg_pull_none>;
|
||||
+ };
|
||||
+
|
||||
+ /omit-if-no-ref/
|
||||
+ pcie30x1m2_1_clkreqn: pcie30x1m2-1-clkreqn {
|
||||
+ rockchip,pins =
|
||||
/* pcie30x1_1_clkreqn_m2 */
|
||||
- <1 RK_PA0 4 &pcfg_pull_none>,
|
||||
+ <1 RK_PA0 4 &pcfg_pull_none>;
|
||||
+ };
|
||||
+
|
||||
+ /omit-if-no-ref/
|
||||
+ pcie30x1m2_1_perstn: pcie30x1m2-1-perstn {
|
||||
+ rockchip,pins =
|
||||
/* pcie30x1_1_perstn_m2 */
|
||||
- <1 RK_PA7 4 &pcfg_pull_none>,
|
||||
+ <1 RK_PA7 4 &pcfg_pull_none>;
|
||||
+ };
|
||||
+
|
||||
+ /omit-if-no-ref/
|
||||
+ pcie30x1m2_1_waken: pcie30x1m2-1-waken {
|
||||
+ rockchip,pins =
|
||||
/* pcie30x1_1_waken_m2 */
|
||||
<1 RK_PA1 4 &pcfg_pull_none>;
|
||||
};
|
||||
@@ -1721,45 +1816,85 @@
|
||||
|
||||
pcie30x2 {
|
||||
/omit-if-no-ref/
|
||||
- pcie30x2m0_pins: pcie30x2m0-pins {
|
||||
+ pcie30x2m0_clkreqn: pcie30x2m0-clkreqn {
|
||||
rockchip,pins =
|
||||
/* pcie30x2_clkreqn_m0 */
|
||||
- <0 RK_PD1 12 &pcfg_pull_none>,
|
||||
+ <0 RK_PD1 12 &pcfg_pull_none>;
|
||||
+ };
|
||||
+
|
||||
+ /omit-if-no-ref/
|
||||
+ pcie30x2m0_perstn: pcie30x2m0-perstn {
|
||||
+ rockchip,pins =
|
||||
/* pcie30x2_perstn_m0 */
|
||||
- <0 RK_PD4 12 &pcfg_pull_none>,
|
||||
+ <0 RK_PD4 12 &pcfg_pull_none>;
|
||||
+ };
|
||||
+
|
||||
+ /omit-if-no-ref/
|
||||
+ pcie30x2m0_waken: pcie30x2m0-waken {
|
||||
+ rockchip,pins =
|
||||
/* pcie30x2_waken_m0 */
|
||||
<0 RK_PD2 12 &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
- pcie30x2m1_pins: pcie30x2m1-pins {
|
||||
+ pcie30x2m1_clkreqn: pcie30x2m1-clkreqn {
|
||||
rockchip,pins =
|
||||
/* pcie30x2_clkreqn_m1 */
|
||||
- <4 RK_PA6 4 &pcfg_pull_none>,
|
||||
+ <4 RK_PA6 4 &pcfg_pull_none>;
|
||||
+ };
|
||||
+
|
||||
+ /omit-if-no-ref/
|
||||
+ pcie30x2m1_perstn: pcie30x2m1-perstn {
|
||||
+ rockchip,pins =
|
||||
/* pcie30x2_perstn_m1 */
|
||||
- <4 RK_PB0 4 &pcfg_pull_none>,
|
||||
+ <4 RK_PB0 4 &pcfg_pull_none>;
|
||||
+ };
|
||||
+
|
||||
+ /omit-if-no-ref/
|
||||
+ pcie30x2m1_waken: pcie30x2m1-waken {
|
||||
+ rockchip,pins =
|
||||
/* pcie30x2_waken_m1 */
|
||||
<4 RK_PA7 4 &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
- pcie30x2m2_pins: pcie30x2m2-pins {
|
||||
+ pcie30x2m2_clkreqn: pcie30x2m2-clkreqn {
|
||||
rockchip,pins =
|
||||
/* pcie30x2_clkreqn_m2 */
|
||||
- <3 RK_PD2 4 &pcfg_pull_none>,
|
||||
+ <3 RK_PD2 4 &pcfg_pull_none>;
|
||||
+ };
|
||||
+
|
||||
+ /omit-if-no-ref/
|
||||
+ pcie30x2m2_perstn: pcie30x2m2-perstn {
|
||||
+ rockchip,pins =
|
||||
/* pcie30x2_perstn_m2 */
|
||||
- <3 RK_PD4 4 &pcfg_pull_none>,
|
||||
+ <3 RK_PD4 4 &pcfg_pull_none>;
|
||||
+ };
|
||||
+
|
||||
+ /omit-if-no-ref/
|
||||
+ pcie30x2m2_waken: pcie30x2m2-waken {
|
||||
+ rockchip,pins =
|
||||
/* pcie30x2_waken_m2 */
|
||||
<3 RK_PD3 4 &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
- pcie30x2m3_pins: pcie30x2m3-pins {
|
||||
+ pcie30x2m3_clkreqn: pcie30x2m3-clkreqn {
|
||||
rockchip,pins =
|
||||
/* pcie30x2_clkreqn_m3 */
|
||||
- <1 RK_PD7 4 &pcfg_pull_none>,
|
||||
+ <1 RK_PD7 4 &pcfg_pull_none>;
|
||||
+ };
|
||||
+
|
||||
+ /omit-if-no-ref/
|
||||
+ pcie30x2m3_perstn: pcie30x2m3-perstn {
|
||||
+ rockchip,pins =
|
||||
/* pcie30x2_perstn_m3 */
|
||||
- <1 RK_PB7 4 &pcfg_pull_none>,
|
||||
+ <1 RK_PB7 4 &pcfg_pull_none>;
|
||||
+ };
|
||||
+
|
||||
+ /omit-if-no-ref/
|
||||
+ pcie30x2m3_waken: pcie30x2m3-waken {
|
||||
+ rockchip,pins =
|
||||
/* pcie30x2_waken_m3 */
|
||||
<1 RK_PB6 4 &pcfg_pull_none>;
|
||||
};
|
||||
@@ -1774,45 +1909,85 @@
|
||||
|
||||
pcie30x4 {
|
||||
/omit-if-no-ref/
|
||||
- pcie30x4m0_pins: pcie30x4m0-pins {
|
||||
+ pcie30x4m0_clkreqn: pcie30x4m0-clkreqn {
|
||||
rockchip,pins =
|
||||
/* pcie30x4_clkreqn_m0 */
|
||||
- <0 RK_PC6 12 &pcfg_pull_none>,
|
||||
+ <0 RK_PC6 12 &pcfg_pull_none>;
|
||||
+ };
|
||||
+
|
||||
+ /omit-if-no-ref/
|
||||
+ pcie30x4m0_perstn: pcie30x4m0-perstn {
|
||||
+ rockchip,pins =
|
||||
/* pcie30x4_perstn_m0 */
|
||||
- <0 RK_PD0 12 &pcfg_pull_none>,
|
||||
+ <0 RK_PD0 12 &pcfg_pull_none>;
|
||||
+ };
|
||||
+
|
||||
+ /omit-if-no-ref/
|
||||
+ pcie30x4m0_waken: pcie30x4m0-waken {
|
||||
+ rockchip,pins =
|
||||
/* pcie30x4_waken_m0 */
|
||||
<0 RK_PC7 12 &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
- pcie30x4m1_pins: pcie30x4m1-pins {
|
||||
+ pcie30x4m1_clkreqn: pcie30x4m1-clkreqn {
|
||||
rockchip,pins =
|
||||
/* pcie30x4_clkreqn_m1 */
|
||||
- <4 RK_PB4 4 &pcfg_pull_none>,
|
||||
+ <4 RK_PB4 4 &pcfg_pull_none>;
|
||||
+ };
|
||||
+
|
||||
+ /omit-if-no-ref/
|
||||
+ pcie30x4m1_perstn: pcie30x4m1-perstn {
|
||||
+ rockchip,pins =
|
||||
/* pcie30x4_perstn_m1 */
|
||||
- <4 RK_PB6 4 &pcfg_pull_none>,
|
||||
+ <4 RK_PB6 4 &pcfg_pull_none>;
|
||||
+ };
|
||||
+
|
||||
+ /omit-if-no-ref/
|
||||
+ pcie30x4m1_waken: pcie30x4m1-waken {
|
||||
+ rockchip,pins =
|
||||
/* pcie30x4_waken_m1 */
|
||||
<4 RK_PB5 4 &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
- pcie30x4m2_pins: pcie30x4m2-pins {
|
||||
+ pcie30x4m2_clkreqn: pcie30x4m2-clkreqn {
|
||||
rockchip,pins =
|
||||
/* pcie30x4_clkreqn_m2 */
|
||||
- <3 RK_PC4 4 &pcfg_pull_none>,
|
||||
+ <3 RK_PC4 4 &pcfg_pull_none>;
|
||||
+ };
|
||||
+
|
||||
+ /omit-if-no-ref/
|
||||
+ pcie30x4m2_perstn: pcie30x4m2-perstn {
|
||||
+ rockchip,pins =
|
||||
/* pcie30x4_perstn_m2 */
|
||||
- <3 RK_PC6 4 &pcfg_pull_none>,
|
||||
+ <3 RK_PC6 4 &pcfg_pull_none>;
|
||||
+ };
|
||||
+
|
||||
+ /omit-if-no-ref/
|
||||
+ pcie30x4m2_waken: pcie30x4m2-waken {
|
||||
+ rockchip,pins =
|
||||
/* pcie30x4_waken_m2 */
|
||||
<3 RK_PC5 4 &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
- pcie30x4m3_pins: pcie30x4m3-pins {
|
||||
+ pcie30x4m3_clkreqn: pcie30x4m3-clkreqn {
|
||||
rockchip,pins =
|
||||
/* pcie30x4_clkreqn_m3 */
|
||||
- <1 RK_PB0 4 &pcfg_pull_none>,
|
||||
+ <1 RK_PB0 4 &pcfg_pull_none>;
|
||||
+ };
|
||||
+
|
||||
+ /omit-if-no-ref/
|
||||
+ pcie30x4m3_perstn: pcie30x4m3-perstn {
|
||||
+ rockchip,pins =
|
||||
/* pcie30x4_perstn_m3 */
|
||||
- <1 RK_PB2 4 &pcfg_pull_none>,
|
||||
+ <1 RK_PB2 4 &pcfg_pull_none>;
|
||||
+ };
|
||||
+
|
||||
+ /omit-if-no-ref/
|
||||
+ pcie30x4m3_waken: pcie30x4m3-waken {
|
||||
+ rockchip,pins =
|
||||
/* pcie30x4_waken_m3 */
|
||||
<1 RK_PB1 4 &pcfg_pull_none>;
|
||||
};
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts
|
||||
@@ -310,7 +310,7 @@
|
||||
};
|
||||
|
||||
&pcie2x1l2 {
|
||||
- pinctrl-0 = <&pcie20x1m0_pins>;
|
||||
+ pinctrl-0 = <&pcie2_reset>, <&pcie20x1m0_clkreqn>, <&pcie20x1m0_waken>;
|
||||
pinctrl-names = "default";
|
||||
reset-gpios = <&gpio3 RK_PD1 GPIO_ACTIVE_HIGH>;
|
||||
vpcie3v3-supply = <&vcc3v3_wf>;
|
||||
@@ -328,6 +328,10 @@
|
||||
pow_en: pow-en {
|
||||
rockchip,pins = <0 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
+
|
||||
+ pcie2_reset: pcie2-reset {
|
||||
+ rockchip,pins = <3 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
+ };
|
||||
};
|
||||
|
||||
power {
|
||||
@@ -1,61 +0,0 @@
|
||||
From d7bb71e69f58c1b3665a9f926bf8d3855111bf8e Mon Sep 17 00:00:00 2001
|
||||
From: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
|
||||
Date: Sat, 19 Oct 2024 13:12:10 +0300
|
||||
Subject: arm64: dts: rockchip: Add HDMI0 node to rk3588
|
||||
|
||||
Add support for the HDMI0 output port found on RK3588 SoC.
|
||||
|
||||
Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
|
||||
Link: https://lore.kernel.org/r/20241019-rk3588-hdmi0-dt-v2-1-466cd80e8ff9@collabora.com
|
||||
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
||||
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
|
||||
@@ -1369,6 +1369,47 @@
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
+ hdmi0: hdmi@fde80000 {
|
||||
+ compatible = "rockchip,rk3588-dw-hdmi-qp";
|
||||
+ reg = <0x0 0xfde80000 0x0 0x20000>;
|
||||
+ clocks = <&cru PCLK_HDMITX0>,
|
||||
+ <&cru CLK_HDMITX0_EARC>,
|
||||
+ <&cru CLK_HDMITX0_REF>,
|
||||
+ <&cru MCLK_I2S5_8CH_TX>,
|
||||
+ <&cru CLK_HDMIHDP0>,
|
||||
+ <&cru HCLK_VO1>;
|
||||
+ clock-names = "pclk", "earc", "ref", "aud", "hdp", "hclk_vo1";
|
||||
+ interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH 0>,
|
||||
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH 0>,
|
||||
+ <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH 0>,
|
||||
+ <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH 0>,
|
||||
+ <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
+ interrupt-names = "avp", "cec", "earc", "main", "hpd";
|
||||
+ phys = <&hdptxphy_hdmi0>;
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&hdmim0_tx0_cec &hdmim0_tx0_hpd
|
||||
+ &hdmim0_tx0_scl &hdmim0_tx0_sda>;
|
||||
+ power-domains = <&power RK3588_PD_VO1>;
|
||||
+ resets = <&cru SRST_HDMITX0_REF>, <&cru SRST_HDMIHDP0>;
|
||||
+ reset-names = "ref", "hdp";
|
||||
+ rockchip,grf = <&sys_grf>;
|
||||
+ rockchip,vo-grf = <&vo1_grf>;
|
||||
+ status = "disabled";
|
||||
+
|
||||
+ ports {
|
||||
+ #address-cells = <1>;
|
||||
+ #size-cells = <0>;
|
||||
+
|
||||
+ hdmi0_in: port@0 {
|
||||
+ reg = <0>;
|
||||
+ };
|
||||
+
|
||||
+ hdmi0_out: port@1 {
|
||||
+ reg = <1>;
|
||||
+ };
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
qos_gpu_m0: qos@fdf35000 {
|
||||
compatible = "rockchip,rk3588-qos", "syscon";
|
||||
reg = <0x0 0xfdf35000 0x0 0x20>;
|
||||
@@ -1,51 +0,0 @@
|
||||
From 33b561eb66f1e271f2899e103c857d20425076f4 Mon Sep 17 00:00:00 2001
|
||||
From: Dragan Simic <dsimic@manjaro.org>
|
||||
Date: Wed, 8 Jan 2025 05:26:45 +0100
|
||||
Subject: arm64: dts: rockchip: Use "dma-noncoherent" in base RK3588 SoC dtsi
|
||||
|
||||
The preferred way to denote hardware with non-coherent DMA is to use the
|
||||
"dma-noncoherent" DT property, at both the GIC redistributor and the GIC ITS
|
||||
levels, [1] instead of relying on the compatibles to handle hardware errata,
|
||||
in this case the Rockchip 3588001 errata. [2]
|
||||
|
||||
Let's have the preferred way employed in the base Rockchip RK3588 SoC dtsi,
|
||||
which also goes along with adding initial support for the Rockchip RK3582 SoC
|
||||
variant, with its separate compatible. [2][3]
|
||||
|
||||
[1] Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.yaml
|
||||
[2] https://lore.kernel.org/linux-rockchip/86msgoozqa.wl-maz@kernel.org/
|
||||
[3] https://lore.kernel.org/linux-rockchip/20241222030355.2246-4-naoki@radxa.com/
|
||||
|
||||
Cc: Marc Zyngier <maz@kernel.org>
|
||||
Cc: FUKAUMI Naoki <naoki@radxa.com>
|
||||
Acked-by: Marc Zyngier <maz@kernel.org>
|
||||
Signed-off-by: Dragan Simic <dsimic@manjaro.org>
|
||||
Link: https://lore.kernel.org/r/fa1a672dae3644bb3caa58f03216d0ca349db88b.1736279094.git.dsimic@manjaro.org
|
||||
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
||||
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
|
||||
@@ -2020,6 +2020,7 @@
|
||||
<0x0 0xfe680000 0 0x100000>; /* GICR */
|
||||
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
interrupt-controller;
|
||||
+ dma-noncoherent;
|
||||
mbi-alias = <0x0 0xfe610000>;
|
||||
mbi-ranges = <424 56>;
|
||||
msi-controller;
|
||||
@@ -2031,6 +2032,7 @@
|
||||
its0: msi-controller@fe640000 {
|
||||
compatible = "arm,gic-v3-its";
|
||||
reg = <0x0 0xfe640000 0x0 0x20000>;
|
||||
+ dma-noncoherent;
|
||||
msi-controller;
|
||||
#msi-cells = <1>;
|
||||
};
|
||||
@@ -2038,6 +2040,7 @@
|
||||
its1: msi-controller@fe660000 {
|
||||
compatible = "arm,gic-v3-its";
|
||||
reg = <0x0 0xfe660000 0x0 0x20000>;
|
||||
+ dma-noncoherent;
|
||||
msi-controller;
|
||||
#msi-cells = <1>;
|
||||
};
|
||||
@@ -1,28 +0,0 @@
|
||||
From d0f17738778c12be629ba77ff00c43c3e9eb8428 Mon Sep 17 00:00:00 2001
|
||||
From: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
|
||||
Date: Tue, 4 Feb 2025 14:40:07 +0200
|
||||
Subject: arm64: dts: rockchip: Enable HDMI0 PHY clk provider on RK3588
|
||||
|
||||
Since commit c4b09c562086 ("phy: phy-rockchip-samsung-hdptx: Add clock
|
||||
provider support"), the HDMI PHY PLL can be used as an alternative and
|
||||
more accurate pixel clock source for VOP2 to improve display modes
|
||||
handling on RK3588 SoC.
|
||||
|
||||
Add the missing #clock-cells property to allow using the clock provider
|
||||
functionality of HDMI0 PHY.
|
||||
|
||||
Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
|
||||
Tested-by: FUKAUMI Naoki <naoki@radxa.com>
|
||||
Link: https://lore.kernel.org/r/20250204-vop2-hdmi0-disp-modes-v3-4-d71c6a196e58@collabora.com
|
||||
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
||||
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
|
||||
@@ -2813,6 +2813,7 @@
|
||||
reg = <0x0 0xfed60000 0x0 0x2000>;
|
||||
clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>, <&cru PCLK_HDPTX0>;
|
||||
clock-names = "ref", "apb";
|
||||
+ #clock-cells = <0>;
|
||||
#phy-cells = <0>;
|
||||
resets = <&cru SRST_HDPTX0>, <&cru SRST_P_HDPTX0>,
|
||||
<&cru SRST_HDPTX0_INIT>, <&cru SRST_HDPTX0_CMN>,
|
||||
@@ -1,38 +0,0 @@
|
||||
From eb4262203d7d85eb7b6f2696816db272e41f5464 Mon Sep 17 00:00:00 2001
|
||||
From: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
|
||||
Date: Tue, 4 Feb 2025 14:40:08 +0200
|
||||
Subject: arm64: dts: rockchip: Add HDMI0 PHY PLL clock source to VOP2 on
|
||||
RK3588
|
||||
|
||||
VOP2 on RK3588 is able to use the HDMI PHY PLL as an alternative and
|
||||
more accurate pixel clock source to improve handling of display modes up
|
||||
to 4K@60Hz on video ports 0, 1 and 2.
|
||||
|
||||
For now only HDMI0 output is supported, hence add the related PLL clock.
|
||||
|
||||
Tested-by: FUKAUMI Naoki <naoki@radxa.com>
|
||||
Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
|
||||
Link: https://lore.kernel.org/r/20250204-vop2-hdmi0-disp-modes-v3-5-d71c6a196e58@collabora.com
|
||||
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
||||
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
|
||||
@@ -1261,14 +1261,16 @@
|
||||
<&cru DCLK_VOP1>,
|
||||
<&cru DCLK_VOP2>,
|
||||
<&cru DCLK_VOP3>,
|
||||
- <&cru PCLK_VOP_ROOT>;
|
||||
+ <&cru PCLK_VOP_ROOT>,
|
||||
+ <&hdptxphy_hdmi0>;
|
||||
clock-names = "aclk",
|
||||
"hclk",
|
||||
"dclk_vp0",
|
||||
"dclk_vp1",
|
||||
"dclk_vp2",
|
||||
"dclk_vp3",
|
||||
- "pclk_vop";
|
||||
+ "pclk_vop",
|
||||
+ "pll_hdmiphy0";
|
||||
iommus = <&vop_mmu>;
|
||||
power-domains = <&power RK3588_PD_VOP>;
|
||||
rockchip,grf = <&sys_grf>;
|
||||
@@ -1,44 +0,0 @@
|
||||
From 2efdb041019fd6c58abefba3eb6fdc4d659e576c Mon Sep 17 00:00:00 2001
|
||||
From: Damon Ding <damon.ding@rock-chips.com>
|
||||
Date: Thu, 6 Feb 2025 11:03:30 +0800
|
||||
Subject: arm64: dts: rockchip: Fix label name of hdptxphy for RK3588
|
||||
|
||||
The hdptxphy is a combo transmit-PHY for HDMI2.1 TMDS Link, FRL Link, DP
|
||||
and eDP Link. Therefore, it is better to name it hdptxphy0 other than
|
||||
hdptxphy_hdmi0, which will be referenced by both hdmi0 and edp0 nodes.
|
||||
|
||||
Signed-off-by: Damon Ding <damon.ding@rock-chips.com>
|
||||
Link: https://lore.kernel.org/r/20250206030330.680424-3-damon.ding@rock-chips.com
|
||||
[added armsom-sige7, where hdmi-support was added recently and also
|
||||
the hdptxphy0-as-dclk source I just added]
|
||||
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
||||
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
|
||||
@@ -1262,7 +1262,7 @@
|
||||
<&cru DCLK_VOP2>,
|
||||
<&cru DCLK_VOP3>,
|
||||
<&cru PCLK_VOP_ROOT>,
|
||||
- <&hdptxphy_hdmi0>;
|
||||
+ <&hdptxphy0>;
|
||||
clock-names = "aclk",
|
||||
"hclk",
|
||||
"dclk_vp0",
|
||||
@@ -1387,7 +1387,7 @@
|
||||
<GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH 0>,
|
||||
<GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
interrupt-names = "avp", "cec", "earc", "main", "hpd";
|
||||
- phys = <&hdptxphy_hdmi0>;
|
||||
+ phys = <&hdptxphy0>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&hdmim0_tx0_cec &hdmim0_tx0_hpd
|
||||
&hdmim0_tx0_scl &hdmim0_tx0_sda>;
|
||||
@@ -2810,7 +2810,7 @@
|
||||
#dma-cells = <1>;
|
||||
};
|
||||
|
||||
- hdptxphy_hdmi0: phy@fed60000 {
|
||||
+ hdptxphy0: phy@fed60000 {
|
||||
compatible = "rockchip,rk3588-hdptx-phy";
|
||||
reg = <0x0 0xfed60000 0x0 0x2000>;
|
||||
clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>, <&cru PCLK_HDPTX0>;
|
||||
@@ -1,52 +0,0 @@
|
||||
From ea97212a0f66b7bd71c23c12f781f1770dd6fcff Mon Sep 17 00:00:00 2001
|
||||
From: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
|
||||
Date: Wed, 11 Dec 2024 01:06:15 +0200
|
||||
Subject: arm64: dts: rockchip: Add PHY node for HDMI1 TX port on RK3588
|
||||
|
||||
In preparation to enable the second HDMI output port found on RK3588
|
||||
SoC, add the related PHY node. This requires a GRF, hence add the
|
||||
dependent node as well.
|
||||
|
||||
Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
|
||||
Tested-by: Jagan Teki <jagan@edgeble.ai> # edgeble-6tops-modules
|
||||
Tested-by: Alexandre ARNOUD <aarnoud@me.com>
|
||||
Link: https://lore.kernel.org/r/20241211-rk3588-hdmi1-v2-2-02cdca22ff68@collabora.com
|
||||
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
||||
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk3588-extra.dtsi
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3588-extra.dtsi
|
||||
@@ -67,6 +67,11 @@
|
||||
};
|
||||
};
|
||||
|
||||
+ hdptxphy1_grf: syscon@fd5e4000 {
|
||||
+ compatible = "rockchip,rk3588-hdptxphy-grf", "syscon";
|
||||
+ reg = <0x0 0xfd5e4000 0x0 0x100>;
|
||||
+ };
|
||||
+
|
||||
i2s8_8ch: i2s@fddc8000 {
|
||||
compatible = "rockchip,rk3588-i2s-tdm";
|
||||
reg = <0x0 0xfddc8000 0x0 0x1000>;
|
||||
@@ -395,6 +400,22 @@
|
||||
};
|
||||
};
|
||||
|
||||
+ hdptxphy1: phy@fed70000 {
|
||||
+ compatible = "rockchip,rk3588-hdptx-phy";
|
||||
+ reg = <0x0 0xfed70000 0x0 0x2000>;
|
||||
+ clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>, <&cru PCLK_HDPTX1>;
|
||||
+ clock-names = "ref", "apb";
|
||||
+ #phy-cells = <0>;
|
||||
+ resets = <&cru SRST_HDPTX1>, <&cru SRST_P_HDPTX1>,
|
||||
+ <&cru SRST_HDPTX1_INIT>, <&cru SRST_HDPTX1_CMN>,
|
||||
+ <&cru SRST_HDPTX1_LANE>, <&cru SRST_HDPTX1_ROPLL>,
|
||||
+ <&cru SRST_HDPTX1_LCPLL>;
|
||||
+ reset-names = "phy", "apb", "init", "cmn", "lane", "ropll",
|
||||
+ "lcpll";
|
||||
+ rockchip,grf = <&hdptxphy1_grf>;
|
||||
+ status = "disabled";
|
||||
+ };
|
||||
+
|
||||
usbdp_phy1: phy@fed90000 {
|
||||
compatible = "rockchip,rk3588-usbdp-phy";
|
||||
reg = <0x0 0xfed90000 0x0 0x10000>;
|
||||
@@ -1,63 +0,0 @@
|
||||
From bed6964e779b5853de042da14320edf9f79506fe Mon Sep 17 00:00:00 2001
|
||||
From: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
|
||||
Date: Wed, 11 Dec 2024 01:06:16 +0200
|
||||
Subject: arm64: dts: rockchip: Add HDMI1 node on RK3588
|
||||
|
||||
Add support for the second HDMI TX port found on RK3588 SoC.
|
||||
|
||||
Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
|
||||
Tested-by: Jagan Teki <jagan@edgeble.ai> # edgeble-6tops-modules
|
||||
Tested-by: Alexandre ARNOUD <aarnoud@me.com>
|
||||
Link: https://lore.kernel.org/r/20241211-rk3588-hdmi1-v2-3-02cdca22ff68@collabora.com
|
||||
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
||||
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk3588-extra.dtsi
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3588-extra.dtsi
|
||||
@@ -140,6 +140,47 @@
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
+ hdmi1: hdmi@fdea0000 {
|
||||
+ compatible = "rockchip,rk3588-dw-hdmi-qp";
|
||||
+ reg = <0x0 0xfdea0000 0x0 0x20000>;
|
||||
+ clocks = <&cru PCLK_HDMITX1>,
|
||||
+ <&cru CLK_HDMITX1_EARC>,
|
||||
+ <&cru CLK_HDMITX1_REF>,
|
||||
+ <&cru MCLK_I2S6_8CH_TX>,
|
||||
+ <&cru CLK_HDMIHDP1>,
|
||||
+ <&cru HCLK_VO1>;
|
||||
+ clock-names = "pclk", "earc", "ref", "aud", "hdp", "hclk_vo1";
|
||||
+ interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH 0>,
|
||||
+ <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH 0>,
|
||||
+ <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH 0>,
|
||||
+ <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH 0>,
|
||||
+ <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
+ interrupt-names = "avp", "cec", "earc", "main", "hpd";
|
||||
+ phys = <&hdptxphy1>;
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&hdmim2_tx1_cec &hdmim0_tx1_hpd
|
||||
+ &hdmim1_tx1_scl &hdmim1_tx1_sda>;
|
||||
+ power-domains = <&power RK3588_PD_VO1>;
|
||||
+ resets = <&cru SRST_HDMITX1_REF>, <&cru SRST_HDMIHDP1>;
|
||||
+ reset-names = "ref", "hdp";
|
||||
+ rockchip,grf = <&sys_grf>;
|
||||
+ rockchip,vo-grf = <&vo1_grf>;
|
||||
+ status = "disabled";
|
||||
+
|
||||
+ ports {
|
||||
+ #address-cells = <1>;
|
||||
+ #size-cells = <0>;
|
||||
+
|
||||
+ hdmi1_in: port@0 {
|
||||
+ reg = <0>;
|
||||
+ };
|
||||
+
|
||||
+ hdmi1_out: port@1 {
|
||||
+ reg = <1>;
|
||||
+ };
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
pcie3x4: pcie@fe150000 {
|
||||
compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie";
|
||||
#address-cells = <3>;
|
||||
@@ -1,27 +0,0 @@
|
||||
From aadaa27956e3430217d9e6b8af5880e39b05b961 Mon Sep 17 00:00:00 2001
|
||||
From: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
|
||||
Date: Sun, 23 Feb 2025 11:31:39 +0200
|
||||
Subject: arm64: dts: rockchip: Enable HDMI1 PHY clk provider on RK3588
|
||||
|
||||
Since commit c4b09c562086 ("phy: phy-rockchip-samsung-hdptx: Add clock
|
||||
provider support"), the HDMI PHY PLL can be used as an alternative and
|
||||
more accurate pixel clock source for VOP2 to improve display modes
|
||||
handling on RK3588 SoC.
|
||||
|
||||
Add the missing #clock-cells property to allow using the clock provider
|
||||
functionality of HDMI1 PHY.
|
||||
|
||||
Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
|
||||
Link: https://lore.kernel.org/r/20250223-vop2-hdmi1-disp-modes-v2-3-f4cec5e06fbe@collabora.com
|
||||
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
||||
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk3588-extra.dtsi
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3588-extra.dtsi
|
||||
@@ -446,6 +446,7 @@
|
||||
reg = <0x0 0xfed70000 0x0 0x2000>;
|
||||
clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>, <&cru PCLK_HDPTX1>;
|
||||
clock-names = "ref", "apb";
|
||||
+ #clock-cells = <0>;
|
||||
#phy-cells = <0>;
|
||||
resets = <&cru SRST_HDPTX1>, <&cru SRST_P_HDPTX1>,
|
||||
<&cru SRST_HDPTX1_INIT>, <&cru SRST_HDPTX1_CMN>,
|
||||
@@ -1,48 +0,0 @@
|
||||
From b2e668a60ed866ba960acb5310d1fb6bf81d154f Mon Sep 17 00:00:00 2001
|
||||
From: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
|
||||
Date: Sun, 23 Feb 2025 11:31:40 +0200
|
||||
Subject: arm64: dts: rockchip: Add HDMI1 PHY PLL clock source to VOP2 on
|
||||
RK3588
|
||||
|
||||
VOP2 on RK3588 is able to use the HDMI PHY PLL as an alternative and
|
||||
more accurate pixel clock source to improve handling of display modes up
|
||||
to 4K@60Hz on video ports 0, 1 and 2.
|
||||
|
||||
The HDMI1 PHY PLL clock source cannot be added directly to vop node in
|
||||
rk3588-base.dtsi, along with the HDMI0 related one, because HDMI1 is an
|
||||
optional feature and its PHY node belongs to a separate (extra) DT file.
|
||||
|
||||
Therefore, add the HDMI1 PHY PLL clock source to VOP2 by overwriting its
|
||||
clocks & clock-names properties in the extra DT file.
|
||||
|
||||
Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
|
||||
Link: https://lore.kernel.org/r/20250223-vop2-hdmi1-disp-modes-v2-4-f4cec5e06fbe@collabora.com
|
||||
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
||||
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk3588-extra.dtsi
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3588-extra.dtsi
|
||||
@@ -509,3 +509,24 @@
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
+
|
||||
+&vop {
|
||||
+ clocks = <&cru ACLK_VOP>,
|
||||
+ <&cru HCLK_VOP>,
|
||||
+ <&cru DCLK_VOP0>,
|
||||
+ <&cru DCLK_VOP1>,
|
||||
+ <&cru DCLK_VOP2>,
|
||||
+ <&cru DCLK_VOP3>,
|
||||
+ <&cru PCLK_VOP_ROOT>,
|
||||
+ <&hdptxphy0>,
|
||||
+ <&hdptxphy1>;
|
||||
+ clock-names = "aclk",
|
||||
+ "hclk",
|
||||
+ "dclk_vp0",
|
||||
+ "dclk_vp1",
|
||||
+ "dclk_vp2",
|
||||
+ "dclk_vp3",
|
||||
+ "pclk_vop",
|
||||
+ "pll_hdmiphy0",
|
||||
+ "pll_hdmiphy1";
|
||||
+};
|
||||
@@ -1,34 +0,0 @@
|
||||
From 6ee0b9ad3995ee5fa229035c69013b7dd0d3634b Mon Sep 17 00:00:00 2001
|
||||
From: Nicolas Frattaroli <nicolas.frattaroli@collabora.com>
|
||||
Date: Tue, 4 Feb 2025 16:35:51 +0100
|
||||
Subject: [PATCH] arm64: dts: rockchip: Add rng node to RK3588
|
||||
|
||||
Add the RK3588's standalone hardware random number generator node to its
|
||||
device tree, and enable it.
|
||||
|
||||
Signed-off-by: Nicolas Frattaroli <nicolas.frattaroli@collabora.com>
|
||||
Link: https://lore.kernel.org/r/20250204-rk3588-trng-submission-v2-6-608172b6fd91@collabora.com
|
||||
[changed reset-id to its numeric value while the constant makes its
|
||||
way through the crypto tree]
|
||||
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
||||
---
|
||||
arch/arm64/boot/dts/rockchip/rk3588-base.dtsi | 8 ++++++++
|
||||
1 file changed, 8 insertions(+)
|
||||
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
|
||||
@@ -1921,6 +1921,14 @@
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
+ rng@fe378000 {
|
||||
+ compatible = "rockchip,rk3588-rng";
|
||||
+ reg = <0x0 0xfe378000 0x0 0x200>;
|
||||
+ interrupts = <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
+ clocks = <&scmi_clk SCMI_HCLK_SECURE_NS>;
|
||||
+ resets = <&scmi_reset 48>;
|
||||
+ };
|
||||
+
|
||||
i2s0_8ch: i2s@fe470000 {
|
||||
compatible = "rockchip,rk3588-i2s-tdm";
|
||||
reg = <0x0 0xfe470000 0x0 0x1000>;
|
||||
@@ -1,91 +0,0 @@
|
||||
From b8c6c136971c0e9750eec89f367529b2854d3a3c Mon Sep 17 00:00:00 2001
|
||||
From: Detlev Casanova <detlev.casanova@collabora.com>
|
||||
Date: Mon, 17 Feb 2025 16:47:41 -0500
|
||||
Subject: arm64: dts: rockchip: Add HDMI audio outputs for rk3588
|
||||
|
||||
For hdmi0_sound, use the simple-audio-card driver with the hdmi0 QP node
|
||||
as CODEC and the i2s5 device as CPU.
|
||||
|
||||
Similarly for hdmi1_sound, the CODEC is the hdmi1 node and the CPU is
|
||||
i2s6, but only added in the rk3588-extra.dtsi device tree as the second
|
||||
TX HDMI port is not available on base versions of the SoC.
|
||||
|
||||
The simple-audio-card,mclk-fs value is set to 128 as it is done in
|
||||
the downstream driver.
|
||||
|
||||
The #sound-dai-cells value is set to 0 in the hdmi0 and hdmi1 nodes so
|
||||
that they can be used as audio codec nodes.
|
||||
|
||||
Tested-by: Quentin Schulz <quentin.schulz@cherry.de> # RK3588 Tiger Haikou
|
||||
Signed-off-by: Detlev Casanova <detlev.casanova@collabora.com>
|
||||
Fixes: 419d1918105e ("ASoC: simple-card-utils: use __free(device_node) for device node")
|
||||
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
|
||||
Link: https://lore.kernel.org/r/20250217215641.372723-3-detlev.casanova@collabora.com
|
||||
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
||||
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
|
||||
@@ -382,6 +382,22 @@
|
||||
};
|
||||
};
|
||||
|
||||
+ hdmi0_sound: hdmi0-sound {
|
||||
+ compatible = "simple-audio-card";
|
||||
+ simple-audio-card,format = "i2s";
|
||||
+ simple-audio-card,mclk-fs = <128>;
|
||||
+ simple-audio-card,name = "hdmi0";
|
||||
+ status = "disabled";
|
||||
+
|
||||
+ simple-audio-card,codec {
|
||||
+ sound-dai = <&hdmi0>;
|
||||
+ };
|
||||
+
|
||||
+ simple-audio-card,cpu {
|
||||
+ sound-dai = <&i2s5_8ch>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
pmu-a55 {
|
||||
compatible = "arm,cortex-a55-pmu";
|
||||
interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_partition0>;
|
||||
@@ -1396,6 +1412,7 @@
|
||||
reset-names = "ref", "hdp";
|
||||
rockchip,grf = <&sys_grf>;
|
||||
rockchip,vo-grf = <&vo1_grf>;
|
||||
+ #sound-dai-cells = <0>;
|
||||
status = "disabled";
|
||||
|
||||
ports {
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk3588-extra.dtsi
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3588-extra.dtsi
|
||||
@@ -7,6 +7,22 @@
|
||||
#include "rk3588-extra-pinctrl.dtsi"
|
||||
|
||||
/ {
|
||||
+ hdmi1_sound: hdmi1-sound {
|
||||
+ compatible = "simple-audio-card";
|
||||
+ simple-audio-card,format = "i2s";
|
||||
+ simple-audio-card,mclk-fs = <128>;
|
||||
+ simple-audio-card,name = "hdmi1";
|
||||
+ status = "disabled";
|
||||
+
|
||||
+ simple-audio-card,codec {
|
||||
+ sound-dai = <&hdmi1>;
|
||||
+ };
|
||||
+
|
||||
+ simple-audio-card,cpu {
|
||||
+ sound-dai = <&i2s6_8ch>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
usb_host1_xhci: usb@fc400000 {
|
||||
compatible = "rockchip,rk3588-dwc3", "snps,dwc3";
|
||||
reg = <0x0 0xfc400000 0x0 0x400000>;
|
||||
@@ -165,6 +181,7 @@
|
||||
reset-names = "ref", "hdp";
|
||||
rockchip,grf = <&sys_grf>;
|
||||
rockchip,vo-grf = <&vo1_grf>;
|
||||
+ #sound-dai-cells = <0>;
|
||||
status = "disabled";
|
||||
|
||||
ports {
|
||||
@@ -1,46 +0,0 @@
|
||||
From f94500eb7328b35f3d0927635b1aba26c85ea4b0 Mon Sep 17 00:00:00 2001
|
||||
From: Sebastian Reichel <sebastian.reichel@collabora.com>
|
||||
Date: Thu, 20 Feb 2025 19:58:11 +0100
|
||||
Subject: arm64: dts: rockchip: Add GPU power domain regulator dependency for
|
||||
RK3588
|
||||
MIME-Version: 1.0
|
||||
Content-Type: text/plain; charset=UTF-8
|
||||
Content-Transfer-Encoding: 8bit
|
||||
|
||||
Enabling the GPU power domain requires that the GPU regulator is
|
||||
enabled. The regulator is enabled at boot time, but gets disabled
|
||||
automatically when there are no users.
|
||||
|
||||
This means the system might run into a failure state hanging the
|
||||
whole system for the following use cases:
|
||||
|
||||
* if the GPU driver is being probed late (e.g. build as a
|
||||
module and firmware is not in initramfs), the regulator
|
||||
might already have been disabled. In that case the power
|
||||
domain is enabled before the regulator.
|
||||
* unbinding the GPU driver will disable the PM domain and
|
||||
the regulator. When the driver is bound again, the PM
|
||||
domain will be enabled before the regulator and error
|
||||
appears.
|
||||
|
||||
Avoid this by adding an explicit regulator dependency to the
|
||||
power domain.
|
||||
|
||||
Tested-by: Heiko Stuebner <heiko@sntech.de>
|
||||
Reported-by: Adrián Martínez Larumbe <adrian.larumbe@collabora.com>
|
||||
Tested-by: Adrian Larumbe <adrian.larumbe@collabora.com> # On Rock 5B
|
||||
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
|
||||
Link: https://lore.kernel.org/r/20250220-rk3588-gpu-pwr-domain-regulator-v6-8-a4f9c24e5b81@kernel.org
|
||||
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
||||
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
|
||||
@@ -880,7 +880,7 @@
|
||||
};
|
||||
};
|
||||
/* These power domains are grouped by VD_GPU */
|
||||
- power-domain@RK3588_PD_GPU {
|
||||
+ pd_gpu: power-domain@RK3588_PD_GPU {
|
||||
reg = <RK3588_PD_GPU>;
|
||||
clocks = <&cru CLK_GPU>,
|
||||
<&cru CLK_GPU_COREGROUP>,
|
||||
@@ -1,25 +0,0 @@
|
||||
From 55a43c346d24434e46ef7fcc09a9df8179c346e4 Mon Sep 17 00:00:00 2001
|
||||
From: Heiko Stuebner <heiko@sntech.de>
|
||||
Date: Sun, 16 Feb 2025 16:27:42 +0100
|
||||
Subject: [PATCH] arm64: dts: rockchip: change rng reset id back to its
|
||||
constant value
|
||||
|
||||
With the binding header now providing the SCMI_SRST_H_TRNG_NS constant,
|
||||
switch back to it from the temporary numeric value.
|
||||
|
||||
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
||||
---
|
||||
arch/arm64/boot/dts/rockchip/rk3588-base.dtsi | 2 +-
|
||||
1 file changed, 1 insertion(+), 1 deletion(-)
|
||||
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
|
||||
@@ -1943,7 +1943,7 @@
|
||||
reg = <0x0 0xfe378000 0x0 0x200>;
|
||||
interrupts = <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
clocks = <&scmi_clk SCMI_HCLK_SECURE_NS>;
|
||||
- resets = <&scmi_reset 48>;
|
||||
+ resets = <&scmi_reset SCMI_SRST_H_TRNG_NS>;
|
||||
};
|
||||
|
||||
i2s0_8ch: i2s@fe470000 {
|
||||
@@ -1,88 +0,0 @@
|
||||
From 0327238991ba2d1de25e1116b1c064f433e45b8d Mon Sep 17 00:00:00 2001
|
||||
From: Shreeya Patel <shreeya.patel@collabora.com>
|
||||
Date: Fri, 7 Mar 2025 12:18:56 +0300
|
||||
Subject: arm64: dts: rockchip: Add device tree support for HDMI RX Controller
|
||||
|
||||
Add device tree support for Synopsys DesignWare HDMI RX
|
||||
Controller.
|
||||
|
||||
Reviewed-by: Dmitry Osipenko <dmitry.osipenko@collabora.com>
|
||||
Tested-by: Dmitry Osipenko <dmitry.osipenko@collabora.com>
|
||||
Co-developed-by: Dingxian Wen <shawn.wen@rock-chips.com>
|
||||
Signed-off-by: Dingxian Wen <shawn.wen@rock-chips.com>
|
||||
Signed-off-by: Shreeya Patel <shreeya.patel@collabora.com>
|
||||
Signed-off-by: Dmitry Osipenko <dmitry.osipenko@collabora.com>
|
||||
Link: https://lore.kernel.org/r/20250307091857.646581-2-dmitry.osipenko@collabora.com
|
||||
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
||||
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk3588-extra.dtsi
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3588-extra.dtsi
|
||||
@@ -23,6 +23,30 @@
|
||||
};
|
||||
};
|
||||
|
||||
+ reserved-memory {
|
||||
+ #address-cells = <2>;
|
||||
+ #size-cells = <2>;
|
||||
+ ranges;
|
||||
+
|
||||
+ /*
|
||||
+ * The 4k HDMI capture controller works only with 32bit
|
||||
+ * phys addresses and doesn't support IOMMU. HDMI RX CMA
|
||||
+ * must be reserved below 4GB.
|
||||
+ * The size of 160MB was determined as follows:
|
||||
+ * (3840 * 2160 pixels) * (4 bytes/pixel) * (2 frames/buffer) / 10^6 = 66MB
|
||||
+ * To ensure sufficient support for practical use-cases,
|
||||
+ * we doubled the 66MB value.
|
||||
+ */
|
||||
+ hdmi_receiver_cma: hdmi-receiver-cma {
|
||||
+ compatible = "shared-dma-pool";
|
||||
+ alloc-ranges = <0x0 0x0 0x0 0xffffffff>;
|
||||
+ size = <0x0 (160 * 0x100000)>; /* 160MiB */
|
||||
+ alignment = <0x0 0x40000>; /* 64K */
|
||||
+ no-map;
|
||||
+ status = "disabled";
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
usb_host1_xhci: usb@fc400000 {
|
||||
compatible = "rockchip,rk3588-dwc3", "snps,dwc3";
|
||||
reg = <0x0 0xfc400000 0x0 0x400000>;
|
||||
@@ -198,6 +222,37 @@
|
||||
};
|
||||
};
|
||||
|
||||
+ hdmi_receiver: hdmi_receiver@fdee0000 {
|
||||
+ compatible = "rockchip,rk3588-hdmirx-ctrler", "snps,dw-hdmi-rx";
|
||||
+ reg = <0x0 0xfdee0000 0x0 0x6000>;
|
||||
+ interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH 0>,
|
||||
+ <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH 0>,
|
||||
+ <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
+ interrupt-names = "cec", "hdmi", "dma";
|
||||
+ clocks = <&cru ACLK_HDMIRX>,
|
||||
+ <&cru CLK_HDMIRX_AUD>,
|
||||
+ <&cru CLK_CR_PARA>,
|
||||
+ <&cru PCLK_HDMIRX>,
|
||||
+ <&cru CLK_HDMIRX_REF>,
|
||||
+ <&cru PCLK_S_HDMIRX>,
|
||||
+ <&cru HCLK_VO1>;
|
||||
+ clock-names = "aclk",
|
||||
+ "audio",
|
||||
+ "cr_para",
|
||||
+ "pclk",
|
||||
+ "ref",
|
||||
+ "hclk_s_hdmirx",
|
||||
+ "hclk_vo1";
|
||||
+ memory-region = <&hdmi_receiver_cma>;
|
||||
+ power-domains = <&power RK3588_PD_VO1>;
|
||||
+ resets = <&cru SRST_A_HDMIRX>, <&cru SRST_P_HDMIRX>,
|
||||
+ <&cru SRST_HDMIRX_REF>, <&cru SRST_A_HDMIRX_BIU>;
|
||||
+ reset-names = "axi", "apb", "ref", "biu";
|
||||
+ rockchip,grf = <&sys_grf>;
|
||||
+ rockchip,vo1-grf = <&vo1_grf>;
|
||||
+ status = "disabled";
|
||||
+ };
|
||||
+
|
||||
pcie3x4: pcie@fe150000 {
|
||||
compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie";
|
||||
#address-cells = <3>;
|
||||
@@ -1,74 +0,0 @@
|
||||
From 849d9db170fc8a03ce9f64133a1d0cd46c135105 Mon Sep 17 00:00:00 2001
|
||||
From: Nicolas Frattaroli <nicolas.frattaroli@collabora.com>
|
||||
Date: Tue, 4 Feb 2025 16:35:46 +0100
|
||||
Subject: [PATCH] dt-bindings: reset: Add SCMI reset IDs for RK3588
|
||||
|
||||
When TF-A is used to assert/deassert the resets through SCMI, the
|
||||
IDs communicated to it are different than the ones mainline Linux uses.
|
||||
|
||||
Import the list of SCMI reset IDs from mainline TF-A so that devicetrees
|
||||
can use these IDs more easily.
|
||||
|
||||
Co-developed-by: XiaoDong Huang <derrick.huang@rock-chips.com>
|
||||
Signed-off-by: XiaoDong Huang <derrick.huang@rock-chips.com>
|
||||
Acked-by: Conor Dooley <conor.dooley@microchip.com>
|
||||
Signed-off-by: Nicolas Frattaroli <nicolas.frattaroli@collabora.com>
|
||||
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
|
||||
---
|
||||
.../dt-bindings/reset/rockchip,rk3588-cru.h | 41 ++++++++++++++++++-
|
||||
1 file changed, 40 insertions(+), 1 deletion(-)
|
||||
|
||||
--- a/include/dt-bindings/reset/rockchip,rk3588-cru.h
|
||||
+++ b/include/dt-bindings/reset/rockchip,rk3588-cru.h
|
||||
@@ -1,6 +1,6 @@
|
||||
/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
|
||||
/*
|
||||
- * Copyright (c) 2021 Rockchip Electronics Co. Ltd.
|
||||
+ * Copyright (c) 2021, 2024 Rockchip Electronics Co. Ltd.
|
||||
* Copyright (c) 2022 Collabora Ltd.
|
||||
*
|
||||
* Author: Elaine Zhang <zhangqing@rock-chips.com>
|
||||
@@ -753,4 +753,43 @@
|
||||
|
||||
#define SRST_A_HDMIRX_BIU 660
|
||||
|
||||
+/* SCMI Secure Resets */
|
||||
+
|
||||
+/* Name=SECURE_SOFTRST_CON00,Offset=0xA00 */
|
||||
+#define SCMI_SRST_A_SECURE_NS_BIU 10
|
||||
+#define SCMI_SRST_H_SECURE_NS_BIU 11
|
||||
+#define SCMI_SRST_A_SECURE_S_BIU 12
|
||||
+#define SCMI_SRST_H_SECURE_S_BIU 13
|
||||
+#define SCMI_SRST_P_SECURE_S_BIU 14
|
||||
+#define SCMI_SRST_CRYPTO_CORE 15
|
||||
+/* Name=SECURE_SOFTRST_CON01,Offset=0xA04 */
|
||||
+#define SCMI_SRST_CRYPTO_PKA 16
|
||||
+#define SCMI_SRST_CRYPTO_RNG 17
|
||||
+#define SCMI_SRST_A_CRYPTO 18
|
||||
+#define SCMI_SRST_H_CRYPTO 19
|
||||
+#define SCMI_SRST_KEYLADDER_CORE 25
|
||||
+#define SCMI_SRST_KEYLADDER_RNG 26
|
||||
+#define SCMI_SRST_A_KEYLADDER 27
|
||||
+#define SCMI_SRST_H_KEYLADDER 28
|
||||
+#define SCMI_SRST_P_OTPC_S 29
|
||||
+#define SCMI_SRST_OTPC_S 30
|
||||
+#define SCMI_SRST_WDT_S 31
|
||||
+/* Name=SECURE_SOFTRST_CON02,Offset=0xA08 */
|
||||
+#define SCMI_SRST_T_WDT_S 32
|
||||
+#define SCMI_SRST_H_BOOTROM 33
|
||||
+#define SCMI_SRST_A_DCF 34
|
||||
+#define SCMI_SRST_P_DCF 35
|
||||
+#define SCMI_SRST_H_BOOTROM_NS 37
|
||||
+#define SCMI_SRST_P_KEYLADDER 46
|
||||
+#define SCMI_SRST_H_TRNG_S 47
|
||||
+/* Name=SECURE_SOFTRST_CON03,Offset=0xA0C */
|
||||
+#define SCMI_SRST_H_TRNG_NS 48
|
||||
+#define SCMI_SRST_D_SDMMC_BUFFER 49
|
||||
+#define SCMI_SRST_H_SDMMC 50
|
||||
+#define SCMI_SRST_H_SDMMC_BUFFER 51
|
||||
+#define SCMI_SRST_SDMMC 52
|
||||
+#define SCMI_SRST_P_TRNG_CHK 53
|
||||
+#define SCMI_SRST_TRNG_S 54
|
||||
+
|
||||
+
|
||||
#endif
|
||||
@@ -24,3 +24,22 @@ Signed-off-by: wevsty <ty@wevs.org>
|
||||
resets = <&cru SRST_TRNG_NS>;
|
||||
status = "disabled";
|
||||
};
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
|
||||
@@ -1857,6 +1857,16 @@
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
+ rng: rng@fe378000 {
|
||||
+ compatible = "rockchip,trngv1";
|
||||
+ reg = <0x0 0xfe378000 0x0 0x200>;
|
||||
+ interrupts = <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>;
|
||||
+ clocks = <&scmi_clk SCMI_HCLK_SECURE_NS>;
|
||||
+ clock-names = "hclk_trng";
|
||||
+ resets = <&scmi_reset SRST_H_TRNG_NS>;
|
||||
+ reset-names = "reset";
|
||||
+ };
|
||||
+
|
||||
sdhci: mmc@fe2e0000 {
|
||||
compatible = "rockchip,rk3588-dwcmshc";
|
||||
reg = <0x0 0xfe2e0000 0x0 0x10000>;
|
||||
|
||||
Reference in New Issue
Block a user